JP3360835B2 - Wiring formation method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring applied to the manufacture of a semiconductor device and the like, and more particularly to a method for forming an aluminum-based material layer uniformly on a contact portion having a barrier metal structure. How to embed. 2. Description of the Related Art In a semiconductor device such as a VLSI or ULSI with a high density, an opening diameter of a connection hole formed in an interlayer insulating film in order to connect a lower wiring and an upper wiring. And the aspect ratio has become more than one. The upper wiring is generally formed by depositing an aluminum (Al) -based material by a sputtering method. However, sufficient step coverage is achieved to fill the connection hole having such a high aspect ratio. It is difficult to cause disconnection. Therefore, a high-temperature bias sputtering method has been proposed as a measure for improving the lack of step coverage. This technique involves heating a wafer to several hundred degrees Celsius through a heater block, as shown, for example, in Monthly Semiconductor World, December 1989, pages 186-188 (published by Press Journal). Sputtering is performed while applying an RF bias through a block. According to this method, the step coverage can be improved by the Al reflow effect due to the high temperature and the ion bombardment due to the bias application, and an Al-based material layer having a flat surface can be formed. In the above paper, when a Ti layer is provided as an underlayer of an Al-based material layer,
It is described that the Ti layer contributes to the surface movement (migration) of Al atoms to achieve excellent step coverage. [0004] Incidentally, the Ti layer provided as a base of the Al-based material layer functions as a barrier metal. However, the Ti layer has a low resistance ohmic
Although it is an excellent contact material that achieves contact, it alone cannot sufficiently function as a barrier metal. Even if a Ti layer is solely interposed between a silicon (Si) substrate and an Al-based material layer, since both the reaction between Si and Ti and the reaction between Ti and Al proceed, Al spikes on the Si substrate are caused. This is because the occurrence of the problem cannot be prevented. Therefore, a barrier metal (Ti / TiN-based) having a two-layer structure in which a TiN layer is further laminated on a Ti layer is employed.
Further, a barrier metal (Ti / TiON-based) having a two-layer structure has been proposed in which oxygen is introduced during the formation of a TiN layer to form a TiON layer. This is because segregation of oxygen at the grain boundaries of TiN can further enhance the effect of preventing Al grain boundary diffusion. [0005] However, Ti / Ti
In the case where an ON-based barrier metal is formed, it is difficult to uniformly fill the connection holes when the Al-based material layer is formed by applying a high-temperature bias sputtering method. For example, as shown in FIG.
An interlayer insulating film 23 having a connection hole 24 facing the impurity diffusion region 22 is laminated on a silicon substrate 21 on which the Ti layer 2 is formed.
Consider a wafer in which No. 5 and the TiON layer 26 are sequentially stacked as a barrier metal. This wafer is subjected to, for example, an Al-based material layer 27 by a high-temperature bias sputtering method.
However, even if an attempt is made to form a contact hole, the connection hole 24 cannot be uniformly buried, and a void 28 is likely to occur. this is,
This is because Al in the process of high-temperature bias sputtering is in an intermediate state between solid and liquid and is extremely sensitive to the surface morphology of the underlying layer. That is, the TiON layer 26 has a columnar crystal structure, and the longitudinal direction of the crystal is oriented almost perpendicular to the film surface, so that the surface morphology is rough and the wettability and reactivity with Al-based materials are poor. Therefore, the present inventors have further laminated a Ti layer, which has already been proved to have good wettability and reactivity with Al-based materials, on the above-mentioned TiON layer 26, and changed the barrier metal to a Ti / TiON / Ti-based material. We tried to make a three-layer structure. However, the surface morphology was not sufficiently improved even with the newly laminated Ti layer, and the connection holes 24 were not uniformly filled with the Al-based material with good reproducibility. As described above, it is difficult to form a contact that can simultaneously satisfy low resistance, high barrier properties, and excellent step coverage with the conventional technology. Accordingly, an object of the present invention is to provide a wiring forming method that can simultaneously satisfy these requirements. [0008] The present invention has been proposed to achieve the above-mentioned object, and is intended to provide a silicon-based substrate.
Removal of natural oxide film on the surface of the upper device formation area
Then , an SiO ₂ layer or Si ₃ N is formed on the silicon substrate.
_A titanium / silicide-based material layer is formed by performing a heat treatment in an inert gas atmosphere on a substrate in which _four layers and a first titanium material layer are sequentially formed, and further , an interlayer insulating film is formed on the substrate. And forming a connection hole facing the titanium-silicide-based material layer, thereafter covering at least a bottom surface and a side wall portion of the connection hole with a second titanium material layer, and thereafter filling at least the connection hole. An aluminum-based material layer is formed as much as possible. The present inventors consider that it is difficult to uniformly embed connection holes with an Al-based material layer as long as barrier properties are required for the TiON layer.
No. 30 formed by the method proposed in
Attention was paid to the Si ₂ layer. The method disclosed in the above publication discloses a conventional general salicide (SALICIDE = self align) formed for the purpose of reducing the contact resistance, the diffusion layer resistance and the like.
ed silicide).
That is, as in the conventional case, Ti
Instead of stacking layers and performing heat treatment, first remove the natural oxide film on the silicon substrate, form a new silicon compound layer, further stack a Ti layer, and perform heat treatment in an inert gas atmosphere. To form a silicide.
In particular, for a process using a silicon oxide layer formed by thermal oxidation or the like as a silicon compound layer, the applicant of the present invention has SITOX (= silicidation through oxidization) since the silicidation reaction is performed via the oxide layer.
e). The TiSi ₂ layer formed by this method is a field oxide film or a MOS.
In order to achieve the LDD structure in the transistor, the transistor selectively exists only in the element formation region without crawling on the sidewall formed on the side wall of the gate electrode.
There is no risk of causing a leak between the source / drain region and the gate electrode. Further, since the silicidation reaction rate at the time of film formation is low, the film quality is extremely dense and uniform, exhibiting high barrier properties, and the sheet resistance is kept low even after high-temperature annealing. As is clear from the above description, TiSi ₂ formed by the above-described method has a sufficiently low sheet resistance and a dense and uniform film quality, and therefore has excellent performance as a barrier metal. Can demonstrate. Therefore, in the present invention, a titanium-silicide-based material layer formed by a silicidation reaction between the first titanium-based material layer and the silicon-based substrate is used as a barrier metal. In the present invention, next, an interlayer insulating film is formed on the surface of the base, and a connection hole is opened facing the titanium / silicide-based material layer. At this point, the titanium / silicide-based material layer is exposed at the bottom of the connection hole. However, since the titanium-silicide-based material layer has a large thermal stress, if the Al-based material layer is applied as it is, it causes a stress migration. Further, the wettability between the inner wall portion of the connection hole and the Al-based material layer is insufficient. Therefore, a second titanium-based material layer is formed by covering the bottom surface and the inner wall portion of the connection hole. Thereby, the inner wall portions of the connection holes are all in a state in which the wettability and reactivity with the Al-based material layer are improved and the thermal stress is reduced. Thereafter, if an Al-based material layer is applied to the entire surface of the substrate, the Al-based material gradually enters the connection hole while causing an interfacial reaction with the titanium-based material, and is uniformly filled without generating voids. . Preferred embodiments of the present invention will be described below. This embodiment is an example in which the present invention is applied to the manufacture of a MOS transistor. This process will be described with reference to FIGS. First, as shown in FIG. 1, a field oxide film 2 is formed on a silicon substrate 1 by LOCOS, for example.
Was formed, and a gate electrode 4 made of DOPOS or the like was formed in an element formation region defined by the field oxide film 2 via a gate oxide film 3 made of silicon oxide or the like. Next, after the first ion implantation for forming the source / drain regions 5 using the gate electrode 4 as a mask, sidewalls made of silicon oxide or the like are conventionally formed by a CVD method or RIE. 6 was formed. Further, after removing the natural oxide film present on the surface of the element forming region with dilute hydrofluoric acid, SiO ₂ layers 7 and 8 each having a thickness of 50 ° are formed on the element forming region and the gate electrode 4 by, for example, thermal oxidation. did. The reason for removing the natural oxide film in advance is to make the thickness of the SiO ₂ layer 7 over the element formation region uniform. The SiO ₂ layers 7 and 8 are not formed by oxidizing the surface of the substrate as described above. For example, a thick SiO ₂ layer is formed by applying a polycrystalline silicon layer over the entire surface of the substrate and then performing thermal oxidation. May be formed, followed by etching with dilute hydrofluoric acid to reduce the layer thickness to a desired thickness. Further, using the gate electrode 4 and the sidewall 6 as a mask, a second ion implantation for increasing the impurity concentration in a part of the source / drain region 5 is performed by S.
This was performed via the iO ₂ layer 7. In this way, an LDD structure is achieved. At this time, the SiO ₂ on the gate electrode 4
The layer 8 also functions as a layer for preventing channeling due to implanted ions. Next, as an example, an argon flow rate of 100 SC
CM, gas pressure 0.47 Pa (3.5 mTorr), DC
Sputtering of Ti is performed under the conditions of a sputtering power of 4 kW, a substrate temperature of 300 ° C., and a sputtering rate of 3500 ° / min., And a first Ti layer 9 is formed to a thickness of about 300 ° on the entire surface of the substrate as shown in FIG. did. Next, the substrate shown in FIG. 2 is subjected to lamp annealing in an Ar atmosphere at about 650 ° C.
Part of the Ti layer 9 and the silicon substrate 1 (more precisely, the source /
The drain region 5) and the gate electrode 4 are each formed of SiO.
_The reaction was performed via the _two layers 7 and 8 to form TiSi layers (not shown). Subsequently, an unreacted portion of the first Ti layer 9 was selectively etched away using, for example, a mixed solution of ammonia and hydrogen peroxide solution. Further, lamp annealing is performed again at about 900 ° C. to further react the TiSi layer with the silicon substrate 1 and the gate electrode 4, thereby forming TiSi ₂ layers 7a and 8a as shown in FIG. did. Here, the reason why the lamp annealing for silicidation is performed in two stages as described above is as follows.
This is because the TiSi ₂ layers 7a and 8a are formed with good selectivity on the element forming region and the gate electrode. 900 from the beginning
When the silicidation is performed at about 0 ° C., TiSi ₂ layers 7 a and 8 a are formed to extend over field oxide film 2 and sidewall 6, and a leakage current between gate electrode 4 and source / drain region 5 is formed. Is likely to increase. Next, as shown in FIG. 4, an interlayer insulating film 10 is formed by depositing silicon oxide or the like on the entire surface of the substrate by, for example, CVD, and then the interlayer insulating film 10 is patterned to form a source / drain region. 5 on TiSi ₂ layer 7a
The contact hole 11 was opened. Further, for example, by performing sputtering under the same conditions as when forming the first Ti layer 9, the second Ti layer 1
2 was formed to a thickness of about 500 °. As a result, at least the bottom surface and the side wall of the contact hole 11 are covered with the second Ti layer 12, and the Al-1% Si layer 13 (see FIG. 5) formed later and the contact portion are not covered. The wettability and the reactivity are improved, and the thermal stress with the TiSi ₂ layer 7a is also reduced. Next, Al is formed by two-stage sputtering.
A -1% Si layer 13 was formed. Sputtering atmosphere: Ar flow rate 100 SCCM, gas pressure 0.47 Pa
(3.5 mTorr), and as the first step, the DC sputtering power was 22.degree. Without heating the substrate and applying a bias.
Sputtering at 7 kW, Al-1% Si layer 1
3 was formed to a thickness of about 1000 °. Subsequently, as a second step, the substrate is heated to about 450 ° C. by bringing the back surface of the substrate into contact with a high-temperature Ar gas, and high-temperature bias sputtering is performed while applying an RF bias power of 300 V, and Al-1% An Si layer 13 was further formed to a thickness of 3000 °. Thereby, as shown in FIG.
Finally, an Al-1% Si layer 13 having a thickness of 4000 ° was formed on the entire surface of the substrate, and the contact holes 11 were uniformly buried without generating voids. The formation of the Al-1% Si layer 13 does not necessarily have to go through the two-step process described above.
However, if the substrate is heated to a high temperature from the beginning of the film formation, the Al-1% Si layer 13 grows in an island shape depending on the conditions.
In order to prevent this, it is desirable to divide the film formation process into two stages and to make the first stage a low-temperature process. Thereby, the film quality of the Al-1% Si layer 13 can be further improved. Further, as shown in FIG.
The Si layer 13 and the second Ti layer 12 were patterned by dry etching using a chlorine-based gas or the like to form an Al-based electrode 13a having a Ti layer pattern 12a as a base. In the MOS transistor manufactured in this embodiment, the sheet resistance of the source / drain region 5 and the gate electrode 4 is reduced by the TiSi ₂ layers 7a and 8a, and the silicide layer is formed by the conventional SALICIDE method. Junction leakage current was significantly reduced even after high-temperature annealing as compared with MOS transistors. This is because in the MOS transistor of this embodiment, TiS
i _2-layer 7a, are associated with the 8a quality of is excellent. FIG. 8 shows a voltage of -5.5 V applied to the gate electrode of a MOS transistor held at a predetermined annealing temperature for 30 minutes.
7 is a graph showing measurement results of junction leak current when a voltage of? The vertical axis represents the junction leak current (A), the horizontal axis represents the annealing temperature (° C.), the open circle (丸) plots the data of the conventional MOS transistor, and the black square (■) plots the data of the MOS transistor of this embodiment. Shown respectively.
In a conventional MOS transistor, T
Aggregation of iSi ₂ crystals occurs, increasing sheet resistance.
When the substrate was heated to about 400 ° C., the resistance to Al spikes deteriorated, and the junction leak current increased sharply.
However, in the MOS transistor manufactured in this embodiment, since the TiSi ₂ layers 7a and 8a have a large crystal grain size and a dense grain boundary, the diffusion of Ti and Si even after being heated to 500 ° C. , The sheet resistance was kept low, the junction leakage current hardly changed, and high resistance to Al spikes was maintained. This means that A
In the step of forming the 1-1% Si layer 13, a high temperature bias
This shows that the characteristics of the MOS transistor of this embodiment do not deteriorate even after sputtering. The present invention is not limited to the above-described embodiment. For example, as the silicon compound layer, in addition to the above-mentioned SiO ₂ layer, a silicon nitride layer (Si ₃ N ₄ )
Etc. can be used. As is apparent from the above description, when the present invention is applied, low resistance and high barrier properties are guaranteed by the TiSi ₂ layer, and excellent step coverage by the second Ti layer. Therefore, it is possible to bury the connection hole with high reliability by using the Al-based material. Therefore, the present invention is extremely suitable for manufacturing a semiconductor device that requires high integration and high performance based on a fine design rule.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing an example in which the present invention is applied to the manufacture of a MOS transistor having an LDD structure, in which an SiO ₂ layer is formed on an element formation region and a gate electrode. Indicates the status. FIG. 2 is a schematic cross-sectional view showing a state where a first Ti layer is formed on the entire surface of the base shown in FIG. FIG. 3 is a schematic cross-sectional view showing a state where a TiSi ₂ layer is selectively formed on a source / drain region and a gate electrode by a silicidation reaction. FIG. 4 is a schematic cross-sectional view showing a state in which a contact hole facing a TiSi ₂ layer is opened by patterning an interlayer insulating film, and a second Ti layer is applied to the entire surface of a substrate. FIG. 5 is a schematic cross-sectional view showing a state in which an Al-1% Si layer is formed on the entire surface of the substrate shown in FIG. FIG. 6 is a schematic sectional view showing a state where an Al-based electrode is formed by patterning. FIG. 7 is a schematic cross-sectional view showing a state in which a contact portion having a conventional barrier metal structure is not uniformly filled with an Al-based material in a contact hole and a hole is generated. FIG. 8 is a characteristic diagram showing a comparison between annealing temperature dependence of junction leak current of a MOS transistor manufactured by applying the present invention and a conventional MOS transistor. [Description of Signs] 1 silicon substrate, 4 gate electrode, 5 source /
Drain region, 7,8 SiO ₂ layer, 7a, 8a
TiSi ₂ layer, 9 first Ti layer, 10 interlayer insulating film, 11 contact hole, 12 second Ti
Layer, 13Al-1% Si layer, 13a Al-based electrode

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 29/46 (56) References JP-A-2-260630 (JP, A) JP-A-1-125927 (JP, A)

Claims (1)

(57) [Claims] [Claim 1] The surface of an element formation region on a silicon-based substrate
Is removed, and then a SiO ₂ layer or Si ₃ N _{4 is formed} on the silicon substrate.
A titanium / silicide-based material layer is formed by performing a heat treatment in an inert gas atmosphere on a substrate in which a layer and a first titanium material layer are sequentially formed, and further forming an interlayer insulating film on the substrate. Forming the titanium
A connection hole is opened facing the silicide-based material layer.
And further forming an aluminum-based material layer so as to fill at least the connection hole.