JP2001284284A - Wiring structure in semiconductor device and mos transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide wiring structure in a semiconductor device that can reduce sheet resistance in a lower layer conductive region, can inhibit crease of contact resistance and junction leakage, and has a superior barrier property. SOLUTION: This wiring structure in the semiconductor device consists of a lower layer conductive region 18 formed on a semiconductor substrate 10, an upper layer wiring layer 32 formed on an insulation layer 22B for covering the lower layer conductor region 18, and a connection hole 28 that electrically connects the lower layer conductive layer to the upper layer wiring layer. Then, at the bottom part of the connection hole 28, a single crystal CoSi2 layer 20 and a single crystal TiN layer 26 are formed from the side of the semiconductor substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a wiring structure and a wiring forming method in a semiconductor device, and a MOS transistor.

[0002]

2. Description of the Related Art As semiconductor devices become more highly integrated, the junction depth is becoming smaller. When the dimensional rule of the semiconductor device reaches the 0.1 μm level, the sheet resistance of the bonding region becomes 1
kΩ / □ or more, which causes a problem that the response speed of the semiconductor element is reduced. One method for solving this problem is to form a silicide such as CoSi ₂ or TiSi _{2 on} the surface of a source / drain region formed on a semiconductor substrate.

In order to electrically connect the source / drain region and the upper wiring layer, it is necessary to form a connection hole.
The connection hole forms an opening in the insulating layer above the source / drain region after forming an insulating layer covering the source / drain region, and forms a barrier layer on the insulating layer including the opening. The opening is formed by depositing a metal wiring material on the barrier layer to fill the opening with the barrier layer and the metal wiring material. The barrier layer is formed to suppress a reaction between the source / drain region and the metal wiring material in the opening.

As the dimensional rules of semiconductor devices become finer, the diameter of connection holes also tends to become finer. As a result, there is a problem that the coverage of the barrier layer in the opening decreases, and the barrier property of the barrier layer decreases.

Here, an outline of a conventional semiconductor device manufacturing process will be briefly described below with reference to FIG.

[Step-10] An element isolation region 12 and a gate electrode 14 are formed on a semiconductor substrate 10 by a conventional method.

[Step-20] LDD (Lightly-Doped Dr.
ain) Ion implantation is performed to form a structure, and then a gate sidewall 16 is formed, followed by ion implantation to form a lower conductor region 18 composed of source / drain regions (see FIG. 6A).

[Step-30] In order to reduce the sheet resistance of the lower conductor region 18 composed of the source / drain region,
The CoSi ₂ silicide layer 10 is formed on the surface of the lower conductor region 18.
0 (see FIG. 6B). For this purpose, after forming a Co layer on the entire surface, heat treatment is performed to form the lower conductor region 1.
8 reacts with Co in the Co layer to form CoSi ₂
The layer 100 is formed. The unreacted Co layer is selectively removed with hydrochloric acid / hydrogen peroxide.

[Step-40] Thereafter, the insulating layer 22 is formed on the entire surface.
And an opening 24 is formed above the lower conductor region 18 (see FIG. 6C).

[Step-50] Next, a barrier layer (composed of a Ti layer / TiN layer) 102 is formed on the insulating layer 22 including the opening 24 by, for example, a sputtering method, and a tungsten layer 104 is formed by a CVD method. After depositing on the whole surface at
Tungsten layer 104 and barrier layer 10 on insulating layer 22
2 is selectively removed to form a connection hole 28 made of a tungsten plug in the opening 24 (see FIG. 7A). Then, from below, Ti layer / TiON layer / Al-S
After an i-layer is deposited over the entire surface by sputtering, these layers are patterned to form the wiring 106 (see FIG. 7B). The reference number 106A is Ti
2 shows a layer / TiON layer.

In the above process, since the barrier layer 102 formed in the opening 24 is formed by a sputtering method, the coverage of the barrier layer 102 in the opening 24 becomes very high as the aspect ratio of the opening 24 increases. Worse. As a result, the thickness of the barrier layer 102 at the bottom of the opening 24 is reduced. Therefore, the tungsten layer 1 is formed by the CVD method.
When 04 is deposited, the barrier layer 102 is eroded by fluorine contained in the source gas for CVD (WF ₆ ),
Further, the lower conductor region (source / drain region) 18 is corroded by fluorine. As a result, there arises a problem that junction leakage increases.

As a method for solving the problem of the coverage of the barrier layer 102 in the opening 24, T
Formation of a barrier layer composed of an i layer / TiN layer can be mentioned. When the CVD method is used, the coverage problem of the barrier layer 102 at the bottom of the opening 24 can be solved. However, since the TiN layer formed by the CVD method is polycrystalline, when a high-temperature heat treatment such as a diffusion step or an annealing step is performed on the semiconductor substrate, the TiN grain boundary portion is corroded by fluorine, There is a problem that the metal wiring material in the connection hole 28 diffuses in the TiN grain boundary and corrodes the semiconductor substrate. That is, the polycrystalline TiN layer cannot be said to have a sufficient barrier property.

In order to solve the problem caused by the polycrystallinity of the TiN layer, the present applicant has proposed that a single-crystal TiN layer is epitaxially grown directly on a silicon semiconductor substrate (see Japanese Patent Application No. 5-69197). ).

[0014]

However, it is difficult to obtain a good electrical ohmic junction even if a single crystal TiN layer is simply formed on a silicon semiconductor substrate. This is because a natural oxide film exists on the semiconductor substrate and T
Even if an iN layer is formed on this natural oxide film, the TiN layer cannot reduce the natural oxide film, so that electrical conduction is difficult to obtain. Furthermore, if a native oxide film remains,
There is also a problem that the TiN layer is difficult to epitaxially grow on the semiconductor substrate.

As a method for solving these problems, there are the following methods. That is, before the TiN layer is formed, the natural oxide film is reduced by hydrogen plasma. This removes the natural oxide film, exposing a clean surface of the silicon semiconductor substrate. After that, a source gas for CVD is introduced to form a TiN layer by a CVD method.

However, the problem with this method is that
As a pretreatment before forming the TiN layer, the surface of the silicon semiconductor substrate is exposed to a hydrogen plasma treatment. As a result, there is a problem that hydrogen atoms enter the silicon crystal, crystal defects occur in the silicon crystal, and junction leakage increases.

When a TiN layer is formed on a silicon semiconductor substrate by the CVD method, a thin SiN film is formed on the surface of the silicon semiconductor substrate because the surface of the silicon semiconductor substrate is exposed to nitrogen plasma, thereby increasing contact resistance. There is also the problem of doing.

Further, in this method, it is required that the silicon surface is exposed on the surface of the source / drain region. Therefore, a silicide layer cannot be formed on the surface of the source / drain region in order to reduce the sheet resistance of the source / drain region as described above. That is,
There is also a problem that a single crystal TiN layer cannot be formed on the silicide layer.

Accordingly, an object of the present invention is to reduce the sheet resistance of the lower conductor region, suppress an increase in contact resistance and junction leak, and furthermore, provide a wiring structure and a semiconductor device having excellent barrier properties. An object of the present invention is to provide a method of forming the same and a MOS transistor.

[0020]

The object of the present invention is to provide a lower conductor region formed on a semiconductor substrate, an upper wiring layer formed on an insulating layer covering the lower conductor region, a lower conductor region and an upper wiring layer. A wiring structure in a semiconductor device, comprising: a connection hole for electrically connecting a single crystal CoSi ₂ layer and a single crystal TiN layer to the bottom of the connection hole from the semiconductor substrate side. This can be achieved by the wiring structure of the present invention characterized by the following.

In the wiring structure according to the present invention, the semiconductor substrate is desirably made of a silicon semiconductor substrate. Also,
The orientation of the silicon semiconductor substrate is preferably (100).

Alternatively, the above object is achieved by electrically connecting a lower conductor region formed on a semiconductor substrate, an upper wiring layer formed on an insulating layer covering the lower conductor region, and a lower conductor region and an upper wiring layer. consisting of connecting holes for connecting to a wiring forming method for forming an interconnection structure in a semiconductor device, the bottom of at least the connection hole, the step of epitaxially growing a single-crystal CoSi ₂ layer, and the single-crystal CoSi ₂
This can be achieved by the wiring forming method of the present invention, which includes a step of epitaxially growing a single crystal TiN layer on the layer.

In the wiring forming method of the present invention, it is desirable that the degree of vacuum in the atmosphere before the single crystal TiN layer is epitaxially grown is 1.3 × 10 ⁻⁵ Pa or less. Further, before epitaxially growing a single crystal TiN layer,
It is preferable to include a step of removing a natural oxide film formed on the surface of the single crystal CoSi ₂ layer by hydrogen plasma treatment.

Further, the above object is achieved by providing a source / drain region formed on a semiconductor substrate, an upper wiring layer formed on an insulating layer covering the source / drain region, a source / drain region and an upper wiring layer. A MOS transistor having a wiring structure comprising a connection hole for electrically connecting the semiconductor substrate to a single crystal CoSi ₂ layer and a single crystal TiN layer at the bottom of the connection hole from the semiconductor substrate side. This can be achieved by the MOS transistor according to the present invention.

In the present invention, the single-crystal CoSi ₂ layer is formed at least at the bottom of the connection hole, and the lower sheet resistance of the lower conductor region can be reduced. On the single crystal CoSi ₂ layer, a single crystal TiN having excellent barrier properties is provided.
A layer is formed. When removing the native oxide film by hydrogen plasma treatment before forming the TiN layer, CoS
Since the i ₂ layer is formed, entry of hydrogen atoms into the silicon crystal can be suppressed. Furthermore, T
When the iN layer is formed, the surface of the silicon semiconductor substrate is not exposed to the nitrogen plasma, so that the formation of the SiN film can be prevented.

Conventionally, it has been known that CoSi ₂ grows epitaxially on a (111) silicon semiconductor substrate. However, in manufacturing a normal MOS transistor, a (100) silicon semiconductor substrate is often used. (100) Co on silicon semiconductor substrate
In order to epitaxially grow Si ₂ , two layers of a Co layer / Ti layer are previously formed on a semiconductor substrate. afterwards,
When heat treatment is applied to these two layers, a single crystal CoSi ₂ layer / Si structure can be obtained. At this time, the single crystal CoS
A TiO _x layer is formed on the surface of the i ₂ layer.

On this single crystal CoSi ₂ layer, a single crystal Ti
In order to epitaxially grow an N layer, hydrogen plasma treatment is performed in an apparatus for forming a TiN layer, and a single crystal C
It is necessary to reduce and remove TiO _x on the surface of the oSi ₂ layer. Subsequently, a single-crystal TiN layer / single-crystal CoSi ₂ layer / Si structure can be obtained by continuously forming a single-crystal TiN layer by a CVD method.

Here, in order to epitaxially grow the single crystal TiN layer, the degree of vacuum before film formation is also an important factor. According to gas kinetics, temperature T ゜ K, pressure P (torr)
The number N at which a molecule having a molecular weight M collides with a unit area (1 cm ² ) per second in an atmosphere of N is: N = 2.89 × 10 ²² P (MT) ^−1/2 cm ⁻² s ⁻¹ (1) ).

The degree of vacuum before the introduction of the CVD source gas in the chamber of the single crystal TiN layer film forming apparatus is 0.133P.
In the case of a (1 × 10 ⁻³ torr), from the equation (1), for example,
At room temperature (25 ° C.), 3.0 × 10 ¹⁷ oxygen molecules collide per 1 cm ^{2 of} the silicon semiconductor substrate.

The intermolecular distance is 0.24 nm (interatomic distance +
Atomic diameter). Therefore, the unit area (1 cm ² )
Per layer in (0.01 / 0.24 × 10 ^-9 )
² = 1.74 × 10 ¹⁵ oxygen molecules / cm ² are present.
All of the oxygen molecules hitting the semiconductor substrate are single crystal CoSi
Assuming adsorbed on the surface of the _second layer, 1.74 × 10 ^{1 5}
/3.0×10 ¹⁷ = approximately 0.0058 seconds to form one oxygen molecule layer.

If ten layers of TiN are to be grown in one minute, the surface of the semiconductor substrate must be kept clean during this time. For that purpose, it is necessary to maintain the chamber of the film forming apparatus at a vacuum level at which no oxygen molecular layer is formed on the surface of the semiconductor substrate for one minute or more.
In other words, the time required for forming one oxygen molecular layer needs to be 1 minute or more. From the equation (1), a degree of vacuum is required such that 2.9 × 10 ¹³ / second or less oxygen molecules collide with the single crystal CoSi ₂ layer per second. That is, if a vacuum degree of 1.3 × 10 ⁻⁵ Pa or less is maintained, a single crystal TiN layer can be formed on a clean semiconductor substrate surface.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described based on embodiments with reference to the drawings. In the first embodiment, a single-crystal TiN layer is formed at the bottom of the connection hole by an epitaxial growth method. In the second and third embodiments, the single-crystal Ti was formed in the source / drain regions by an epitaxial growth method.
An N layer is formed.

(Embodiment 1) Embodiment 1 is an example in which the wiring structure and the wiring forming method of the present invention are applied to the manufacture of a MOS transistor.

As shown in a schematic partial cross-sectional view of FIG. 1, the wiring structure of the first embodiment includes a lower conductor region 18 formed on a semiconductor substrate 10 and an insulating layer 22A covering the lower conductor region 18. An upper wiring layer 32 formed on the upper wiring layer 22B, and a connection hole 28 for electrically connecting the lower conductor region 18 and the upper wiring layer 32 are formed. Then, at the bottom of the connection hole 28,
A single crystal CoSi ₂ layer 20 and a single crystal TiN layer 26 are formed from the semiconductor substrate side. The lower conductor region 18 is specifically a source / drain region. The semiconductor substrate 10 is made of a silicon semiconductor substrate, and its orientation is (100). In FIG. 1, reference numeral 12 denotes an element isolation region, reference numeral 14 denotes a gate electrode, and reference numeral 30.
Is a barrier layer.

The method for forming the wiring structure according to the first embodiment shown in FIG. 1 will be described below with reference to FIGS.

[Step-100] First, an element isolation region 12 and a gate electrode 14 are formed on a silicon semiconductor substrate 10 having an orientation (100) by a conventional method.
Next, ion implantation is performed to form an LDD structure. Thereafter, an SiO ₂ film is formed on the entire surface by a CVD method in order to form the gate sidewall 16. SiO ₂
The conditions for forming the film can be, for example, as follows. Gas used: SiH ₄ / O ₂ / N ₂ = 250/250 /
100 sccm Temperature: 420 ° C. Pressure: 13.3 Pa Film thickness: 0.25 μm

Thereafter, for example, the SiO ₂ film is entirely etched back under the following conditions to form a gate sidewall 16 on the side wall of the gate electrode 14. Working gas: C ₄ F ₈ = 50 sccm RF power: 1200 W Pressure: 2 Pa

Next, impurity ion implantation for forming the source / drain regions is performed, for example, under the following conditions to form the lower conductor region 18 composed of the source / drain regions (see FIG. 2A). [In the case of N channel formation] Ion species: As 20 KeV 5 × 10 ¹⁵ / cm ² [In the case of P channel formation] Ion species: BF _{2 20} KeV 3 × 10 ¹⁵ / cm ²

[Step-110] Next, a single-crystal CoSi film is formed on the surface of the lower conductor region 18 comprising a source / drain region.
_{The two} layers 20 are formed. For this purpose, first, a Ti layer having a thickness of 5 nm is formed on the entire surface by, for example, a sputtering method under the following conditions. Process gas: Ar = 100 sccm Power: 1 kW Film formation temperature: 150 ° C. Pressure: 0.47 Pa

Further, a Co layer is continuously formed by a sputtering method.
For example, it is formed under the following conditions. Process gas: Ar = 100 sccm Power: 3 kW Film formation temperature: 150 ° C. Pressure: 0.47 Pa

Thereafter, heat treatment is performed to form a single crystal CoSi ₂ layer 20 from the Co layer by a silicidation reaction. The conditions of the heat treatment are, for example, 600 ° C. × 60 seconds in a nitrogen gas (1 atm) atmosphere. by this,
And the reaction with Si in Co and the semiconductor substrate, CoSi _X is formed. Thereafter, unreacted Ti and Co are selectively removed by immersing the entire semiconductor substrate in a mixed solution of hydrochloric acid, hydrogen peroxide and pure water for 10 minutes. Thereafter, for example, a heat treatment at 850 ° C. × 60 seconds is performed in a nitrogen gas (1 atm) atmosphere to convert CoSi _x into stable CoS.
i ₂ . Thus, the CoSi ₂ layer 20 is formed on the surface of the lower conductor region 18 composed of the source / drain regions (see FIG. 2B). When the CoSi ₂ layer 20 is formed, a natural oxide film (not shown) made of TiO _x is formed on the surface thereof, and this natural oxide film is removed by a later hydrogen plasma processing step.

[Step-120] Thereafter, SiO _{2 is applied to the} entire surface.
The insulating layer 22A made of, for example, CV using TEOS
Formed by method D. The conditions for forming the insulating layer 22A can be, for example, gas used: TEOS = 50 sccm, pressure: 40 Pa, temperature: 720 ° C., and film thickness: 400 nm. Further, B is further placed on the insulating layer 22A.
The insulating layer 22B made of PSG is formed, for example, under the following conditions. Gas used: SiH ₄ / PH ₃ / B ₂ H ₆ / O ₂ / N ₂ = 8
0/7/7/1000/32000 sccm Temperature: 400 ° C. Pressure: 1.0 × 10 5 Pa Film thickness: 500 nm

Next, after heat treatment is performed to flatten the surface of the insulating layer, resist patterning is performed on the insulating layers 22A and 22B, and then the insulating layer 22 is formed by dry etching.
Openings 24 are formed in A and 22B (see FIG. 2C). Dry etching conditions can be, for example, as follows. Working gas: C ₄ F ₈ = 50 sccm RF power: 1200 W Pressure: 2 Pa

Thereafter, a junction region is formed by performing ion implantation. The conditions for ion implantation are exemplified below. [In the case of forming an N channel] Ion species: As 20 KeV 5 × 10 ¹⁵ / cm ² [In the case of forming a P channel] Ion species: BF _{2 20} KeV 3 × 10 ¹⁵ / cm ² Then, at 1050 ° C. × 5 seconds Activation annealing is performed.

[Step-130] Next, a single crystal TiN layer 26 is formed at the bottom of the opening 24. First of all,
The substrate on which the processing up to [Step-110] has been performed is subjected to ECRC.
Carry in the VD device. Here, an ECRCVD apparatus is used in which the degree of vacuum in the atmosphere before epitaxial growth of the single crystal TiN layer is 1.3 × 10 ⁻⁵ Pa or less. After carrying the substrate into the ECRCVD apparatus, a natural oxide film or the like existing on the surface of the CoSi ₂ layer 20 exposed at the bottom of the opening 24 is reduced and removed by, for example, hydrogen plasma treatment under the following conditions. Gas used: H ₂ / Ar = 26/60 sccm Microwave power: 2.8 kW

Next, a single crystal TiN layer 26 is formed by ECRCVD. The conditions for forming the single crystal TiN layer 26 can be, for example, as follows. In the first film forming step, a nucleus of TiN is formed on the surface of the single crystal CoSi ₂ layer 20, and in the second film forming step, a single crystal T
Grow iN. In the first film formation stage, the single crystal T
It is desirable to grow iN epitaxially at a growth rate of 10 monolayers / minute or less. By providing the first film forming step, the single crystal T in the second film forming step
The growth rate of the iN layer can be increased. [Conditions of the first film formation stage] Gas used: TiCl ₄ / H ₂ / N ₂ = 2 / 2.6 / 0.8 sccm Temperature: 750 ° C Film thickness: 0.5 nm Pressure: 6.6 × 10 ^-4 Pa Microwave power: 2.8 kW [Conditions of the second film forming stage] Gas used: TiCl ₄ / H ₂ / N ₂ = 20/26/8 sccm Temperature: 750 ° C Film thickness: 70 nm Pressure: 0.12 Pa Microwave Power: 2.8 kW As a result, an epitaxially grown single crystal TiN layer 26 is formed on the entire surface of the insulating layer 22B including the bottom of the opening 24 (see FIG. 3A). In the first embodiment, the temperature during the film formation in the first film formation stage is 700 to 12
It is desirable that the temperature be 50 ° C. Note that, depending on the conditions for forming the single crystal TiN layer, the single crystal TiN layer 26
Although complete epitaxial growth may not occur on B, there is no problem because the object of the present invention can be sufficiently achieved.

[Step-140] Thereafter, a metal wiring material is buried in the opening 24 to form a connection hole 28. In Example 1, tungsten (W) was used as a metal wiring material. That is, tungsten is deposited on the single crystal TiN layer 26 by, for example, a CVD method under the following conditions. The thickness of the tungsten layer on the insulating layer 22B is 400
nm. Working gas: WF ₆ / H ₂ = 95/550 sccm Temperature: 450 ° C. Pressure: 1.1 × 10 4 Pa

Next, etch back is performed to form the insulating layer 22.
B, the tungsten layer and the single crystal TiN layer 26 are removed, and the tungsten layer and the single crystal TiN
The N layer 26 is left. Thus, the connection hole 28 is completed (FIG. 3
(B)). The conditions of the etch back are exemplified below. Working gas: SF ₆ = 50 sccm Microwave power: 850 W RF power: 150 W Pressure: 1.33 Pa

[Step-150] After that, the barrier layer 30 and the upper wiring layer 32 are formed by the sputtering method. Example 1
In the above, the barrier layer 30 is formed of a Ti layer (thickness 30) from below.
nm) / TiON layer (thickness: 70 nm). The upper wiring layer 32 is made of Al-1% Si (having a thickness of 50%).
0 nm). The sputtering conditions for each layer are exemplified below. [Ti film formation conditions] Process gas: Ar = 100 sccm Power: 4 kW Film formation temperature: 150 ° C. Pressure: 0.47 Pa [TiON film formation conditions] Process gas: Ar / N ₂ -6% O ₂ = 40/70 sccm power : 5 kW Pressure: 0.47 Pa [Al-1% Si film formation conditions] Process gas: Ar = 40 sccm Power: 22.5 kW Film formation temperature: 150 ° C Pressure: 0.47 Pa

Thereafter, resist patterning and dry etching are performed to form the upper wiring layer 32 and the barrier layer 30 into desired wiring pattern shapes. The conditions of the dry etching are exemplified below. Working gas: BCl ₃ / Cl ₂ = 60/90 sccm Microwave power: 1000 W RF power: 50 W Pressure: 0.016 Pa

Thus, the wiring structure shown in FIG. 1 can be formed. The single-crystal CoSi ₂ layer 20 is formed on the surface of the lower conductor region 18 composed of the source / drain region, so that the lower conductor region 18 can have a low sheet resistance. On the single crystal CoSi ₂ layer 20, a single crystal TiN layer 26 having excellent barrier properties is formed.
Before removing the natural oxide film or the like by hydrogen plasma treatment before forming the single crystal TiN layer 26, the CoSi ₂ layer 2
Since 0 is formed, the entry of hydrogen atoms into the silicon crystal can be suppressed. Furthermore, when the single crystal TiN layer 26 is formed, the surface of the silicon semiconductor substrate is not exposed to the nitrogen plasma, and the formation of the SiN film can be prevented.

(Embodiment 2) In the embodiment 1, the single-crystal TiN layer 26 is
It is in contact with the i ₂ layer 20. On the other hand, in Example 2, the single crystal TiN layer is formed on the entire surface of the single crystal CoSi ₂ layer. In the first embodiment, the opening 2
4 was filled with tungsten to form a connection hole 28. On the other hand, in the second embodiment, when the upper wiring layer is formed by the sputtering of the aluminum-based wiring material, the inside of the opening 24 is also buried with the aluminum-based wiring material to form the connection hole 28.

[Step-200] First, an element isolation region 12 and a gate electrode 14 are formed on a silicon semiconductor substrate 10 having an orientation (100) by a conventional method, and then an LDD structure is formed and a gate side is formed. Formation of wall 16, lower conductor region 18 composed of source / drain regions
Is formed. These forming conditions can be the same as in [Step-100] of the first embodiment.

[Step-210] Next, a single-crystal CoSi film is formed on the surface of the lower conductor region 18 comprising a source / drain region.
_{The two} layers 20 are formed. This step is also the same as the [Step-
110].

[Step-220] Thereafter, single-crystal CoSi
_A single crystal TiN layer 40 is formed on the _two layers 20. For this purpose, first, the hydrogen plasma treatment described in [Step-130] of the first embodiment is performed to remove a natural oxide film and the like formed on the surface of the single crystal CoSi ₂ layer 20. Next, ECR
The single crystal TiN layer 40 is formed by CVD using a single crystal CoSi
_It is selectively formed only on the _two layers 20. The single-crystal TiN layer 40 is selectively formed only on the single-crystal CoSi ₂ layer 20 by setting the temperature at the time of film formation lower than [Step-130] of the first embodiment. It is desirable to further promote single crystallization of TiN by applying a substrate bias during film formation. The conditions for forming the single crystal TiN layer 40 can be, for example, as follows. In the first film forming stage, a nucleus of TiN is formed on the surface of the CoSi ₂ layer 20,
In the second film formation stage, single crystal TiN is grown from this nucleus. [Conditions of First Film Forming Step] Gas used: TiCl ₄ / H ₂ / N ₂ = 2 / 2.6 / 0.8 sccm Temperature: 300 ° C. Film thickness: 0.5 nm Pressure: 6.6 × 10 ^-4 Pa Microwave power: 2.8 kW [Conditions of the second film forming stage] Gas used: TiCl ₄ / H ₂ / N ₂ = 20/26/8 sccm Temperature: 300 ° C Film thickness: 70 nm Pressure: 0.12 Pa Microwave Power: 2.8 kW As a result, an epitaxially grown single crystal TiN layer 40 is formed on the single crystal CoSi ₂ layer 20 (FIG. 4).
(A)). Note that a polycrystalline TiN layer 40A is formed above the gate electrode 14. Further, under the above film formation conditions, the TiN layer is not formed on the element isolation region 12.

[Step-230] Next, as in [Step-120] of the first embodiment, after the insulating layers 22A and 22B are formed on the entire surface, the openings 24 are formed in the insulating layers 22A and 22B (FIG. 4 (B)), ion implantation is performed to form a junction region, and activation annealing is performed at 1050 ° C. × 5 seconds.

[Step-240] Next, a 30-nm-thick underlayer 42 made of Ti is formed on the insulating layer 22B including the opening 24 by a sputtering method, and then the underlayer 42 is formed by a high-temperature aluminum sputtering method. An upper wiring layer 44 made of Al-1% Si and having a thickness of 500 nm is formed thereon. The conditions for forming the underlayer 42 and the upper wiring layer 44 can be, for example, as follows. [Conditions for forming underlayer] Process gas: Ar = 100 sccm Power: 4 kW Film formation temperature: 150 ° C. Pressure: 0.47 Pa [Conditions for forming upper wiring layer] Process gas: Ar = 40 sccm Power: 22.5 kW Film formation temperature : 500 ° C Pressure: 0.47Pa

Thereafter, in the same manner as in [Step-150] of the first embodiment, resist patterning and dry etching are performed to form the upper wiring layer 44 and the underlying layer 42 into desired wiring pattern shapes.

Third Embodiment A third embodiment is a modification of the second embodiment. In Example 2, the single crystal TiN layer 40 was selectively formed on the single crystal CoSi ₂ layer 20. In Example 3, the entire surface of the semiconductor substrate including a single crystal CoSi ₂ layer to form a TiN layer, then, the single-crystal CoSi ₂ layer on the single crystal TiN layer, and single crystal Ti used as a wiring portion
Other portions of the TiN layer are removed, leaving the N layer.

[Step-300] First, an element isolation region 12 and a gate electrode 14 are formed on a silicon semiconductor substrate 10 having an orientation (100) by a conventional method, and then an LDD structure is formed and a gate side is formed. Formation of wall 16, lower conductor region 18 composed of source / drain regions
Is formed. These forming conditions can be the same as in [Step-100] of the first embodiment.

[Step-310] Next, a single-crystal CoSi film is formed on the surface of the lower conductor region 18 comprising a source / drain region.
_{The two} layers 20 are formed. This step is also the same as the [Step-
110].

[Step-320] Thereafter, single-crystal CoSi
_A single crystal TiN layer 40 is formed on the _two layers 20. Also,
The single crystal TiN layer 40 may be formed in a region other than the single crystal CoSi ₂ layer.
Form A. For that purpose, first, [Step-
130], the natural oxide film formed on the surface of the single crystal CoSi ₂ layer 20 is removed. Next, single-crystal CoSi _{2 is formed} by ECRCVD.
The single-crystal TiN layer 40 is formed on the layer 20, and the single-crystal TiN layer 40A is formed in another region. Note that, depending on the conditions for forming the single crystal TiN layer, the single crystal TiN layer 40A may be used.
In some cases, complete epitaxial growth may not occur on another region (for example, the element isolation region 12). However, the object of the present invention can be sufficiently achieved.

The temperature at the time of film formation was set to [Step-22] in Example 2.
0], the single crystal TiN layer 40
Is formed on the single-crystal CoSi ₂ layer 20, and a single-crystal TiN layer 40A is also formed in other regions. It is desirable to further promote single crystallization of TiN by applying a substrate bias during film formation. TiN layers 40 and 40A
Can be formed, for example, as follows. In the first film forming step, a nucleus of TiN is formed on the surface of the CoSi ₂ layer 20 or the like, and in the second film forming step, a single crystal TiN layer is grown from this nucleus. [Conditions of the first film formation stage] Gas used: TiCl ₄ / H ₂ / N ₂ = 2 / 2.6 / 0.8 sccm Temperature: 750 ° C Film thickness: 0.5 nm Pressure: 6.6 × 10 ^-4 Pa Microwave power: 2.8 kW Substrate RF bias: -50 W [Conditions of the second film forming stage] Gas used: TiCl ₄ / H ₂ / N ₂ = 20/26/8 sccm Temperature: 750 ° C. Film thickness: 70 nm Pressure : 0.12 Pa Microwave power: 2.8 kW Substrate RF bias: −50 W As a result, the single crystal TiN layer 40 epitaxially grown is formed on the single crystal CoSi ₂ layer 20, and the single crystal TiN layer 40 A is formed in other regions. Is formed.

[Step-330] Thereafter, unnecessary single-crystal TiN layer 40A is removed by dry etching after resist patterning, leaving single-crystal TiN layer 40A necessary as a wiring portion. Dry etching conditions
For example, it can be as follows. Working gas: BCl ₃ / Cl ₂ = 60/90 sccm Power: 50 W Pressure: 2 Pa

[Step-340] Next, as in [Step-120] of the first embodiment, after the insulating layers 22A and 22B are formed on the entire surface, the openings 24 are formed in the insulating layers 22A and 22B. Implantation is performed to form a junction region, and activation annealing is performed at 1050 ° C. × 5 seconds.

[Step-350] Next, similarly to [Step-240] of the second embodiment, a 30-nm-thick underlayer 42 made of Ti is formed on the insulating layer 22 including the opening 24 by sputtering.
B, followed by a high-temperature aluminum sputtering method on the underlying layer 42 to a thickness of 500 n made of Al-1% Si.
m upper wiring layer 44 is formed. Thereafter, in the same manner as in [Step-150] of Example 1, resist patterning and dry etching are performed, and the upper wiring layer 44 and the underlying layer 4 are formed.
2 is a desired wiring pattern shape. Thus, a wiring structure whose schematic partial cross-sectional view is shown in FIG. 5 can be formed.

Although the present invention has been described based on the preferred embodiments, the present invention is not limited to these embodiments. The various conditions and numerical values described in the embodiments are merely examples, and can be changed as appropriate.

The insulating layers 22A and 22B are made of SiO ₂ and BP.
In addition to the combination of SG, PSG, BSG, AsS
A known insulating material such as G, PbSG, SbSG, or SiN, or a combination of these insulating materials can be used. As an aluminum-based wiring material, in addition to Al-1% Si, pure Al or Al-
Al alloys such as Si-Cu, Al-Cu, and Al-Ge can be given.

The method for forming the connection holes in the first embodiment can be replaced with the method for forming the connection holes described in the second embodiment. That is, in the first embodiment, after forming the single crystal TiN layer 26, the single crystal T
500 nm thickness of Al-1% Si on iN layer 26
By forming the upper wiring layer 32, the upper wiring layer and the connection hole can be formed.

The formation of various layers by the sputtering method can be performed by various sputtering devices such as a magnetron sputtering device, a DC sputtering device, an RF sputtering device, an ECR sputtering device, and a bias sputtering device for applying a substrate bias. In addition to ECRCVD equipment,
Thermal CVD equipment, plasma CVD equipment, helicon waves, IC
A CVD apparatus provided with a plasma generation source such as P (Inductively Coupled Plasma) can be used. In addition to removing the natural oxide film, in addition to the hydrogen plasma treatment,
An Ar sputter etching method in which ion bias such as C soft etching is reduced can be employed.

The wiring structures described in the first and second embodiments and the forming method thereof can be combined. That is, the single crystal TiN layer 4 is formed on the surface of the single crystal CoSi ₂ layer 20.
0, and the single crystal TiN is also formed at the bottom of the opening.
The layer 26 may be formed.

The wiring structure of the present invention can be applied to devices other than MOS transistors, such as bipolar transistors and CCDs.

[0073]

According to the present invention, since the single crystal CoSi ₂ layer is formed at the bottom of the opening, the sheet resistance of the lower conductor region can be reduced, and the lower conductor region and the wiring material in the connection hole can be reduced. Can be prevented by the single crystal TiN layer. Further, since the single crystal TiN layer is formed at the bottom of the connection hole, the barrier property is significantly improved.

In addition, since the natural oxide film and the like are removed and the single-crystal TiN layer is subsequently formed, the single-crystal CoSi
The interface between the _two layers and the single crystal TiN layer is kept clean at the atomic level. Therefore, it becomes an ideal ohmic junction, and the contact resistance can be reduced.

Further, the surface of the semiconductor substrate is made of single crystal CoSi _2.
Since the silicon layer is covered and the silicon surface is not exposed, it is possible to suppress the occurrence of crystal defects in the semiconductor substrate even if a hydrogen plasma treatment is performed as a pretreatment before the formation of the single crystal TiN layer. Also, formation of a SiN film by nitrogen plasma can be prevented.

Further, conventionally, the wiring portion is formed by patterning a polycrystalline TiN layer. However, in the wiring structure of the third embodiment, since the single crystal TiN layer 40A is used as the wiring portion, the wiring resistance is low. Can be achieved.

[Brief description of the drawings]

FIG. 1 is a schematic partial cross-sectional view of a semiconductor device, showing a wiring structure according to a first embodiment.

FIG. 2 is a schematic partial cross-sectional view of a semiconductor element for explaining each step of a wiring forming method of Example 1.

FIG. 3 is a schematic partial cross-sectional view of the semiconductor element for explaining each step of the wiring forming method of Example 1 following FIG. 2;

FIG. 4 is a schematic partial cross-sectional view of a semiconductor element for describing each step of a wiring forming method according to a second embodiment.

FIG. 5 is a schematic partial cross-sectional view of a semiconductor device, showing a wiring structure of Example 1.

FIG. 6 is a schematic partial cross-sectional view of a semiconductor device for explaining each step of a conventional wiring forming method.

FIG. 7 is a schematic partial cross-sectional view of the semiconductor element for explaining each step of the conventional wiring forming method, following FIG. 6;

[Explanation of symbols]

Reference Signs List 10 semiconductor substrate 12 element isolation region 14 gate electrode 16 gate sidewall 18 lower conductor region 20 single crystal CoSi ₂ layer 22A, 22B insulating layer 24 opening 26, 40 single crystal TiN layer 28 connection hole 30 barrier layer 32, 44 upper layer wiring Layer 40A Wiring section composed of single crystal TiN layer 42 Underlayer

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 29/78 H01L 29/78 301P 21/336

Claims (4)

[Claims] A lower conductor region formed on a semiconductor substrate;
A wiring structure in a semiconductor device, comprising: an upper wiring layer formed on an insulating layer covering the lower conductor region; and a connection hole for electrically connecting the lower conductor region to the upper wiring layer. At the bottom of the hole, a single crystal CoSi
A wiring structure in a semiconductor device, wherein _two layers and a single crystal TiN layer are formed. 2. The wiring structure according to claim 1, wherein the semiconductor substrate comprises a silicon semiconductor substrate. 3. The wiring structure according to claim 2, wherein the orientation of the silicon semiconductor substrate is (100). 4. An electrical connection between a source / drain region formed on a semiconductor substrate, an upper wiring layer formed on an insulating layer covering the source / drain region, and an electrical connection between the source / drain region and the upper wiring layer. A MOS transistor having a wiring structure consisting of a connection hole connected to the substrate and a single crystal CoSi
A MOS transistor comprising _two layers and a single-crystal TiN layer.