JPH0645614A - Manufacture of read-only semiconductor memory - Google Patents

Manufacture of read-only semiconductor memory

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Publication number
JPH0645614A
JPH0645614A JP4199326A JP19932692A JPH0645614A JP H0645614 A JPH0645614 A JP H0645614A JP 4199326 A JP4199326 A JP 4199326A JP 19932692 A JP19932692 A JP 19932692A JP H0645614 A JPH0645614 A JP H0645614A
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JP
Japan
Prior art keywords
insulating film
forming
formed
peripheral circuit
electrode
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4199326A
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Japanese (ja)
Inventor
Tatsuro Inoue
達朗 井上
Original Assignee
Nec Corp
日本電気株式会社
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Application filed by Nec Corp, 日本電気株式会社 filed Critical Nec Corp
Priority to JP4199326A priority Critical patent/JPH0645614A/en
Publication of JPH0645614A publication Critical patent/JPH0645614A/en
Application status is Pending legal-status Critical

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11517Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate
    • H01L27/11526Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11517Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate
    • H01L27/11526Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
    • H01L27/11531Simultaneous manufacturing of periphery and memory cells
    • H01L27/11546Simultaneous manufacturing of periphery and memory cells including different types of peripheral transistor

Abstract

PURPOSE:To form a gate insulating film wherein its thickness for a transistor in a high-withstand voltage peripheral circuit is different from that for a transistor in an ordinary peripheral circuit without increasing a resist process. CONSTITUTION:After an element isolation and insulating film 2 has been formed on a semiconductor substrate 1, a first insulating film 3 is formed. Then, after a first electrode 4 has been formed, the first insulating film 3 in an exposed peripheral circuit and in a high-withstand voltage circuit is etched. Then, after a second insulating film 5 has been formed, a second electrode 6 is formed. Then, the second insulating film 5 which is exposed in the peripheral circuit and in the highwithstand voltage circuit is etched. Then, after a third insulating film 7 has been formed, gate electrodes 4, 6 for a memory cell are patterned. Then, after the first exposed insulating film 3 has been etched, a side-face insulating film 9 is formed. Then, shallow source-drains 10 and deep source- drains 11 are formed. Then, after an interlayer insulating film 12 has been formed, a metal interconnection 14 is formed.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明はPROM(読出し専用半導体メモリ)の製造方法に関し、特に2層ゲート電極構造のPROMメモリセルの浮遊ゲート電極上の絶縁膜、 The present invention relates relates to a method of manufacturing a PROM (read-only semiconductor memory), in particular two-layer insulating film on the floating gate electrode of the PROM memory cell gate electrode structure,
高耐圧回路用トランジスタのゲート絶縁膜および周辺回路用トランジスタのゲート絶縁膜の製造方法に関するものである。 Manufacturing method of the gate insulating film of the gate insulating film and the peripheral circuit transistor of the high voltage circuit transistor relate.

【0002】 [0002]

【従来の技術】従来のPROMの製造方法として、公開特許公報 平3−9572の内容について、図3(a) BACKGROUND ART As a method for producing the conventional PROM, the contents of Patent Publication Rights 3-9572, FIGS. 3 (a)
〜(e)を参照して説明する。 It will be described with reference to - the (e).

【0003】はじめに図3(a)に示すように、半導体基板1の表面に選択酸化法により素子分離絶縁膜2を形成したのち、二酸化シリコンからなる第1の絶縁膜3を形成する。 [0003] First, as shown in FIG. 3 (a), after forming the device isolation insulating film 2 by the selective oxidation method on the surface of the semiconductor substrate 1, a first insulating film 3 made of silicon dioxide. つぎにメモリセル領域にポリシリコンからなる第1の電極4を形成したのち、通常の周辺回路領域および高耐圧の周辺回路領域の第1の絶縁膜(図示せず) Then after forming the first electrode 4 made of polysilicon in the memory cell region, a first insulating film of a conventional peripheral circuit region and a peripheral circuit region of the high voltage (not shown)
をエッチングする。 It is etched.

【0004】つぎに図3(b)に示すように、つぎに二酸化シリコンからなる第2の絶縁膜5を形成したのち、 [0004] Next, as shown in FIG. 3 (b), then after forming the second insulating film 5 made of silicon dioxide,
第1の電極4を覆ってポリシリコンからなる第2の電極6を形成する。 Covering the first electrode 4 to form a second electrode 6 made of polycrystalline silicon.

【0005】つぎに図3(c)に示すように、露出した周辺回路領域および高耐圧回路領域の第2の絶縁膜5をエッチングする。 [0005] Next, as shown in FIG. 3 (c), etching the second insulating film 5 of the exposed peripheral circuit region and the high-voltage circuit area.

【0006】つぎに図3(d)に示すように、二酸化シリコンからなる第3の絶縁膜7を形成したのち、周辺回路領域および高耐圧回路領域のゲート電極予定領域にポリシリコンからなる第3の電極8を形成する。 [0006] Next, as shown in FIG. 3 (d), third consisting of a third after forming the insulating film 7, the polysilicon gate electrode region where the peripheral circuit region and the high-voltage circuit area made of silicon dioxide forming the electrode 8.

【0007】つぎに図3(e)に示すように、レジスト(図示せず)をマスクとして第3の絶縁膜7、第2の電極6、第2の絶縁膜5、第1の電極4、第1の絶縁膜3 [0007] Next, as shown in FIG. 3 (e), the resist third insulating film 7 (not shown) as a mask, the second electrode 6, the second insulating film 5, the first electrode 4, the first insulating film 3
をエッチングしたのちレジストを除去する。 The removal of the resist After the etching. つぎに露出した第3の絶縁膜7をエッチングしたのち、側面絶縁膜9を形成する。 A third insulating film 7 exposed next After etching, to form the side surface insulating film 9. つぎに高耐圧回路領域に高耐圧ソース・ Next, the high-voltage source to the high-voltage circuit area,
ドレイン10を形成し、周辺回路領域およびメモリセル領域に通常のソース・ドレイン11を形成する。 The drain 10 is formed, to form a conventional drain 11 in the peripheral circuit region and the memory cell region. つぎにTEOSを用いたBPSGからなる層間絶縁膜12を形成したのち、コンタクト13を開口してからアルミニウム系合金からなる金属配線14を形成して素子部が完成する。 Then after forming an interlayer insulating film 12 made of BPSG with TEOS, element by forming a metal wiring 14 made of aluminum alloy from the opening contact 13 is completed.

【0008】この製造方法では図3(c)に示すように、メモリセル領域のみに第2の電極6が形成される。 [0008] As shown in FIG. 3 In this production method (c), the second electrode 6 is formed only in the memory cell region.
そのため図3(d)に示すように周辺回路領域および高耐圧回路領域の第2の絶縁膜5が同時にエッチングされ、同一の膜厚の第3の絶縁膜7が形成される。 Therefore the second insulating film 5 in the peripheral circuit region and the high voltage circuit area as shown in FIG. 3 (d) are simultaneously etched, the third insulating film 7 of the same thickness is formed.

【0009】 [0009]

【発明が解決しようとする課題】従来の製造方法においては、高耐圧系周辺回路および通常の周辺回路のゲート絶縁膜を同一工程で形成している。 In the conventional production method [SUMMARY OF THE INVENTION], to form a gate insulating film of the high-voltage system peripheral circuits and the normal of the peripheral circuit in the same step. そのため2つの絶縁膜の膜厚は同一となっている。 Thickness of for two insulating films are the same.

【0010】しかし、トランジスタの動作電流を大きくするため通常の周辺回路のゲート絶縁膜を薄くしたい。 [0010] However, like to thin the gate insulating film of a conventional peripheral circuit for increasing the operating current of the transistor.
一方、耐圧を高くするため高耐圧系周辺回路のゲート酸化膜の膜厚を最適の厚さにしたいという要請がある。 On the other hand, there is a demand for the film thickness of the gate oxide film of the high-voltage system peripheral circuit for increasing the breakdown voltage in the optimal thickness.

【0011】この2つのゲート絶縁膜は同一の厚さになるので、高耐圧系周辺回路のゲート絶縁膜の耐圧の制限によってゲート絶縁膜の膜厚の加減が決定される。 [0011] Since the two gate insulating film is the same thickness, degree of thickness of the gate insulating film is determined by the breakdown voltage of the limiting of the gate insulating film of the high-voltage system peripheral circuit. そこで、高耐圧係周辺回路のゲート絶縁膜の耐圧条件を満たす条件で、通常の周辺回路のゲート絶縁膜を形成すると、通常の周辺回路のトランジスタの動作電流が低下してしまうという問題があった。 Therefore, in a pressure satisfies the conditions of the gate insulating film of the high breakdown voltage engaging peripheral circuit, when a gate insulating film of a conventional peripheral circuit, the operating current of the transistors of the conventional peripheral circuit is disadvantageously lowered .

【0012】本発明の目的は、高耐圧系の周辺回路領域と通常の周辺回路領域のゲート絶縁膜の膜厚を最適化した読出し専用半導体メモリの製造方法を提供することにある。 An object of the present invention is to provide a peripheral circuit region and the normal manufacturing process of the read-only semiconductor memory with optimized thickness of the gate insulating film of the peripheral circuit region of the high withstand voltage.

【0013】 [0013]

【課題を解決するための手段】本発明の読出し専用半導体メモリの製造方法は、半導体基板の一主面上に素子分離絶縁膜を形成する工程と、全面に第1の絶縁膜を形成したのち、メモリセル形成予定領域の前記第1の絶縁膜上に第1の導電膜からなるゲート電極を形成する工程と、高耐圧回路形成予定領域および周辺回路形成予定領域の前記第1の絶縁膜をエッチングする工程と、全面に第2の絶縁膜を形成したのち、前記第2の絶縁膜上の前記高耐圧回路形成予定領域に第2の導電膜からなるゲート電極を形成する工程と、露出した前記第2の絶縁膜をエッチングする工程と、全面に第3の絶縁膜を形成する工程とを含むものである。 Method of manufacturing a read only semiconductor memory of the problem-solving means for the present invention includes the steps of forming an element isolation insulating film on one principal surface of the semiconductor substrate, after forming the first insulating film on the entire surface and forming a gate electrode made of the first conductive film on the first insulating film of the memory cell forming region, the first insulating film of the high voltage circuit forming region and the peripheral circuit formation region and etching, after forming a second insulating film on the entire surface, forming a gate electrode made of the second conductive film in the high voltage circuit forming area on the second insulating film, exposed etching the second insulating film, in which a step of forming a third insulating film on the entire surface.

【0014】 [0014]

【実施例】つぎに本発明の第1の実施例について、図1 A first embodiment of the Embodiment] Next the present invention. FIG. 1
(a)〜(d)を参照して説明する。 (A) it will be described with reference to - the (d).

【0015】はじめに図1(a)に示すように、P型シリコンなどからなる半導体基板1の表面に、選択酸化により二酸化シリコンなどからなる厚さ750nmの素子分離絶縁膜2を形成したのち、厚さ20nmの第1の絶縁膜3を形成する。 [0015] First, as shown in FIG. 1 (a), the surface of the semiconductor substrate 1 made of P-type silicon, after forming the device isolation insulating film 2 having a thickness of 750nm composed of silicon dioxide by selective oxidation, a thickness It is to form a first insulating film 3 of 20 nm. つぎにメモリセル領域のフローテイングゲートを形成するため、燐などのN型不純物をドープした厚さ200nmのポリシリコンからなる第1の電極4を形成する。 Next, in order to form a floating gate of a memory cell region to form a first electrode 4 made of polysilicon having a thickness of 200nm doped with N-type impurities such as phosphorus. つぎに露出している通常の周辺回路領域および高耐圧系の周辺回路領域の第1の絶縁膜3(図示せず)をエッチングする。 Then the first insulating film of a conventional peripheral circuit region and a peripheral circuit region of the high withstand voltage that is exposed 3 (not shown) is etched.

【0016】つぎに図1(b)に示すように、1150 [0016] Then, as shown in FIG. 1 (b), 1150
℃のドライ酸素雰囲気により二酸化シリコンからなる厚さ25nmの第2の絶縁膜5を形成する。 By dry oxygen atmosphere at ℃ forming a second insulating film 5 having a thickness of 25nm made of silicon dioxide. つぎに高耐圧回路のゲート電極およびメモリセルのコントロールゲートとなる、燐などのN型不純物をドープした厚さ300 Then the control gate of the gate electrode and the memory cell of the high voltage circuit, thickness 300 doped with N-type impurities such as phosphorus
nmのポリシリコンからなる第2の電極6を形成する。 Forming a second electrode 6 made of nm of polysilicon.

【0017】つぎに図1(c)に示すように、周辺回路領域および高耐圧回路領域に露出している第2の絶縁膜5をエッチングする。 [0017] Then, as shown in FIG. 1 (c), etching the second insulating film 5 exposed in the peripheral circuit region and the high voltage circuit area. つぎに750℃のスチーム雰囲気により二酸化シリコンからなる厚さ15nmの第3の絶縁膜7を形成する。 Then by steam atmosphere at 750 ° C. to form a third insulating film 7 having a thickness of 15nm made of silicon dioxide. つぎに周辺回路領域のゲート電極となる厚さ300nmのN型ポリシリコンからなる第3の電極8を形成する。 Then to form the third electrode 8 consisting of N-type polysilicon having a thickness of 300nm as a gate electrode of the peripheral circuit region.

【0018】つぎに図1(d)に示すように、レジスト(図示せず)をマスクとして第3の酸化膜7、第2の電極6、第2の絶縁膜5、第1の電極4をエッチングしたのち、レジストを除去する。 [0018] Next, as shown in FIG. 1 (d), a resist (not shown) as a mask the third oxide film 7, the second electrode 6, the second insulating film 5, the first electrode 4 After etching, the resist is removed. つぎに露出した第1の絶縁膜3をエッチングする。 A first insulating film 3 exposed then are etched. つぎに900℃のドライO 2雰囲気により二酸化シリコンからなる厚さ20nmの側面絶縁膜9を形成したのち、高耐圧回路のソース・ドレイン10を形成してから周辺回路およびメモリセルのソース・ドレイン11を形成する。 Then after forming the side insulating film 9 having a thickness of 20nm made of silicon dioxide by a dry O 2 atmosphere at 900 ° C., the source-drain 11 of the peripheral circuit and the memory cell after forming the source and drain 10 of the high voltage circuit to form. つぎに層間絶縁膜12を形成したのち、コンタクト13を開口してからアルミニウム合金からなる厚さ1μmの金属配線14を形成して素子部が完成する。 Then after forming an interlayer insulating film 12, the element portion and forming a metal interconnect 14 having a thickness of 1μm made of an aluminum alloy from the opening contact 13 is completed.

【0019】本実施例では図1(b)に示すように、第2の電極6が高耐圧回路領域のゲート部にも形成されるので、周辺回路領域の第2の絶縁膜5をエッチングするときにも、高耐圧回路領域のゲート部の第2の絶縁膜5 As shown in FIG. 1 (b) in the present embodiment, since the second electrode 6 is also formed on the gate part of a high voltage circuit region, etching the second insulating film 5 in the peripheral circuit region the second insulating film 5 also, the gate part of a high voltage circuit region when
は除去されない。 It is not removed. こうして高耐圧回路領域と周辺回路領域とに、互に異なった膜厚のゲート絶縁膜を形成することができる。 Thus in a high-voltage circuit area and the peripheral circuit region, it is possible to form the gate insulating film of each other different thickness.

【0020】つぎに本発明の第2の実施例について、図2(a)〜(d)を参照して説明する。 [0020] Next, a second embodiment of the present invention will be described with reference to FIG. 2 (a) ~ (d).

【0021】はじめに図2(a)に示すように、半導体基板1の表面に素子分離絶縁膜2を形成したのち第1の絶縁膜3を形成する。 [0021] First, as shown in FIG. 2 (a), forming a first insulating film 3 after forming the element isolation insulating film 2 on the surface of the semiconductor substrate 1. つぎに第1の電極4を形成したのち、露出している周辺回路領域および高耐回路領域の第1の絶縁膜3(図示せず)をエッチングする。 Then after forming the first electrode 4, etching the first insulating film 3 in the peripheral circuit region and the high 耐回 path region is exposed (not shown). つぎに第2の絶縁膜5を形成する。 Then the second insulating film 5. ここまでは第1の実施例と同様である。 Up to this point is the same as in the first embodiment.

【0022】つぎに燐などのN型不純物をドープした厚さ100nmのポリシリコンからなる第2の電極6を形成する。 [0022] Next, a second electrode 6 having a thickness of 100nm polysilicon doped with N-type impurities such as phosphorus. つぎにスパッタ法により厚さ200nmのモリブデンシリサイドまたはタングステンシリサイドからなる第4の電極15を形成する。 Then to form the fourth electrode 15 made of molybdenum silicide or tungsten silicide having a thickness of 200nm by sputtering. つぎに厚さ30nmの第1のシリコン膜16を堆積したのちパターニングして、 Then the first silicon film 16 having a thickness of 30nm by patterning after depositing,
高耐圧回路領域およびメモリセル領域のゲート電極部を形成する。 Forming a gate electrode portion of the high-voltage circuit area and the memory cell region.

【0023】つぎに図2(b)に示すように、露出している周辺回路領域および高耐圧回路領域のゲート部以外の第2の絶縁膜5をエッチングする。 [0023] Next, as shown in FIG. 2 (b), etching the second insulating film 5 other than the gate of the peripheral circuit region and the high-voltage circuit area are exposed.

【0024】つぎに図2(c)に示すように、750℃ [0024] Next, as shown in FIG. 2 (c), 750 ℃
のスチーム雰囲気により二酸化シリコン膜からなる厚さ15nmの第3の絶縁膜7を形成する。 The steam atmosphere to form a third insulating film 7 having a thickness of 15nm made of silicon dioxide film.

【0025】つぎに図2(d)に示すように、周辺回路領域にN型不純物をドープした厚さ100nmのポリシリコンからなる第3の電極8を形成したのち、モリブデンシリサイドまたはタングステンシリサイドからなる厚さ200nmの第5の電極17を形成する。 [0025] Next, as shown in FIG. 2 (d), after forming the third electrode 8 of polysilicon having a thickness of 100nm doped with N-type impurities in the peripheral circuit region, consisting of molybdenum silicide or tungsten silicide forming a fifth electrode 17 having a thickness of 200 nm. つぎに厚さ30nmの第2のシリコン膜18を形成したのち、高圧回路領域および周辺回路領域のゲート部をパターニングする。 Then after forming a second silicon film 18 having a thickness of 30 nm, to pattern the gate of the high voltage circuit area and the peripheral circuit region.

【0026】つぎに側面絶縁膜9を形成したのち、高耐圧回路のソース・ドレイン10を形成してから周辺回路およびメモリセルのソース・ドレイン11を形成する。 [0026] Then after forming the side insulating film 9, to form the source and drain 11 of the peripheral circuit and the memory cell after forming the source and drain 10 of the high voltage circuit.
つぎに層間絶縁膜12を堆積したのちコンタクト13を開口し、金属配線14を形成して素子部が完成する。 Then forming a contact 13 after the deposition of the interlayer insulating film 12, the element section is completed by forming a metal wire 14.

【0027】本実施例では図2(b)に示すように周辺回路領域および高耐圧回路領域のゲート部を除いて露出した第2の絶縁膜5をエッチングするときのマスクとなるゲート電極としてポリサイドを用いた。 The polycide the second insulating film 5 exposed except for a gate portion of the peripheral circuit region and the high voltage circuit area as in the present embodiment shown in FIG. 2 (b) as the gate electrode as a mask in etching It was used. ポリサイドにより高耐圧回路とメモリセルのゲート電極の抵抗を低減することができ、高速化が可能になった。 It is possible to reduce the resistance of the gate electrode of the high voltage circuit and the memory cell by polycide has allowed speed.

【0028】 [0028]

【発明の効果】高耐圧系周辺回路領域と通常の周辺回路領域とのゲート絶縁膜を別々の工程で形成したので、従来のように高耐圧系周辺回路領域のゲート絶縁膜の耐圧によって通常の周辺回路領域のゲート絶縁膜の厚さが制限されることはなくなった。 [Effect of the Invention] Since the gate insulating film of a high-voltage system peripheral circuit region and the normal of the peripheral circuit region are formed in separate steps, normal by the breakdown voltage of the gate insulating film of a conventional high-voltage system peripheral circuit region as no longer the thickness of the gate insulating film of the peripheral circuit region is limited.

【0029】高耐圧系周辺回路領域のゲート絶縁膜は耐圧を満たす厚さに設定し、通常の周辺回路のゲート絶縁膜も最適の厚さに形成することができる。 The gate insulating film of the high-voltage system peripheral circuit region is set to a thickness satisfying the breakdown voltage, the gate insulating film of a conventional peripheral circuit can also be formed to a thickness of optimum. 通常の周辺回路の動作速度が向上して高性能化が可能になった。 The operating speed of a normal peripheral circuit has been made available for high performance improved.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の第1の実施例を工程順に示す断面図である。 1 is a cross-sectional views sequentially showing the steps of a first embodiment of the present invention.

【図2】本発明の第2の実施例を工程順に示す断面図である。 2 is a cross-sectional views sequentially showing the steps of a second embodiment of the present invention.

【図3】従来のPROMの製造方法を示す断面図である。 3 is a cross-sectional view showing a manufacturing method of a conventional PROM.

【符号の説明】 1 半導体基板 2 素子分離絶縁膜 3 第1の絶縁膜 4 第1の電極 5 第2の絶縁膜 6 第2の電極 7 第3の絶縁膜 8 第3の電極 9 側面絶縁膜 10 高耐圧ソース・ドレイン 11 通常のソース・ドレイン 12 層間絶縁膜 13 コンタクト 14 金属配線 15 第4の電極 16 第1のシリコン膜 17 第5の電極 18 第2のシリコン膜 [Reference Numerals] 1 semiconductor substrate 2 the element isolation insulating film 3 first insulating film 4 first electrode 5 second insulating film 6 and the second electrode 7 third insulating film 8 the third electrode 9 side insulating film 10 high-voltage source and the drain 11 normal drain 12 interlayer insulating film 13 contacts 14 metal wires 15 fourth electrode 16 first silicon film 17 fifth electrode 18 and the second silicon film

Claims (2)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 半導体基板の一主面上に素子分離絶縁膜を形成する工程と、全面に第1の絶縁膜を形成したのち、メモリセル形成予定領域の前記第1の絶縁膜上に第1の導電膜からなるゲート電極を形成する工程と、高耐圧回路形成予定領域および周辺回路形成予定領域の前記第1の絶縁膜をエッチングする工程と、全面に第2の絶縁膜を形成したのち、前記第2の絶縁膜上の前記高耐圧回路形成予定領域に第2の導電膜からなるゲート電極を形成する工程と、露出した前記第2の絶縁膜をエッチングする工程と、全面に第3の絶縁膜を形成する工程とを含む読出し専用半導体メモリの製造方法。 And 1. A process for forming an element isolation insulating film on one principal surface of the semiconductor substrate, after forming the first insulating film on the entire surface, the on the first insulating film of the memory cell formation region forming a gate electrode consisting of a conductive film, etching the first insulating film of the high voltage circuit forming region and the peripheral circuit formation region, after forming the second insulating film on the entire surface and forming the high voltage circuit gate electrode made of the second conductive film forming area on the second insulating film, and etching the exposed second insulating film, the third on the entire surface the method of manufacturing a read only semiconductor memory and a step of forming an insulating film.
  2. 【請求項2】 第2の絶縁膜の膜厚よりも第3の絶縁膜の膜厚の方が薄くなっている請求項1記載の読出し専用半導体メモリの製造方法。 2. A second insulating film thickness third manufacturing method of the read-only semiconductor memory according to claim 1, wherein it is thinner in the thickness of the insulating film than the.
JP4199326A 1992-07-27 1992-07-27 Manufacture of read-only semiconductor memory Pending JPH0645614A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4199326A JPH0645614A (en) 1992-07-27 1992-07-27 Manufacture of read-only semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4199326A JPH0645614A (en) 1992-07-27 1992-07-27 Manufacture of read-only semiconductor memory

Publications (1)

Publication Number Publication Date
JPH0645614A true JPH0645614A (en) 1994-02-18

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JP4199326A Pending JPH0645614A (en) 1992-07-27 1992-07-27 Manufacture of read-only semiconductor memory

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JP (1) JPH0645614A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0854509A1 (en) * 1997-01-17 1998-07-22 Programmable Microelectronics Corporation Fabrication method for non-volatile memory with high-voltage and logic components
EP1104022A1 (en) * 1999-11-29 2001-05-30 STMicroelectronics S.r.l. Process for the fabrication of an integrated circuit comprising low and high voltage MOS transistors and EPROM cells
US6706593B1 (en) 1996-08-29 2004-03-16 Nec Electroincs Corporation Method for manufacturing a nonvolatile semiconductor storage device
US6949790B2 (en) 2001-09-19 2005-09-27 Ricoh Company, Ltd. Semiconductor device and its manufacturing method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6706593B1 (en) 1996-08-29 2004-03-16 Nec Electroincs Corporation Method for manufacturing a nonvolatile semiconductor storage device
EP0854509A1 (en) * 1997-01-17 1998-07-22 Programmable Microelectronics Corporation Fabrication method for non-volatile memory with high-voltage and logic components
EP1104022A1 (en) * 1999-11-29 2001-05-30 STMicroelectronics S.r.l. Process for the fabrication of an integrated circuit comprising low and high voltage MOS transistors and EPROM cells
US6319780B2 (en) 1999-11-29 2001-11-20 Stmicroelectronics S.R.L. Process for the fabrication of an integrated circuit comprising MOS transistors for low voltage, EPROM cells and MOS transistors for high voltage
US6949790B2 (en) 2001-09-19 2005-09-27 Ricoh Company, Ltd. Semiconductor device and its manufacturing method
US7314797B2 (en) 2001-09-19 2008-01-01 Ricoh Company, Ltd. Semiconductor device and its manufacturing method

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