JPH0645614A - Manufacture of read-only semiconductor memory - Google Patents
Manufacture of read-only semiconductor memoryInfo
- Publication number
- JPH0645614A JPH0645614A JP4199326A JP19932692A JPH0645614A JP H0645614 A JPH0645614 A JP H0645614A JP 4199326 A JP4199326 A JP 4199326A JP 19932692 A JP19932692 A JP 19932692A JP H0645614 A JPH0645614 A JP H0645614A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- peripheral circuit
- electrode
- forming
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 230000002093 peripheral effect Effects 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000015556 catabolic process Effects 0.000 claims description 26
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 2
- 239000011229 interlayer Substances 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 235000012239 silicon dioxide Nutrition 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 2
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はＰＲＯＭ（読出し専用半
導体メモリ）の製造方法に関し、特に２層ゲート電極構
造のＰＲＯＭメモリセルの浮遊ゲート電極上の絶縁膜、
高耐圧回路用トランジスタのゲート絶縁膜および周辺回
路用トランジスタのゲート絶縁膜の製造方法に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a PROM (read-only semiconductor memory), and more particularly to an insulating film on a floating gate electrode of a PROM memory cell having a two-layer gate electrode structure,
The present invention relates to a method for manufacturing a gate insulating film of a transistor for high voltage circuit and a gate insulating film of a transistor for peripheral circuit.
【０００２】[0002]
【従来の技術】従来のＰＲＯＭの製造方法として、公開
特許公報 平３−９５７２の内容について、図３（ａ）
〜（ｅ）を参照して説明する。2. Description of the Related Art As a conventional PROM manufacturing method, the contents of Japanese Patent Laid-Open No. 3-9572 are disclosed in FIG.
This will be described with reference to (e).
【０００３】はじめに図３（ａ）に示すように、半導体
基板１の表面に選択酸化法により素子分離絶縁膜２を形
成したのち、二酸化シリコンからなる第１の絶縁膜３を
形成する。つぎにメモリセル領域にポリシリコンからな
る第１の電極４を形成したのち、通常の周辺回路領域お
よび高耐圧の周辺回路領域の第１の絶縁膜（図示せず）
をエッチングする。First, as shown in FIG. 3A, an element isolation insulating film 2 is formed on the surface of a semiconductor substrate 1 by a selective oxidation method, and then a first insulating film 3 made of silicon dioxide is formed. Next, after forming the first electrode 4 made of polysilicon in the memory cell region, the first insulating film (not shown) in the normal peripheral circuit region and the high-voltage peripheral circuit region is formed.
To etch.
【０００４】つぎに図３（ｂ）に示すように、つぎに二
酸化シリコンからなる第２の絶縁膜５を形成したのち、
第１の電極４を覆ってポリシリコンからなる第２の電極
６を形成する。Next, as shown in FIG. 3B, a second insulating film 5 made of silicon dioxide is formed next, and then,
A second electrode 6 made of polysilicon is formed so as to cover the first electrode 4.
【０００５】つぎに図３（ｃ）に示すように、露出した
周辺回路領域および高耐圧回路領域の第２の絶縁膜５を
エッチングする。Next, as shown in FIG. 3C, the second insulating film 5 in the exposed peripheral circuit region and high breakdown voltage circuit region is etched.
【０００６】つぎに図３（ｄ）に示すように、二酸化シ
リコンからなる第３の絶縁膜７を形成したのち、周辺回
路領域および高耐圧回路領域のゲート電極予定領域にポ
リシリコンからなる第３の電極８を形成する。Next, as shown in FIG. 3D, after forming a third insulating film 7 made of silicon dioxide, a third insulating film 7 made of polysilicon is formed in the gate electrode planned region of the peripheral circuit region and the high breakdown voltage circuit region. The electrode 8 is formed.
【０００７】つぎに図３（ｅ）に示すように、レジスト
（図示せず）をマスクとして第３の絶縁膜７、第２の電
極６、第２の絶縁膜５、第１の電極４、第１の絶縁膜３
をエッチングしたのちレジストを除去する。つぎに露出
した第３の絶縁膜７をエッチングしたのち、側面絶縁膜
９を形成する。つぎに高耐圧回路領域に高耐圧ソース・
ドレイン１０を形成し、周辺回路領域およびメモリセル
領域に通常のソース・ドレイン１１を形成する。つぎに
ＴＥＯＳを用いたＢＰＳＧからなる層間絶縁膜１２を形
成したのち、コンタクト１３を開口してからアルミニウ
ム系合金からなる金属配線１４を形成して素子部が完成
する。Next, as shown in FIG. 3 (e), a third insulating film 7, a second electrode 6, a second insulating film 5, a first electrode 4, a resist (not shown) is used as a mask. First insulating film 3
After etching, the resist is removed. Next, the exposed third insulating film 7 is etched, and then the side surface insulating film 9 is formed. Next, in the high voltage circuit area,
The drain 10 is formed, and the normal source / drain 11 is formed in the peripheral circuit region and the memory cell region. Next, after forming the interlayer insulating film 12 made of BPSG using TEOS, the contact 13 is opened and then the metal wiring 14 made of an aluminum alloy is formed to complete the element portion.
【０００８】この製造方法では図３（ｃ）に示すよう
に、メモリセル領域のみに第２の電極６が形成される。
そのため図３（ｄ）に示すように周辺回路領域および高
耐圧回路領域の第２の絶縁膜５が同時にエッチングさ
れ、同一の膜厚の第３の絶縁膜７が形成される。In this manufacturing method, as shown in FIG. 3C, the second electrode 6 is formed only in the memory cell region.
Therefore, as shown in FIG. 3D, the second insulating film 5 in the peripheral circuit region and the high breakdown voltage circuit region is simultaneously etched, and the third insulating film 7 having the same film thickness is formed.
【０００９】[0009]
【発明が解決しようとする課題】従来の製造方法におい
ては、高耐圧系周辺回路および通常の周辺回路のゲート
絶縁膜を同一工程で形成している。そのため２つの絶縁
膜の膜厚は同一となっている。In the conventional manufacturing method, the gate insulating films of the high breakdown voltage peripheral circuit and the normal peripheral circuit are formed in the same step. Therefore, the two insulating films have the same film thickness.
【００１０】しかし、トランジスタの動作電流を大きく
するため通常の周辺回路のゲート絶縁膜を薄くしたい。
一方、耐圧を高くするため高耐圧系周辺回路のゲート酸
化膜の膜厚を最適の厚さにしたいという要請がある。However, in order to increase the operating current of the transistor, it is desired to thin the gate insulating film of the normal peripheral circuit.
On the other hand, in order to increase the breakdown voltage, there is a demand to make the thickness of the gate oxide film of the high breakdown voltage peripheral circuit optimum.
【００１１】この２つのゲート絶縁膜は同一の厚さにな
るので、高耐圧系周辺回路のゲート絶縁膜の耐圧の制限
によってゲート絶縁膜の膜厚の加減が決定される。そこ
で、高耐圧係周辺回路のゲート絶縁膜の耐圧条件を満た
す条件で、通常の周辺回路のゲート絶縁膜を形成する
と、通常の周辺回路のトランジスタの動作電流が低下し
てしまうという問題があった。Since these two gate insulating films have the same thickness, the thickness of the gate insulating film can be adjusted depending on the limitation of the breakdown voltage of the gate insulating film of the high breakdown voltage peripheral circuit. Therefore, if the gate insulating film of the normal peripheral circuit is formed under the condition that the breakdown voltage of the gate insulating film of the high breakdown voltage related circuit is satisfied, there is a problem that the operating current of the transistor of the normal peripheral circuit decreases. .
【００１２】本発明の目的は、高耐圧系の周辺回路領域
と通常の周辺回路領域のゲート絶縁膜の膜厚を最適化し
た読出し専用半導体メモリの製造方法を提供することに
ある。An object of the present invention is to provide a method of manufacturing a read-only semiconductor memory in which the film thickness of the gate insulating film in the high breakdown voltage peripheral circuit region and the normal peripheral circuit region is optimized.
【００１３】[0013]
【課題を解決するための手段】本発明の読出し専用半導
体メモリの製造方法は、半導体基板の一主面上に素子分
離絶縁膜を形成する工程と、全面に第１の絶縁膜を形成
したのち、メモリセル形成予定領域の前記第１の絶縁膜
上に第１の導電膜からなるゲート電極を形成する工程
と、高耐圧回路形成予定領域および周辺回路形成予定領
域の前記第１の絶縁膜をエッチングする工程と、全面に
第２の絶縁膜を形成したのち、前記第２の絶縁膜上の前
記高耐圧回路形成予定領域に第２の導電膜からなるゲー
ト電極を形成する工程と、露出した前記第２の絶縁膜を
エッチングする工程と、全面に第３の絶縁膜を形成する
工程とを含むものである。According to a method of manufacturing a read-only semiconductor memory of the present invention, a step of forming an element isolation insulating film on one main surface of a semiconductor substrate and a step of forming a first insulating film on the entire surface. A step of forming a gate electrode made of a first conductive film on the first insulating film in the memory cell formation planned region, and a step of forming the first insulating film in the high breakdown voltage circuit formation planned region and the peripheral circuit formation planned region An etching step, a step of forming a second insulating film on the entire surface, and a step of forming a gate electrode made of a second conductive film in the high breakdown voltage circuit formation-scheduled region on the second insulating film; It includes a step of etching the second insulating film and a step of forming a third insulating film on the entire surface.
【００１４】[0014]
【実施例】つぎに本発明の第１の実施例について、図１
（ａ）〜（ｄ）を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to FIG.
This will be described with reference to (a) to (d).
【００１５】はじめに図１（ａ）に示すように、Ｐ型シ
リコンなどからなる半導体基板１の表面に、選択酸化に
より二酸化シリコンなどからなる厚さ７５０ｎｍの素子
分離絶縁膜２を形成したのち、厚さ２０ｎｍの第１の絶
縁膜３を形成する。つぎにメモリセル領域のフローテイ
ングゲートを形成するため、燐などのＮ型不純物をドー
プした厚さ２００ｎｍのポリシリコンからなる第１の電
極４を形成する。つぎに露出している通常の周辺回路領
域および高耐圧系の周辺回路領域の第１の絶縁膜３（図
示せず）をエッチングする。First, as shown in FIG. 1A, a device isolation insulating film 2 of 750 nm thick made of silicon dioxide is formed on the surface of a semiconductor substrate 1 made of P-type silicon by selective oxidation, and then the thickness is increased. A first insulating film 3 having a thickness of 20 nm is formed. Next, in order to form a floating gate in the memory cell region, a first electrode 4 made of polysilicon having a thickness of 200 nm doped with N-type impurities such as phosphorus is formed. Next, the first insulating film 3 (not shown) in the exposed normal peripheral circuit area and high-voltage system peripheral circuit area is etched.
【００１６】つぎに図１（ｂ）に示すように、１１５０
℃のドライ酸素雰囲気により二酸化シリコンからなる厚
さ２５ｎｍの第２の絶縁膜５を形成する。つぎに高耐圧
回路のゲート電極およびメモリセルのコントロールゲー
トとなる、燐などのＮ型不純物をドープした厚さ３００
ｎｍのポリシリコンからなる第２の電極６を形成する。Next, as shown in FIG.
A second insulating film 5 made of silicon dioxide and having a thickness of 25 nm is formed in a dry oxygen atmosphere at 0 ° C. Next, a thickness of 300, which is doped with N-type impurities such as phosphorus, is used as a gate electrode of a high voltage circuit and a control gate of a memory cell.
A second electrode 6 made of polysilicon of nm is formed.
【００１７】つぎに図１（ｃ）に示すように、周辺回路
領域および高耐圧回路領域に露出している第２の絶縁膜
５をエッチングする。つぎに７５０℃のスチーム雰囲気
により二酸化シリコンからなる厚さ１５ｎｍの第３の絶
縁膜７を形成する。つぎに周辺回路領域のゲート電極と
なる厚さ３００ｎｍのＮ型ポリシリコンからなる第３の
電極８を形成する。Next, as shown in FIG. 1C, the second insulating film 5 exposed in the peripheral circuit region and the high breakdown voltage circuit region is etched. Next, a 15 nm-thick third insulating film 7 made of silicon dioxide is formed in a steam atmosphere at 750 ° C. Next, a third electrode 8 made of N-type polysilicon and having a thickness of 300 nm, which will be a gate electrode in the peripheral circuit region, is formed.
【００１８】つぎに図１（ｄ）に示すように、レジスト
（図示せず）をマスクとして第３の酸化膜７、第２の電
極６、第２の絶縁膜５、第１の電極４をエッチングした
のち、レジストを除去する。つぎに露出した第１の絶縁
膜３をエッチングする。つぎに９００℃のドライＯ2 雰
囲気により二酸化シリコンからなる厚さ２０ｎｍの側面
絶縁膜９を形成したのち、高耐圧回路のソース・ドレイ
ン１０を形成してから周辺回路およびメモリセルのソー
ス・ドレイン１１を形成する。つぎに層間絶縁膜１２を
形成したのち、コンタクト１３を開口してからアルミニ
ウム合金からなる厚さ１μｍの金属配線１４を形成して
素子部が完成する。Next, as shown in FIG. 1D, the third oxide film 7, the second electrode 6, the second insulating film 5, and the first electrode 4 are formed using a resist (not shown) as a mask. After etching, the resist is removed. Next, the exposed first insulating film 3 is etched. Then, a side insulating film 9 made of silicon dioxide and having a thickness of 20 nm is formed in a dry O 2 atmosphere at 900 ° C., and then a source / drain 10 of a high breakdown voltage circuit is formed and then a source / drain 11 of a peripheral circuit and a memory cell. To form. Next, after forming the interlayer insulating film 12, the contact 13 is opened and then the metal wiring 14 made of an aluminum alloy and having a thickness of 1 μm is formed to complete the element portion.
【００１９】本実施例では図１（ｂ）に示すように、第
２の電極６が高耐圧回路領域のゲート部にも形成される
ので、周辺回路領域の第２の絶縁膜５をエッチングする
ときにも、高耐圧回路領域のゲート部の第２の絶縁膜５
は除去されない。こうして高耐圧回路領域と周辺回路領
域とに、互に異なった膜厚のゲート絶縁膜を形成するこ
とができる。In this embodiment, as shown in FIG. 1B, since the second electrode 6 is also formed in the gate portion of the high breakdown voltage circuit region, the second insulating film 5 in the peripheral circuit region is etched. Sometimes, the second insulating film 5 in the gate portion of the high breakdown voltage circuit region is also included.
Is not removed. Thus, gate insulating films having different film thicknesses can be formed in the high breakdown voltage circuit region and the peripheral circuit region.
【００２０】つぎに本発明の第２の実施例について、図
２（ａ）〜（ｄ）を参照して説明する。Next, a second embodiment of the present invention will be described with reference to FIGS.
【００２１】はじめに図２（ａ）に示すように、半導体
基板１の表面に素子分離絶縁膜２を形成したのち第１の
絶縁膜３を形成する。つぎに第１の電極４を形成したの
ち、露出している周辺回路領域および高耐回路領域の第
１の絶縁膜３（図示せず）をエッチングする。つぎに第
２の絶縁膜５を形成する。ここまでは第１の実施例と同
様である。First, as shown in FIG. 2A, the element isolation insulating film 2 is formed on the surface of the semiconductor substrate 1, and then the first insulating film 3 is formed. Next, after the first electrode 4 is formed, the first insulating film 3 (not shown) in the exposed peripheral circuit region and exposed high circuit region is etched. Next, the second insulating film 5 is formed. The process up to this point is the same as in the first embodiment.
【００２２】つぎに燐などのＮ型不純物をドープした厚
さ１００ｎｍのポリシリコンからなる第２の電極６を形
成する。つぎにスパッタ法により厚さ２００ｎｍのモリ
ブデンシリサイドまたはタングステンシリサイドからな
る第４の電極１５を形成する。つぎに厚さ３０ｎｍの第
１のシリコン膜１６を堆積したのちパターニングして、
高耐圧回路領域およびメモリセル領域のゲート電極部を
形成する。Next, a second electrode 6 made of polysilicon having a thickness of 100 nm doped with N-type impurities such as phosphorus is formed. Next, the fourth electrode 15 made of molybdenum silicide or tungsten silicide having a thickness of 200 nm is formed by the sputtering method. Then, a first silicon film 16 having a thickness of 30 nm is deposited and then patterned,
A gate electrode portion in the high breakdown voltage circuit region and the memory cell region is formed.
【００２３】つぎに図２（ｂ）に示すように、露出して
いる周辺回路領域および高耐圧回路領域のゲート部以外
の第２の絶縁膜５をエッチングする。Next, as shown in FIG. 2B, the second insulating film 5 other than the gate portion of the exposed peripheral circuit region and high breakdown voltage circuit region is etched.
【００２４】つぎに図２（ｃ）に示すように、７５０℃
のスチーム雰囲気により二酸化シリコン膜からなる厚さ
１５ｎｍの第３の絶縁膜７を形成する。Next, as shown in FIG. 2 (c), 750 ° C.
The third insulating film 7 made of a silicon dioxide film and having a thickness of 15 nm is formed by the steam atmosphere.
【００２５】つぎに図２（ｄ）に示すように、周辺回路
領域にＮ型不純物をドープした厚さ１００ｎｍのポリシ
リコンからなる第３の電極８を形成したのち、モリブデ
ンシリサイドまたはタングステンシリサイドからなる厚
さ２００ｎｍの第５の電極１７を形成する。つぎに厚さ
３０ｎｍの第２のシリコン膜１８を形成したのち、高圧
回路領域および周辺回路領域のゲート部をパターニング
する。Next, as shown in FIG. 2D, a third electrode 8 made of polysilicon with a thickness of 100 nm doped with N-type impurities is formed in the peripheral circuit region, and then molybdenum silicide or tungsten silicide is used. A fifth electrode 17 having a thickness of 200 nm is formed. Next, after forming the second silicon film 18 having a thickness of 30 nm, the gate portions of the high voltage circuit region and the peripheral circuit region are patterned.
【００２６】つぎに側面絶縁膜９を形成したのち、高耐
圧回路のソース・ドレイン１０を形成してから周辺回路
およびメモリセルのソース・ドレイン１１を形成する。
つぎに層間絶縁膜１２を堆積したのちコンタクト１３を
開口し、金属配線１４を形成して素子部が完成する。Next, after forming the side surface insulating film 9, the source / drain 10 of the high breakdown voltage circuit is formed and then the source / drain 11 of the peripheral circuit and the memory cell are formed.
Next, after depositing the interlayer insulating film 12, the contact 13 is opened and the metal wiring 14 is formed to complete the element portion.
【００２７】本実施例では図２（ｂ）に示すように周辺
回路領域および高耐圧回路領域のゲート部を除いて露出
した第２の絶縁膜５をエッチングするときのマスクとな
るゲート電極としてポリサイドを用いた。ポリサイドに
より高耐圧回路とメモリセルのゲート電極の抵抗を低減
することができ、高速化が可能になった。In the present embodiment, as shown in FIG. 2B, polycide is used as a gate electrode which serves as a mask when the second insulating film 5 exposed except for the gate portion in the peripheral circuit region and the high breakdown voltage circuit region is etched. Was used. By using polycide, the resistance of the high voltage circuit and the gate electrode of the memory cell can be reduced, and the speed can be increased.
【００２８】[0028]
【発明の効果】高耐圧系周辺回路領域と通常の周辺回路
領域とのゲート絶縁膜を別々の工程で形成したので、従
来のように高耐圧系周辺回路領域のゲート絶縁膜の耐圧
によって通常の周辺回路領域のゲート絶縁膜の厚さが制
限されることはなくなった。Since the gate insulating films of the high withstand voltage peripheral circuit region and the normal peripheral circuit region are formed in separate steps, the conventional gate insulating film with the withstand voltage of the high withstand voltage peripheral circuit region has a normal withstand voltage. The thickness of the gate insulating film in the peripheral circuit area is no longer limited.
【００２９】高耐圧系周辺回路領域のゲート絶縁膜は耐
圧を満たす厚さに設定し、通常の周辺回路のゲート絶縁
膜も最適の厚さに形成することができる。通常の周辺回
路の動作速度が向上して高性能化が可能になった。The gate insulating film in the high breakdown voltage peripheral circuit region is set to have a thickness that satisfies the breakdown voltage, and the gate insulating film for a normal peripheral circuit can also be formed to have an optimum thickness. The operating speed of normal peripheral circuits has been improved and higher performance has become possible.
【図１】本発明の第１の実施例を工程順に示す断面図で
ある。FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in process order.
【図２】本発明の第２の実施例を工程順に示す断面図で
ある。FIG. 2 is a cross-sectional view showing a second embodiment of the present invention in process order.
【図３】従来のＰＲＯＭの製造方法を示す断面図であ
る。FIG. 3 is a cross-sectional view showing a conventional PROM manufacturing method.
【符号の説明】 １ 半導体基板 ２ 素子分離絶縁膜 ３ 第１の絶縁膜 ４ 第１の電極 ５ 第２の絶縁膜 ６ 第２の電極 ７ 第３の絶縁膜 ８ 第３の電極 ９ 側面絶縁膜 １０ 高耐圧ソース・ドレイン １１ 通常のソース・ドレイン １２ 層間絶縁膜 １３ コンタクト １４ 金属配線 １５ 第４の電極 １６ 第１のシリコン膜 １７ 第５の電極 １８ 第２のシリコン膜[Description of Reference Signs] 1 semiconductor substrate 2 element isolation insulating film 3 first insulating film 4 first electrode 5 second insulating film 6 second electrode 7 third insulating film 8 third electrode 9 side insulating film 10 High Voltage Source / Drain 11 Normal Source / Drain 12 Interlayer Insulation Film 13 Contact 14 Metal Wiring 15 Fourth Electrode 16 First Silicon Film 17 Fifth Electrode 18 Second Silicon Film
Claims (2)
を形成する工程と、全面に第１の絶縁膜を形成したの
ち、メモリセル形成予定領域の前記第１の絶縁膜上に第
１の導電膜からなるゲート電極を形成する工程と、高耐
圧回路形成予定領域および周辺回路形成予定領域の前記
第１の絶縁膜をエッチングする工程と、全面に第２の絶
縁膜を形成したのち、前記第２の絶縁膜上の前記高耐圧
回路形成予定領域に第２の導電膜からなるゲート電極を
形成する工程と、露出した前記第２の絶縁膜をエッチン
グする工程と、全面に第３の絶縁膜を形成する工程とを
含む読出し専用半導体メモリの製造方法。1. A step of forming an element isolation insulating film on one main surface of a semiconductor substrate, a step of forming a first insulating film on the entire surface, and a step of forming a first insulating film on the first insulating film in a memory cell formation planned region. 1 forming a gate electrode made of a conductive film, a step of etching the first insulating film in the high breakdown voltage circuit formation planned region and the peripheral circuit formation planned region, and after forming a second insulation film on the entire surface. A step of forming a gate electrode made of a second conductive film in the high breakdown voltage circuit formation planned region on the second insulating film, a step of etching the exposed second insulating film, and a third step over the entire surface. And a method of manufacturing a read-only semiconductor memory including the step of forming an insulating film.
の膜厚の方が薄くなっている請求項１記載の読出し専用
半導体メモリの製造方法。2. The method for manufacturing a read-only semiconductor memory according to claim 1, wherein the film thickness of the third insulating film is smaller than the film thickness of the second insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4199326A JPH0645614A (en) | 1992-07-27 | 1992-07-27 | Manufacture of read-only semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4199326A JPH0645614A (en) | 1992-07-27 | 1992-07-27 | Manufacture of read-only semiconductor memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0645614A true JPH0645614A (en) | 1994-02-18 |
Family
ID=16405940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4199326A Pending JPH0645614A (en) | 1992-07-27 | 1992-07-27 | Manufacture of read-only semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0645614A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0854509A1 (en) * | 1997-01-17 | 1998-07-22 | Programmable Microelectronics Corporation | Fabrication method for non-volatile memory with high-voltage and logic components |
| EP1104022A1 (en) * | 1999-11-29 | 2001-05-30 | STMicroelectronics S.r.l. | Process for the fabrication of an integrated circuit comprising low and high voltage MOS transistors and EPROM cells |
| WO2003028113A1 (en) * | 2001-09-19 | 2003-04-03 | Ricoh Company, Ltd. | Semiconductor device and its manufacturing method |
| US6706593B1 (en) | 1996-08-29 | 2004-03-16 | Nec Electroincs Corporation | Method for manufacturing a nonvolatile semiconductor storage device |
| KR100493021B1 (en) * | 2002-07-10 | 2005-06-07 | 삼성전자주식회사 | Semiconductor memory device and method for manufacturing the same |
| CN100397330C (en) * | 2002-01-25 | 2008-06-25 | 株式会社日立制作所 | Semiconductor device |
-
1992
- 1992-07-27 JP JP4199326A patent/JPH0645614A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6706593B1 (en) | 1996-08-29 | 2004-03-16 | Nec Electroincs Corporation | Method for manufacturing a nonvolatile semiconductor storage device |
| EP0854509A1 (en) * | 1997-01-17 | 1998-07-22 | Programmable Microelectronics Corporation | Fabrication method for non-volatile memory with high-voltage and logic components |
| EP1104022A1 (en) * | 1999-11-29 | 2001-05-30 | STMicroelectronics S.r.l. | Process for the fabrication of an integrated circuit comprising low and high voltage MOS transistors and EPROM cells |
| US6319780B2 (en) | 1999-11-29 | 2001-11-20 | Stmicroelectronics S.R.L. | Process for the fabrication of an integrated circuit comprising MOS transistors for low voltage, EPROM cells and MOS transistors for high voltage |
| WO2003028113A1 (en) * | 2001-09-19 | 2003-04-03 | Ricoh Company, Ltd. | Semiconductor device and its manufacturing method |
| US6949790B2 (en) | 2001-09-19 | 2005-09-27 | Ricoh Company, Ltd. | Semiconductor device and its manufacturing method |
| US7314797B2 (en) | 2001-09-19 | 2008-01-01 | Ricoh Company, Ltd. | Semiconductor device and its manufacturing method |
| CN100397330C (en) * | 2002-01-25 | 2008-06-25 | 株式会社日立制作所 | Semiconductor device |
| KR100493021B1 (en) * | 2002-07-10 | 2005-06-07 | 삼성전자주식회사 | Semiconductor memory device and method for manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2780986B2 (en) | Manufacturing method of integrated circuit | |
| JP2616569B2 (en) | Method for manufacturing semiconductor integrated circuit device | |
| JP3665426B2 (en) | Manufacturing method of semiconductor device | |
| US4935378A (en) | Method for manufacturing a semiconductor device having more than two conductive layers | |
| JPS61198780A (en) | Manufacture of semiconductor device | |
| JPH05206451A (en) | Mosfet and its manufacture | |
| JPH0645614A (en) | Manufacture of read-only semiconductor memory | |
| JPH04290447A (en) | Charge coupled device and its formation, and semiconductor integrated circuit device with same and its manfuacture | |
| JPS5856263B2 (en) | Manufacturing method of semiconductor device | |
| JPH04212426A (en) | Semiconductor device and its manufacture | |
| JPS59195870A (en) | Semiconductor device | |
| JPH0254960A (en) | Manufacture of semiconductor device | |
| JPH11307745A (en) | Nonvolatile semiconductor device and fabrication thereof | |
| JPH039572A (en) | Manufacture of semiconductor device | |
| JPH0142147B2 (en) | ||
| JP2000353796A (en) | Semiconductor device and manufacture thereof | |
| JPH09298281A (en) | Manufacturing method of semiconductor device | |
| JP2950620B2 (en) | Semiconductor device | |
| JP3194303B2 (en) | Semiconductor device | |
| JPH0252859B2 (en) | ||
| JPH07226502A (en) | Mos transistor and manufacture thereof | |
| JPH0338732B2 (en) | ||
| JPH1117165A (en) | Laminated gate structure in semiconductor device | |
| JPH04340277A (en) | Manufacture of mos semiconductor integrated circuit | |
| JPH0936358A (en) | Fabrication of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19990518 |