JPH11307745A - Nonvolatile semiconductor device and fabrication thereof - Google Patents
Nonvolatile semiconductor device and fabrication thereofInfo
- Publication number
- JPH11307745A JPH11307745A JP10182897A JP18289798A JPH11307745A JP H11307745 A JPH11307745 A JP H11307745A JP 10182897 A JP10182897 A JP 10182897A JP 18289798 A JP18289798 A JP 18289798A JP H11307745 A JPH11307745 A JP H11307745A
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- insulating film
- predetermined portion
- memory cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 62
- 238000004519 manufacturing process Methods 0.000 title claims description 43
- 239000003990 capacitor Substances 0.000 claims abstract description 63
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 229920005591 polysilicon Polymers 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims description 70
- 230000008569 process Effects 0.000 claims description 36
- 239000000758 substrate Substances 0.000 claims description 36
- 238000002955 isolation Methods 0.000 claims description 27
- 230000002093 peripheral effect Effects 0.000 claims description 25
- 239000003963 antioxidant agent Substances 0.000 claims description 23
- 230000003078 antioxidant effect Effects 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 19
- 239000011229 interlayer Substances 0.000 claims description 18
- 230000003647 oxidation Effects 0.000 claims description 16
- 238000007254 oxidation reaction Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 14
- 230000005641 tunneling Effects 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 239000002131 composite material Substances 0.000 abstract description 12
- 230000015572 biosynthetic process Effects 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 241000255777 Lepidoptera Species 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、非揮発性半導体素
子及びその製造方法に係るもので、詳しくはフラッシュ
メモリが内蔵された複合チップの実現に際して、電圧及
び温度の変化に拘わらずに安定した特性を有する抵抗と
キャパシタを形成し得る非揮発性半導体素子及びその製
造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor device and a method of manufacturing the same, and more particularly, to realizing a composite chip having a built-in flash memory, regardless of changes in voltage and temperature. The present invention relates to a nonvolatile semiconductor element capable of forming a resistor and a capacitor having characteristics and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】最近、半導体の製造技術及び半導体を用
いた電子製品の応用分野が拡大されるに従い多様な単一
素子を一つのチップ内に実現して様々な機能を行い得る
複合半導体チップの必要性が増大している。このように
メモリチップの機能とマイクロコントローラ或いは応用
目的に従い特定のコントロールを行う機能を一つの半導
体チップ内に実現すると、半導体チップの生産原価節減
及び体積縮小と共に、これらを用いた応用製品の製造原
価節減及び性能向上を図ることができるので、これに対
する研究開発が次第に一般化されつつある。2. Description of the Related Art Recently, as semiconductor manufacturing technology and application fields of electronic products using semiconductors have been expanded, various single elements have been realized in one chip to realize various functions of a composite semiconductor chip. The need is increasing. As described above, when the functions of the memory chip and the function of performing a specific control according to the microcontroller or the application purpose are realized in one semiconductor chip, the production cost and the volume of the semiconductor chip are reduced, and the manufacturing cost of the application product using the same is reduced. R & D for this is being increasingly generalized because savings and performance improvements can be achieved.
【０００３】このような複合的な機能を一つのチップ内
に実現するためには、素子の製造技術として、メモリセ
ル、トランジスタ、ダイオードのような能動素子だけで
なく、抵抗及びキャパシタのような受動素子の製造技術
も重要である。これはＡＤＣ(Analog to Digital Co
nverter)及び比較器又は演算増幅器などのようなアナロ
グ回路の実現に際して、非常に精密な電圧値及び電流値
の制御が要求されるが、精密な電圧値及び電流値の供給
と直接に関連する抵抗体及びキャパシタが入力電圧とか
外部温度に敏感な特性を有すれば精密な製品の設計が不
可能であるためである。従って、外部温度及び入力電圧
に拘わらずに安定した特性を有する抵抗とキャパシタを
製造する技術は、複合半導体チップの実現に際して必須
の非常に重要な技術として考えられている。In order to realize such a complex function in one chip, as a device manufacturing technology, not only active devices such as memory cells, transistors and diodes but also passive devices such as resistors and capacitors are used. Device manufacturing technology is also important. This is ADC (Analog to Digital Co.)
In the realization of analog circuits such as comparators and operational amplifiers, very precise control of voltage and current values is required, but the resistance is directly related to the supply of precise voltage and current values. This is because if the body and the capacitor have characteristics that are sensitive to the input voltage or the external temperature, it is impossible to design a precise product. Therefore, a technology for manufacturing a resistor and a capacitor having stable characteristics irrespective of an external temperature and an input voltage is considered as a very important technology indispensable for realizing a composite semiconductor chip.
【０００４】しかし、高安定性が要求されるという理由
で複合チップの非揮発性メモリセルの製造時、通常は、
抵抗及びキャパシタのような受動素子は内蔵させていな
い。しかし、抵抗及びキャパシタのような受動素子の内
蔵なしに複合チップを製造した場合は、そうでない場合
よりもフラッシュメモリセルの動作特性が劣り、高速動
作が不可能であるという短所が発生する。However, when manufacturing a nonvolatile memory cell of a composite chip because of the demand for high stability, usually,
Passive elements such as resistors and capacitors are not included. However, when a composite chip is manufactured without incorporating a passive element such as a resistor and a capacitor, the operating characteristics of the flash memory cell are inferior to those without the passive chip, and high speed operation is impossible.
【０００５】これを改善するため、最近、一般半導体回
路で頻繁に使用される高濃度の不純物領域（例えばｎ+
又はｐ+ 活性領域）を用いた抵抗体やモス製造時に使用
されるＭＩＭ(metal/interlayer/metal)構造（例えば、
スタック型、トレンチ型、ピン型又は円筒型など）のキ
ャパシタをそのままフラッシュメモリ内蔵の複合半導体
チップ製造に適用させる技術が提案されている。In order to improve this, recently, a high-concentration impurity region (for example, n +) frequently used in a general semiconductor circuit is used.
Or p + active region) or a MIM (metal / interlayer / metal) structure (eg,
A technique has been proposed in which a capacitor of a stack type, a trench type, a pin type, a cylindrical type, or the like) is directly applied to the manufacture of a composite semiconductor chip with a built-in flash memory.
【０００６】[0006]
【発明が解決しようとする課題】しかるに、このように
一般半導体回路で頻繁に使用される抵抗体とキャパシタ
をそのままフラッシュメモリ内蔵の複合チップに適用し
た場合は、抵抗形成時の工程による変動が大きくてメモ
リセルの抵抗値が不均一になり、よって、抵抗体とキャ
パシタが入力電圧及び外部温度変化に敏感な特性を有す
るため、精密な半導体製品の設計が難しくなって非揮発
性半導体素子の全体的な動作特性が低下するという問題
点がある。However, when a resistor and a capacitor frequently used in a general semiconductor circuit are directly applied to a composite chip with a built-in flash memory as described above, the variation due to the step of forming the resistor is large. As a result, the resistance value of the memory cell becomes non-uniform, so that the resistor and the capacitor are sensitive to the input voltage and the external temperature change. However, there is a problem that the dynamic operation characteristics are degraded.
【０００７】本発明の目的は、フラッシュメモリが内蔵
された複合チップの実現に際して、安定した抵抗値及び
静電容量の抵抗とキャパシタを非揮発性メモリセルと同
時に形成することにより、半導体素子の全体的な動作特
性を向上させ得る非揮発性半導体素子及びその製造方法
を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to realize a composite chip having a built-in flash memory, by forming a resistor and a capacitor having stable resistance and capacitance at the same time as a nonvolatile memory cell, thereby achieving an overall semiconductor device. It is an object of the present invention to provide a non-volatile semiconductor device capable of improving a dynamic operation characteristic and a method for manufacturing the same.
【０００８】[0008]
【課題を解決するための手段】本発明の非揮発性半導体
素子は、メモリセル形成部と周辺回路部が定義された半
導体基板と、この基板上のメモリセル形成部に形成さ
れ、電子を貯蔵するフローティングゲートとこれを制御
するコントロールゲートがアイソレーション絶縁膜とト
ンネリング絶縁膜を介して積層される構造を有する非揮
発性メモリトランジスタと、前記基板上の周辺回路部所
定部分に形成され、前記フローティングゲートと同じ材
質の抵抗ラインと、この抵抗ラインと所定間隔離隔され
て前記基板上の周辺回路部所定部分に形成され、前記フ
ローティングゲートと同じ材質の第１電極端子と前記コ
ントロールゲートと同じ材質の第２電極端子が誘電体膜
を介して積層される構造を有するキャパシタとからなる
ことを特徴とする。この非揮発性半導体素子において、
前記誘電体膜は酸化膜またはＯＮＯ構造で形成すること
ができる。A non-volatile semiconductor device according to the present invention has a semiconductor substrate in which a memory cell forming portion and a peripheral circuit portion are defined, and is formed in the memory cell forming portion on the substrate to store electrons. A non-volatile memory transistor having a structure in which a floating gate to be controlled and a control gate for controlling the floating gate are laminated via an isolation insulating film and a tunneling insulating film; A resistance line formed of the same material as the gate, a first electrode terminal formed of the same material as the floating gate, and a first electrode terminal formed of the same material as the control gate formed at a predetermined portion of the peripheral circuit portion on the substrate at a predetermined distance from the resistance line; The second electrode terminal comprises a capacitor having a structure in which the second electrode terminal is laminated via a dielectric film. In this nonvolatile semiconductor element,
The dielectric layer may be formed of an oxide layer or an ONO structure.
【０００９】本発明の第１の非揮発性半導体素子の製造
方法は、メモリセル形成部と周辺回路部が定義された半
導体基板上に第１導電性膜と酸化防止膜を順次形成する
工程と、前記メモリセル形成部の第１導電性膜表面が所
定部分だけ露出されるように酸化防止膜を食刻する工程
と、前記酸化防止膜をマスクとして酸化工程によりメモ
リセル形成部にアイソレーション絶縁膜を形成し、前記
酸化防止膜を除去する工程と、前記アイソレーション絶
縁膜を含めた前記第１導電性膜上に誘電体膜を形成する
工程と、周辺回路部の前記誘電体膜上に抵抗形成部とキ
ャパシタ形成部を限定する感光膜パターンを形成する工
程と、前記感光膜パターンをマスクとして誘電体膜を食
刻する工程と、前記感光膜パターンと前記アイソレーシ
ョン絶縁膜をマスクとして前記第１導電性膜を食刻して
フローティングゲートと上面に前記誘電体膜が形成され
た抵抗ライン及び第１電極端子を同時に形成し、前記感
光膜パターンを除去する工程と、前記アイソレーション
絶縁膜の両エッジ部と前記フローティングゲートの側壁
を含めた前記基板上の所定部分と前記抵抗ラインの側壁
及び前記第１電極端子の側壁に絶縁膜を形成し、それら
結果物全面に第２導電性膜を形成する工程と、メモリセ
ル形成部所定部分と周辺回路部所定部分の前記第２導電
性膜上に電極形成部とキャパシタ形成部を限定する感光
膜パターンを形成する工程と、前記感光膜パターンをマ
スクとして前記第２導電性膜を食刻してコントロールゲ
ートと第２電極端子を同時に形成し、前記感光膜パター
ンを除去する工程とからなることを特徴とする。A first method for manufacturing a nonvolatile semiconductor device according to the present invention comprises the steps of sequentially forming a first conductive film and an antioxidant film on a semiconductor substrate in which a memory cell forming portion and a peripheral circuit portion are defined. Etching an antioxidant film so that only a predetermined portion of the surface of the first conductive film of the memory cell forming portion is exposed; and oxidizing using the antioxidant film as a mask to isolate the memory cell forming portion from the memory cell forming portion. Forming a film and removing the antioxidant film; forming a dielectric film on the first conductive film including the isolation insulating film; and forming a dielectric film on the peripheral circuit portion on the dielectric film. Forming a photosensitive film pattern defining a resistance forming portion and a capacitor forming portion; etching a dielectric film using the photosensitive film pattern as a mask; and masking the photosensitive film pattern and the isolation insulating film. Etching the first conductive film to simultaneously form a floating gate, a resistance line having the dielectric film formed on the upper surface and a first electrode terminal, and removing the photosensitive film pattern; An insulating film is formed on predetermined portions of the substrate including both edges of the insulating film, the side walls of the floating gate, the side walls of the resistance line, and the side walls of the first electrode terminal, and forms a second conductive layer on the entire surface of the resultant. Forming a conductive film; forming a photosensitive film pattern defining an electrode forming portion and a capacitor forming portion on the second conductive film in a predetermined portion of a memory cell forming portion and a predetermined portion of a peripheral circuit portion; Forming a control gate and a second electrode terminal simultaneously by etching the second conductive film using the film pattern as a mask, and removing the photosensitive film pattern. And butterflies.
【００１０】また、本発明の第２の非揮発性半導体素子
の製造方法は、メモリセル形成部と周辺回路部が定義さ
れた半導体基板上に第１導電性膜と酸化防止膜を順次形
成する工程と、前記メモリセル形成部の第１導電性膜表
面が所定部分だけ露出されるように酸化防止膜を食刻す
る工程と、前記酸化防止膜をマスクとして酸化工程によ
りメモリセル形成部にアイソレーション絶縁膜を形成
し、前記酸化防止膜を除去する工程と、周辺回路部の前
記第１導電性膜上に抵抗形成部とキャパシタ形成部を限
定する感光膜パターンを形成する工程と、前記感光膜パ
ターンと前記アイソレーション絶縁膜をマスクとして第
１導電性膜を食刻してフローティングゲートと抵抗ライ
ン及び第１電極端子を同時に形成し、前記感光膜パター
ンを除去する工程と、前記アイソレーション絶縁膜の両
エッジ部と前記フローティングゲートの側壁を含めた前
記基板上の所定部分と前記抵抗ラインの全表面及び前記
第１電極端子の全表面に絶縁膜を形成し、それら結果物
全面に第２導電性膜を形成する工程と、メモリセル形成
部所定部分と周辺回路部所定部分の前記第２導電性膜上
に電極形成部とキャパシタ形成部を限定する感光膜パタ
ーンを形成する工程と、前記感光膜パターンをマスクと
して前記第２導電性膜を食刻してコントロールゲートと
第２電極端子を同時に形成し、前記感光膜パターンを除
去する工程とからなることを特徴とする。According to a second method of manufacturing a nonvolatile semiconductor device of the present invention, a first conductive film and an antioxidant film are sequentially formed on a semiconductor substrate in which a memory cell forming portion and a peripheral circuit portion are defined. A step of etching the antioxidant film so that only a predetermined portion of the surface of the first conductive film of the memory cell forming portion is exposed; and an oxidation step using the antioxidant film as a mask to isolate the memory cell forming portion. Forming a insulation insulating film and removing the antioxidant film; forming a photosensitive film pattern defining a resistance forming portion and a capacitor forming portion on the first conductive film in a peripheral circuit portion; Etching the first conductive film using the film pattern and the isolation insulating film as a mask to simultaneously form a floating gate, a resistance line, and a first electrode terminal, and removing the photosensitive film pattern; Forming an insulating film on predetermined portions of the substrate including both edges of the isolation insulating film and side walls of the floating gate, on the entire surface of the resistance line, and on the entire surface of the first electrode terminal; Forming a second conductive film on the entire surface, and forming a photosensitive film pattern defining an electrode forming portion and a capacitor forming portion on the predetermined portion of the memory cell forming portion and the predetermined portion of the peripheral circuit portion on the second conductive film; And a step of etching the second conductive film using the photosensitive film pattern as a mask to simultaneously form a control gate and a second electrode terminal, and removing the photosensitive film pattern.
【００１１】上記のような本発明によれば、抵抗及びキ
ャパシタ形成時の工程による変動を減らすことができ、
外部温度及び入力電圧の変化に拘わらずに安定した抵抗
値と静電容量を有する抵抗とキャパシタを複合チップ内
の非揮発性メモリセルと同時に形成することができる。According to the present invention as described above, it is possible to reduce the variation due to the steps of forming the resistor and the capacitor,
A resistor and a capacitor having a stable resistance value and a stable capacitance regardless of changes in the external temperature and the input voltage can be formed simultaneously with the nonvolatile memory cells in the composite chip.
【００１２】[0012]
【発明の実施の形態】以下、本発明の実施の形態を説明
する。本発明は、外部温度及び入力電圧の変化に拘わら
ずに安定した抵抗値と静電容量を有する抵抗とキャパシ
タを複合チップ内の非揮発性メモリセルの製造時に同時
に形成可能とすることにより精密な製品の設計が可能と
なるようにした技術である。その場合、非揮発性メモリ
が内蔵されたチップを駆動するのに必要な抵抗は非揮発
性メモリセル（非揮発性メモリトランジスタ）のフロー
ティングゲートを形成するポリシリコンで実現し、キャ
パシタは前記メモリトランジスタのフローティングゲー
ト用ポリシリコンとコントロールゲート用ポリシリコン
を両電極端子とし、その間に別途に形成された誘電体膜
（例えばＯＮＯ構造の絶縁膜または酸化膜材質の絶縁
膜）が置かれる構造を有するように実現する。これを図
１乃至図１８に提示した図面を参照して具体的に説明す
る。ここで、図１乃至図１１は本発明による非揮発性半
導体素子の製造方法の第１実施形態を示す工程断面図、
図１２乃至図１８は本発明による非揮発性半導体素子の
製造方法の第２実施形態を示す工程断面図である。これ
らの図中、参照符号ａで表示された部分は前記素子の非
揮発性メモリセルの形成部を示し、参照符号ｂで表示さ
れた部分は前記素子の抵抗形成部を示し、参照符号ｃで
表示された部分は前記素子のキャパシタ形成部を示す。Embodiments of the present invention will be described below. The present invention is precise by making it possible to simultaneously form a resistor and a capacitor having a stable resistance value and capacitance irrespective of changes in external temperature and input voltage when manufacturing a nonvolatile memory cell in a composite chip. This technology enables product design. In this case, a resistor necessary for driving a chip in which a nonvolatile memory is built is realized by polysilicon forming a floating gate of a nonvolatile memory cell (a nonvolatile memory transistor), and a capacitor is provided by the memory transistor. Having a structure in which a separately formed dielectric film (for example, an insulating film of an ONO structure or an insulating film of an oxide film) is placed between the floating gate polysilicon and the control gate polysilicon as both electrode terminals. To be realized. This will be specifically described with reference to the drawings presented in FIGS. Here, FIGS. 1 to 11 are process cross-sectional views showing a first embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention,
12 to 18 are process sectional views showing a second embodiment of the method for manufacturing a nonvolatile semiconductor device according to the present invention. In these figures, a portion indicated by reference numeral a indicates a formation portion of the nonvolatile memory cell of the element, a portion indicated by reference numeral b indicates a resistance formation portion of the element, and reference numeral c indicates The indicated part shows the capacitor forming part of the element.
【００１３】まず、第１実施形態を説明する。ここで
は、便宜上、工程を大きく１１段階に区分して説明す
る。第１段階として、図１に示すように、半導体基板10
0 上の所定部分にフィールド酸化膜102 を形成して該半
導体基板100 上を周辺回路部（抵抗形成部ｂ及びキャパ
シタ形成部ｃ）とメモリセル形成部ａに定義した後、基
板100 上のメモリセル形成部ａのみに選択的にゲート絶
縁膜104 を形成する。第２段階として、図２に示すよう
に、前記ゲート絶縁膜104 とフィールド酸化膜102 上に
ポリシリコン材質の第１導電性膜106 と窒化膜材質の酸
化防止膜108を順次形成する。このとき、前記第１導電
性膜106 は1000〜2000Åの厚さに形成する。First, a first embodiment will be described. Here, for the sake of convenience, the process will be roughly divided into 11 stages. As a first step, as shown in FIG.
A field oxide film 102 is formed on a predetermined portion of the semiconductor substrate 100 to define a peripheral circuit portion (a resistor forming portion b and a capacitor forming portion c) and a memory cell forming portion a. The gate insulating film 104 is selectively formed only in the cell formation part a. As a second step, as shown in FIG. 2, a first conductive film 106 made of polysilicon and an antioxidant film 108 made of nitride are sequentially formed on the gate insulating film 104 and the field oxide film 102. At this time, the first conductive film 106 is formed to a thickness of 1000 to 2000 mm.
【００１４】第３段階として、図３に示すように、酸化
防止膜108 上の全面に感光膜を形成し、メモリセル形成
部ａの酸化防止膜108 の表面が特定部分だけ露出される
ように感光膜を露光現像して感光膜パターン110aを形成
した後、これをマスクとして酸化防止膜108 を乾式食刻
する。このとき、抵抗形成部ｂ及びキャパシタ形成部ｃ
の酸化防止膜108 は感光膜パターン110aにより保護され
るため食刻されない。As a third step, as shown in FIG. 3, a photosensitive film is formed on the entire surface of the antioxidant film 108 so that only a specific portion of the surface of the antioxidant film 108 in the memory cell forming portion a is exposed. After the photosensitive film is exposed and developed to form a photosensitive film pattern 110a, the antioxidant film 108 is dry-etched using this as a mask. At this time, the resistance forming part b and the capacitor forming part c
The oxidation preventing film 108 is not etched because it is protected by the photosensitive film pattern 110a.
【００１５】第４段階として、図４に示すように、感光
膜パターン110aを除去し、酸化防止膜108 をマスクとし
て酸化工程を施す。その結果、酸化防止膜108 により保
護されないメモリセル形成部ａの所定部分の第１導電膜
106 表面のみに選択的に熱酸化膜からなるアイソレーシ
ョン絶縁膜112 が形成される。As a fourth step, as shown in FIG. 4, the photosensitive film pattern 110a is removed, and an oxidation process is performed using the antioxidant film 108 as a mask. As a result, the first conductive film in a predetermined portion of the memory cell forming portion a which is not protected by the oxidation preventing film 108 is formed.
An isolation insulating film 112 made of a thermal oxide film is selectively formed only on the surface.
【００１６】第５段階として、図５に示すように、酸化
防止膜108 を除去する。第６段階として、図６に示すよ
うに、アイソレーション絶縁膜112 を含めた第１導電性
膜106 の全面にＯＮＯ構造の誘電体膜114 を形成し、抵
抗形成部ｂとキャパシタ形成部ｃのみの誘電体膜114 上
に選択的に感光膜パターン110bを形成する。As a fifth step, as shown in FIG. 5, the antioxidant film 108 is removed. As a sixth step, as shown in FIG. 6, a dielectric film 114 having an ONO structure is formed on the entire surface of the first conductive film 106 including the isolation insulating film 112, and only the resistance forming portion b and the capacitor forming portion c are formed. The photosensitive film pattern 110b is selectively formed on the dielectric film 114 of FIG.
【００１７】第７段階として、図７に示すように、感光
膜パターン110bをマスクとして誘電体膜114 を食刻し、
さらに前記アイソレーション絶縁膜112 と感光膜パター
ン110bをマスクとしてメモリセル形成部ａとその周りの
回路部全領域に亙って第１導電性膜106 を食刻処理した
後、感光膜パターン110bを除去する。その結果、メモリ
セル形成部ａのみにポリシリコン材質のフローティング
ゲート106aとアイソレーション絶縁膜112 が形成され、
抵抗形成部ｂにはポリシリコン材質の抵抗ライン106bが
形成され、この抵抗ライン106bと所定間隔離隔されたキ
ャパシタ形成部ｃにはポリシリコン材質の第１電極端子
106cが形成される。第８段階として、図８に示すよう
に、フローティングゲート106aと後に形成されるコント
ロールゲート間の絶縁及びトランジスタのゲート絶縁膜
として使用される酸化膜材質の絶縁膜を形成するため酸
化工程を施す。その結果、メモリセル形成部ａにはアイ
ソレーション絶縁膜112 の両エッジ部とフローティング
ゲート106aの両側壁を含めたゲート絶縁膜104 上にトン
ネリング酸化膜の役割をする約50〜200 Åの厚さの絶縁
膜116 が形成され、抵抗形成部ｂとキャパシタ形成部ｃ
には抵抗ライン106bの両側壁と第１電極端子106cの両側
壁に約50〜200 Åの厚さの絶縁膜116 がそれぞれ形成さ
れる。As a seventh step, as shown in FIG. 7, the dielectric film 114 is etched using the photoresist pattern 110b as a mask.
Further, after the first conductive film 106 is etched over the memory cell forming portion a and the entire circuit portion surrounding the memory cell forming portion a using the isolation insulating film 112 and the photosensitive film pattern 110b as a mask, the photosensitive film pattern 110b is removed. Remove. As a result, a floating gate 106a made of polysilicon and an isolation insulating film 112 are formed only in the memory cell forming portion a,
A resistance line 106b made of polysilicon is formed in the resistance formation part b, and a first electrode terminal made of polysilicon is formed in a capacitor formation part c separated from the resistance line 106b by a predetermined distance.
106c is formed. As an eighth step, as shown in FIG. 8, an oxidation step is performed to form an insulating film made of an oxide film used as an insulation between the floating gate 106a and a control gate formed later and a gate insulating film of the transistor. As a result, the memory cell forming portion a has a thickness of about 50 to 200 mm which functions as a tunneling oxide film on the gate insulating film 104 including both edges of the isolation insulating film 112 and both side walls of the floating gate 106a. Is formed, and a resistance forming part b and a capacitor forming part c are formed.
An insulating film 116 having a thickness of about 50 to 200 mm is formed on both side walls of the resistance line 106b and both side walls of the first electrode terminal 106c.
【００１８】第９段階として、図９に示すように、基板
100 上の全面、すなわち、トンネリング絶縁膜116 とア
イソレーション絶縁膜112 が形成されたフローティング
ゲート106a、および上部に誘電体膜114 が形成された抵
抗ライン106bと第１電極端子106cを含む基板100 の全面
にポリシリコン材質の第２導電性膜を1000〜2000Åの厚
さに形成する。このような第２導電性膜の形成は、メモ
リセル（メモリトランジスタ）のコントロールゲート及
びキャパシタの第２電極端子を形成するためである。次
いで、第２導電性膜上にコントロールゲートが形成され
る部分と第２電極端子が形成される部分だけを限定する
感光膜パターン110cを形成し、これをマスクとして第２
導電性膜を乾式食刻する。この工程で周辺回路部の抵抗
形成部ｂは感光膜パターン110cにより保護されないので
第２導電性膜の全てが除去されて、抵抗ライン106b上の
誘電体膜114 の表面の全てが露出される。一方、キャパ
シタ形成部ｃでは感光膜パターン110cにより保護されな
い部分の誘電体膜114 表面だけが露出される。また、メ
モリセル形成部ａでは、感光膜パターン110cにより保護
されない部分のトンネリング絶縁膜116 とアイソレーシ
ョン絶縁膜112 表面だけが露出される。その結果、メモ
リセル形成部ａにはポリシリコン材質のコントロールゲ
ート118aが形成され、周辺回路部のキャパシタ形成部ｃ
にはポリシリコン材質の第２電極端子118cが形成され
る。即ち、前記図面を参照すると、抵抗ライン106bとキ
ャパシタの第１電極端子106cはフローティングゲート10
6aと同じ材質で形成され、キャパシタの第２電極端子11
8cはコントロールゲート118aと同じ材質で形成されるこ
とが分かる。As a ninth step, as shown in FIG.
The substrate 100 including the floating gate 106a on which the tunneling insulating film 116 and the isolation insulating film 112 are formed, and the resistance line 106b and the first electrode terminal 106c on which the dielectric film 114 is formed. A second conductive film made of polysilicon is formed on the entire surface to a thickness of 1000 to 2000 mm. The formation of such a second conductive film is for forming a control gate of a memory cell (memory transistor) and a second electrode terminal of a capacitor. Next, a photosensitive film pattern 110c is formed on the second conductive film to define only a portion where a control gate is formed and a portion where a second electrode terminal is formed.
Dry-etch the conductive film. In this step, since the resistance forming portion b of the peripheral circuit portion is not protected by the photosensitive film pattern 110c, the entire second conductive film is removed, and the entire surface of the dielectric film 114 on the resistance line 106b is exposed. On the other hand, in the capacitor forming portion c, only the surface of the dielectric film 114 that is not protected by the photosensitive film pattern 110c is exposed. In the memory cell forming portion a, only the surfaces of the tunneling insulating film 116 and the isolation insulating film 112 which are not protected by the photosensitive film pattern 110c are exposed. As a result, a control gate 118a made of polysilicon is formed in the memory cell forming portion a, and a capacitor forming portion c in the peripheral circuit portion is formed.
Is formed with a second electrode terminal 118c made of polysilicon. That is, referring to the drawing, the resistance line 106b and the first electrode terminal 106c of the capacitor are connected to the floating gate 10b.
The second electrode terminal 11 of the capacitor is formed of the same material as 6a.
It can be seen that 8c is formed of the same material as the control gate 118a.
【００１９】第１０段階として、図１０に示すように、
感光膜パターン110cを除去し、メモリトランジスタのソ
ースとドレイン形成部のみに選択的に高濃度の不純物を
イオン注入してメモリセル形成部ａの基板100 内にソー
スとドレイン領域120 、122を形成する。As a tenth step, as shown in FIG.
The photosensitive film pattern 110c is removed, and high-concentration impurities are selectively ion-implanted only in the source and drain formation portions of the memory transistor to form source and drain regions 120 and 122 in the substrate 100 of the memory cell formation portion a. .
【００２０】第１１段階として、図１１に示すように、
それら結果物が形成された基板100上の全面に層間絶縁
膜124 を形成し、ドレイン領域122 の基板100 表面所定
部分と抵抗ライン106b及び第１、第２電極端子106c、11
8cの表面所定部分が露出されるように層間絶縁膜124 と
誘電体膜114 とゲート絶縁膜104 を食刻してコンタクト
ホールを形成する。次いで、コンタクトホールを含めた
層間絶縁膜124 上の所定部分にAl或いはCu合金材質のビ
ットライン126 を形成して、全工程を終了する。As an eleventh stage, as shown in FIG.
An interlayer insulating film 124 is formed on the entire surface of the substrate 100 on which the resultant is formed, and a predetermined portion of the drain region 122 on the surface of the substrate 100, the resistance line 106b and the first and second electrode terminals 106c, 11c
The contact hole is formed by etching the interlayer insulating film 124, the dielectric film 114, and the gate insulating film 104 so that a predetermined portion of the surface of 8c is exposed. Next, a bit line 126 made of an Al or Cu alloy material is formed on a predetermined portion of the interlayer insulating film 124 including the contact hole, and the entire process is completed.
【００２１】その結果、図１１から分かるように、半導
体基板100 上のメモリセル形成部ａには電子を貯蔵する
フローティングゲート106aとこれを制御するコントロー
ルゲート118aがトンネリング酸化膜（符号116 で表示さ
れた部分）とアイソレーション絶縁膜112 を介して積層
される構造の非揮発性メモリトランジスタが形成され、
基板100 上の抵抗形成部ｂにはフローティングゲート10
6aと同じ材質の抵抗ライン106bが形成され、基板100 上
のキャパシタ形成部ｃには誘電体膜114 の表面が所定部
分だけ露出されるようにして、フローティングゲート10
6aと同じ材質の第１電極端子106cとコントロールゲート
118aと同じ材質の第２電極端子118cが誘電体膜114 を介
して積層される構造のキャパシタが形成され、このキャ
パシタと抵抗ライン106bと非揮発性メモリトランジスタ
が形成された基板100 上の全面には前記メモリトランジ
スタの特定部分、前記抵抗ライン106bの表面所定部分、
及び前記第１、第２電極端子106c、118cの表面所定部分
が露出されるようにコンタクトホールが開けられた層間
絶縁膜124 が形成され、コンタクトホールを含めた層間
絶縁膜124 上の所定部分には前記コントロールゲート11
8aと垂直交差するようにビットライン126 が形成された
構造の非揮発性半導体素子が完成する。As a result, as can be seen from FIG. 11, a floating gate 106a for storing electrons and a control gate 118a for controlling the floating gate 106a are indicated by a tunneling oxide film (reference numeral 116) in the memory cell forming portion a on the semiconductor substrate 100. ) And a non-volatile memory transistor having a structure laminated via the isolation insulating film 112,
The floating gate 10 is connected to the resistance forming portion b on the substrate 100.
A resistance line 106b made of the same material as that of the floating gate 6a is formed on the capacitor forming portion c on the substrate 100 so that only a predetermined portion of the surface of the dielectric film 114 is exposed.
First electrode terminal 106c and control gate made of the same material as 6a
A capacitor having a structure in which a second electrode terminal 118c made of the same material as the material 118a is laminated via the dielectric film 114 is formed, and the capacitor, the resistance line 106b, and the entire surface of the substrate 100 on which the nonvolatile memory transistor is formed are formed. Is a specific portion of the memory transistor, a predetermined portion of the surface of the resistance line 106b,
And an interlayer insulating film 124 having a contact hole formed so as to expose a predetermined portion of the surface of the first and second electrode terminals 106c and 118c, and to a predetermined portion of the interlayer insulating film 124 including the contact hole. Is the control gate 11
A nonvolatile semiconductor device having a structure in which a bit line 126 is formed so as to intersect perpendicularly with 8a is completed.
【００２２】次いで、第２実施形態を説明する。この第
２実施形態はキャパシタの第１電極端子と第２電極端子
間に形成される誘電体膜を別の膜（例えばＯＮＯ構造の
絶縁膜）蒸着工程で形成せず、トンネリング絶縁膜を形
成するため実施する酸化工程で作られる酸化膜材質の絶
縁膜をそのまま誘電体膜に使用する点を除いては基本的
な工程が第１実施形態と同一である。よって、この第２
実施形態は第１実施例と異なる部分を中心にその製造方
法を説明する。ここでは、便宜上、工程を大きく７段階
に区分して説明する。Next, a second embodiment will be described. In the second embodiment, a tunneling insulating film is formed without forming a dielectric film formed between a first electrode terminal and a second electrode terminal of a capacitor by another film (for example, an insulating film having an ONO structure). Therefore, the basic process is the same as that of the first embodiment except that the insulating film made of the oxide film material formed in the oxidizing process is used as the dielectric film. Therefore, this second
In the embodiment, a manufacturing method thereof will be described focusing on parts different from the first embodiment. Here, for the sake of convenience, the process will be described by roughly dividing it into seven stages.
【００２３】第１段階として、図１２に示すように、メ
モリセル形成部ａにはゲート絶縁膜204 が形成され、周
辺回路部（抵抗形成部ｂ及びキャパシタ形成部ｃ）には
フィールド酸化膜202 が形成された半導体基板200 上の
全面にポリシリコン材質の第１導電性膜206 と窒化膜材
質の酸化防止膜（図示せず）を順次形成した後、その上
にメモリセル形成部ａの酸化防止膜表面が特定部分だけ
露出されるように感光膜パターン（図示せず）を形成す
る。このとき、第１導電性膜206 は1000〜2000Åの厚さ
に形成する。次に、感光膜パターンをマスクとして酸化
防止膜を乾式食刻し、感光膜パターンを除去した後、酸
化工程を施して酸化防止膜により保護されないメモリセ
ル形成部ａの所定部分の第１導電性膜206 表面のみに選
択的に熱酸化膜材質のアイソレーション絶縁膜212 を形
成し、酸化防止膜を除去する。As a first step, as shown in FIG. 12, a gate insulating film 204 is formed in the memory cell forming portion a, and a field oxide film 202 is formed in the peripheral circuit portion (the resistor forming portion b and the capacitor forming portion c). After a first conductive film 206 made of polysilicon and an antioxidant film (not shown) made of nitride are sequentially formed on the entire surface of the semiconductor substrate 200 on which is formed, the oxidation of the memory cell forming portion a is formed thereon. A photoresist pattern (not shown) is formed such that a specific portion of the surface of the barrier layer is exposed. At this time, the first conductive film 206 is formed to a thickness of 1000 to 2000 mm. Next, the anti-oxidation film is dry-etched using the photoresist film pattern as a mask, and after removing the photoresist film pattern, an oxidation process is performed to perform a first conductive process on a predetermined portion of the memory cell forming portion a which is not protected by the oxidation prevention film. An isolation insulating film 212 made of a thermal oxide material is selectively formed only on the surface of the film 206, and the antioxidant film is removed.
【００２４】第２段階として、図１３に示すように、抵
抗形成部ｂとキャパシタ形成部ｃのみの第１導電性膜20
6 上に選択的に感光膜パターン210aを形成する。第３段
階として、図１４に示すように、アイソレーション絶縁
膜212 と感光膜パターン210aをマスクとしてメモリセル
形成部ａと周辺回路部の全領域に亙って第１導電性膜20
6 を食刻し、感光膜パターン210aを除去する。その結
果、メモリセル形成部ａにはポリシリコン材質のフロー
ティングゲート206aとアイソレーション絶縁膜212 が形
成され、抵抗形成部ｂにはポリシリコン材質の抵抗ライ
ン206bが形成され、キャパシタ形成部ｃにはポリシリコ
ン材質の第１電極端子206cが形成される。As a second step, as shown in FIG. 13, the first conductive film 20 of only the resistance forming part b and the capacitor forming part c is formed.
6 A photosensitive film pattern 210a is selectively formed on the upper surface. As a third step, as shown in FIG. 14, the first conductive film 20 is formed over the entire region of the memory cell forming portion a and the peripheral circuit portion using the isolation insulating film 212 and the photosensitive film pattern 210a as a mask.
6 is etched to remove the photosensitive film pattern 210a. As a result, a floating gate 206a made of polysilicon and an isolation insulating film 212 are formed in the memory cell formation part a, a resistance line 206b made of polysilicon is formed in the resistance formation part b, and a capacitor formation part c is formed. A first electrode terminal 206c made of polysilicon is formed.
【００２５】第４段階として、図１５に示すように、フ
ローティングゲート206aと後に形成されるコントロール
ゲート間の絶縁及びトランジスタのゲート絶縁膜として
使用される絶縁膜216 を形成するため酸化工程を施す。
その結果、メモリセル形成部ａにはアイソレーション絶
縁膜212 の両エッジ部とフローティングゲート206aの両
側壁を含めたゲート絶縁膜204 上にトンネリング絶縁膜
として用いられる酸化膜材質の絶縁膜216 が約50〜200
Åの厚さに形成され、抵抗形成部ｂとキャパシタ形成部
ｃには抵抗ライン206bと第１電極端子206cの全表面に酸
化膜材質の絶縁膜216 が約50〜200 Åの厚さに形成され
る。As a fourth step, as shown in FIG. 15, an oxidation step is performed to form an insulating film 216 used as an insulating film between the floating gate 206a and a control gate to be formed later and a gate insulating film of the transistor.
As a result, in the memory cell forming portion a, an insulating film 216 of an oxide film material used as a tunneling insulating film is formed on the gate insulating film 204 including both edges of the isolation insulating film 212 and both side walls of the floating gate 206a. 50-200
An insulating film 216 made of an oxide film is formed on the entire surface of the resistance line 206b and the first electrode terminal 206c to a thickness of about 50 to 200 mm in the resistance forming part b and the capacitor forming part c. Is done.
【００２６】第５段階として、図１６に示すように、基
板200 上の全面、すなわち、上面と側面に絶縁膜216 と
アイソレーション絶縁膜212 が形成されたフローティン
グゲート206a及び全表面に絶縁膜216 が形成された抵抗
ライン206bと第１電極端子206cを含む基板200 上の全面
にポリシリコン材質の第２導電性膜を1000〜2000Åの厚
さに形成する。このような第２導電性膜の形成は、メモ
リトランジスタのコントロールゲートとキャパシタの第
２電極端子を形成するためである。次いで、第２導電性
膜上にコントロールゲートが形成される部分と第２電極
端子が形成される部分だけを限定する感光膜パターン21
0bを形成し、これをマスクとして第２導電性膜を乾式食
刻する。この工程で周辺回路部の抵抗形成部ｂは感光膜
パターン210bにより保護されないので抵抗ライン206b上
の絶縁膜216 表面の全てが露出される。一方、キャパシ
タ形成部ｃは感光膜パターン210bにより保護されない部
分の絶縁膜216 表面だけが露出される。また、メモリセ
ル形成部ａでは、感光膜パターン210bにより保護されな
い部分のトンネリング絶縁膜216 とアイソレーション絶
縁膜212 表面だけが露出される。その結果、メモリセル
形成部ａにはポリシリコン材質のコントロールゲート20
8aが形成され、周辺回路部のキャパシタ形成部ｃにはポ
リシリコン材質の第２電極端子208cが形成される。即
ち、前記図面を参照すると、抵抗ライン206bとキャパシ
タの第１電極端子206cはフローティングゲート206aと同
じ材質で形成され、キャパシタの第２電極端子208cはコ
ントロールゲート208aと同じ材質で形成され、キャパシ
タの誘電体膜は酸化膜材質の絶縁膜216 で形成されるこ
とが分かる。As a fifth step, as shown in FIG. 16, a floating gate 206a having an insulating film 216 and an isolation insulating film 212 formed on the entire surface of the substrate 200, ie, the upper surface and side surfaces, and an insulating film 216 formed on the entire surface. A second conductive film made of polysilicon is formed on the entire surface of the substrate 200 including the resistance line 206b and the first electrode terminal 206c having a thickness of 1000 to 2000 mm. The formation of such a second conductive film is for forming the control gate of the memory transistor and the second electrode terminal of the capacitor. Next, on the second conductive film, a photosensitive film pattern 21 for limiting only a portion where a control gate is to be formed and a portion where a second electrode terminal is to be formed.
0b is formed, and the second conductive film is dry-etched using this as a mask. In this step, the entire surface of the insulating film 216 on the resistance line 206b is exposed because the resistance forming portion b of the peripheral circuit portion is not protected by the photosensitive film pattern 210b. On the other hand, in the capacitor forming part c, only the surface of the insulating film 216 which is not protected by the photosensitive film pattern 210b is exposed. In the memory cell forming part a, only the surfaces of the tunneling insulating film 216 and the isolation insulating film 212 which are not protected by the photosensitive film pattern 210b are exposed. As a result, the control gate 20 made of polysilicon material is provided in the memory cell forming portion a.
8a is formed, and a second electrode terminal 208c made of polysilicon is formed in the capacitor forming portion c of the peripheral circuit portion. That is, referring to the drawing, the resistance line 206b and the first electrode terminal 206c of the capacitor are formed of the same material as the floating gate 206a, and the second electrode terminal 208c of the capacitor is formed of the same material as the control gate 208a. It can be seen that the dielectric film is formed of an insulating film 216 made of an oxide film.
【００２７】第６段階として、図１７に示すように、感
光膜パターン210bを除去し、メモリトランジスタのソー
スとドレイン形成部のみに選択的に高濃度の不純物をイ
オン注入して、メモリセル形成部ａの基板200 内にソー
スとドレイン領域220 、222を形成する。As a sixth step, as shown in FIG. 17, the photosensitive film pattern 210b is removed, and high-concentration impurities are selectively ion-implanted only into the source and drain formation portions of the memory transistor to form a memory cell formation portion. Source and drain regions 220 and 222 are formed in a substrate 200 of FIG.
【００２８】第７段階として、図１８に示すように、そ
れら結果物が形成された基板200 上の全面に層間絶縁膜
224 を形成し、ドレイン領域222 の基板200 表面所定部
分と抵抗ライン206b及び第１、第２電極端子206c、208c
の表面所定部分が露出されるように層間絶縁膜224 、絶
縁膜216 およびゲート絶縁膜204 を乾式食刻してコンタ
クトホールを形成する。次いで、コンタクトホールを含
めた層間絶縁膜224 の所定部分上にAl或いはCu合金材質
のビットライン226 を形成して、全工程を終了する。As a seventh step, as shown in FIG. 18, an interlayer insulating film is formed on the entire surface of the substrate 200 on which the resultant is formed.
224 are formed, a predetermined portion of the surface of the substrate 200 of the drain region 222, the resistance line 206b, and the first and second electrode terminals 206c and 208c are formed.
The contact holes are formed by dry-etching the interlayer insulating film 224, the insulating film 216, and the gate insulating film 204 such that a predetermined portion of the surface is exposed. Next, a bit line 226 made of an Al or Cu alloy material is formed on a predetermined portion of the interlayer insulating film 224 including the contact hole, and the entire process is completed.
【００２９】このような工程により非揮発性半導体素子
を製造すると、キャパシタ製造時に別の誘電体膜を形成
する必要がないので、第１実施形態の場合よりも工程単
純化と費用節減の効果が得られる。なお、この第２実施
形態で得られた素子は、キャパシタの誘電体膜が絶縁膜
216 の酸化膜からなることを除いては第１実施形態で得
られた素子と基本構造が同一であるためここでは構造説
明は省略する。When a non-volatile semiconductor element is manufactured by such a process, it is not necessary to form another dielectric film at the time of manufacturing a capacitor. Therefore, the effects of the process simplification and cost reduction are lower than in the first embodiment. can get. In the device obtained in the second embodiment, the dielectric film of the capacitor is an insulating film.
Since the basic structure is the same as that of the device obtained in the first embodiment except that the device is composed of 216 oxide films, the description of the structure is omitted here.
【００３０】そして、上記第１、第２実施形態のように
して、非揮発性メモリセルを動作させるための周辺回路
用抵抗とキャパシタを製造した場合は、フラッシュメモ
リが内蔵された複合チップの実現に際して抵抗体を高濃
度の不純物領域（例えばｎ+又はｐ+ 活性領域）により
形成し、キャパシタをＭＯＳで一般に使用されてきたＭ
ＩＭ(metal/interlay-er/metal) 構造（例えばスタック
型、トレンチ型、ピン型、又は円筒型）により形成する
従来と比べて、これら製造時の工程による変動を減らす
ことができるので、外部温度及び入力電圧の変化に拘わ
らずに安定した抵抗値と静電容量を有する抵抗及びキャ
パシタを得ることができる。その結果、抵抗とキャパシ
タの精密な電圧値と電流値の制御が可能になって精密な
製品の設計が可能で、素子の動作特性も向上するという
効果がある。When a resistor and a capacitor for a peripheral circuit for operating a nonvolatile memory cell are manufactured as in the first and second embodiments, a composite chip incorporating a flash memory is realized. At this time, a resistor is formed by a high-concentration impurity region (for example, an n + or p + active region), and a capacitor is formed of M which has been generally used in MOS.
Variations due to these manufacturing steps can be reduced as compared with the conventional method using an IM (metal / interlay-er / metal) structure (for example, a stack type, trench type, pin type, or cylindrical type). In addition, it is possible to obtain a resistor and a capacitor having a stable resistance value and a stable capacitance regardless of a change in the input voltage. As a result, it is possible to precisely control the voltage value and the current value of the resistor and the capacitor, to design a precise product, and to improve the operation characteristics of the element.
【００３１】[0031]
【発明の効果】以上詳細に説明したように本発明によれ
ば、非揮発性メモリセルの製造時同時に、該非揮発性メ
モリセルを駆動するために必要される抵抗とキャパシタ
とを前記セルのゲートと同一材質で形成するようにした
ので、これら抵抗とキャパシタ製造時の工程による変動
を減らすことができ、外部温度及び入力電圧の変化に拘
わらずに安定した抵抗値と静電容量を有する抵抗及びキ
ャパシタを得ることができ、その結果として、抵抗とキ
ャパシタの精密な電圧値と電流値の制御が可能になって
精密な製品の設計が可能となるとともに、高速動作がで
きる高信頼性の半導体素子を実現できる。As described above in detail, according to the present invention, at the same time when a nonvolatile memory cell is manufactured, a resistor and a capacitor required for driving the nonvolatile memory cell are connected to the gate of the nonvolatile memory cell. Since it is made of the same material as above, it is possible to reduce the variation due to the process of manufacturing the resistor and the capacitor, and to provide a resistor and a capacitor having a stable resistance value and capacitance regardless of changes in the external temperature and the input voltage. Capacitors can be obtained, and as a result, precise voltage and current values of resistors and capacitors can be controlled, enabling precise product design and high-speed operation of highly reliable semiconductor devices. Can be realized.
【図１】本発明による非揮発性半導体素子の製造方法の
第１実施形態を示す工程断面図。FIG. 1 is a process sectional view showing a first embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention.
【図２】本発明による非揮発性半導体素子の製造方法の
第１実施形態を示す工程断面図。FIG. 2 is a process sectional view showing a first embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention.
【図３】本発明による非揮発性半導体素子の製造方法の
第１実施形態を示す工程断面図。FIG. 3 is a process sectional view showing a first embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention.
【図４】本発明による非揮発性半導体素子の製造方法の
第１実施形態を示す工程断面図。FIG. 4 is a process sectional view showing a first embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention.
【図５】本発明による非揮発性半導体素子の製造方法の
第１実施形態を示す工程断面図。FIG. 5 is a process sectional view showing a first embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention.
【図６】本発明による非揮発性半導体素子の製造方法の
第１実施形態を示す工程断面図。FIG. 6 is a process sectional view showing a first embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention.
【図７】本発明による非揮発性半導体素子の製造方法の
第１実施形態を示す工程断面図。FIG. 7 is a process sectional view showing a first embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention.
【図８】本発明による非揮発性半導体素子の製造方法の
第１実施形態を示す工程断面図。FIG. 8 is a process sectional view illustrating a first embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention.
【図９】本発明による非揮発性半導体素子の製造方法の
第１実施形態を示す工程断面図。FIG. 9 is a process sectional view showing a first embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention.
【図１０】本発明による非揮発性半導体素子の製造方法
の第１実施形態を示す工程断面図。FIG. 10 is a process sectional view showing a first embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention.
【図１１】本発明による非揮発性半導体素子の製造方法
の第１実施形態を示す工程断面図。FIG. 11 is a process sectional view showing a first embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention.
【図１２】本発明による非揮発性半導体素子の製造方法
の第２実施形態を示す工程断面図。FIG. 12 is a process sectional view showing a second embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention.
【図１３】本発明による非揮発性半導体素子の製造方法
の第２実施形態を示す工程断面図。FIG. 13 is a process sectional view showing a second embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention.
【図１４】本発明による非揮発性半導体素子の製造方法
の第２実施形態を示す工程断面図。FIG. 14 is a process sectional view showing a second embodiment of the method for manufacturing a nonvolatile semiconductor device according to the present invention.
【図１５】本発明による非揮発性半導体素子の製造方法
の第２実施形態を示す工程断面図。FIG. 15 is a process sectional view showing a second embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention.
【図１６】本発明による非揮発性半導体素子の製造方法
の第２実施形態を示す工程断面図。FIG. 16 is a process sectional view showing a second embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention.
【図１７】本発明による非揮発性半導体素子の製造方法
の第２実施形態を示す工程断面図。FIG. 17 is a process sectional view showing a second embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention.
【図１８】本発明による非揮発性半導体素子の製造方法
の第２実施形態を示す工程断面図。FIG. 18 is a process sectional view showing a second embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention.
１００ 半導体基板 １０６ａ フローティングゲート １０６ｂ 抵抗ライン １０６ｃ 第１電極端子 １１８ａ コントロールゲート １１８ｃ 第２電極端子 １１４ 誘電体膜 １２４ 層間絶縁膜 １２６ ビットライン Reference Signs List 100 semiconductor substrate 106a floating gate 106b resistance line 106c first electrode terminal 118a control gate 118c second electrode terminal 114 dielectric film 124 interlayer insulating film 126 bit line
───────────────────────────────────────────────────── フロントページの続き (72)発明者 鄭 七 熈 大韓民国ソウル市江南区開浦洞649番地 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Zheng Qi Qi, 649 Gaepo-dong, Gangnam-gu, Seoul, Korea
Claims (16)
れた半導体基板と、 この基板上のメモリセル形成部に形成され、電子を貯蔵
するフローティングゲートとこれを制御するコントロー
ルゲートがアイソレーション絶縁膜とトンネリング絶縁
膜を介して積層される構造を有する非揮発性メモリトラ
ンジスタと、 前記基板上の周辺回路部所定部分に形成され、前記フロ
ーティングゲートと同じ材質の抵抗ラインと、 この抵抗ラインと所定間隔離隔されて前記基板上の周辺
回路部所定部分に形成され、前記フローティングゲート
と同じ材質の第１電極端子と前記コントロールゲートと
同じ材質の第２電極端子が誘電体膜を介して積層される
構造を有するキャパシタとからなることを特徴とする非
揮発性半導体素子。A semiconductor substrate in which a memory cell forming portion and a peripheral circuit portion are defined; a floating gate formed in the memory cell forming portion on the substrate for storing electrons; A nonvolatile memory transistor having a structure laminated with a film and a tunneling insulating film, a resistance line formed in a predetermined portion of a peripheral circuit portion on the substrate, and made of the same material as the floating gate; A first electrode terminal formed of the same material as the floating gate and a second electrode terminal formed of the same material as the control gate are formed on a predetermined portion of the peripheral circuit portion on the substrate with a gap therebetween via a dielectric film. A nonvolatile semiconductor element comprising a capacitor having a structure.
徴とする請求項１に記載の非揮発性半導体素子。2. The non-volatile semiconductor device according to claim 1, wherein said dielectric film comprises an oxide film.
を特徴とする請求項１に記載の非揮発性半導体素子。3. The non-volatile semiconductor device according to claim 1, wherein said dielectric film has an ONO structure.
であることを特徴とする請求項１に記載の非揮発性半導
体素子。4. The non-volatile semiconductor device according to claim 1, wherein said isolation insulating film is a thermal oxide film.
抵抗ライン及び前記キャパシタが形成された基板全面に
形成され、前記メモリトランジスタの特定部分と前記抵
抗ラインの表面所定部分及び前記第１、第２電極端子の
表面所定部分が露出されるようにコンタクトホールが開
けられた層間絶縁膜と、 前記コンタクトホールを含めた前記層間絶縁膜上の所定
部分に形成され、前記コントロールゲートと垂直交差す
るように配置されたビットラインとを更に備えることを
特徴とする請求項１に記載の非揮発性半導体素子。5. A specific portion of the memory transistor, a predetermined portion of a surface of the resistance line, and the first and second electrodes formed on the entire surface of the substrate on which the nonvolatile memory transistor, the resistance line, and the capacitor are formed. An interlayer insulating film in which a contact hole is opened such that a predetermined portion of the surface of the terminal is exposed; and a predetermined portion on the interlayer insulating film including the contact hole, which is disposed so as to vertically intersect the control gate. The non-volatile semiconductor device according to claim 1, further comprising: a selected bit line.
れた半導体基板上に第１導電性膜と酸化防止膜を順次形
成する工程と、 前記メモリセル形成部の第１導電性膜表面が所定部分だ
け露出されるように酸化防止膜を食刻する工程と、 前記酸化防止膜をマスクとして酸化工程によりメモリセ
ル形成部にアイソレーション絶縁膜を形成し、前記酸化
防止膜を除去する工程と、 前記アイソレーション絶縁膜を含めた前記第１導電性膜
上に誘電体膜を形成する工程と、 周辺回路部の前記誘電体膜上に抵抗形成部とキャパシタ
形成部を限定する感光膜パターンを形成する工程と、 前記感光膜パターンをマスクとして誘電体膜を食刻する
工程と、 前記感光膜パターンと前記アイソレーション絶縁膜をマ
スクとして前記第１導電性膜を食刻してフローティング
ゲートと上面に前記誘電体膜が形成された抵抗ライン及
び第１電極端子を同時に形成し、前記感光膜パターンを
除去する工程と、 前記アイソレーション絶縁膜の両エッジ部と前記フロー
ティングゲートの側壁を含めた前記基板上の所定部分と
前記抵抗ラインの側壁及び前記第１電極端子の側壁に絶
縁膜を形成し、それら結果物全面に第２導電性膜を形成
する工程と、 メモリセル形成部所定部分と周辺回路部所定部分の前記
第２導電性膜上に電極形成部とキャパシタ形成部を限定
する感光膜パターンを形成する工程と、 前記感光膜パターンをマスクとして前記第２導電性膜を
食刻してコントロールゲートと第２電極端子を同時に形
成し、前記感光膜パターンを除去する工程とからなるこ
とを特徴とする非揮発性半導体素子の製造方法。6. A step of sequentially forming a first conductive film and an oxidation preventing film on a semiconductor substrate in which a memory cell forming portion and a peripheral circuit portion are defined; Etching an antioxidant film so that only a predetermined portion is exposed; forming an isolation insulating film in a memory cell forming portion by an oxidation process using the antioxidant film as a mask; and removing the antioxidant film. Forming a dielectric film on the first conductive film including the isolation insulating film; and forming a photosensitive film pattern defining a resistance forming portion and a capacitor forming portion on the dielectric film in a peripheral circuit portion. Forming a dielectric film using the photosensitive film pattern as a mask; etching the first conductive film using the photosensitive film pattern and the isolation insulating film as a mask; Simultaneously forming a resisting line and a first electrode terminal on which the dielectric film is formed on the insulating gate and the upper surface, and removing the photosensitive film pattern; both edges of the isolation insulating film and sidewalls of the floating gate; Forming an insulating film on a predetermined portion of the substrate including the resistive line, a side wall of the resistance line, and a side wall of the first electrode terminal, and forming a second conductive film over the entire surface of the resultant; Forming a photosensitive film pattern defining an electrode forming portion and a capacitor forming portion on the predetermined portion and the predetermined portion of the peripheral circuit portion on the second conductive film; and forming the second conductive film using the photosensitive film pattern as a mask. Forming a control gate and a second electrode terminal at the same time by etching, and removing the photosensitive film pattern.
を特徴とする請求項６に記載の非揮発性半導体素子の製
造方法。7. The method according to claim 6, wherein the oxidation preventing film is formed of a nitride film.
とを特徴とする請求項６に記載の非揮発性半導体素子の
製造方法。8. The method according to claim 6, wherein the dielectric film has an ONO structure.
前記所定部分に形成される前記絶縁膜は酸化工程により
50〜200 Åの厚さに形成することを特徴とする請求項６
に記載の非揮発性半導体素子の製造方法。9. The insulating film formed on the predetermined portion including a side wall of the floating gate by an oxidation process
7. A film according to claim 6, wherein said film is formed to a thickness of 50 to 200 mm.
3. The method for manufacturing a nonvolatile semiconductor device according to item 1.
Åの厚さのポリシリコンで形成することを特徴とする請
求項６に記載の非揮発性半導体素子の製造方法。10. The first and second conductive films have a thickness of 1000 to 2000.
7. The method according to claim 6, wherein the non-volatile semiconductor element is formed of polysilicon having a thickness of Å.
極端子を同時に形成し、前記感光膜パターンを除去する
工程の以後に、 それら結果物が形成された前記基板全面に層間絶縁膜を
形成する工程と、 前記メモリセル形成部の基板表面所定部分と前記抵抗ラ
インの表面所定部分及び第１、第２電極端子の表面所定
部分が露出されるように前記層間絶縁膜と前記誘電体膜
を選択食刻してコンタクトホールを形成する工程と、 前記コンタクトホールを含めた前記層間絶縁膜上の所定
部分にビットラインを形成する工程とを更に具備するこ
とを特徴とする請求項６に記載の非揮発性半導体素子の
製造方法。11. A step of forming the control gate and the second electrode terminal at the same time and forming an interlayer insulating film on the entire surface of the substrate on which the resultant is formed after the step of removing the photosensitive film pattern; Selectively etching the interlayer insulating film and the dielectric film such that a predetermined portion of the substrate surface of the memory cell forming portion, a predetermined portion of the surface of the resistance line, and a predetermined portion of the surface of the first and second electrode terminals are exposed. 7. The non-volatile method according to claim 6, further comprising: forming a contact hole by forming a bit line in a predetermined portion of the interlayer insulating film including the contact hole. A method for manufacturing a semiconductor device.
された半導体基板上に第１導電性膜と酸化防止膜を順次
形成する工程と、 前記メモリセル形成部の第１導電性膜表面が所定部分だ
け露出されるように酸化防止膜を食刻する工程と、 前記酸化防止膜をマスクとして酸化工程によりメモリセ
ル形成部にアイソレーション絶縁膜を形成し、前記酸化
防止膜を除去する工程と、 周辺回路部の前記第１導電性膜上に抵抗形成部とキャパ
シタ形成部を限定する感光膜パターンを形成する工程
と、 前記感光膜パターンと前記アイソレーション絶縁膜をマ
スクとして第１導電性膜を食刻してフローティングゲー
トと抵抗ライン及び第１電極端子を同時に形成し、前記
感光膜パターンを除去する工程と、 前記アイソレーション絶縁膜の両エッジ部と前記フロー
ティングゲートの側壁を含めた前記基板上の所定部分と
前記抵抗ラインの全表面及び前記第１電極端子の全表面
に絶縁膜を形成し、それら結果物全面に第２導電性膜を
形成する工程と、 メモリセル形成部所定部分と周辺回路部所定部分の前記
第２導電性膜上に電極形成部とキャパシタ形成部を限定
する感光膜パターンを形成する工程と、 前記感光膜パターンをマスクとして前記第２導電性膜を
食刻してコントロールゲートと第２電極端子を同時に形
成し、前記感光膜パターンを除去する工程とからなるこ
とを特徴とする非揮発性半導体素子の製造方法。12. A step of sequentially forming a first conductive film and an antioxidant film on a semiconductor substrate in which a memory cell forming portion and a peripheral circuit portion are defined; Etching an antioxidant film so that only a predetermined portion is exposed; forming an isolation insulating film in a memory cell forming portion by an oxidation process using the antioxidant film as a mask; and removing the antioxidant film. Forming a photoresist pattern on the first conductive film of the peripheral circuit portion defining a resistance forming portion and a capacitor forming portion; and forming the first conductive film using the photosensitive film pattern and the isolation insulating film as a mask. Forming a floating gate, a resistance line, and a first electrode terminal at the same time by removing the photoresist pattern, and removing both edges of the isolation insulating film and An insulating film is formed on a predetermined portion of the substrate including the sidewall of the loading gate, on the entire surface of the resistance line, and on the entire surface of the first electrode terminal, and a second conductive film is formed on the entire surface of the resultant. Forming a photosensitive film pattern defining an electrode forming portion and a capacitor forming portion on the second conductive film in a predetermined portion of a memory cell forming portion and a predetermined portion of a peripheral circuit portion; and using the photosensitive film pattern as a mask. Etching the second conductive film to form a control gate and a second electrode terminal at the same time, and removing the photosensitive film pattern.
とを特徴とする請求項１２に記載の非揮発性半導体素子
の製造方法。13. The method according to claim 12, wherein the oxidation preventing film is formed of a nitride film.
む前記所定部分に形成される前記絶縁膜は酸化工程によ
り50〜200 Åの厚さに形成することを特徴とする請求項
１２に記載の非揮発性半導体素子の製造方法。14. The nonvolatile memory according to claim 12, wherein the insulating film formed on the predetermined portion including the side wall of the floating gate is formed to a thickness of 50 to 200 mm by an oxidation process. A method for manufacturing a semiconductor device.
Åの厚さのポリシリコンで形成することを特徴とする請
求項１２に記載の非揮発性半導体素子の製造方法。15. The first and second conductive films have a thickness of 1000 to 2000.
13. The method according to claim 12, wherein the non-volatile semiconductor element is formed of polysilicon having a thickness of Å.
極端子を同時に形成し、前記感光膜パターンを除去する
工程以後に、 それら結果物が形成された前記基板全面に層間絶縁膜を
形成する工程と、 前記メモリセル形成部の基板表面所定部分と前記抵抗ラ
インの表面所定部分及び前記第１、第２電極端子の表面
所定部分が露出されるように前記層間絶縁膜と前記絶縁
膜を選択食刻してコンタクトホールを形成する工程と、 前記コンタクトホールを含めた前記層間絶縁膜上の所定
部分にビットラインを形成する工程とを更に具備するこ
とを特徴とする請求項１２に記載の非揮発性半導体素子
の製造方法。16. A step of forming the control gate and the second electrode terminal simultaneously and forming an interlayer insulating film on the entire surface of the substrate on which the resultant is formed after the step of removing the photosensitive film pattern; The interlayer insulating film and the insulating film are selectively etched so that a predetermined portion of a substrate surface of the memory cell forming portion, a predetermined portion of a surface of the resistor line, and a predetermined portion of a surface of the first and second electrode terminals are exposed. 13. The nonvolatile semiconductor device according to claim 12, further comprising: a step of forming a contact hole by using a method; and a step of forming a bit line in a predetermined portion on the interlayer insulating film including the contact hole. Device manufacturing method.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980014221A KR100302188B1 (en) | 1998-04-21 | 1998-04-21 | Method for fabricating non-volatile semiconductor device |
| KR1998P-14221 | 1998-04-21 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11307745A true JPH11307745A (en) | 1999-11-05 |
| JP4224149B2 JP4224149B2 (en) | 2009-02-12 |
Family
ID=19536532
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18289798A Expired - Fee Related JP4224149B2 (en) | 1998-04-21 | 1998-06-29 | Nonvolatile semiconductor device manufacturing method |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP4224149B2 (en) |
| KR (1) | KR100302188B1 (en) |
| TW (1) | TW416135B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6583492B2 (en) | 2001-09-26 | 2003-06-24 | Nec Electronics Corporation | Capacitor element having a contact hole structure in an electrode structure |
| KR20040050514A (en) * | 2002-12-10 | 2004-06-16 | 주식회사 하이닉스반도체 | Method of manufacturing analog device |
| CN100438046C (en) * | 2005-10-12 | 2008-11-26 | 台湾积体电路制造股份有限公司 | Non-volatile memory cell and integrated circuit |
| CN103050380A (en) * | 2012-12-20 | 2013-04-17 | 上海宏力半导体制造有限公司 | Semiconductor device forming method |
| CN103077926A (en) * | 2012-12-20 | 2013-05-01 | 上海宏力半导体制造有限公司 | Formation method for semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4367580A (en) * | 1980-03-21 | 1983-01-11 | Texas Instruments Incorporated | Process for making polysilicon resistors |
| JPH0521808A (en) * | 1991-07-09 | 1993-01-29 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
-
1998
- 1998-04-21 KR KR1019980014221A patent/KR100302188B1/en not_active IP Right Cessation
- 1998-06-29 JP JP18289798A patent/JP4224149B2/en not_active Expired - Fee Related
- 1998-07-09 TW TW087111133A patent/TW416135B/en not_active IP Right Cessation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6583492B2 (en) | 2001-09-26 | 2003-06-24 | Nec Electronics Corporation | Capacitor element having a contact hole structure in an electrode structure |
| KR20040050514A (en) * | 2002-12-10 | 2004-06-16 | 주식회사 하이닉스반도체 | Method of manufacturing analog device |
| CN100438046C (en) * | 2005-10-12 | 2008-11-26 | 台湾积体电路制造股份有限公司 | Non-volatile memory cell and integrated circuit |
| CN103050380A (en) * | 2012-12-20 | 2013-04-17 | 上海宏力半导体制造有限公司 | Semiconductor device forming method |
| CN103077926A (en) * | 2012-12-20 | 2013-05-01 | 上海宏力半导体制造有限公司 | Formation method for semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4224149B2 (en) | 2009-02-12 |
| TW416135B (en) | 2000-12-21 |
| KR100302188B1 (en) | 2001-11-22 |
| KR19990080754A (en) | 1999-11-15 |
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