JP2797498B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device such as a thin film transistor and, more particularly, to a method for forming a thin silicon semiconductor layer without damaging the same.

[Summary of the Invention]

The present invention relates to a method for manufacturing a semiconductor device formed on an extremely thin silicon semiconductor layer (hereinafter, referred to as a thin film silicon semiconductor layer) such as a thin film transistor, when a gate electrode is formed on the thin film silicon semiconductor layer. Damage due to over-etching is obtained by forming an insulating layer after leaving a pattern portion made of the same material layer also on the drain region and performing etching at least on the insulating layer with a high selectivity of the insulating layer to the pattern portion. It is intended to form a contact with a source / drain region formed in a thin film silicon semiconductor layer without inducing.

[Prior Art] In order to realize a next-generation SRAM, it is essential to reduce current consumption during standby (when a chip is not selected) and to speed up operation. The memory cell of the SRAM has a load element for supplying current to hold information, and a resistance load made of polycrystalline silicon is mainly used as the load element. But,
The resistance load of polycrystalline silicon is due to the recent high integration of SRAM,
It is becoming impossible to cope with speeding up. This is because it has become more difficult to keep the standby current consumption low as the memory capacity increases. If the current supplied to the storage node is reduced by increasing the value of the load resistance of the memory cell, the current consumption during standby can be reduced.
In this case, the accumulated charges may be lost due to leakage current from the memory cells. In polycrystalline silicon, the magnitude of the cell current with respect to this leakage current can be secured only about two digits. Further, when the integration degree of the SRAM increases, a soft error due to α rays at the time of high-speed operation becomes a serious problem. That is, at the time of high-speed operation, a voltage drop occurs in the storage node because current supply to the storage node has a large time constant.

Therefore, the thin-film PM
OS transistors have been proposed. When turned off, the thin-film PMOS transistor has a higher resistance than polycrystalline silicon,
When turned on, there is an advantage that a current that is 5 to 6 orders of magnitude larger than the leakage current can flow. For example, the Institute of Electrical and Electronics Engineers (IEEE)
Electron Device Meeting (IEDM) Abstracts, pp. 48-59, describe that a thin-film PMOS transistor made of polycrystalline silicon is stacked as a load element on an NMOS driver transistor, and that the gate electrode of the thin-film PMOS transistor is connected to both ends. An SRAM cell in which a stacked capacitor is simultaneously formed by forming an insulating film between transistors has been reported.

[Problems to be solved by the invention]

By the way, when a contact is to be formed in a source / drain region of a PMOS formed in an extremely thin polycrystalline silicon layer as described above, it is extremely difficult to control an etching amount. As overetching proceeds, the contact resistance increases because the thickness of the polycrystalline silicon layer decreases, and in extreme cases, the polycrystalline silicon layer itself may be removed.

Therefore, an object of the present invention is to provide a method for forming a contact even in an extremely thin silicon semiconductor layer such as a thin film transistor formation region without overetching the silicon semiconductor layer.

[Means for solving the problem]

A method for manufacturing a semiconductor device according to the present invention is proposed to achieve the above-described object, and includes a step of forming a material layer containing a silicon semiconductor on a thin-film silicon semiconductor layer formed on a base; Forming a pattern portion facing the gate electrode and the source / drain region by patterning the material layer; forming an insulating layer covering at least the thin-film silicon semiconductor layer; and selecting a ratio of the insulating layer to the pattern portion Forming a contact to the source / drain region by performing at least etching of the insulating layer.

[Action]

In the method for manufacturing a semiconductor device according to the present invention, when a material layer containing a silicon semiconductor is first patterned to form a gate electrode on a thin-film silicon semiconductor layer, a source electrode and a drain region to be contacted in the future are also formed. At the same time, after leaving the pattern portion, an insulating layer is formed. In this state,
When the etching of the insulating layer is started with a large selection ratio of the insulating layer to the pattern portion, the etching rate is rapidly reduced when the surface of the pattern portion is exposed.

Here, when the pattern portion is connected to the source / drain regions, the etching is terminated when the surface of the pattern portion is exposed, and a wiring layer made of a conductive material is formed. At this time, the pattern portion functions as a connection portion between the source / drain region and the wiring layer, and protects the source / drain region from overetching by covering the thickness of the source / drain region. .

Further, when the pattern portion is formed via a gate oxide film, the etching of the pattern portion is further performed by increasing the selectivity of the pattern portion to the gate oxide film at an axial point where the surface of the pattern portion is exposed. Then, the gate oxide film is finally removed by etching. Since the amount of etching of this last gate oxide film is extremely small,
Over-etching of the drain region can be ignored. In this case, the pattern portion functions as a buffer region for preventing the etching of the insulating layer from reaching the source / drain regions rapidly.

In any case, the presence of the pattern portion effectively prevents overetching of the thin film silicon semiconductor layer.

〔Example〕

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 This embodiment is an example in which the manufacturing method of the present invention is applied to the manufacture of a thin-film PMOS transistor. One example of the above manufacturing method,
This will be described with reference to FIGS. 1 (A) to 1 (D).

First, as shown in FIG. 1 (A), for example, polycrystalline silicon is applied to a thickness of about 400 ° on a substrate (1) made of an insulating material such as silicon oxide, and n-type impurities are introduced. An n-type thin film silicon semiconductor layer (2) is formed by patterning in an island shape. Subsequently, a gate oxide film (3) is formed by surface oxidation, and a source / drain region described later [see (7a) and (7b) in FIG. 1 (B)]. The opening (4a),
(4b) is formed.

Next, as shown in FIG. 1 (B), after a material layer containing a silicon semiconductor is deposited on the entire surface to a thickness of about 500 to 1000 °, patterning is performed to form a gate on the gate oxide film (3). An electrode (5), at least the opening (4a),
(4) Pattern portions (6a) and (6b) are formed at positions covering b, and p ⁺ -type source / drain regions (7a) and (7b)
To form Here, as a material containing a silicon semiconductor for forming the material layer, polycrystalline silicon, silicide, polycide, or the like can be applied. The method of forming the source / drain regions (7a) and (7b) is not particularly limited. For example, after forming the gate electrode (5) and the pattern portions (6a) and (6b), the p-type impurity is removed. It suffices to perform ion implantation and further anneal. According to such a process, p-type impurities are first implanted into regions of the n-type thin film silicon semiconductor layer (2) which are not masked by the gate electrode (5) and the pattern portions (6a) and (6b) by ion implantation. The impurity is introduced to form an impurity region.
Subsequently, the p-type impurity introduced into the pattern portions (6a) and (6b) by the annealing diffuses into the thin film silicon semiconductor layer (2) through the openings (4a) and (4b), and the impurity by the previous ion implantation. Source / drain regions (7a) and (7b) are formed in connection with the regions.

Next, as shown in FIG. 1 (C), an insulating layer (8) made of, for example, silicon oxide is formed entirely, and subsequently, the insulating layer (8) is formed facing the formation positions of the pattern portions (6a) and (6b). (8) is opened by anisotropic etching to form contact holes (9a) and (9b). Here, the anisotropic etching is performed by setting the selectivity of the insulating layer (8) to the pattern portions (6a) and (6b) sufficiently large.
When the surfaces of the pattern portions (6a) and (6b) are exposed, the etching rate rapidly decreases. In addition to the above-described setting of the selection ratio, the pattern portions (6a) and (6b) are formed sufficiently thicker than the source / drain regions (7a) and (7b). Even if the determination is slightly delayed, there is almost no risk that the source / drain regions (7a) and (7b) will be over-etched.

Finally, as shown in FIG. 1 (D), after a conductive material is applied to the entire surface, at least the contact holes (9a) and (9b) are covered by patterning to form a wiring layer (10a),
(10b) is formed.

In the conventional general manufacturing method, since the pattern portion as described above does not exist, anisotropic etching of the insulating layer for forming a contact hole must be performed over the entire thickness of the insulating layer. If the end point determination at the time when the surface of the thin film silicon semiconductor layer appears is not performed with extremely high accuracy, serious damage may occur due to overetching, or in an extreme case, a part of the thin film silicon semiconductor layer may be lost. There was.

However, according to the method of this embodiment, the pattern portions (6a) and (6b) connected to the source / drain regions (7a) and (7b) are formed prior to the formation of the insulating layer (8). The etching for forming the contact holes (9a) and (9b) may be completed when the surfaces of the pattern portions (9a) and (9b) are exposed, and the source / drain regions (7a),
It is not necessary to perform until the surface of (7b) appears. Moreover, since the pattern portions (9a) and (9b) are formed sufficiently thick, the source / drain regions (7a) and (7b) may be damaged by over-etching even if the end point determination is slightly delayed. Hardly any.

Embodiment 2 In this embodiment, a thin film PM as described above in Embodiment 1 is used.
14 is another example of a method for manufacturing an OS transistor. The above manufacturing method will be described with reference to FIGS. 2 (A) to 2 (E).

First, as shown in FIG. 2 (A), for example, polycrystalline silicon is applied to a thickness of about 400 ° on a substrate (11) made of an insulating material such as silicon oxide, and n-type impurities are introduced. An n-type thin film silicon semiconductor layer (12) is formed by patterning in an island shape. Subsequently, a gate oxide film (13) is formed by surface oxidation.

Next, as shown in FIG. 2 (B), a material layer containing a silicon semiconductor is deposited on the entire surface to a thickness of about 500 to 1000 °,
Patterning is performed to form a gate electrode (15) and source / drain regions described later ((17a) and (17a) in FIG. 2 (E)).
b) See. ] Pattern portion (16
a) and (16b) are formed. In this state, ion implantation of a p-type impurity is performed, and a portion of the thin film silicon semiconductor layer (12) that is not masked by the gate electrode (15) and the pattern portions (16a) and (16b) is set as ap ⁺ -type impurity region. . These discontinuous p ⁺ -type impurity regions become a part of source / drain regions described later.

Next, as shown in FIG. 2 (C), an insulating layer (18) made entirely of silicon oxide or the like is formed, and then the insulating layer (18) is formed facing the formation positions of the pattern portions (16a) and (16b). Open (18) by anisotropic etching and contact hole (19
a) and (19b) are formed. Here, the anisotropic etching is performed on the insulating layer (1) for the pattern portions (16a) and (16b).
Since the selection ratio of 8) is set to be sufficiently large, the etching rate rapidly decreases when the surfaces of the pattern portions (16a) and (16b) are exposed. Further, in addition to the setting of the selection ratio as described above, the pattern portions (16a) and (16b) are formed sufficiently thicker than the thin-film silicon semiconductor layer (12) (particularly, the source / drain regions later). Therefore, even if the end point determination is slightly delayed, there is almost no risk that the thin film silicon semiconductor layer (12) will be over-etched.

Next, as shown in FIG. 2 (D), the pattern portion (16
a) and (16b) are etched, and contact holes (19a) and (19b) are deeply opened. This etching stops at the surface of the gate oxide film (13).

Further, as shown in FIG. 2 (E), the gate oxide film (13) is etched under the condition of performing anisotropic etching of silicon oxide, and the contact hole (19) is etched.
Complete a) and (19b). Here, only the extremely thin gate oxide film (13) is removed, and since the etching amount is small, over-etching of the thin silicon semiconductor layer (12) is negligible. When ion implantation of a p-type impurity is performed again in this state, the p-type impurity is introduced into the thin-film silicon semiconductor layer (12) through the contact holes (19a) and (19b), and the pattern portions (16a) and ( The region immediately below 16b) is also ap ⁺ -type impurity region. Subsequently, when annealing is performed, these discontinuous impurity regions are connected by diffusion, and p ⁺ -type source / drain regions (17a) and (17b) are formed. Finally, after a conductive material is applied to the entire surface, at least the contact holes (19
Wiring layers (20a) and (20b) are formed to cover a) and (19b).

In the method of this embodiment, the pattern portions (16a) and (16b) function as buffer regions for preventing the etching of the insulating layer (18) from reaching the thin film silicon semiconductor layer (2) rapidly. .

〔The invention's effect〕

As is clear from the above description, by applying the present invention, it is possible to form a contact with a thin-film silicon semiconductor layer, which was conventionally extremely difficult to form, and to manufacture a highly reliable semiconductor device such as a thin film transistor. It becomes possible. In the manufacturing method of the present invention, since the formation of the pattern portion which is the point is performed simultaneously with the formation of the gate electrode, it can be easily carried out by changing the conventional mask pattern, and is extremely excellent in economical efficiency. .

[Brief description of the drawings]

1 (A) to 1 (D) are schematic sectional views showing an example of a method of manufacturing a semiconductor device according to the present invention in the order of steps, and FIG. 1 (A) shows a thin film silicon semiconductor layer and a gate oxide. FIG. 1 (B) is a process for forming a gate electrode, a pattern portion, and a source / drain region, FIG. 1 (C) is a process for forming an insulating layer and a contact hole, FIG. 1 ( D) shows the steps of forming the wiring layer, respectively. FIG. 2 (A) to FIG. 2 (E)
FIG. 2 is a schematic cross-sectional view showing another example of a method of manufacturing a semiconductor device according to the present invention in the order of steps, and FIG. 2A is a step of forming a thin silicon semiconductor layer and a gate oxide film, and FIG. FIG. 2C shows a step of forming a gate electrode, a pattern section and an impurity region, FIG. 2C shows a step of forming an insulating layer and a step of forming a contact hole by etching the insulating layer, and FIG. FIG. 2E shows a step of forming a contact hole by etching a gate oxide film and a step of forming a source / drain region and a wiring layer, respectively. 1,11 Base 2,12 Thin-film silicon semiconductor layer 5,15 Gate electrode 6a, 6b, 16a, 16b Pattern part 7a, 7b, 17a, 17b Source / drain region 8,18 … Insulating layer 9a, 9b, 19a, 19b …… Contact hole

Claims (1)

(57) [Claims] 1. A step of forming a material layer containing a silicon semiconductor on a thin film silicon semiconductor layer formed on a substrate, and forming a pattern portion facing a gate electrode and source / drain regions by patterning the material layer. A step of forming an insulating layer covering at least the thin-film silicon semiconductor layer; and performing at least etching of the insulating layer with a high selectivity of the insulating layer with respect to the pattern portion, to the source / drain region. A method of manufacturing a semiconductor device, comprising the step of forming a contact.