JP2001210834A - Method of forming gate insulating film for semiconductor element - Google Patents
Method of forming gate insulating film for semiconductor elementInfo
- Publication number
- JP2001210834A JP2001210834A JP2000368359A JP2000368359A JP2001210834A JP 2001210834 A JP2001210834 A JP 2001210834A JP 2000368359 A JP2000368359 A JP 2000368359A JP 2000368359 A JP2000368359 A JP 2000368359A JP 2001210834 A JP2001210834 A JP 2001210834A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- gate insulating
- forming
- region
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 14
- 230000003647 oxidation Effects 0.000 claims abstract description 14
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 26
- 238000002955 isolation Methods 0.000 claims description 9
- 239000003963 antioxidant agent Substances 0.000 claims 2
- 230000003078 antioxidant effect Effects 0.000 claims 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 12
- 238000000206 photolithography Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子のゲー
ト絶縁膜形成方法に関し、特に、１つの半導体基板に集
積した電気的特性が相異する半導体素子のゲート絶縁膜
形成方法に関する。The present invention relates to a method of forming a gate insulating film of a semiconductor device, and more particularly to a method of forming a gate insulating film of a semiconductor device having different electrical characteristics integrated on one semiconductor substrate.
【０００２】[0002]
【従来の技術】一般に、制御機能及び駆動機能を一つの
チップ内に組み合わせたスマート集積回路は、出力部
が、約１５〜８０Ｖの高電圧で動作する高電圧（high
power）トランジスタ（以下、高電圧素子と称す）から
構成され、ロジック部が、約５Ｖ以下の低電圧で動作す
る通常のトランジスタ（以下、低電圧素子と称す）から
構成される。2. Description of the Related Art Generally, in a smart integrated circuit in which a control function and a driving function are combined in one chip, an output section operates at a high voltage of about 15 to 80V.
power) transistor (hereinafter, referred to as a high-voltage element), and the logic unit includes a normal transistor (hereinafter, referred to as a low-voltage element) that operates at a low voltage of about 5 V or less.
【０００３】このようなスマート集積回路は、主に、液
晶表示装置（Liquid Crystal Display；ＬＣＤ）のよ
うな表示装置及びＨＤＴＶ（High Definition TV）な
どの駆動用に利用される。そして、前記高電圧素子と、
低電圧素子とは、構造及び製造方法が相異し、特に、そ
れらのゲート絶縁膜の厚さが相異する。即ち、高電圧素
子の場合、ゲート電極に高電圧が印加されるため、ゲー
ト絶縁膜が薄いと、破壊される恐れがある。そこで、高
い印加電圧にも耐え得るように、高電圧素子のゲート絶
縁膜を当該印加電圧に応じて、低電圧素子のゲート絶縁
膜よりも厚く形成する必要がある。[0003] Such a smart integrated circuit is mainly used for driving a display device such as a liquid crystal display device (Liquid Crystal Display; LCD) and a HDTV (High Definition TV). And the high voltage element;
The structure and the manufacturing method are different from those of the low-voltage element, and particularly, the thicknesses of their gate insulating films are different. That is, in the case of a high-voltage element, since a high voltage is applied to the gate electrode, the thin gate insulating film may be broken. Therefore, the gate insulating film of the high-voltage element needs to be formed thicker than the gate insulating film of the low-voltage element according to the applied voltage so as to withstand a high applied voltage.
【０００４】例えば、通常のスマート集積回路におい
て、高電圧素子のゲート絶縁膜は、一般に、約４００Å
の厚さに形成されるのに対して、低電圧素子のゲート絶
縁膜は、約２００Åの厚さに形成される。このため、高
電圧素子のゲート絶縁膜及び低電圧素子のゲート絶縁膜
を同時に形成することができない。このように構成され
る従来のスマート集積回路素子のゲート絶縁膜の製造方
法を、図２（Ａ）〜（Ｃ）を参照しながら説明する。
尚、図２は、従来のスマート集積回路素子の構造を概略
的に示した図であって、実際の構造及び寸法を示してい
るものではない。For example, in a typical smart integrated circuit, a gate insulating film of a high-voltage element generally has a thickness of about 400 Å.
Whereas the gate insulating film of the low-voltage element is formed to a thickness of about 200 °. Therefore, the gate insulating film of the high-voltage element and the gate insulating film of the low-voltage element cannot be formed simultaneously. A method for manufacturing a gate insulating film of a conventional smart integrated circuit device configured as described above will be described with reference to FIGS.
FIG. 2 schematically shows the structure of a conventional smart integrated circuit device, and does not show the actual structure and dimensions.
【０００５】先ず、図２（Ａ）に示したように、半導体
基板１００、即ち、ウェーハの上面全体に、熱酸化法に
より形成される二酸化シリコン酸化膜からなる約３００
Åの第１ゲート絶縁膜１１０を形成する。半導体基板１
００は、図２（Ａ）に示したように、素子分離領域１０
０ｃで区分された高電圧素子形成領域１００ａと、低電
圧素子形成領域１００ｂとを有する。前記半導体基板１
００の所定深さには、絶縁膜１００ｄが形成されて、素
子分離特性を向上させる機能を奏する。且つ、前記高電
圧素子形成領域１００ａ内には、不純物ウェル１０１、
１０２が形成されている。First, as shown in FIG. 2A, the semiconductor substrate 100, that is, the entire upper surface of the wafer, is formed of a silicon dioxide oxide film formed by a thermal oxidation method.
The first gate insulating film 110 of Å is formed. Semiconductor substrate 1
00 denotes an element isolation region 10 as shown in FIG.
It has a high-voltage element formation region 100a and a low-voltage element formation region 100b, which are divided by 0c. The semiconductor substrate 1
At a predetermined depth of 00, an insulating film 100d is formed, and has a function of improving element isolation characteristics. In addition, the impurity well 101,
102 are formed.
【０００６】次いで、図２（Ｂ）に示したように、高電
圧素子形成領域１００ａ及び素子分離領域１００ｃの上
面にフォトレジスト膜パターン１１１を形成した後、前
記低電圧素子形成領域１００ｂの上面の第１ゲート絶縁
膜１１０を湿式食刻法を利用して除去する。さらに、前
記高電圧素子形成領域１００ａ及び素子分離領域１００
ｃの上面のフォトレジスト膜パターン１１１を除去す
る。Next, as shown in FIG. 2B, after a photoresist film pattern 111 is formed on the upper surfaces of the high-voltage element formation region 100a and the element isolation region 100c, the upper surface of the low-voltage element formation region 100b is formed. The first gate insulating film 110 is removed using a wet etching method. Further, the high-voltage element formation region 100a and the element isolation region 100
The photoresist film pattern 111 on the upper surface of c is removed.
【０００７】その後、前記高電圧素子形成領域１００ａ
及び素子分離領域１００ｃ上の第１ゲート絶縁膜１１０
と、低電圧素子形成領域１００ｂの上面全体に、熱酸化
法を施して二酸化シリコン酸化膜からなる第２ゲート絶
縁膜１１２を形成する。こうして、図２（Ｃ）に示した
ように、従来のスマート集積回路素子のゲート絶縁膜の
製造が完了する。Thereafter, the high-voltage element forming region 100a
And first gate insulating film 110 on element isolation region 100c
Then, a second gate insulating film 112 made of a silicon dioxide oxide film is formed by performing a thermal oxidation method on the entire upper surface of the low voltage element formation region 100b. Thus, as shown in FIG. 2C, the fabrication of the gate insulating film of the conventional smart integrated circuit device is completed.
【０００８】前記第２ゲート絶縁膜１１２は、素子上面
に渡って同一工程で形成されるのにも関わらず、例え
ば、低電圧素子形成領域１００ｂの上面では約２００Å
の厚さに形成されるのに対し、高電圧素子形成領域１０
０ａの上面では約１００Åの厚さに形成され、各領域上
で異なる厚さとなる。結果的に、高電圧素子形成領域１
００ａの上面には、約３００Åの第１ゲート絶縁膜１１
０と、約１００Åの第２ゲート絶縁膜１１２が形成され
て、約４００Å の厚さのゲート絶縁膜が形成される。
このように形成される理由は、前記高電圧素子形成領域
１００ａ上に形成された第１絶縁膜１１０がシリコンか
らなる半導体基板の酸化を抑制することによって、高電
圧素子形成領域１００ａに対応する第２ゲート絶縁膜１
１２の成長速度が遅くなるためである。Although the second gate insulating film 112 is formed in the same process over the upper surface of the element, for example, about 200 ° on the upper surface of the low-voltage element forming region 100b.
Of the high-voltage element formation region 10
The upper surface of Oa is formed to a thickness of about 100 °, and has a different thickness on each region. As a result, the high voltage element formation region 1
On the upper surface of the first gate insulating film 11 of about 300 °
A second gate insulating film 112 having a thickness of about 0 ° and about 100 ° is formed, and a gate insulating film having a thickness of about 400 ° is formed.
The reason for this is that the first insulating film 110 formed on the high-voltage element formation region 100a suppresses the oxidation of the semiconductor substrate made of silicon, so that the first insulation film 110 corresponding to the high-voltage element formation region 100a can be formed. 2 gate insulating film 1
This is because the growth rate of No. 12 becomes slow.
【０００９】図２（Ｃ）に示したように、ゲート絶縁膜
の製造が完了すると、該ゲート絶縁膜の上面にゲート電
極の形成など、高電圧素子及び低電圧素子の製造を行う
が、本発明の趣旨から外れるため説明を省略する。As shown in FIG. 2C, when the manufacture of the gate insulating film is completed, the manufacture of a high-voltage element and a low-voltage element such as formation of a gate electrode on the upper surface of the gate insulating film is performed. The description is omitted because it departs from the spirit of the invention.
【００１０】[0010]
【発明が解決しようとする課題】然るに、このような従
来のスマート集積回路素子のゲート絶縁膜形成方法にお
いては、第１ゲート絶縁膜を形成した後、低電圧素子形
成領域の上面の第１ゲート絶縁膜を湿式食刻法を施して
除去する過程で、低電圧素子のアクティブ領域となる半
導体基板上面の損傷が発生して、素子の特性が低下する
という不都合な点があった。However, in such a conventional method for forming a gate insulating film of a smart integrated circuit device, after forming the first gate insulating film, the first gate on the upper surface of the low voltage element forming region is formed. In the process of removing the insulating film by wet etching, the upper surface of the semiconductor substrate, which is the active region of the low-voltage element, is damaged, and the characteristics of the element are disadvantageously deteriorated.
【００１１】また、第２ゲート絶縁膜の形成工程では、
高電圧素子形成領域の上面に第１ゲート絶縁膜が形成さ
れた状態で第２ゲート絶縁膜を形成するため、高電圧素
子形成領域のゲート絶縁膜の厚さを調節し難いという不
都合な点があった。そこで、本発明は、このような従来
の問題点に鑑みてなされたもので、その目的は、第１素
子形成領域内のアクティブ領域となる半導体基板部位の
損傷を防止でき、ゲート絶縁膜の厚さを容易に調節し得
る半導体素子のゲート絶縁膜形成方法を提供することに
ある。In the step of forming the second gate insulating film,
Since the second gate insulating film is formed in a state where the first gate insulating film is formed on the upper surface of the high voltage element forming region, it is difficult to adjust the thickness of the gate insulating film in the high voltage element forming region. there were. Therefore, the present invention has been made in view of such conventional problems, and an object of the present invention is to prevent a semiconductor substrate portion serving as an active region in a first element formation region from being damaged, and to reduce the thickness of a gate insulating film. It is an object of the present invention to provide a method of forming a gate insulating film of a semiconductor device, which can easily adjust the thickness.
【００１２】[0012]
【課題を解決するための手段】このため、請求項１に係
る発明は、素子分離領域により分離された第１及び第２
素子形成領域を有する半導体基板の上面全体に第１ゲー
ト絶縁膜を形成する工程と、前記第１素子形成領域の前
記第１ゲード絶縁膜上面にのみ酸化防止マスクパターン
を形成する工程と、前記酸化防止マスクパターンをマス
クとして、前記第２素子形成領域の前記第１ゲート絶縁
膜上面に第２ゲート絶縁膜を形成する工程と、前記酸化
防止マスクパターンを除去する工程と、を備えたことを
特徴とした。For this reason, the invention according to claim 1 is based on the first and second elements separated by an element isolation region.
Forming a first gate insulating film over the entire upper surface of the semiconductor substrate having an element forming region, forming an oxidation preventing mask pattern only on the upper surface of the first gate insulating film in the first element forming region; Forming a second gate insulating film on the upper surface of the first gate insulating film in the second element formation region using an anti-oxidation mask pattern as a mask; and removing the oxidation prevention mask pattern. And
【００１３】また、請求項２に係る発明は、前記第１素
子形成領域は、低電圧素子を形成するための領域で、前
記第２素子形成領域は、高電圧素子を形成するための領
域であることを特徴とした。また、請求項３に係る発明
は、前記第１ゲート絶縁膜及び第２ゲート絶縁膜は、熱
酸化法で形成することを特徴とした。Further, in the invention according to claim 2, the first element formation region is a region for forming a low voltage element, and the second element formation region is a region for forming a high voltage element. There was a feature. The invention according to claim 3 is characterized in that the first gate insulating film and the second gate insulating film are formed by a thermal oxidation method.
【００１４】また、請求項４に係る発明は、前記酸化防
止マスクパターンは、シリコン窒化膜であることを特徴
とした。また、請求項５に係る発明は、素子特性の相異
する複数の素子を集積したスマート集積回路の素子のゲ
ート絶縁膜を形成するために適用することを特徴とし
た。Further, the invention according to claim 4 is characterized in that the oxidation preventing mask pattern is a silicon nitride film. The invention according to claim 5 is characterized in that it is applied to form a gate insulating film of a device of a smart integrated circuit in which a plurality of devices having different device characteristics are integrated.
【００１５】[0015]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を用いて説明する。本発明に係る半導体素子のゲ
ート絶縁膜形成方法をスマート集積回路に適用した一実
施形態を、図１（Ａ）〜（Ｅ）を参照しながら以下に説
明する。図１（Ａ）に示したように、半導体基板２００
は、従来と同様に、素子分離領域２０１で区分された第
１素子形成領域としての低電圧素子形成領域２０２と、
第２素子形成領域としての高電圧素子形成領域２０３と
を備える。また、半導体基板２００の所定深さには、絶
縁膜２０８が形成される。さらに、高電圧素子形成領域
２０３内には、不純物ウェル２０９、２１０が形成され
ている。Embodiments of the present invention will be described below with reference to the drawings. One embodiment in which the method for forming a gate insulating film of a semiconductor device according to the present invention is applied to a smart integrated circuit will be described below with reference to FIGS. As shown in FIG. 1A, the semiconductor substrate 200
Is a low-voltage element formation region 202 as a first element formation region divided by an element isolation region 201,
And a high-voltage element formation region 203 as a second element formation region. At a predetermined depth of the semiconductor substrate 200, an insulating film 208 is formed. Further, impurity wells 209 and 210 are formed in the high voltage element formation region 203.
【００１６】次に、前記半導体基板２００の上面に、熱
酸化法を施して第１ゲート絶縁膜２０４を、例えば約２
００Åの厚さに形成する。この場合、前記第１ゲート絶
縁膜２０４は、熱酸化法によりシリコン酸化膜で形成す
ることが好ましい。次に、図１（Ｂ）に示したように、
前記第１ゲート絶縁膜２０４の上面にシリコン窒化膜２
０５を形成する。Next, a first gate insulating film 204 is formed on the upper surface of the semiconductor
It is formed to a thickness of 00 °. In this case, it is preferable that the first gate insulating film 204 is formed of a silicon oxide film by a thermal oxidation method. Next, as shown in FIG.
A silicon nitride film 2 is formed on the upper surface of the first gate insulating film 204.
05 is formed.
【００１７】次に、前記シリコン窒化膜２０５の上面に
フォトレジスト膜を形成した後、フォトリソグラフィ工
程を施して、図１（Ｃ）に示したように、低電圧素子形
成領域２０２の上面にのみフォトレジスト膜を残し、フ
ォトレジストパターン２０６を形成し、前記フォトレジ
ストパターン２０６をマスクとして前記高電圧素子形成
領域２０３上面のシリコン窒化膜２０５を部分的に除去
してシリコン窒化膜パターン２０５ａを形成する。その
後、前記フォトレジストパターン２０６を除去し、図１
（Ｄ）に示したように、前記シリコン窒化膜パターン２
０５ａを酸化防止マスクパターンとして、前記高電圧素
子形成領域２０３上の第１ゲート絶縁膜２０４の上面の
みに第２ゲート絶縁膜２０７を形成する。このとき、前
記第２ゲート絶縁膜２０７は、熱酸化法を施して二酸化
シリコン膜を形成することが好ましい。このようにする
と、前記シリコン窒化膜パターン２０５ａにより、低電
圧素子形成領域２０２の上面の第１ゲート絶縁膜２０４
の酸化が防止されるため、低電圧素子の素子特性変化を
考慮することなく、高電圧素子の特性のみを考慮して充
分な厚さに第２ゲート絶縁膜２０７を形成することがで
きる。Next, after a photoresist film is formed on the upper surface of the silicon nitride film 205, a photolithography process is performed, and only the upper surface of the low-voltage element forming region 202 is formed as shown in FIG. A photoresist pattern 206 is formed while leaving the photoresist film, and the silicon nitride film 205 on the upper surface of the high voltage element formation region 203 is partially removed using the photoresist pattern 206 as a mask to form a silicon nitride film pattern 205a. . Thereafter, the photoresist pattern 206 is removed, and FIG.
As shown in (D), the silicon nitride film pattern 2
The second gate insulating film 207 is formed only on the upper surface of the first gate insulating film 204 on the high voltage element forming region 203 using the mask 05a as an oxidation prevention mask pattern. At this time, the second gate insulating film 207 is preferably formed by performing a thermal oxidation method to form a silicon dioxide film. Thus, the first gate insulating film 204 on the upper surface of the low-voltage element forming region 202 is formed by the silicon nitride film pattern 205a.
Therefore, the second gate insulating film 207 can be formed to a sufficient thickness by considering only the characteristics of the high-voltage element without considering changes in the element characteristics of the low-voltage element.
【００１８】即ち、前記高電圧素子形成領域２０３上の
ゲート絶縁膜の全体厚さが、４００Åである場合、第１
ゲート絶縁膜２０４で既に２００Åが形成されているた
め、２００Åの第２ゲート絶縁膜２０７を更に追加して
形成すれば良い。最後に、湿式食刻法を施して前記シリ
コン窒化膜パターン２０５ａを除去して、図１（Ｅ）に
示したように、半導体素子のゲート絶縁膜形成工程を完
了する。That is, when the total thickness of the gate insulating film on the high voltage element forming region 203 is 400 °, the first
Since 200 ° has already been formed in the gate insulating film 204, a second gate insulating film 207 of 200 ° may be additionally formed. Finally, the silicon nitride film pattern 205a is removed by a wet etching method, and as shown in FIG. 1E, the step of forming the gate insulating film of the semiconductor device is completed.
【００１９】尚、本実施形態では、スマート集積回路に
適用した場合の半導体素子のゲート絶縁膜形成方法につ
いて示したが、適用回路はこれに限らず、電気的特性が
相異する複数の半導体素子を１つの半導体基板に集積し
た回路であればよい。In this embodiment, the method of forming a gate insulating film of a semiconductor device when applied to a smart integrated circuit has been described. However, the applied circuit is not limited to this, and a plurality of semiconductor devices having different electrical characteristics are applicable. Any circuit may be used as long as it is integrated on one semiconductor substrate.
【００２０】[0020]
【発明の効果】以上説明したように、本発明によれば、
１つのチップ内に集積した第１、第２素子形成領域の各
ゲート絶縁膜の厚さを、各素子特性に合わせて調節でき
るため、半導体素子の信頼性を向上できる。さらに、従
来のようにゲート絶縁膜を食刻する必要がないので、半
導体基板表面の損傷を防止することが可能となるため、
半導体素子の信頼性を向上できる。As described above, according to the present invention,
Since the thickness of each gate insulating film in the first and second element formation regions integrated in one chip can be adjusted according to each element characteristic, the reliability of the semiconductor element can be improved. Further, since it is not necessary to etch the gate insulating film as in the conventional case, it is possible to prevent the semiconductor substrate surface from being damaged.
The reliability of the semiconductor element can be improved.
【図１】本発明による半導体素子のゲート絶縁膜形成方
法の一実施形態を説明する工程図FIG. 1 is a process diagram illustrating one embodiment of a method for forming a gate insulating film of a semiconductor device according to the present invention.
【図２】従来技術による半導体素子のゲート絶縁膜形成
方法を説明する工程図FIG. 2 is a process diagram illustrating a method for forming a gate insulating film of a semiconductor device according to a conventional technique.
２００ 半導体基板 ２０１ 素子分離領域 ２０２ 低電圧素子形成領域 ２０３ 高電圧素子形成領域 ２０４ 第１ゲート絶縁膜 ２０５ シリコン窒化膜 ２０５ａ シリコン窒化膜パターン ２０６ フォトレジストパターン ２０７ 第２ゲート絶縁膜 Reference Signs List 200 semiconductor substrate 201 device isolation region 202 low-voltage device formation region 203 high-voltage device formation region 204 first gate insulating film 205 silicon nitride film 205a silicon nitride film pattern 206 photoresist pattern 207 second gate insulating film
Claims (5)
２素子形成領域を有する半導体基板の上面全体に第１ゲ
ート絶縁膜を形成する工程と、 前記第１素子形成領域の前記第１ゲード絶縁膜上面にの
み酸化防止マスクパターンを形成する工程と、 前記酸化防止マスクパターンをマスクとして、前記第２
素子形成領域の前記第１ゲート絶縁膜上面に第２ゲート
絶縁膜を形成する工程と、 前記酸化防止マスクパターンを除去する工程と、を備え
たことを特徴とする半導体素子のゲート絶縁膜形成方
法。A step of forming a first gate insulating film over an entire upper surface of a semiconductor substrate having first and second element formation regions separated by an element isolation region; and a step of forming a first gate insulating film in the first element formation region. Forming an antioxidant mask pattern only on the upper surface of the insulating film; and using the antioxidant mask pattern as a mask,
A method for forming a gate insulating film for a semiconductor device, comprising: forming a second gate insulating film on an upper surface of the first gate insulating film in an element forming region; and removing the oxidation preventing mask pattern. .
成するための領域で、前記第２素子形成領域は、高電圧
素子を形成するための領域であることを特徴とする請求
項１に記載の半導体素子のゲート絶縁膜形成方法。2. The device according to claim 1, wherein the first element forming region is a region for forming a low voltage element, and the second element forming region is a region for forming a high voltage element. 2. The method for forming a gate insulating film of a semiconductor device according to item 1.
膜は、熱酸化法で形成することを特徴とする請求項１ま
たは２に記載の半導体素子のゲート絶縁膜形成方法。3. The method according to claim 1, wherein the first gate insulating film and the second gate insulating film are formed by a thermal oxidation method.
窒化膜であることを特徴とする請求項１〜３のいずれか
１つに記載の半導体素子のゲート絶縁膜形成方法。4. The method according to claim 1, wherein the oxidation preventing mask pattern is a silicon nitride film.
スマート集積回路の素子のゲート絶縁膜を形成するため
に適用することを特徴とする請求項１〜４のいずれか１
つに記載の半導体素子のゲート絶縁膜形成方法。5. The method according to claim 1, wherein the device is applied to form a gate insulating film of a device of a smart integrated circuit in which a plurality of devices having different device characteristics are integrated.
7. A method for forming a gate insulating film of a semiconductor device according to any one of the above.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR55769/1999 | 1999-12-08 | ||
| KR1019990055769A KR100336779B1 (en) | 1999-12-08 | 1999-12-08 | Fabrication method of making a gate insulation film for semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001210834A true JP2001210834A (en) | 2001-08-03 |
Family
ID=19624232
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000368359A Pending JP2001210834A (en) | 1999-12-08 | 2000-12-04 | Method of forming gate insulating film for semiconductor element |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2001210834A (en) |
| KR (1) | KR100336779B1 (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003094248A1 (en) | 2002-05-02 | 2003-11-13 | Josuke Nakata | Light-receiving panel or light-emitting panel, and manufacturing method thereof |
| JP2005303037A (en) * | 2004-04-13 | 2005-10-27 | Ricoh Co Ltd | Semiconductor device and its manufacturing method |
| US7214557B2 (en) | 2003-10-24 | 2007-05-08 | Kyosemi Corporation | Light receiving or light emitting modular sheet and process for producing the same |
| US7220997B2 (en) | 2002-06-21 | 2007-05-22 | Josuke Nakata | Light receiving or light emitting device and itsd production method |
| US7238968B2 (en) | 2001-08-13 | 2007-07-03 | Josuke Nakata | Semiconductor device and method of making the same |
| US7244998B2 (en) | 2001-08-13 | 2007-07-17 | Josuke Nakata | Light-emitting or light-receiving semiconductor module and method of its manufacture |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100705231B1 (en) * | 2001-12-11 | 2007-04-06 | 매그나칩 반도체 유한회사 | Method of manufacturing a semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2819302B2 (en) * | 1989-04-26 | 1998-10-30 | 富士通株式会社 | Method for manufacturing semiconductor device |
-
1999
- 1999-12-08 KR KR1019990055769A patent/KR100336779B1/en not_active IP Right Cessation
-
2000
- 2000-12-04 JP JP2000368359A patent/JP2001210834A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7238968B2 (en) | 2001-08-13 | 2007-07-03 | Josuke Nakata | Semiconductor device and method of making the same |
| US7244998B2 (en) | 2001-08-13 | 2007-07-17 | Josuke Nakata | Light-emitting or light-receiving semiconductor module and method of its manufacture |
| US7602035B2 (en) | 2001-10-19 | 2009-10-13 | Josuke Nakata | Light emitting or light receiving semiconductor module and method for manufacturing same |
| WO2003094248A1 (en) | 2002-05-02 | 2003-11-13 | Josuke Nakata | Light-receiving panel or light-emitting panel, and manufacturing method thereof |
| US7238966B2 (en) | 2002-05-02 | 2007-07-03 | Josuke Nakata | Light-receiving panel or light-emitting panel, and manufacturing method thereof |
| US7220997B2 (en) | 2002-06-21 | 2007-05-22 | Josuke Nakata | Light receiving or light emitting device and itsd production method |
| KR100874647B1 (en) * | 2002-09-17 | 2008-12-17 | 엘지디스플레이 주식회사 | LCD and its manufacturing method |
| US7387400B2 (en) | 2003-04-21 | 2008-06-17 | Kyosemi Corporation | Light-emitting device with spherical photoelectric converting element |
| US7378757B2 (en) | 2003-06-09 | 2008-05-27 | Kyosemi Corporation | Power generation system |
| US7214557B2 (en) | 2003-10-24 | 2007-05-08 | Kyosemi Corporation | Light receiving or light emitting modular sheet and process for producing the same |
| JP2005303037A (en) * | 2004-04-13 | 2005-10-27 | Ricoh Co Ltd | Semiconductor device and its manufacturing method |
| JP4518830B2 (en) * | 2004-04-13 | 2010-08-04 | 株式会社リコー | Manufacturing method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010054796A (en) | 2001-07-02 |
| KR100336779B1 (en) | 2002-05-16 |
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