KR100265824B1 - Method for fabricating transistor of ldd structure - Google Patents
Method for fabricating transistor of ldd structure Download PDFInfo
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- KR100265824B1 KR100265824B1 KR1019930011745A KR930011745A KR100265824B1 KR 100265824 B1 KR100265824 B1 KR 100265824B1 KR 1019930011745 A KR1019930011745 A KR 1019930011745A KR 930011745 A KR930011745 A KR 930011745A KR 100265824 B1 KR100265824 B1 KR 100265824B1
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- 238000000034 method Methods 0.000 title claims abstract description 14
- 238000005468 ion implantation Methods 0.000 claims abstract description 22
- 125000006850 spacer group Chemical group 0.000 claims abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 5
- 238000002425 crystallisation Methods 0.000 abstract 1
- 230000008025 crystallization Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 7
- 238000001953 recrystallisation Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 2
- 210000003050 axon Anatomy 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 210000000056 organ Anatomy 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
제 1 도는 본 발명의 바람직한 실시예에 따른 LDD 구조의 트랜지스터 제조방법을 나타낸 공정 단면도.1 is a cross-sectional view illustrating a method of manufacturing a transistor having an LDD structure according to a preferred embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘기관 2, 6 : 절연막1: silicon organ 2, 6: insulating film
3 : 게이트전극 4 : 실리콘질화막3: gate electrode 4: silicon nitride film
5, 7 : 이온주입영역5, 7: ion implantation zone
본 발명은 반도체 소자의 제조공정중 트랜지스터 제조방법에 관한 것으로, 특히 LDD(Lightly Doped Drain : 이하 LDD라 칭함) 구조의 접합을 갖는 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor manufacturing method during a semiconductor device manufacturing process, and more particularly to a transistor manufacturing method having a junction of a LDD (Lightly Doped Drain) structure.
일반적으로 LDD 구조 형성은 소스와 드레인 영역이 얕아짐에 따라 발생되는 핫캐리어효과(Hot Carrier Effect) 를 줄이기 위하여 사용되는 방법이다.In general, LDD structure formation is a method used to reduce the hot carrier effect caused by the shallow source and drain regions.
종래의 LDD 구조 형성방법은 저농도 N 형(N) 불순물을 이온주입한 다음 측벽 스페이서를 이용하여 고농도 N형(N) 불순물을 이온주입하는 방법으로, 이온주입시 실리콘기판 상에 아몰포스(amorphous) 층이 형성되므로 재결정화를 위한 열처리 공정이 수반되어야 한다.Conventional LDD structure formation method is low concentration N type (N ) High concentration N-type (N) by ion implantation of impurities ) As a method of ion implantation of impurities, an amorphous layer is formed on a silicon substrate during ion implantation, and thus a heat treatment process for recrystallization must be accompanied.
이때, 소자의 집적도가 높아짐에 따라 소스/드레인의 얕은 접합 형성을 위해 재결정화를 위한 열처리 온도는 낮게 조정되어야 한다.At this time, as the degree of integration of the device increases, the heat treatment temperature for recrystallization must be lowered to form a shallow junction of the source / drain.
그러나 열처리시의 낮은 온도는 이온 주입영역에 남아 있는 결함의 제거에 불충분하여 누설전류 증가와 소자의 특성 저하를 요인으로 작용하는 문제점이 따랐다.However, the low temperature during the heat treatment is insufficient to remove the defects remaining in the ion implantation region, resulting in an increase in leakage current and deterioration of device characteristics.
본 발명은 상기 문제점을 해결하기 위하여 안출된 것으로서, 소스/드레인 이온주입시 실리콘기판에 발생된 결정결함을 줄이고, 이에 의해 후속 재결정화 열처리시 그 온도를 낮게 가져갈 수 있어 얕은 접합의 형성이 가능한 LDD 구조의 트랜지스터 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, LDD which can reduce the crystal defects generated in the silicon substrate during the source / drain ion implantation, thereby bringing the temperature lower during subsequent recrystallization heat treatment can form a shallow junction It is an object of the present invention to provide a method of manufacturing a transistor having a structure.
상기 목적을 달성하기 위한 본 발명은, LDD 구조의 트랜지스터 제조방법에 있어서, 실리콘기판 상에 게이트산화막(SiO2)을 형성하는 제 1 단계; 상기 게이트산화막 상에 게이트전극 패턴을 형성하되, 상기 게이트전극 패턴으로 덮힌 이외의 부분에서도 상기 실리콘기판 상에 상기 게이트산화막을 잔류시키는 제 2 단계; 상기 게이트전극 및 상기 잔류 게이트산화막을 덮도록 상기 제 2 단계가 완료된 결과물 표면을 따라 상기 게이트산화막 보다 고결합에너지를 갖는 실리콘질화막(Si3N4)을 형성하는 제 3 단계; 저농도 불순물 이온주입을 실시하고 전체구조 상부에 절연막을 증착한 다음 식각하여 측벽 스페이서 절연막을 형성한 후 고농도 불순물 이온주입을 실시하여 LDD구조의 소스/드레인 접합을 형성하는 제 4 단계; 상기 측벽 스페이서 절연막과 상기 실리콘질화막을 제거하는 제 5 단계; 및 상기 이온주입시 발생된 비정질 층을 재결정화하기 위한 열처리를 실시하는 제 6 단계를 포함하여 이루어진 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a transistor having an LDD structure, the method comprising: forming a gate oxide film (SiO 2 ) on a silicon substrate; Forming a gate electrode pattern on the gate oxide layer, and leaving the gate oxide layer on the silicon substrate in a portion other than that covered by the gate electrode pattern; A third step of forming a silicon nitride film (Si 3 N 4 ) having a higher bonding energy than the gate oxide film along a surface of the resultant product in which the second step is completed to cover the gate electrode and the remaining gate oxide film; A fourth step of forming a source / drain junction of an LDD structure by performing a low concentration impurity ion implantation, depositing an insulating film on the entire structure, and then etching to form a sidewall spacer insulating film; A fifth step of removing the sidewall spacer insulating film and the silicon nitride film; And a sixth step of performing a heat treatment to recrystallize the amorphous layer generated during the ion implantation.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
본 발명의 구성상 특징은 다음의 두 가지로 대변될 수 있다.Configuration features of the present invention can be represented by the following two.
첫째, 이온주입시 상용되는 마스크로써 게이트산화막인 SiO2의 단일막 대신 Si3N4/SiO2의 이중막을 사용하는 것으로, 이 방법은 Si3N4막 내부의 니트로젠 결합을 깨기 위한 에너지가 SiO2막 내부의 산소 결합을 깨기 위한 에너지보다 크다는 원리를 이용해 이온주입시 재결합되는 원자의 수를 줄이고 재결정시의 결정결함을 감소 시키기 위한 것이다.First, as a mask commonly used for ion implantation, a double layer of Si 3 N 4 / SiO 2 is used instead of a single layer of SiO 2, which is a gate oxide film. This method requires energy to break the nitrogen bond inside the Si 3 N 4 film. This principle is to reduce the number of atoms recombined during ion implantation and to reduce crystal defects during recrystallization by using the principle that it is larger than the energy for breaking the oxygen bond inside the SiO 2 film.
둘째, 이온주입후 측벽 스페이서를 제거함으로써 스트레스를 감소시키는 것이다.Second, stress is reduced by removing sidewall spacers after ion implantation.
그러면, 상기 특징들을 구현하기 위한 공정 절차를 첨부된 도면 제 1도를 통하여 살펴본다.Next, a process procedure for implementing the features will be described with reference to FIG. 1.
우선, 제 1a도는 실리콘기판(1) 상에 게이트산화막으로 SiO2막(2)을 200Å 두께로 형성한 단면도이다.First, FIG. 1A is a cross-sectional view in which a SiO 2 film 2 is formed with a gate oxide film on the silicon substrate 1 to a thickness of 200 Å.
제 1b도는 상기 SiO2막(2)상부에 게이트전극(3)을 소정크기로 형성한 다음 고결합에너지막인 Si3N4막(4)을 200Å두께로 형성한 단면도이다. 이때, 상기 게이트전극(3) 형성을 위한 식각 단계에서 상기 SiO2막(2)도 소정두께 식각되어 100Å 두께로 남게된다. 주의해야 할 점은 상기 고결합에너지막인 Si3N4막(4)과 게이트산화막인 SiO2막(2)의 형성비로는 2로 하되 각각의 막 두께는 이온주입후의 사영비정(projected straggle) Rp에 의해 결정된다. 참고적으로 사영비정에 대해 간단히 설명하면, 에너지를 가진 이온들은 기판내의 전자와 핵에 충돌하면 그들의 에너지를 잃고 드디어는 정지하게 되는데 이와 같이 이온이 주입되어 정지하기까지의 전체 거리를 비정(range) R이라 하고, 입사축을 따르는 이 거리의 사영을 사영비정 Rp라 한다.FIG. 1B is a cross-sectional view in which the gate electrode 3 is formed on the SiO 2 film 2 to a predetermined size, and then the Si 3 N 4 film 4 , which is a high bonding energy film, is formed to have a thickness of 200 kHz. At this time, in the etching step for forming the gate electrode 3, the SiO 2 film 2 is also etched to a predetermined thickness to remain 100 Å thickness. It should be noted that the formation ratio of the Si 3 N 4 film 4 , which is a high bonding energy film, and the SiO 2 film 2, which is a gate oxide film, is 2, but the thickness of each film is projected straggle after ion implantation. Determined by R p . For the sake of simplicity, the projective axon states that energy ions collide with electrons and nuclei in the substrate and lose their energy and finally stop. as R, and is referred to as joined to the projection distance of the projection along the axis non-integer R p.
이어서, 제 1c 도는 상기 구조 상부에 N형 불순물을 저농도로 이온주입하여 N이온주입영역(5)을 형성하고, 전체구조 상부에 절연막을 증착한 다음, 식각하여 측벽 스페이서 절연막(6)을 형성한 후 다시 N형 불술물을 고농도로 이온주입하여 N이온주입영역(7)을 형성한 상태의 단면도이다. 이때, 상기 측벽스페이서 절연막(6) 형성시 비등방성 식각인 RIE(Reactive Ion Etching)와 등방성 식각제인 HF에서 연속하여 식각한다.Subsequently, the ion is implanted at a low concentration into the N-type impurity on the structure of FIG. The ion implantation region 5 is formed, an insulating film is deposited on the entire structure, and then etched to form a sidewall spacer insulating film 6, and then ion implantation is performed at high concentration with N-type impurities. It is sectional drawing of the state in which the ion implantation area | region 7 was formed. In this case, the sidewall spacer insulating layer 6 is continuously etched by RIE (reactive ion etching), which is anisotropic etching, and HF, which is an isotropic etching agent.
제 1d 도는 상기 측벽 스페이서 절연막(6)을 HF로 제거하고, 상기 Si3N4막(4)을 식각제 HNO3로 제거한 후 950℃의 온도에서 30분간 열처리한 상태의 단면도이다. 이때, 열처리 단계를 거침으로써 상기 이온주입에 의한 아폴포스층은 재결정화 된다.1D is a cross-sectional view of the sidewall spacer insulating film 6 removed with HF, the Si 3 N 4 film 4 removed with an etchant HNO 3, and then heat-treated at a temperature of 950 ° C. for 30 minutes. At this time, by passing through the heat treatment step the apollo force layer by the ion implantation is recrystallized.
상기와 같이 이루어지는 본 발명은 LDD 접합 구조 형성시 이온주입에 의해 발생되는 결정결함을 Si3N4마스크를 추가로 사용함으로써 효과적으로 줄일 수 있어 접합 누설을 효과적으로 낮출 수 있으며, 이에 따라 재결정화를 위한 열처리 온도 및 시간을 줄일수 있어 얕은 접합의 형성이 가능하다.The present invention made as described above can effectively reduce the crystal defects caused by the ion implantation when forming the LDD junction structure can be effectively reduced by additionally using a Si 3 N 4 mask, thereby effectively lowering the junction leakage, accordingly heat treatment for recrystallization The temperature and time can be reduced, enabling the formation of shallow junctions.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
Claims (5)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930011745A KR100265824B1 (en) | 1993-06-25 | 1993-06-25 | Method for fabricating transistor of ldd structure |
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| KR1019930011745A KR100265824B1 (en) | 1993-06-25 | 1993-06-25 | Method for fabricating transistor of ldd structure |
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| KR950001957A KR950001957A (en) | 1995-01-04 |
| KR100265824B1 true KR100265824B1 (en) | 2000-09-15 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100769415B1 (en) * | 2001-05-23 | 2007-10-22 | 마츠시타 덴끼 산교 가부시키가이샤 | Method of fabricating semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100769415B1 (en) * | 2001-05-23 | 2007-10-22 | 마츠시타 덴끼 산교 가부시키가이샤 | Method of fabricating semiconductor device |
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