JP3161510B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor integrated circuit having N-channel and P-channel thin film transistors (hereinafter referred to as TFTs) on a substrate having the same insulating surface. The present invention relates to an integrated circuit having a thin film transistor, such as a liquid crystal display device or a three-dimensional integrated circuit, in particular, a complementary MOS (metal-oxide-semiconductor) or MIS (metal-insulator-semiconductor) field effect. The present invention relates to a method for manufacturing an integrated circuit having a pattern element (the above is referred to as a CMOS circuit).

[0002]

2. Description of the Related Art In recent years, studies have been made on an insulating gate type semiconductor device having a thin-film active layer (also called an active region) on an insulating substrate. In particular, a thin film insulated gate transistor, a so-called thin film transistor (TFT), has been enthusiastically studied. These are intended to be used to control each pixel in a display device such as a liquid crystal having a matrix structure, and are distinguished as amorphous silicon TFTs or polycrystalline silicon TFTs depending on the material and crystal state of the semiconductor used. Have been.

[0003] Also in a single-crystal silicon integrated circuit, a polycrystalline silicon TFT is used as a so-called SOI technique, which is used as a load transistor in, for example, a highly integrated SRAM. However, in this case, the amorphous silicon TFT is hardly used. Further, in a semiconductor circuit on an insulating substrate, since there is no capacitive coupling between the substrate and the wiring, an extremely high-speed operation is possible, and a technology for using as an ultra-high-speed microprocessor or an ultra-high-speed memory has been proposed.

Generally, the electric field mobility of a semiconductor in an amorphous state is small, and therefore, a TF which requires high-speed operation is required.
Not available for T. Further, in the case of amorphous silicon, the P-type electric field mobility is extremely small, so that a P-channel TFT (PMOS TFT) cannot be manufactured.
T) and complementary MOS circuit (CMOS)
Cannot be formed.

[0005] On the other hand, a polycrystalline semiconductor has a higher electric field mobility than an amorphous semiconductor, and therefore can operate at high speed. For example, in a TFT using a silicon film recrystallized by laser annealing, a value as high as 300 cm ² / Vs is obtained as the electric field mobility.
Since the electric field mobility of a MOS transistor formed on a normal single crystal silicon substrate is about 500 cm ² / Vs, the value is extremely large, and the MOS circuit on the single crystal silicon has a large parasitic capacitance between the substrate and the wiring. However, since the operation speed is limited, the operation speed is limited, and there is no such restriction because the operation is performed on an insulating substrate, and a remarkably high-speed operation is expected.

In polycrystalline silicon, NMOS T
Since not only FT but also PMOS TFT can be obtained in the same manner, a CMOS circuit can be formed. For example, in an active matrix type liquid crystal display device, not only the active matrix portion but also peripheral circuits (drivers, etc.) are required. Also, there is known a device having a so-called monolithic structure constituted by a CMOS polycrystalline TFT. The TFT used in the above-mentioned SRAM also pays attention to this point, and the PMOS is constituted by the TFT, which is used as a load transistor.

[0007]

The thickness of the active layer of the TFT is 100 to 2000 °, preferably 200 to 1000 °.
For example, in a TFT doping process, it is necessary to implant a doping impurity at an optimum concentration for this thickness. Moreover, the gate insulating film on the active layer is
Generally, it is required to be thicker than the VLSI and to have a thickness of 500 to 3000 degrees. Therefore, the doping technique of the conventional semiconductor integrated circuit technique, in particular, the through doping (doping the active layer (= semiconductor surface) with the gate insulating film attached). Technology)
It was difficult to use as it was.

For example, phosphorus (mass number 3) is used as an N-type impurity.
When 1) or arsenic (mass number 75) is implanted with boron (mass number 11) as a P-type impurity, ions of boron and borohydride are light in mass, so that a relatively low accelerating voltage of 70 kV or less, for example, 40 kV or less. Although through doping could be performed even at 65 kV, the ions of phosphorus and hydrogen phosphide have a large mass, so they are 80 kV or more, for example, 85 to 110.
It was necessary to accelerate at a high voltage of kV. When ions having such high energy are irradiated on a substrate having an insulating surface, charge-up or the like causes
In the case where an organic material such as a resist is provided as a mask material on the substrate to selectively perform ion implantation, if the organic material such as a resist is deteriorated, the carbonization thereof causes
There was a problem that peeling became difficult. An object of the present invention is to provide an optimal doping method in view of such a current situation.

[0009]

According to the present invention, when an element having a small mass, for example, boron is implanted, an impurity is implanted into the active layer through a gate insulating film in the same manner as in a known through doping technique. When a heavy element such as phosphorus or arsenic is implanted, at least the gate insulating film in the region into which phosphorus or arsenic is implanted is removed or thinned so that a heavy element such as phosphorus or arsenic can be sufficiently transmitted. Perform doping.

[0010]

The acceleration voltage of ions containing heavy ions such as phosphorus or arsenic is 10 to 30 keV.
The required dose can be reduced by effectively injecting the amount previously injected into the gate insulating film to the source / drain. As a result, the problems of charge-up and difficulty in peeling off the mask material could be solved. Hereinafter, the present invention will be described in more detail with reference to Examples.

[0011]

【Example】

Embodiment 1 FIG. 1 shows an NM for implementing the present invention.
FIG. 4 shows a process chart of an example of manufacturing an OS and a PMOS element. In this example, a TFT was manufactured by a high-temperature process. First, a quartz substrate 101 (width 105 mm × length 105
mm × thickness 1.1 mm), a 2000-cm-thick silicon oxide film 102 is formed as a base film by a plasma CVD method, and then amorphous silicon without impurities is formed by a low-pressure CVD method using disilane as a raw material. A silicon film having a thickness of 100 to 2000 mm, preferably 500
~ 1500 ° formed. The substrate temperature during the formation of the amorphous silicon film was 150 to 550 ° C.

Then, this is patterned into an island shape,
The island-shaped silicon regions 103 and 104 were formed. afterwards,
It is crystallized by thermal annealing at 500 to 750 ° C., and then is oxidized in a high-temperature oxygen atmosphere to form a silicon oxide film 105, 106 having a thickness of 500 to 1500 °, preferably 500 to 700 ° on the surface of the silicon region.
Was formed. The temperature is in the range of 850 to 1100 ° C.
50-1050 <0> C was particularly preferred. The crystallization step may be performed by irradiating a laser or an equivalent strong light.

In the step of crystallizing the amorphous silicon film by thermal annealing, a very small amount of nickel,
By adding an element that promotes the crystallization of amorphous silicon, such as cobalt and copper, the crystallization temperature can be further lowered, and a silicon film having excellent crystallinity can be obtained. However, in this case, the concentration of these catalytic elements is not more than 1 × 10 ²⁰ cm ⁻³ (concentration notation meaning that 1 × 10 ²⁰ atoms are present per 1 cm ³ ), typically, It is preferably 1 × 10 ¹⁵ to 1 × 10 ¹⁹ cm ⁻³ .

After that, the phosphorus is 1 × 10 ¹⁹ to 2 × 10 ²⁰ c
m ⁻³ , for example, 8 × 10 ¹⁹ cm ⁻³ doped silicon film having a thickness of 2000-5000 °, preferably 3500-4
Then, a gate 107 of an N-channel TFT (NMOS) and a gate 108 of a P-channel TFT (PMOS) were formed. Then, as shown in FIG. 1A, covering the NMOS region,
A photoresist mask 109 was formed. (Figure 1
(A))

Then, ions containing boron were implanted by a plasma doping method. Plasma doping is also called ion doping, in which a gas containing a doping impurity element is discharged into a plasma state, which is extracted at a high voltage, accelerated, and injected into an irradiation target. In this case, different from the known ion implantation method, mass separation of ions is not performed, so that various ion species are implanted. For example, when boron is implanted, diborane (B ₂ H ₆ ) may be used as a gas. In this case, not only B (boron) ions but also BH ions, BH ₂ ions, and H
Other ions, such as ions, are also implanted.

Despite the above-mentioned drawbacks, the plasma doping method is a simple doping method and can be used for doping that does not require much accuracy. In this embodiment, an acceleration voltage of 30 to 70 kV, preferably 5
P-type impurity regions 110 and 111 were formed by doping at a dose of 0 to 65 kV, 1 × 10 ^{14 to} 6 × 10 ¹⁵ cm ⁻² , preferably 5 × 10 ¹⁴ to 2 × 10 ¹⁵ cm ⁻² . . This becomes the source / drain of the PMOS.
(FIG. 1 (B))

After doping with boron, ashing was performed in oxygen plasma to oxidize and remove the surface of the resist mask 109 lightly, and then removed by dipping in a stripper. Then, a photoresist mask 112 was newly formed by a known photolithography method. In this case, the NMOS island-shaped silicon region 103
Was exposed except for the outer periphery. Here, the reason why the outer peripheral portion of the silicon region 103 is covered with the mask is to prevent the base film 102 from being etched in a later step of removing silicon oxide.

Thereafter, using the mask 112, the silicon oxide film 105 was etched to expose the silicon region 103. (FIG. 1C) Then, ions containing phosphorus were implanted into the island-shaped silicon region 103 by a plasma doping method. Phosphine (PH ₃ ) is used as a gas, and an acceleration voltage of 10 to 30 kV, preferably 10 to 20 kV, and 1 × 10 ^{14 to} 6 × 1
0 ¹⁵ cm ⁻² , preferably 5 × 10 ¹⁴ to 2 × 10 ¹⁵ cm ⁻²
Doping was performed to form N-type impurity regions 113 and 114. This is the NMOS source /
Becomes a drain. (Fig. 1 (D))

After forming the impurity region, ashing is performed in oxygen plasma to form a resist mask 112.
After lightly oxidizing and removing the surface of the substrate, the substrate was immersed in a stripper to remove it. The time required for this step was short because the accelerating voltage at the time of implanting ions containing phosphorus was low. Then, the crystallinity of the impurity region was recovered by thermal annealing at 650 to 1050 ° C., for example, 750 ° C. After that, an interlayer insulator (phosphorus glass) 115 was deposited, flattened by reflow, and a contact hole was formed to form metal wirings 116 to 119 in the same manner as in a normal TFT manufacturing process. By the above process, NM
OS (120) and PMOS (121) were made.

Embodiment 2 FIG. 2 shows a CM using the present invention.
An example of manufacturing a liquid crystal display having an OS circuit will be described. In the present embodiment, as shown in FIG.
1, a display circuit section (active matrix) 23 and its driving circuit (peripheral circuit, that is, data driver 21).
And a gate driver 22), and the driving circuit is a CMOS circuit. Drive circuit 21, 2
An active matrix 23 having PMOS TFTs is formed in the center, and the driver section and the active matrix are connected to a gate line 25,
The display devices connected by data lines 26 are shown.

As shown in FIG. 4B, peripheral circuits, that is, data drivers 21 and 21 'and gate drivers 22 and 22' are provided on the upper, lower, left, and right sides of the active matrix 23.
May be provided. The active matrix 23 is an aggregate of pixel cells 24 having a PMOS. Here, the reason why the PMOS is selected as the TFT of the active matrix is that the leakage current between the source and the drain when the pixel is not selected is small, and therefore, the ability to hold the charge of the pixel is excellent. Hereinafter, the manufacturing process will be described with reference to FIGS.

As substrate 201, Corning 7059
No. glass substrate was used. Various other types of substrates can be used, but it is necessary to take measures according to the substrate so that mobile ions such as sodium do not enter the semiconductor film. An ideal substrate is a synthetic quartz substrate having a low alkali concentration, but when it is difficult to use it in terms of cost, a commercially available low-alkali glass or non-alkali glass is used. In this embodiment, a thickness of 200 to 10000 °, for example, 20 μm, is formed on the substrate 201 for the purpose of preventing mobile ions from entering the substrate.
A silicon oxide film 202 of 00 ° was formed. The thickness of these films is designed according to the degree of penetration of mobile ions or the degree of influence on the active layer.

Thereafter, an amorphous silicon film having a thickness of 200 to 2000 Å, for example, 1000 Å was formed from monosilane as a raw material by a plasma CVD method. The substrate temperature was 160 to 400 ° C., for example, 250 ° C. Further, a silicon oxide film having a thickness of 200 to 1000 ° was formed thereon as a protective film. The amorphous silicon film thus obtained was thermally annealed at 600 ° C. for 24 hours to be crystallized. In order to promote crystallization of the upper silicon film, it is desirable that the concentrations of carbon, nitrogen and oxygen contained in the film are all 7 × 10 ¹⁹ cm ⁻³ or less. In the present embodiment, 1 × 1
It was confirmed to be 0 ¹⁷ cm ⁻³ or less.

After the amorphous silicon film is converted into a crystalline silicon film by thermal annealing, the crystalline silicon film is etched into an appropriate pattern to form an island-shaped semiconductor region 203 for a peripheral CMOS circuit and an island-shaped semiconductor region 204 for a pixel TFT. Was formed. Thereafter, the gate insulating film (silicon oxide) 205 is formed to a thickness of 500 to 3000 Å, for example, 120 by a sputtering method using silicon oxide as a target in an oxygen atmosphere.
0 ° was formed. This thickness is determined by the operating conditions of the TFT and the like.

Next, an aluminum (containing scandium of 0.05 to 0.5% by weight, preferably 0.1 to 0.3% by weight) film is formed by sputtering to a thickness of 3000Å.
-5 μm, for example, 5000 °, and mixed with mixed acid (5
% Phosphoric acid solution to which nitric acid was added) to form gate electrodes and wirings. The etching rate is 225 nm when the etching temperature is 40 ° C.
/ Min. Thus, the outer shape of the TFT was adjusted.

Further, aluminum oxide was formed on the surface of the aluminum wiring by anodic oxidation. The method of anodic oxidation is disclosed in Japanese Patent Application No. 3-23, which is an invention of the present inventors.
1188 or the method described in Japanese Patent Application No. 3-238713. A detailed embodiment may be changed depending on the characteristics of the target device, process conditions, investment scale, and the like. In this embodiment, an aluminum oxide film 207 having a thickness of 1000 to 3000 Å, for example, 2000 Å is formed around the wiring 206 by anodic oxidation.
Thus, the gate electrode / wiring 20 for NMOS is
8. Gate electrode / wiring 209 for PMOS, pixel TFT
Gate electrode / wiring 210 was formed. (Figure 2
(A))

Then, by plasma doping,
Ions containing boron were implanted into the entire surface of the substrate. The doping condition is that the accelerating voltage is 30 to 70 kV, for example, 65 kV.
The kV and the dose were 1 × 10 ^{14 to} 6 × 10 ¹⁵ cm ⁻² , for example, 1 × 10 ¹⁵ cm ⁻² . As a result, the P-type impurity regions 211 to 21 are
5 was formed. (FIG. 1 (B))

Thereafter, the silicon oxide film 205 was etched with a buffered hydrofluoric acid solution, and a photoresist mask 216 was formed. In this case as well, a region to be implanted with phosphorus (a region to be the source / drain of the NMOS) was opened as in the first embodiment. Then, ions having phosphorus were implanted by a plasma doping method. The doping condition is that the accelerating voltage is 10 to 30 kV, for example, 10 kV.
V and the dose amount were 1 × 10 ^{14 to} 6 × 10 ¹⁵ cm ⁻² , for example, 2 × 10 ¹⁵ cm ⁻² . As a result, in the island-shaped silicon region 203, a part of the regions 211 and 212 are inverted from the P-type up to that point to become N-type regions (regions serving as source / drain of NMOS) 217 and 218. . In addition, the other portions of the island-shaped silicon region 203 remain P-type, and are regions that become the source / drain of the PMOS) 219,
220. The outer peripheral portion 211 'of the NMOS remained P-type. The island-shaped silicon region 204 (pixel TF
Since the regions 214 and 215 of T) were entirely covered with the resist, they remained P-type. (FIG. 1 (B))

After the impurity region was formed as described above, the surface of the resist mask 216 was lightly oxidized and removed by performing ashing in oxygen plasma, and then removed by dipping in a stripping solution.

Further, the source / drain regions were recrystallized by laser annealing using the gate electrode as a mask. The conditions of the laser annealing were, for example, the methods described in Japanese Patent Application Nos. 3-231188 and 3-238713. In this embodiment, since the silicon oxide film or the like does not exist on the surface of the silicon film to be annealed at the time of laser annealing, the loss due to the absorption of the laser light in the middle is small, and the energy density of the laser light is reduced in the case of the above invention. Even at 50 to 80%, a sufficient annealing effect was observed. As a result, the laser processing ability was able to be improved. (FIG. 2 (D))

Then, as an interlayer insulator, a thickness of 3000
A silicon oxide film 221 of Å to 3 μm, for example, 5000 Å is formed by an RF plasma CVD method, and further, I-thickness of 500 to 1000 Å, for example, 800 に よ っ て is formed by sputtering.
A TO (indium tin oxide) film was formed, and this was patterned and etched to form a pixel electrode 222 of an active matrix. Then, holes for forming electrodes were formed in the silicon oxide film 221, and aluminum wirings 223 to 227 were formed. Thus, the CMOS circuit of the peripheral circuit and the pixel T
FT was completed.

In the present embodiment, unlike the first embodiment, the selective doping was not performed at the time of doping with boron, so that the photolithography step and the mask material removing step could be omitted once each. In addition, during the doping with phosphorus, the silicon oxide film 205 serving as the gate insulating film is completely removed, so that in the subsequent contact hole opening step, the depth of the contact hole becomes the same for both NMOS and PMOS. . In this embodiment, since the anodic oxide is formed on the side surface of the gate electrode, the gate electrode and the source / drain are in an offset state. As a result, it was possible to increase the breakdown voltage and reduce the leak current between the source and the drain.

Embodiment 3 FIG. 3 shows this embodiment. First, a substrate (Corning 7059, 300 mm × 400 m
(m or 100 mm × 100 mm) 301, a silicon oxide film having a thickness of 1000 to 3000 ° was formed as a base oxide film 302. And plasma CVD or LPCVD
100-3000 amorphous silicon film
{Preferably 500-1000} and deposit 5
It was left in a reducing atmosphere at 50 to 600 ° C. for 24 hours to be crystallized. This step may be performed by laser irradiation. Then, the silicon film crystallized in this manner is patterned to form island regions 303 (NMOS
) And 304 (for PMOS). Further, a silicon oxide film 305 having a thickness of 700 to 1500 °, for example, 1200 ° was formed thereon by sputtering.

Thereafter, an aluminum (containing 1% by weight of Si or 0.1 to 0.3% by weight of Sc (scandium)) film having a thickness of 1000 to 3 μm was formed by an electron beam evaporation method or a sputtering method. Then, a photoresist (for example, OFPR800 / 3 manufactured by Tokyo Ohka)
0 cp) by spin coating. Before the formation of the photoresist, a thickness of 100 to 1
By forming an aluminum oxide film of 2,000 mm on the surface, adhesion to the photoresist is good, and current leakage from the photoresist is suppressed, so that a porous anodic oxide is formed in a subsequent anodic oxidation step. Was effective in forming only on the side surface. Thereafter, the photoresist and the aluminum film were patterned and etched together with the aluminum film to form gate electrodes 306 and 307 crossing each of the island regions 303 and 304. The mask films 308 and 309 remain on the gate electrode. As the material of the mask film, a photosensitive polyimide or an ordinary polyimide which can be etched may be used.

Next, by applying a current in the electrolytic solution only to the NMOS gate electrode 306 of the gate electrodes, a thickness of 3000 to 3000 is applied to the side surface of each gate electrode.
A porous anodic oxide 310 having a thickness of 6000Å, for example, 5000Å was formed. In this case, it is desirable that a circuit in which a current flows only through the NMOS is provided in advance. The anodic oxidation may be performed using a 3 to 20% aqueous solution of citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, or the like, and applying a constant current of 10 to 30 V to the gate electrode. In this example, the voltage was set to 10 V in an oxalic acid solution (30 ° C.), and anodization was performed for 20 to 40 minutes. The thickness of the anodic oxide was controlled by the anodic oxidation time. (FIG. 3
(A))

Next, the masks 308 and 309 were removed, and a current was again applied to the gate electrode in the electrolytic solution.
This time, an ethylene glycol solution containing 3-10% tartaric acid, boric acid and nitric acid was used, and NMOS, PMO
Current was applied to both S. A better oxide film was obtained when the temperature of the solution was lower than room temperature around 10 ° C. In this step, a barrier type anodic oxide 31 is formed on the upper and side surfaces of the gate electrode.
1, 312 were formed. The thickness of the barrier type anodic oxide is proportional to the applied voltage.
Of anodic oxide was formed. (FIG. 3 (B))

It should be noted that, despite barrier-type anodization being a later step, porous anodic oxide 310
Is not formed outside the barrier anodic oxide 311, but the barrier anodic oxide 311 is a porous anodic oxide 311.
10 and the gate electrode 306.
With this structure, ions having boron accelerated over the entire surface were implanted into the active layer. Doping conditions are as follows.
70 kV, for example, 65 kV, and the dose amount is 1 × 10 ¹⁴
６6 × 10 ¹⁵ cm ⁻² , for example, 5 × 10 ¹⁴ cm ⁻² . As a result, the island-like silicon regions 303 and 304 have P
Type impurity regions 313 to 316 were formed. (FIG. 3
(C))

Then, the insulating film 305 was etched by a dry etching method, a wet etching method, or the like.
At this time, the insulating film below the region covered with the anodic oxides 310 to 312 and the gate electrodes 306 and 307 is not substantially etched. That is, when the gate electrode is mainly composed of aluminum, tantalum, or titanium, and the insulating film 104 is mainly composed of silicon oxide, if a dry etching method is used, a fluorine-based (for example, N
With F _3, the etching gas of SF _6), by performing the dry etching, although the insulating film 305 is a silicon oxide is quickly etched, aluminum oxide, tantalum oxide, the etching rate of the titanium oxide is sufficiently small insulated The film 305 can be selectively etched.

In wet etching, 1
A hydrofluoric acid-based etchant such as / 100 hydrofluoric acid may be used. In this case as well, the insulating film 305 made of silicon oxide is quickly etched, but the etching rate of aluminum oxide, tantalum oxide, and titanium oxide is sufficiently small, so that the insulating film 305 can be selectively etched.

Thereafter, the anodic oxide 310 was etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. In this phosphoric acid-based etchant, the etching rate of the porous anodic oxide was at least 10 times the etching rate of the barrier anodic oxide. Therefore, the barrier type anodic oxide 31
Since Nos. 1 and 312 were not substantially etched by the phosphoric acid-based etchant, the inner gate electrode could be protected. In this etching, the etching rate of the porous anodic oxide was about 600 ° / min. Gate insulating film (silicon oxide) thereunder and barrier type anodic oxide 31
1, 312 remained as they were.

Thereafter, a photoresist is formed in the same manner as in the first embodiment.
Is formed, and the PMOS region is formed with a resist.
Covered. Then, arsenic is formed by plasma doping.
Was implanted. Doping conditions accelerated
Voltage is 10 to 30 kV, for example, 10 kV, dose amount
Is 1 × 10¹⁴~ 6 × 10^Fifteencm^-2, For example, 1 × 10
^Fifteencm^-2And As a result, the island-shaped silicon region 303
In regions 313 and 314, the P-type is inverted, and N
Region (region serving as source / drain of NMOS) 3
18, 319. Region of island-shaped silicon region 304
315 and 316 were completely covered with resist
And remained P-type. (FIG. 3 (D))

Further, the ion source, the accelerating voltage,
By changing the dose, by plasma doping,
Phosphorus-containing ions were implanted. The doping condition is such that the acceleration voltage is as high as 80 to 110 kV, for example, 90 kV, while the dose is 1 × 10 ¹³ to 1 × 10 ¹⁴ c.
m ⁻² , for example, 5 × 10 ¹³ cm ⁻² . In this doping step, phosphorus penetrates the insulating film 305 'and is implanted into the active layer below, and the N-type regions 320, 32
1 was formed. However, since the dose is small in the regions 320 and 321, the conductivity type of the formed impurity region is a weak N-type (N ⁻ type). (FIG. 3 (E))

Thereafter, the surface of the resist mask 317 was lightly oxidized and removed by ashing in oxygen plasma, and then the resist mask 317 was removed by dipping in a stripper. In this embodiment, in the process of high-speed ion implantation,
It may be feared that the carbonization of the resist proceeds due to the high acceleration energy, thereby hindering the removal of the resist mask. However, since the dose of the high-speed ions is 1/10 or less of the low-speed ion implantation, the effect on the resist mask is sufficiently small, and there is almost no problem in the actual process.

Thereafter, as in Example 2, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec)
To activate the impurity ions introduced into the active layer.

According to the result of SIMS (secondary ion mass spectrometry), the arsenic concentration in the regions 318 and 319 is 1 × 10
^{20 to} 2 × 10 ²¹ cm ⁻³ and the concentration of phosphorus in the regions 320 and 321 were 1 × 10 ¹⁷ to 2 × 10 ¹⁸ cm ⁻³ . In terms of dose, the former was 5 × 10 ^{14 to} 5 × 10 ¹⁵ cm ⁻² and the latter was 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² . Then, as an interlayer insulating material, a thickness of 3000 to 3 μm, for example, 50
A 00 ° silicon oxide film 322 was formed by an RF plasma CVD method, holes for forming electrodes were formed in the silicon oxide film 322, and aluminum wirings 323 to 326 were formed.

In this embodiment, the PMOS has a structure similar to that of the second embodiment, whereas the NMOS has a structure close to a so-called low-concentration drain structure (hereinafter, the regions 320 and 321 are called high-resistance regions). did it. This is NMOS
This is effective in reducing the influence of deterioration due to hot carriers that are susceptible to heat. It may seem that it is preferable for the PMOS to have a structure having a high resistance region similar to the NMOS. That is not impossible, and the invention does not deny it,
The field-effect mobility of S is usually about half as compared with that of NMOS, but it is further high-resistance region (functions as a resistor inserted in series between source / solein).
Is not preferable because the actual drain current further decreases.

Rather, a PMOS having a small deterioration due to hot carriers has a normal structure, and a high-resistance region is formed only in an NMOS which has a high mobility but deteriorates due to hot carriers.
It is preferable because it balances with that of S. Of course, P
Even with MOS, deterioration due to hot carriers cannot be ignored.
This is not the case for a TFT having a design rule of submicron or less.

Embodiment 4 FIG. 5 shows this embodiment. First, a substrate (Corning 7059, 300 mm × 400 m
m or 100 mm × 100 mm) 501 as a base oxide film 502, a silicon oxide film having a thickness of 1000 to 3000 ° is deposited, and an amorphous silicon film is further deposited by a plasma CVD method or LPCVD method at 100 to 3000 °, preferably 500 to 1000 °, This is 550-6
It was left in a reducing atmosphere at 00 ° C. for 24 hours to be crystallized. Then, the silicon film thus crystallized is patterned to form island-like regions 503 (for NMOS), 50
4 (for PMOS). Further, a thickness of 700 to 1500 ° is formed thereon by a plasma CVD method, for example,
A 1200 ° silicon oxide film 505 was formed.

Thereafter, an aluminum (containing 1% by weight of Si or 0.1 to 0.3% by weight of Sc (scandium)) film having a thickness of 1000 to 3 μm was formed by a sputtering method. Then, this is patterned to form a gate electrode / wiring 506 (for NMOS) and 508 (for PMOS).
), And anodized in the same manner as in Example 2.
Barrier type anodic oxide films 507 and 509 were formed. At this time, by making the anodic oxidation time longer than that of the PMOS, the thickness of the anodic oxide 507 of the NMOS gate electrode / wiring is set to 2000 to 3000 °, and the thickness of the anodic oxide 509 of the PMOS gate electrode / wiring. From 500 to 10
00 °. (FIG. 5 (A))

In this structure, ions having boron accelerated over the entire surface were implanted into the active layer by a plasma doping method. Doping conditions are as follows: acceleration voltage is 30 to 70 kV,
For example, 65 kV, dose amount is 1 × 10 ^{14 to} 6 × 10
^{It was 15} cm ^-2 , for example, 5 × 10 ¹⁴ cm ^-2 . As a result, P-type impurity regions 510 to 513 were formed in the island-shaped silicon regions 503 and 504. (FIG. 5 (B))

Then, the insulating film 505 was etched by a dry etching method, a wet etching method, or the like. Thereafter, a photoresist mask 514 was formed in the same manner as in Example 1, and the region of the PMOS was covered with the resist. Then, ions having phosphorus were implanted by a plasma doping method. The doping conditions are as follows: the acceleration voltage is 10 to 30 kV, for example, 10 kV, and the dose is 5 ×
10 ^{14 to} 5 × 10 ¹⁵ cm ⁻² , for example, 1 × 10 ¹⁵ cm ⁻²
And As a result, the region 51 of the island-shaped silicon region 503 is formed.
0 and 511 are N-type regions (regions to be the source / drain of NMOS) 515 and 5
It was 16. (FIG. 5 (C))

Subsequently, ions having phosphorus were implanted by the plasma doping method while changing the acceleration voltage and the dose. The doping condition is that the acceleration voltage is 6
5 to 110 kV, for example, 80 kV, while the dose is 1 × 10 ^{13 to} 5 × 10 ¹⁴ cm ⁻² , for example, 5
× 10 ¹³ cm ^-2 , which is lower by one digit or more than that in the previous source / drain fabrication. In this doping step, as shown by the dotted line in FIG. 5 (D), phosphorus penetrates the active layer and is implanted deep into the underlying film, and the ion doping method has poor ion directivity. It spread not only in the direction but also in the lateral direction. However, in this doping step, since the dose was small, the conductivity type of the impurity region formed was a weak N-type (N ⁻ type).
(FIG. 5 (D))

In this embodiment, after the slow ions are implanted,
Although high-speed ions are implanted, it is needless to say that the reverse is also possible. Further, slow ions and fast ions may be implanted simultaneously. Further, the doping impurities to be implanted with the fast ions and the slow ions may be changed. For example, the former may be phosphorus with good diffusibility, and the latter may be arsenic which is relatively hard to diffuse.

Thereafter, the surface of the resist mask 514 was lightly oxidized and removed by ashing in oxygen plasma, and then the resist mask 514 was removed by dipping in a stripper. Then, similarly to Example 2, irradiation with a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was performed to activate the impurity ions introduced into the active layer. As a result, adjacent to the N-type impurity regions 515 and 516, the N-type impurity regions 517 and
18 were formed. However, for convenience, the boundaries are shown in the figure, but actually the regions 517 and 518 and the region 51 are shown.
It should be noted that the boundaries between 5,516 are not clear and the density changes gradually.

According to the result of SIMS (secondary ion mass spectrometry), the impurity concentration of the regions 515 and 516 is 1 × 10
^{20 to} 2 × 10 ²¹ cm ⁻³ , 1 × 1 in regions 517 and 518
0 ^{17 to} 2 × 10 ¹⁸ cm ⁻³ . In dose conversion,
The former is 5 × 10 ^{14 to} 5 × 10 ¹⁵ cm ⁻² and the latter is 2 × 10
¹³ was ~5 × 10 ¹⁴ cm ^-2. Thereafter, a silicon oxide film 519 having a thickness of 3000 to 3 μm, for example, 5000 mm is formed as an interlayer insulator by RF plasma CVD, and holes for forming electrodes are formed in the silicon oxide film 519.
523 were formed.

In this embodiment, the offset width is different between the NMOS and the PMOS because the thickness of the anodic oxide is different.
In addition, since the NMOS was subjected to two-stage doping, a region having a lower impurity concentration than the source / drain could be formed adjacent to the source / drain.
Such a region has the same effect as the low-concentration drain structure of the third embodiment, and is effective in reducing the influence of deterioration due to hot carriers. Moreover, this embodiment is characterized in that the same configuration as that of the low-concentration drain can be easily obtained, as is clear from comparison with the third embodiment.

Embodiment 5 FIG. 6 shows this embodiment. First, a substrate (manufactured by NH Techno Glass, NA35, 300 m
m × 400mm or 100mm × 100mm) 60
1 as a base oxide film 602 having a thickness of 1000 to 3000
The silicon oxide film of Å is further subjected to plasma CVD or LPC.
Amorphous silicon film is 100 to 30 by VD method.
Deposited at 00 °, preferably 500-1000 °, and left in a reducing atmosphere at 550-600 ° C. for 24 hours to crystallize. Then, the silicon film crystallized in this manner is patterned to form island-shaped regions 603 (N
MOS) and 604 (for PMOS). Further, a thickness of 700 to 1 is formed thereon by plasma CVD.
A silicon oxide film 605 having a thickness of 500 °, for example, 1200 ° was formed.

Thereafter, an N-type polycrystalline silicon film having a thickness of 500 to 2000 .ANG. Was deposited by a low-pressure CVD method, and a tungsten silicide, molybdenum silicide, or titanium silicide film having a thickness of 2000 to 3 .mu.m was formed by a sputtering method. Then, this was patterned to form a gate electrode and a wiring. Gate electrode is silicon film 6 below
06, 607, a coating 608 of tungsten silicide or the like thereon,
609. (FIG. 6 (A))

In this structure, ions having boron accelerated over the entire surface were implanted into the active layer. The doping conditions are as follows: acceleration voltage is 30 to 70 kV, for example, 65 kV, and dose is 1 × 10 ^{14 to} 6 × 10 ¹⁵ cm ⁻² , for example, 5 × 10
^{It was 14} cm ^-2 . As a result, the island-shaped silicon region 603,
At 604, P-type impurity regions 610 to 613 are formed. (FIG. 6 (B))

Then, the insulating film 605 was etched by a dry etching method, a wet etching method, or the like. Thereafter, a photoresist mask 614 was formed as in Example 1, and the region of the PMOS was covered with the resist. Then, ions having phosphorus were implanted by a plasma doping method. The doping conditions are as follows: the acceleration voltage is 10 to 30 kV, for example, 10 kV, and the dose is 1 ×
10 ^{14 to} 6 × 10 ¹⁵ cm ⁻² , for example, 1 × 10 ¹⁵ cm ⁻²
And As a result, the region 61 of the island-shaped silicon region 603 is formed.
0 and 611 are N-type regions (regions that become NMOS source / drain) 615 and 6 in which the P-type is inverted.
It was 16. (FIG. 6 (C))

After that, the surface of the resist mask 614 was lightly oxidized and removed by ashing in oxygen plasma, and then the resist mask 614 was removed by immersion in a stripping solution. Then, similarly to Example 2, irradiation with a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was performed to activate the impurity ions introduced into the active layer. After that, as an interlayer insulator, the thickness is 3000 mm.
To 3 μm, for example, 5000 °
An aluminum wiring 618 to 621 was formed by forming a hole for electrode formation in this by F plasma CVD.

[0062]

According to the present invention, a TFT is produced with a good yield by using a TFT.
I believe it is extremely effective in constructing MOS. In the above embodiment, only the case where a TFT is formed on a glass substrate or the like has been described. However, a three-dimensional integrated circuit (an integrated circuit formed on the surface of a single crystal semiconductor and further provided with an insulating film therebetween) is provided. It is obvious that the present invention can be applied to a three-dimensional integrated circuit.

In addition, the present invention can be used not only for manufacturing MIS type circuits but also for manufacturing bipolar type transistors. For example, an NPN-type bipolar transistor has N
It can be manufactured by selectively ion-implanting boron through silicon oxide into a semiconductor film of a mold to form a base, further removing or thinning the silicon oxide film, and adding phosphorus. Such a bipolar transistor can also be manufactured on the same substrate as the MIS device, and a bi-CMOS circuit can be obtained.

[Brief description of the drawings]

FIG. 1 shows a manufacturing process of an example (see Example 1).

FIG. 2 shows a manufacturing process of an example (see Example 2).

FIG. 3 shows a manufacturing process of an example (see Example 3).

FIG. 4 is a block diagram of a liquid crystal display to which the present invention is applied. (See Example 2)

FIG. 5 shows a manufacturing process of an example (see Example 4).

FIG. 6 shows a manufacturing process of an example (see Example 5).

[Explanation of symbols]

101: substrate (quartz) 102: underlying film (silicon oxide) 103, 104: island-shaped active layer (silicon) 105: gate insulating film (silicon oxide) 106, 107... Gate electrode (phosphorus-doped silicon) 108... Mask (photoresist) for boron ion implantation 109, 110... P-type region (source / drain of P-channel TFT) 111. ... Masks (photoresist) for phosphorus ion implantation 113, 114... N-type region (source / drain of N-channel TFT) 115... Interlayer insulator (phosphorus glass) 116 ~ 119 ・ ・ Metal electrode ・ Wiring

──────────────────────────────────────────────────続 き Continuation of front page (51) Int.Cl. ⁷ Identification symbol FI H01L 27/092 H01L 27/08 321B 321E (56) References JP-A-1-310574 (JP, A) JP-A-6-301056 (JP, A) JP-A-5-160153 (JP, A) JP-A-5-267567 (JP, A)

Claims (3)

(57) [Claims] A step of forming a plurality of island-shaped semiconductor thin films on a substrate having an insulating surface; a step of forming an insulating film covering the plurality of semiconductor thin films; A step of forming a plurality of gate electrodes via a coating; a step of selectively injecting ions containing boron into a region of the plurality of semiconductor thin films that is to become a P-type semiconductor; A region to be formed is covered with a resist mask, the insulating film is removed from a region of the plurality of semiconductor thin films which is to be an N-type semiconductor, and ions containing phosphorus or arsenic are selectively applied to the region to be formed as the N-type semiconductor. A method of manufacturing a semiconductor integrated circuit, comprising: A step of forming a plurality of island-shaped semiconductor thin films on a substrate having an insulating surface; a step of forming an insulating film covering the plurality of semiconductor thin films; A step of forming a plurality of gate electrodes via a coating; a step of injecting ions containing boron into at least a region of the plurality of semiconductor thin films to be a P-type semiconductor; and a region of the P-type semiconductor. Is covered with a resist mask, and the insulating coating is removed from a region of the plurality of semiconductor thin films that is to become an N-type semiconductor so that the end of the insulating coating is present beyond the end of the gate electrode. Is selectively implanted into the region to become the N-type semiconductor at a first acceleration voltage, and then ions containing phosphorus or arsenic are implanted at a second acceleration voltage higher than the first acceleration voltage. Selectively implanting into a region of the semiconductor thin film under an insulating film existing beyond a region to be a semiconductor of a mold and an end of the gate electrode. How to make a circuit. A step of forming a plurality of island-shaped semiconductor thin films on a substrate having an insulating surface; a step of forming an insulating film covering the plurality of island-shaped semiconductor thin films; Forming a plurality of gate electrodes via the insulating film, anodizing the plurality of gate electrodes, and applying boron-containing ions to a region of the plurality of semiconductor thin films to be a P-type semiconductor. Implanting, covering the region to be a P-type semiconductor with a resist mask, removing the insulating film in a region to be an N-type semiconductor among the plurality of semiconductor thin films, and removing ions containing phosphorus or arsenic. After selectively implanting the region to be the N-type semiconductor with the first acceleration voltage, ions containing phosphorus or arsenic are implanted.
Selectively implanting into a region to be the N-type semiconductor at a second acceleration voltage different from the first acceleration voltage.