JPH06301056A - Production of thin-film semiconductor device - Google Patents

Abstract

PURPOSE:To realize the liquid crystal display having an excellent pixel holding characteristic by decreasing the off-leak currents of thin-film transistors(TFTs) with simple stages. CONSTITUTION:Only the Nch TFTs in the regions of L<off> from the ends of gate electrodes are selectively made into an LDD structure by remaining a gate insulating film and implanting ions thereto. The off-leak currents of the pixel switching TFTs and the soaring up of the off-leak currents are decreased. Consequently, the liquid crystal display which lessens flickering and unequal display and has the excellent pixel holding characteristic is realized. Photolithographic stages are not increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention has a plurality of scanning lines arranged in parallel on a substrate and a plurality of signal lines arranged orthogonally to the scanning lines, and intersections of the signal lines and the scanning lines. A pixel switching thin film transistor having a gate electrode integrated with the scanning line, the source region being connected to the signal line and the drain region being connected to the pixel electrode.
In an active matrix type liquid crystal display device in which a driving circuit composed of an Nch thin film transistor and a Pch thin film transistor for driving the pixel switching thin film transistor is integrated on the same substrate, an off leak current of the pixel switching thin film transistor is reduced, The present invention relates to a method of manufacturing a thin film semiconductor device for improving the holding characteristics of the device and realizing an active matrix type liquid crystal display device having excellent display unevenness, flicker and resolution.

[0002]

2. Description of the Related Art A thin film transistor is a switching element or driver circuit of a pixel in an active matrix type liquid crystal display device (hereinafter referred to as a liquid crystal display), a contact image sensor, or an SRAM.
(Static Random Access Memo
ries) etc.

A liquid crystal display will be described. A sufficiently large on-current is required for the thin film transistor that constitutes the drive circuit. On the other hand, the pixel switching thin film transistor is required to have a sufficiently low off-leakage current in order to improve the retention characteristics of the pixel and realize an active matrix type liquid crystal display device having excellent display unevenness, flicker and resolution. Further, an increase in off-leakage current (hereinafter referred to as “off-leakage current jump”) when a reverse bias voltage is applied to the gate electrode must be suppressed as much as possible (flat panel display 9).
1, pp80-87, Nikkei BP).

A thin film transistor (hereinafter abbreviated as poly-Si TFT) using a polycrystalline silicon thin film will be described from the viewpoint that a sufficient on-current can be obtained.
In the poly-Si thin film, crystal grain boundaries in which defect levels are distributed at a high density are present in the boundary region between crystal grains.
Due to the synergistic effect of the presence of this defect level and the reverse bias electric field applied to the drain end, the off-leakage current of the poly-Si TFT is extremely large (Jpn.
J. Appl. Phys. , Vol. 31 (1992)
pp. 206-209). In order to alleviate the electric field at the drain end, an LDD (Lightly Doped Drain) is used.
n) It is known that it is effective to form a structure, but since a difficult step of forming a side wall at the end of the gate electrode by using a technique such as anisotropic etching is required, the TFT process Has not been adopted so far.

In the conventional liquid crystal display, the pixel switching thin film transistor does not have the LDD structure, so that the off-leakage current jumps significantly. Its characteristics are shown in FIG. The horizontal axis shows the gate voltage,
The vertical axis represents the drain current. The gate voltage 0V to -20V is the off region. The off-leakage current rapidly increases as the reverse bias voltage increases.

As described above, in the conventional liquid crystal display, since the off-leakage current of the pixel switching thin film transistor is extremely large, the pixel retention characteristic is insufficient. Therefore, the liquid crystal display has large flicker and uneven display. Further, it becomes a problem when manufacturing a panel of a larger size or a panel for high definition. In addition, when a new driving method such as common swing is adopted, a larger reverse bias voltage is applied, so the requirement for off-leakage current becomes even more severe (seminar text, development technology and characteristics analysis / application of TFT color liquid crystal). Design, 1991
21st and 22nd, Japan Industrial Technology Center, pp9-2
4).

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art and to selectively select only pixel switching thin film transistors in a very simple method with the same number of photo processes as in the prior art. By using the LDD structure, it is possible to prevent the off-leakage current from rising.
Further, it is a great object to provide a method for easily producing a liquid crystal display having excellent display characteristics by improving pixel retention characteristics.

[0008]

According to the present invention, pixels arranged in a matrix and pixel switching thin film transistors provided for each pixel to select the pixel are provided.
In a method of manufacturing a thin film semiconductor device in which a pixel driving circuit configured by an Nch thin film transistor and a Pch thin film transistor is integrated on the same insulating transparent substrate, the same conductivity type thin film transistor as the pixel switching thin film transistor is LDD (Lightly Doped) formed by an ion implantation process
The conduction type thin film transistor, which has a drain structure and is different from the pixel switching thin film transistor, has a normal self-aligned structure.

Further, when the pixel switching thin film transistor is composed of an Nch thin film transistor, (1)
Forming a Pch thin film transistor in a self-aligned manner by forming a resist mask after forming a first thin film semiconductor layer, a gate insulating film and a gate electrode, and ion-implanting impurities such as boron. After removing the resist mask, a second resist mask is formed by a photo process on the gate insulating film other than the Pch thin film transistor, leaving the gate insulating film thicker by 1 to 5 μm from the end of the gate electrode, and over the source and drain regions. The gate insulating film is removed by etching, and (3) after the second resist mask is removed, an impurity such as phosphorus or arsenic is ion-implanted.

Further, when the pixel switching thin film transistor is composed of a Pch thin film transistor, (1)
After forming the first thin film semiconductor layer, the gate insulating film, and the gate electrode, a resist mask is formed, and impurities such as phosphorus or arsenic are ion-implanted to self-align Nc
h Step of forming a thin film transistor, (2) After removing the resist mask, a second resist mask is formed by a photo step in the gate insulating film other than the Nch thin film transistor, and 1 to 5 μm from the gate electrode end.
(3) A step of etching away the gate insulating film above the source and drain regions, leaving the thick gate insulating film.
After removing the second resist mask, at least a step of ion-implanting boron or the like is included.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the structure of a thin film semiconductor device according to the present invention is shown in FIG. FIG. 1 is a structural sectional view. Figure 1
1-14 indicates a pixel switching thin film transistor, and 1-15 indicates a conductive type thin film transistor different from the pixel switching thin film transistor. 1
-1 is an insulating transparent substrate, 1-2 is a semiconductor thin film that constitutes an active region of a thin film transistor, 1-3 is a gate insulating film,
1-4 are gate electrodes. The gate insulating film of the pixel switching thin film transistor is L _off from the end of the gate electrode.
Is thicker than the gate electrode, and the other portion is removed by etching. Then, the source region 1-5 and the drain region 1-6 are formed by implanting impurity ions. At this time, since impurity ions are implanted into the region away from the end of the gate electrode by a distance L _off through the gate insulating film, the impurity concentration in this region is smaller than that in the source and drain regions, and the LDD is automatically performed. It becomes an area. When L _off is about 1-2 μm,
The rise of off-leakage current decreases sharply, but 2μ
When it exceeds m, the on-current starts to decrease. Therefore, the length of L _off must be determined by the balance between the off leak current and the on current. According to the experiment, L _off is 1 to 5
It is thought that about μm is suitable. 1-7 in the figure is the L
The DD area is shown. On the other hand, in a conductive type thin film transistor different from the pixel switching thin film transistor, since the entire surface is ion-implanted through the gate insulating film, LDD
Not a structure. Reference numeral 1-9 indicates a source region, and 1-10 indicates a drain region. Reference numeral 1-11 indicates an interlayer insulating film, 1-12 indicates a source electrode, and 1-13 indicates a drain electrode.

Hereinafter, the manufacturing method of the present invention will be described by taking as an example the case of manufacturing an active matrix substrate using Nch thin film transistors as pixel switching thin film transistors. Of course, a Pch thin film transistor may be used as the pixel switching thin film transistor. Basically, only the difference in the ion species due to the ion implantation is given, and the description is omitted here.

First, the present invention will be described with reference to FIG. The non-single-crystal semiconductor thin film 2-2 is formed on the insulating amorphous material 2-1. As the insulating amorphous material,
A quartz substrate, a glass substrate, a nitride film, a SiO ₂ film or the like is used. Process temperature is 1 when using quartz substrate
Up to about 200 ° C is allowed, but when a glass substrate is used, it is limited to a low temperature process of 600 ° C or lower. Hereinafter, a case where a quartz substrate is used and a solid phase growth Si thin film is used as the non-single crystal semiconductor thin film will be described as an example. Of course, not only solid-phase-grown Si thin film but also reduced pressure C
Polycrystalline Si thin films and SOI (Silicon on) formed by VD method, plasma CVD method, sputtering method, etc.
The present invention can also be realized by using an Insulator.

Using a plasma CVD apparatus, a mixed gas of SiH ₄ and H ₂ is decomposed by a high frequency glow discharge of 13.56 MHz on a quartz substrate 2-1 as shown in FIG. A high quality Si film 2-2 is deposited. The SiH ₄ partial pressure of the mixed gas is 10 to 20%, and the internal pressure in the depot is 0.5.
It is about 1.5 torr. The substrate temperature is preferably 250 ° C. or lower, about 180 ° C. When the amount of bound hydrogen was determined by infrared absorption measurement, it was about 8 atomic%. The chamber before deposition of the amorphous Si film 2-2 was subjected to Freon cleaning, and the amorphous Si film deposited subsequently was 2 × 10.
Contains ¹⁸ cm ^-3 of fluorine. Therefore, in the present invention, after the Freon cleaning, the dummy is deposited,
Perform the actual deposition. Or abolish Freon cleaning,
The chamber is cleaned by another method such as beading.

Then, the amorphous Si film is formed at 400 ° C. to 5 ° C.
Heat treatment is performed at 00 ° C. to release hydrogen. This process is intended to prevent the explosive desorption of hydrogen.

Next, the amorphous thin film 2-2 is solid-phase grown. For the solid phase growth method, a furnace anneal using a quartz tube is convenient. Nitrogen gas, hydrogen gas, argon gas, helium gas or the like is used as the anneal atmosphere. 1 x 1
Annealed in a high vacuum atmosphere of 0 ^-6 to 1 x 10 ^-10 Torr.
You may go le. Solid phase growth anneal temperature is 500 ° C ~
The temperature is 700 ° C. In such low temperature annealing, selectively,
Only the crystal grains having a crystal orientation with a small activation energy for crystal growth grow, and slowly grow large.
In an experiment conducted by the inventor, an annealing temperature of 600 ° C.
A large-grain silicon thin film of 2 μm or more is obtained by solid phase growth for 16 hours. In FIG. 2B, 2-3 indicates a solid phase growth silicon thin film.

The method for producing a silicon thin film by the solid phase growth method has been described above.
The silicon thin film may be formed by a method such as a sputtering method or a vapor deposition method.

Next, the solid phase growth silicon thin film is patterned by photolithography into an island shape as shown in FIG. 2 (c).

Next, as shown in FIG. 2D, a gate oxide film 2-4 is formed. The gate oxide film is formed at 500 ° C. such as LPCVD method, photo-excited CVD method, plasma CVD method, ECR plasma CVD method, high vacuum vapor deposition method, plasma oxidation method or high pressure oxidation method. There are the following low temperature methods. The gate oxide film formed by the low temperature method is heat-treated to be a denser and excellent film having less interface states. When a quartz substrate is used as the amorphous insulating substrate 2-1, a thermal oxidation method can be used. D for the thermal oxidation method
There are a ry oxidation method and a wet oxidation method. An oxide film is formed at about 800 ° C. or higher. To use a quartz substrate, for example, 1
It is suitable to carry out dry oxidation at a temperature as high as possible of 000 ° C. or higher. Gate oxide film thickness is from 500Å to 1
About 500Å is suitable.

After formation of the gate oxide film, boron may be channel ion-implanted and channel-doped if necessary.
This is intended to prevent the threshold voltage of the Nch thin film transistor from shifting to the negative side. The amorphous silicon film has a deposition thickness of 500 to 1
In case of 500Å, the dose of boron is 1 × 10 ^12.
About 5 × 10 ¹² cm ^-2 is suitable. If the thickness of the amorphous silicon film is less than 500Å, boron-
The amount of scratches is reduced, and as a guideline, it is 1 × 10 ¹² cm ^-2 or less. When the film thickness is 1500 Å or more, the boron dose is increased, and as a guide, it is 5 × 10 ¹² cm.
^-Set to ² or more.

Instead of channel ion implantation, boron may be added at the time of depositing the silicon film 2-2. This is obtained by flowing diborane gas (B ₂ H ₆ ) together with silane gas into the chamber during the deposition of the silicon film to cause a reaction.

Next, as shown in FIG. 2E, the method for forming the gate electrode 2-5 will be described. Here, a case of using a low resistance polycrystalline silicon film will be described as an example. First, a film forming method using the diffusion method will be described.
A polycrystalline silicon film is deposited by a method such as LPCVD, and then P is added to the polycrystalline silicon film by a POCl ₃ diffusion method at 900 to 1000 ° C. At this time, since a thin oxide film is coated on the polycrystalline silicon film, the oxide film is removed with an aqueous solution containing hydrofluoric acid. There is also a method of adding P by an ion implantation method. In addition, by depositing a doped polycrystalline silicon film, the upper layer film 2-
There is also a method of setting 6. This is a method of forming a film by decomposing a mixed gas of SiO ₂ gas and PH ₃ gas. In the LPCVD method, thermal decomposition at 500 to 700 ° C., P
In the ECVD method, an impurity-added polycrystalline silicon film is formed by glow discharge decomposition. 300 ° C by PECVD method
An amorphous silicon film can be formed to some extent. It is also an effective method to grow this doped amorphous silicon film into a high quality polycrystalline silicon film by the solid phase growth method as described above.

A polycrystalline silicon film containing 1 × 10 ¹⁹ cm ⁻³ or more of P added thereto in the above-described manner is used in an amount of 500 to 2000.
Å Deposit about. In this case, the sheet resistance of the gate electrode is about 20 to 30 Ω / □.

In order to further reduce the sheet resistance of the gate electrode, there is also a method of using a two-layer gate electrode in which an impurity-doped polycrystalline silicon film and a silicide film are laminated. As the silicide film, cobalt silicide (CoSi ₂ ), nickel silicide (NiSi), titanium silicide (TiSi ₂ ), molybdenum silicide (MoSi ₂ ), or tungsten silicide (WS) is used.
i ₂ ) etc. When a MoSi ₂ film is used as the silicide film, the sheet resistance is 7-
It becomes about 8Ω / □. The resistance of the gate line is reduced to about one third.

Next, the formation of the Pch thin film transistor will be described first. As shown in FIG. 3A, Nch
A P photoresist mask 2-6 is formed on the thin film transistor.

Subsequently, as shown in FIG. 3B, ion implantation for forming a source region and a drain region is performed. An acceptor type impurity is ion-implanted into the first semiconductor layer by an ion implantation method to form a source region and a drain region in a self-aligned manner with respect to the upper layer film 2-6. In FIG. 3B, 2-7 indicates a source region in which a high concentration of ions are implanted, and 2-8 indicates a drain region.

Boron (B) or the like is used as the acceptor type impurity. As a method for adding impurities, there are methods such as a laser doping method and a plasma doping method in addition to the ion implantation method. The arrows indicated by 2-9 represent ion beams of impurities. When a quartz substrate is used as the insulating amorphous material 2-1, a thermal diffusion method can be used. The impurity dose is 1 × 10 ¹⁴
To about 1 × 10 ¹⁷ cm ^-2 . Converted to the impurity concentration, it is about 1 × 10 ¹⁹ to 1 × 10 ²² cm ^{−3 in the} source region 2-7 and the drain region 2-8. Further, the ion acceleration energy is set so that the maximum value of the concentration distribution of the implanted impurities exists near the interface between the polycrystalline silicon thin film 2-3 and the gate insulating film 2-4. For example, when the film thickness of the gate oxide film is 1200Å, the ion acceleration energy of 30 to 60 keV is suitable.

Next, a method of forming an Nch thin film transistor which constitutes a pixel switching thin film transistor will be described. As shown in FIG. 3C, an N photoresist mask 2-10 is formed thicker by L _off from both ends of the gate electrode of the Nch thin film transistor. The N photoresist mask 2-10 also covers the Pch thin film transistor. Then, the gate insulating film is etched to surround L _off of the gate electrode of the Nch thin film transistor.
The gate insulating film is left in the region (1) and the gate insulating film is removed in the other portions to expose the surface of the polycrystalline silicon thin film.

After removing the N photoresist mask 2-10, as shown in FIG. 3D, a donor-type impurity ion is implanted by an ion implantation method. Phosphorus (P), arsenic (As), or the like is used as the donor-type impurity. 2-14 has shown the ion beam.

As a method of adding impurities, there are methods such as a laser doping method and a plasma doping method in addition to the ion implantation method. The arrow indicated by 2-14 represents the ion beam of impurities. When a quartz substrate is used as the insulating amorphous material 2-1, a thermal diffusion method can be used. Since the source and drain regions of Pch will be doped with phosphorus in addition to boron, Nc
The impurity dose amount N ⁺ of h is the impurity dose amount P ^{+ of} Pch.
Must be less than one digit. Further, the ion acceleration energy is set so that the maximum value of the concentration distribution of the implanted impurities exists on the surface of the exposed polycrystalline silicon thin film 2-3. Therefore, it is important to set the ion acceleration energy as low as possible.
About 0 to 30 keV is suitable.

At this time, since the region 2-19 in the periphery L _off of the gate insulating film is to be ion-implanted through the gate oxide film, compared with the concentration of the source region 2-12 and the drain region 2-13. The density is reduced by more than one digit. Therefore, 2-19 is an LDD region formed in a self-aligned manner.

Then, an interlayer insulating film 2-15 is formed as shown in FIG. The method for forming the oxide film is L
PCVD method, APCVD method Plasma CVD method, ECR
There are methods such as a plasma CVD method and a photoexcited CVD method. Further, as a source gas, an organic silicon compound TEOS (T
etra Ethyl Ortho-Silicat
There is a method using e) or ozone. When TEOS is used, excellent step coverage is realized. In addition, PSG (Pho
sposilicate glass) and BSG (B
When reflowing the orthosilicate glass), a more excellent step coverage can be realized. Regarding the film thickness, it is common that the film thickness is several thousand liters to several μm. LPCVD or plasma CVD is a simple method for forming the nitride film. For the reaction, a mixed gas of ammonia gas (NH ₃ ) and silane gas and nitrogen gas, a mixed gas of silane gas and nitrogen gas, or the like is used. If the step coverage of the interlayer insulating film is good, the lower insulating film 2-12 described above is unnecessary.

Subsequently, an activation anneal is performed for the purpose of densifying the interlayer insulating film, activating the source region and drain region, and recovering the crystallinity. As the conditions for the activation anneal, the temperature is lowered to about 800 to 1000 ° C. in an N ₂ gas atmosphere, and the annealing time is set to about 20 minutes to 1 hour. At 900 to 1000 ° C, impurities are considerably activated by annealing for about 20 minutes. 20 at 800-900 ° C
Anneal for 1 hour from a minute. On the other hand, first 500
A two-step activation anneal method in which the crystallinity is sufficiently recovered by annealing at ˜800 ° C. for about 1 to 20 hours and then activated at a high temperature of 900 to 1000 ° C. is also effective. In addition, RT using infrared lamp or halogen lamp
A (Rapid Thermal Annealin
The g) method is also effective. Furthermore, it is also effective to use a laser activation method using a laser beam or the like.

Next, when hydrogen ions are introduced by a method such as a hydrogen plasma method, a hydrogen ion implantation method, or a method of diffusing hydrogen from a plasma nitride film, dangling bonds or gates existing at grain boundaries are formed. Defects existing at the oxide film interface and the like, and defects existing at the source / junction portion between the drain portion and the channel portion are inactivated. Such a hydrogenation step may be performed before stacking the interlayer insulating films 2-13. Alternatively, the hydrogenation step may be performed after forming a source electrode and a drain electrode, which will be described later.

Next, as shown in FIG. 4B, contact holes are formed in the interlayer insulating film 2-15 and the gate oxide film 2-4 by photoetching. Then, as shown in the figure, a source electrode 2-16 and a drain electrode 2-17 are formed. The source electrode and the drain electrode are made of a metal material such as aluminum or chromium. In this way, a thin film transistor is formed.

[0036]

As described in the above embodiments, it becomes possible to form only the conductive type thin film transistor which constitutes the pixel switching thin film transistor with the LDD structure by a very simple method. According to the present invention, the off-leakage current of the pixel switching thin film transistor can be reduced. The characteristics are shown in FIG. This corresponds to FIG. 6 described above. The off-leakage current is very small even at a gate voltage of -20 V, and the rebound is significantly suppressed. As a result, flicker and display unevenness of the liquid crystal display are remarkably improved, and a very large effect on the improvement of panel characteristics is expected. Moreover, the present invention is realized by the same number of photo processes as the conventional process. Therefore, the manufacturing cost is the same as before.

Since only the pixel switching thin film transistor has the LDD structure selectively, it has no adverse effect on the drive circuit. Therefore, a sufficient on-current can be obtained, and high-speed operation is possible. It also meets the requirements for high definition and high definition TV (HDTV).

The off-leakage current of the pixel switching thin film transistor is reduced, and the off-leakage current remarkably decreases. As a result, the pixel holding characteristic is improved, and it becomes possible to realize a good liquid crystal display with extremely few flicker and display unevenness. On the other hand, there is a driving method called common swing in order to improve display characteristics. According to this driving method, a larger reverse bias voltage is applied to the pixel switching thin film transistor. According to the present invention, the rise of the off-leakage current is remarkably reduced, so that it can sufficiently withstand a driving method such as common swing. Therefore, further improvement in display characteristics is expected.

The LDD structure can be formed by a very simple method of etching the gate oxide film. Conventionally, the LDD structure has been formed by forming a sidewall at the end of the gate electrode by anisotropic etching. However, according to the present invention, it is possible to omit the difficult and poorly controlled process as in the conventional technique.

When the two-layer scanning line using the silicide film is applied to the present invention, the sheet resistance of the scanning line is reduced from 25Ω / □ in the case of the conventional polycrystalline silicon to about one third, 8Ω / □. You can Also in this case, the LDD structure can be easily formed. As a result, it is possible to easily manufacture an active matrix substrate having an extremely small off-leakage current and a low scanning line resistance value.

Since the gate signals are sent to the scanning lines from both the left and right sides, even if the scanning lines are broken, the resistance of the scanning lines is sufficiently small so that the signal delay is small and the screen display of the liquid crystal display is not affected. Absent. Therefore, even if a short circuit occurs between the source line and the scanning line, the short circuit defect can be repaired by cutting the scanning lines on both sides of the short circuit point. Thus, there is a great effect on the improvement of yield.

Since the scanning line resistance decreases, the scanning line time constant τ decreases. Therefore, the rising characteristics of the pixel transistor are uniform at the center and the edges of the screen. as a result,
Flicker or display unevenness can be reduced. Moreover, since it is not necessary to reduce the line capacitance of the scanning line,
The pixel retention characteristics do not deteriorate. As described above, according to the present invention, it is possible to realize a liquid crystal display with extremely little flicker or display unevenness without deteriorating the pixel holding characteristic.

With respect to the high-definition TFT, a light valve or the like is required in order to configure it as a projection type display, so that a large TFT panel of about 4 inches must be prepared. When a panel having such long scanning lines is produced, the effect of the present invention is further enhanced.

Since the resistance of the scanning line is lowered, it is possible to eliminate the additional pixel holding capacitance line. Therefore, the aperture ratio is improved, and as a result, a very bright liquid crystal display can be realized.

Since it has an offset gate structure,
The pixel retention characteristics are improved. Furthermore, a great effect is expected in reducing the current consumption.

By using the solid phase growth method, it becomes possible to form a silicon thin film having excellent crystallinity on an amorphous insulating substrate, which greatly contributes to the development of SOI technology. Lowering the resistance of the gate line has a great effect in maximizing the characteristics of the thin film transistor improved by a method such as solid phase growth and realizing a very excellent liquid crystal display.

When the present invention is applied to a contact-type image sensor in which a photoelectric conversion element and its scanning circuit are integrated in the same chip, it is extremely useful for increasing the reading speed, increasing the resolution, and obtaining gradation. Produce a great effect on. When higher resolution is achieved, contact type image for color reading
The application to a di-sensor becomes easy. Of course, the effect is great also for the reduction of power supply voltage, the reduction of current consumption, and the improvement of reliability. Further, since it can be manufactured by a low temperature process, the contact type image sensor chip can be lengthened, and a single chip can realize a reading device for a large facsimile such as A4 size or A3 size. Therefore, it is possible to avoid a technique such as double joining of the sensor chips and which is unreliable, and the mounting yield is improved.

Not only a quartz substrate or a glass substrate, but also a sapphire substrate or MgO.Al ₂ O ₃ , BP, CaF ₂
A crystalline insulating substrate such as the above can also be used.

Although the thin film transistor has been described above as an example, an element using a thin film such as a bipolar transistor or a heterojunction bipolar transistor can be used as well.
The present invention can be applied. Further, the present invention can be applied to an element using SOI technology such as a three-dimensional device.

Although the present invention has been described by taking the solid phase growth method as an example, the present invention is not limited to the solid phase growth method, and the LPC method may be used.
The present invention can also be applied to a case where a thin film semiconductor device is formed by using a poly-Si thin film formed by the VD method or other methods such as the EB vapor deposition method, the sputtering method or the MBE method. It can also be applied to a general MOS type semiconductor device.

[Brief description of drawings]

FIG. 1 is a structural cross-sectional view of a thin film semiconductor device showing an embodiment of the present invention.

2A to 2E are process cross-sectional views showing a method for manufacturing a thin film semiconductor device of the present invention.

3A to 3D are process cross-sectional views showing a method of manufacturing a thin film semiconductor device of the present invention. However,
(A) continues from FIG. 2 (e).

4A to 4B are process cross-sectional views showing a method for manufacturing a thin film semiconductor device of the present invention. However,
(A) continues from FIG. 3 (d).

FIG. 5 is a diagram showing characteristics of an Nch thin film transistor used in a pixel switching thin film transistor according to the present invention.

FIG. 6 is a diagram showing characteristics of an Nch thin film transistor used for a conventional pixel switching thin film transistor.

[Explanation of symbols]

1-2 Polycrystalline silicon thin film 1-3 Gate electrode 1-7 LDD region 1-4 Pixel electrode 1-5 Source region 1-6 Drain region 1-11 Interlayer insulating film 1-14 Same conductivity type as pixel switching thin film transistor Thin film transistor 1-15 1-14, a reverse-conductivity type thin film transistor 2-1 insulating transparent substrate 2-3 polycrystal silicon thin film 2-4 gate insulating film 2-5 gate electrode 2-6 P photoresist mask 2-7 Source region of Pch thin film transistor 2-8 Drain region of Pch thin film transistor 2-10 N photoresist mask 2-12 Source region of Pch thin film transistor 2-13 Drain region of Pch thin film transistor 2-19 LDD region 2-15 Interlayer insulating film

Claims (3)

[Claims] 1. A pixel arranged in a matrix, a pixel switching thin film transistor provided for each pixel to select the pixel, and a pixel drive circuit configured by an Nch thin film transistor and a Pch thin film transistor are the same. In the method of manufacturing a thin film semiconductor device integrated on an insulating transparent substrate, a thin film transistor of the same conductivity type as the pixel switching thin film transistor is formed by one ion implantation process.
A method of manufacturing a thin film semiconductor device, characterized in that a conduction type thin film transistor having a (Lightly Doped Drain) structure and different from the pixel switching thin film transistor has an ordinary self-aligned structure. 2. When the pixel switching thin film transistor according to claim 1 is composed of an Nch thin film transistor,
(1) A step of forming a Pch thin film transistor in a self-aligned manner by forming a resist mask after forming a first thin film semiconductor layer, a gate insulating film and a gate electrode, and ion-implanting impurities such as boron. 2) After removing the resist mask, a second resist mask is formed by a photo process on the gate insulating film other than the Pch thin film transistor, leaving the gate insulating film 1 to 5 μm thick from the end of the gate electrode to form the source and drain. A thin film semiconductor device comprising: a step of etching away the gate insulating film above the region; and (3) a step of ion-implanting impurities such as phosphorus or arsenic after removing the second resist mask. Production method. 3. When the pixel switching thin film transistor according to claim 1 is composed of a Pch thin film transistor,
(1) A step of forming a first thin film semiconductor layer, a gate insulating film, and a gate electrode, and then forming a resist mask, ion-implanting impurities such as phosphorus or arsenic, and forming a Nch thin film transistor in a self-aligned manner (2) After removing the resist mask, a second resist mask is formed by a photo process on the gate insulating film other than the Nch thin-film transistor, and 1 is formed from the gate electrode end.
A step of etching away the gate insulating film above the source and drain regions, leaving the gate insulating film thick by ~ 5 μm,
(3) A method for manufacturing a thin film semiconductor device, which comprises at least a step of ion-implanting boron or the like after removing the second resist mask.