JP3307021B2 - Method for manufacturing thin film semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION In a thin film semiconductor device in which a pixel switching Nch thin film transistor and a driving circuit constituted by an Nch thin film transistor and a Pch thin film transistor for driving the pixel switching thin film transistor are integrated on the same substrate, the pixel switching Nch thin film transistor is used. A thin-film semiconductor device for reducing the off-leak current of a thin film transistor, improving the retention characteristics of pixels, and realizing an active matrix type liquid crystal display device having a large driving frequency while having excellent display unevenness, flicker and resolution. It relates to a manufacturing method.

[0002]

2. Description of the Related Art Thin film transistors are used in an active matrix type liquid crystal display device (hereinafter, referred to as a liquid crystal display) as a pixel switching element, a driver circuit, a contact type image sensor, and an SRAM.
(Static Random Access Memo
ries).

A liquid crystal display will be described. A sufficiently large on-state current is required for a thin film transistor constituting a drive circuit. On the other hand, a pixel switching thin film transistor is required to have a sufficiently low off-leak current in order to improve the retention characteristics of the pixel and realize an active matrix liquid crystal display device having excellent display unevenness, flicker and resolution. Further, an increase in the off-leak current when a reverse bias voltage is applied to the gate electrode (hereinafter, referred to as a jump of the off-leak current) must be minimized (the flat panel display 9).
1, pp80-87, Nikkei BP).

A description will be given of a thin film transistor (hereinafter abbreviated as poly-Si TFT) using a polycrystalline silicon thin film in that a sufficient on-current can be obtained.
In the poly-Si thin film, a crystal grain boundary in which defect levels are distributed at a high density exists in a boundary region between crystal grains.
Due to the synergistic effect of the existence of the defect level and the reverse bias electric field applied to the drain end, the jump of the off-leak current of the poly-Si TFT is very large (Jpn.
J. Appl. Phys. , Vol. 31 (1992)
pp. 206-209). In order to reduce the electric field at the drain end, an LDD (Lightly Doped Drain) is used.
n) It is said that it is effective to form a structure, but it is necessary to use a technique such as anisotropic etching to form a side wall at the end of the gate electrode. Has not been adopted so far.

In a conventional liquid crystal display, since the pixel switching thin film transistor does not have the LDD structure, the off-leak current greatly increases. FIG. 6 shows the characteristics. The horizontal axis shows the gate voltage,
The vertical axis indicates the drain current. An off region is a gate voltage from 0V to -20V. The off-leak current increases rapidly as the reverse bias voltage increases.

As described above, in the conventional liquid crystal display, the off-leakage current of the pixel switching thin film transistor jumped very much, and the pixel holding characteristics were insufficient. Therefore, the liquid crystal display had large flicker and large display unevenness. Furthermore, there is a problem when producing a panel of a larger size or a panel for high definition. In addition, when a new driving method such as common swing is adopted, a larger reverse bias voltage is applied, so that the demand for the off-leak current becomes more severe (see seminar text, TFT color liquid crystal development technology and characteristic analysis / application). Design, 1991
21st and 22nd, Japan Industrial Technology Center, pp9-2
4).

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and to achieve a very simple method by using the same number of photo steps as before or less than the conventional number of photo steps. By selectively forming only the Nch thin film transistor into the LDD structure, it is possible to suppress the rise of the off leak current and to secure a sufficient on current. It is a major object to provide a method for easily producing a liquid crystal display having excellent display characteristics by improving the pixel holding characteristics.

[0008]

SUMMARY OF THE INVENTION The present invention comprises pixels arranged in a matrix, pixel switching Nch thin film transistors provided for each pixel to select the pixels, Nch thin film transistors and Pch thin film transistors. In a method of manufacturing a thin film semiconductor device in which a pixel driving circuit and a pixel driving circuit are integrated on the same insulating transparent substrate, (1) after forming a thin film semiconductor layer, a gate insulating film, and a gate electrode, Forming a resist mask, ion-implanting a P-type impurity, and forming a Pch thin film transistor in a self-aligned manner; (2) removing the first resist mask;
(3) forming a second resist mask on the Pch thin film transistor, ion-implanting an N-type impurity, and forming a source and drain portion of the Nch thin film transistor and L
Simultaneously forming a DD (Lightly Doped Drain) region; (4) removing the second resist mask,
At least a step of laminating an interlayer insulating film. With the above-described configuration, only the Nch thin film transistor can be selectively made to have the LDD structure by a very simple method using the same number of photo steps as before or the number of photo steps less than before.

The present invention also relates to a pixel arranged in a matrix, a pixel switching Nch thin film transistor provided for each pixel for selecting the pixel,
In a method of manufacturing a thin film semiconductor device in which a pixel driving circuit composed of an h thin film transistor and a Pch thin film transistor are integrated on the same insulating transparent substrate, (1) a thin film semiconductor layer, a gate insulating film, and a gate electrode are formed. Thereafter, a first resist mask is formed on the Nch thin film transistor, a P-type impurity is ion-implanted, and a Pch thin film transistor is formed in a self-aligned manner. (2) After removing the first resist mask, 1
(3) stacking the first interlayer insulating film, ion-implanting an N-type impurity to form a source and a drain of the Nch thin film transistor and an LDD (Lightly Dope);
(d Drain) region, and (4) a step of laminating a second interlayer insulating film after the N-type impurity ions are implanted.

Further, the ion implantation amount of the P-type impurity N
By setting p to be larger than the ion implantation amount Nn of the N-type impurity, there is an effect that it is not necessary to form an Nch resist mask.

[0011]

【Example】

Embodiment 1 First, the first invention will be described with reference to FIG. On the insulating amorphous material 1-1, a non-single-crystal semiconductor thin film 1-2 is formed. As the insulating amorphous material, a quartz substrate, a glass substrate, a nitride film or S
An iO ₂ film or the like is used. When a quartz substrate is used, the process temperature is allowed up to about 1200 ° C., but when a glass substrate is used, the process is limited to a low temperature process of 600 ° C. or less. Hereinafter, an example in which a quartz substrate is used and a solid-phase grown Si thin film is used as the non-single-crystal semiconductor thin film will be described. Of course, not only a solid-phase grown Si thin film, but also a polycrystalline Si thin film formed by a low pressure CVD method, a plasma CVD method, a sputtering method, or the like, or an SOI (Silic)
The present invention can also be realized using "on on Insulator".

As shown in FIG. 1A, a mixed gas of SiH ₄ and H ₂ is decomposed by a high frequency glow discharge of 13.56 MHz to form an amorphous phase on a quartz substrate 1-1 using a plasma CVD apparatus. A Si film 1-2 is deposited. The SiH ₄ partial pressure of the mixed gas is 10 to 20%, and the internal pressure in the deposit is 0.5.
About 1.5 torr. A substrate temperature of 250 ° C. or less and about 180 ° C. is suitable. The amount of bonded hydrogen determined by infrared absorption measurement was about 8 atomic%. The chamber before the deposition of the amorphous Si film 1-2 is subjected to Freon cleaning, and the deposited amorphous Si film is 2 × 10
Contains ¹⁸ cm ^-3 of fluorine. Therefore, in the present invention, after the freon cleaning, dummy deposition is performed,
Perform the actual deposition. Alternatively, abolish freon cleaning,
The chamber is washed by another method such as bead treatment.

Subsequently, the amorphous Si film is formed at a temperature of 400.degree.
Heat treatment at 00 ° C. to release hydrogen. This step is intended to prevent explosive desorption of hydrogen.

Next, the amorphous thin film 1-2 is solid-phase grown. For the solid phase growth method, furnace annealing using a quartz tube is convenient. As an annealing atmosphere, a nitrogen gas, a hydrogen gas, an argon gas, a helium gas, or the like is used. 1x1
Annealing may be performed in a high vacuum atmosphere of 0 ⁻⁶ to 1 × 10 ⁻¹⁰ Torr. Solid phase growth annealing temperature is 500 ° C ~
700 ° C. In such low temperature annealing, selectively,
Only crystal grains having a crystal orientation with a small activation energy for crystal growth grow and grow slowly and slowly.
In the experiment of the inventor, a large-diameter silicon thin film of 2 μm or more was obtained by performing solid phase growth at an annealing temperature of 600 ° C. and an annealing time of 16 hours. In FIG. 1B, reference numeral 1-3 denotes a solid-phase grown silicon thin film.

Although the method of forming a silicon thin film by the solid phase growth method has been described above, in addition, LPCVD
The silicon thin film may be formed by a method such as a sputtering method or a vapor deposition method.

Next, the solid-phase-grown silicon thin film is patterned by photolithography into an island shape as shown in FIG.

Next, as shown in FIG. 1D, a gate oxide film 1-4 is formed. As a method for forming the gate oxide film, LPCVD method, photo-excitation CVD method, plasma CVD method, ECR plasma CVD method, high vacuum evaporation method, plasma oxidation method, high-pressure oxidation method, etc. There is a low temperature method. The gate oxide film formed by the low-temperature method becomes an excellent film which is denser and has less interface states by heat treatment. When a quartz substrate is used as the amorphous insulating substrate 1-1, a thermal oxidation method can be used. The thermal oxidation method includes d
There are a ry oxidation method and a wet oxidation method. At about 800 ° C. or higher, an oxide film is formed. To use a quartz substrate, for example, 1
It is suitable to carry out dry oxidation at a temperature as high as 000 ° C. or higher. The thickness of the gate oxide film is from 500 ° to 1
About 500 ° is suitable.

After the gate oxide film is formed, if necessary, boron may be channel-ion-implanted and channel-doped.
This is intended to prevent the threshold voltage of the Nch thin film transistor from shifting to the negative side. The amorphous silicon film has a deposition thickness of 500 to 1;
In the case of about 500 °, the dose amount of boron is 1 × 10 ¹²
About 5 × 10 ¹² cm ⁻² is suitable. When the thickness of the amorphous silicon film is as thin as 500 ° or less, the amount of boron dose is reduced, and as a guide, it is set to 1 × 10 ¹² cm ⁻² or less. When the film thickness is 1500 ° or more, the boron dose is increased, and the standard is 5 × 10 ¹² cm.
^-2 or more.

Instead of channel ion implantation, boron may be added during the deposition of the 1-2 silicon film. This is obtained by flowing a diborane gas (B ₂ H ₆ ) together with a silane gas into the chamber during the silicon film deposition to cause a reaction.

Next, as shown in FIG. 1E, a description will be given of a method of forming the gate electrode 1-5. Here, a case where a low-resistance polycrystalline silicon film is used will be described as an example. First, a film formation method using a diffusion method will be described.
A polycrystalline silicon film is deposited by a method such as the LPCVD method, and then P is added to the polycrystalline silicon film by POCl ₃ diffusion at 900 to 1000 ° C. At this time, since a thin oxide film is formed on the polycrystalline silicon film, the oxide film is removed with an aqueous solution containing hydrofluoric acid. There is also a method of adding P by an ion implantation method. In addition, there is a method of forming the gate electrode 1-5 by depositing a doped polycrystalline silicon film. This is a method of forming a film by decomposing a mixed gas of a SiH ₄ gas and a PH ₃ gas. An impurity-added polycrystalline silicon film is formed by thermal decomposition at 500 to 700 ° C. in the LPCVD method and glow discharge decomposition in the PECVD method. In the PECVD method, a doped amorphous silicon film can be formed at about 300 ° C. It is also an effective method to grow this doped amorphous silicon film into a high-quality polycrystalline silicon film by the solid phase growth method as described above.

The P-doped polycrystalline silicon film having a concentration of 1 × 10 ¹⁹ cm ⁻³ or more is formed by the above-described method.
Deposit about Å. In this case, the sheet resistance of the gate electrode is about 20 to 30 Ω / □.

In order to further reduce the sheet resistance of the gate electrode, there is a method using a two-layer gate electrode in which an impurity-doped polycrystalline silicon film and a silicide film are laminated. As the silicide film, cobalt silicide (CoSi ₂ ), nickel silicide (NiSi), titanium silicide (TiSi ₂ ), molybdenum silicide (MoSi ₂ ), or tungsten silicide (WS)
i ₂ ). When a MoSi ₂ film is used as the silicide film, the sheet resistance is 7 to 8 when deposited at 1500 °.
It is about Ω / □. The resistance of the gate line is reduced by about one third.

Next, formation of a Pch thin film transistor will be described first. As shown in FIG.
Pch photoresist mask 1 on the thin film transistor
6 is formed.

Subsequently, as shown in FIG. 2B, ion implantation for forming a source region and a drain region is performed. By ion implantation, an acceptor-type impurity is ion-implanted into the first semiconductor layer, and the gate electrode 1-
5, a source region and a drain region are formed in a self-aligned manner. In FIG. 2B, reference numeral 1-7 denotes a source region into which ions are implanted at a high concentration, and 1-8 denotes a drain region.

As the acceptor type impurity, boron (B) or the like is used. As a method for adding impurities, there is a method such as a laser doping method or a plasma doping method in addition to the ion implantation method. Arrows indicated by 1-9 indicate ion beams of impurities. When a quartz substrate is used as the insulating amorphous material 1-1, a thermal diffusion method can be used. The impurity dose is 1 × 10 ¹⁴
From about 1 × 10 ¹⁷ cm ⁻² . In terms of impurity concentration, it is about 1 × 10 ¹⁹ to 1 × 10 ²² cm ^{−3 in} the source region 1-7 and the drain region 1-8. Further, the acceleration energy of the ions is set so that the maximum value of the concentration distribution of the implanted impurity exists near the interface between the polycrystalline silicon thin film 1-3 and the gate insulating film 1-4. For example, when the thickness of the gate oxide film is 1200 °, an ion acceleration energy of 30 to 40 keV is suitable.

After peeling off the Pch photoresist mask 1-6, a first interlayer insulating film 1-10 is laminated as shown in FIG. As the first interlayer insulating film, S
An iO ₂ film is suitable. The film is deposited at a thickness of about 1000 to 3000 °.

At the end of the gate electrode 1-5, the thickness of the first interlayer insulating film is increased by the thickness of the gate electrode. For example, assuming that the thickness of the gate electrode is 5000 °, the thickness of the gate insulating film 1-4 is 1200 °, and the thickness of the first interlayer insulating film is 2000 °, the variation in the thickness of the first interlayer insulating film is caused at the end of the gate electrode. 8200 °, while 1
When the distance is about μm, the thickness becomes thin and becomes 3200 °. As will be described later, the Nch thin film transistor has an LDD structure by utilizing this fact.

Next, a method of forming an Nch thin film transistor constituting the pixel switching thin film transistor will be described. As shown in FIG. 2D, an Nch photoresist mask 2-11 is formed. The Nch photoresist mask 1-11 covers the Pch thin film transistor.

Subsequently, as shown in FIG. 2E, donor type impurity ions are implanted by an ion implantation method. As the donor-type impurity, phosphorus (P) or arsenic (As) is used. Reference numeral 1-15 denotes an ion beam.

As an impurity doping method, there are a laser doping method and a plasma doping method other than the ion implantation method. When a quartz substrate is used as the insulating amorphous material 1-1, a thermal diffusion method can be used.

When the ion implantation method is used, the acceleration energy of ions is an important parameter. As described above, in the region about 1 μm from the end of the gate electrode, the thickness of the first interlayer insulating film is as large as 8200 ° to 3200 °.
However, at a distance of about 1 μm or more from the end of the gate electrode, it becomes substantially constant at 3200 °. The acceleration energy of ions is set so that the highest value of the concentration distribution of the implanted impurity is present on the surface of the polycrystalline silicon thin film 1-3 in a region where the thickness of the first interlayer insulating film is substantially constant at 3200 °. I do. Therefore, when phosphorus is ion-implanted, the LSS theory (references IEICE '73 /
3 Vol. 56-C No. 3 page 179), it is suitable to set the ion acceleration energy from 280 keV to 330 keV. In the region of about 1 μm from the end of the gate electrode, the thickness of the first interlayer insulating film is large and varies from 8200 ° to 3200 °, and the implanted ions are normally distributed with respect to the depth. Therefore, the impurity concentration in the range of 1 μm from the end of the gate electrode is about two orders of magnitude lower than the impurity concentration in the region separated by 1 μm or more. Therefore, as shown in FIG. 2E, a low concentration LDD region 1-12 and a high concentration source region 1-13 and drain region 1-14 are automatically formed.

Subsequently, an Nch photoresist mask 1-
After peeling off 11, a second interlayer insulating film 1-16 is formed as shown in FIG. As a method for forming an oxide film, LPCVD, APCVD, plasma CVD,
There are methods such as an ECR plasma CVD method and a light excitation CVD method. Further, an organic silicon compound TEO is used as a source gas.
S (Tetra Ethyl Ortho-Silic)
ate) and a method using ozone. The use of TEOS achieves excellent step coverage. In addition, PSG (P
phosphosilicate glass) or BSG
By reflowing (Borosilicate glass), more excellent step coverage can be realized. Regarding the film thickness, the thickness is usually several thousand to several μm. As a method for forming a nitride film, an LPCVD method, a plasma CVD method, or the like is simple. For the reaction, a mixed gas of ammonia gas (NH ₃ ), silane gas and nitrogen gas, or a mixed gas of silane gas and nitrogen gas is used.

Subsequently, activation annealing is performed for the purpose of densifying the interlayer insulating film, activating the source and drain regions, and restoring crystallinity. The conditions for the activation annealing are as follows: the temperature is lowered to about 800 to 1000 ° C. in an N ₂ gas atmosphere, and the annealing time is about 20 minutes to 1 hour. At 900 to 1000 ° C., impurities are considerably activated by annealing for about 20 minutes. 20 at 800-900 ° C
Anneal for a minute to one hour. On the other hand, first 500
There is also an effect of a two-step activation annealing method in which the crystallinity is sufficiently recovered by annealing at a temperature of about 800 ° C. for about 1 to 20 hours and then activated at a high temperature of 900 to 1000 ° C. In addition, RT using an infrared lamp or a halogen lamp
A (Rapid Thermal Annealin)
The method g) is also effective. Further, it is also effective to use a laser activation method using a laser beam or the like.

Next, when hydrogen ions are introduced by a method such as a hydrogen plasma method, a hydrogen ion implantation method, or a method of diffusing hydrogen from a plasma nitride film, dangling bonds existing at crystal grain boundaries and gate oxide films are removed. Defects existing at the interface and the like, and defects existing at the junction between the source / drain portion and the channel portion are inactivated. Such a hydrogenation step may be performed before laminating the second interlayer insulating film 1-16. Alternatively, the hydrogenation step may be performed after forming a source electrode and a drain electrode described later.

Next, as shown in FIG. 3B, contact holes are formed in the first interlayer insulating film 1-10, the second interlayer insulating film 1-16, and the gate oxide film 1-4 by photoetching. . Then, as shown in FIG.
7 and the drain electrode 1-18 are formed. The source electrode and the drain electrode are formed of a metal material such as aluminum or chromium. Thus, a thin film transistor is formed.

(Embodiment 2) The photo step can be further reduced by one step by defining the impurity concentration of the source and drain regions of the Pch thin film transistor and the Nch thin film transistor. This will be described below as a second invention.

Since the steps up to the step of forming the first interlayer insulating film are the same as those of the first invention, the description is omitted here. Therefore, a description will be given with reference to a diagram subsequent to FIG.

After the first interlayer insulating film 1-10 is formed as shown in FIG. 4A, phosphorus or arsenic ions are implanted as shown in FIG. Form. At this time, it is important that the dose Nn of phosphorus or arsenic be smaller than the dose Np of boron. By setting the respective dose amounts in this manner, the source and drain portions of the Pch thin film transistor maintain the properties of a P-type semiconductor. Therefore, it is not necessary to perform the Nch photo process.

FIG. 4B is the same as FIG. 2E. As described above, since the ions are implanted through the first interlayer insulating film, the Nch thin film transistor automatically
D structure.

In the subsequent steps, a thin film transistor is manufactured by the same steps as those described with reference to FIG.

[0041]

As described in the above embodiments, it is possible to form only the conductive type thin film transistor constituting the pixel switching thin film transistor with the LDD structure by a very simple method. According to the present invention, the off-leak current of the pixel switching thin film transistor can be reduced. The characteristics are shown in FIG. This corresponds to FIG. 6 described above. Even at a gate voltage of -20 V, the off-leakage current is very small, and the jump is significantly suppressed. As a result, flicker, display unevenness and the like of the liquid crystal display are remarkably improved, and a very large effect is expected to improve panel characteristics. In addition, the present invention is realized by the same number of photo processes as the conventional processes. Therefore, the manufacturing cost is not different from the conventional one.

Since only the pixel switching thin film transistor has the LDD structure selectively, there is no adverse effect on the drive circuit. Also, there is no increase in the contact resistance of the source and drain electrodes. Therefore, a sufficient on-current can be obtained, and high-speed operation can be performed. It also meets the requirements for higher definition and HDTV (HDTV).

The off-leak current of the pixel switching thin film transistor is reduced, and the jump of the off-leak current is significantly reduced. As a result, the pixel holding characteristics are improved, and a favorable liquid crystal display with extremely little flicker and display unevenness can be realized. On the other hand, there is a driving method called common swing to improve display characteristics. According to this driving method, a larger reverse bias voltage is applied to the pixel switching thin film transistor. According to the present invention, the jump of the off-leakage current is remarkably reduced, so that it can sufficiently withstand a driving method such as common swing. Therefore, further improvement in display characteristics is expected.

In the past, since ion implantation was performed only through the gate oxide film, the lateral diffusion of the implanted ions created an overlap region between the source and drain ends and the gate. The current could not be reduced. However, in the present invention, since the ion implantation is performed after forming the relatively thin first interlayer insulating film, the LDD structure can be obtained automatically.
Thus, an LDD structure can be formed by a very simple method. Conventionally, an LDD structure has been formed by forming a side wall at an end of a gate electrode by anisotropic etching.
However, according to the present invention, difficult and poorly controllable steps as in the related art can be omitted.

By reducing the ion dose of the source and drain portions of the Nch than that of the Pch, the number of photo steps can be further reduced by one.

When a two-layer scanning line using a silicide film is applied to the present invention, the sheet resistance of the scanning line is reduced from 25 Ω / □ in the case of conventional polycrystalline silicon to about one-third 8 Ω / □. I can do it. Also in this case, the LDD structure can be easily formed. As a result, an active matrix substrate having extremely low off-leakage current and low scanning line resistance can be easily manufactured.

Since gate signals are sent to the scanning lines from both the left and right sides, even if a disconnection occurs in the scanning lines, the signal delay is small because the resistance of the scanning lines is sufficiently small, and there is no effect on the screen display of the liquid crystal display. Absent. Therefore, even if a short circuit occurs between the source line and the scanning line, the short-circuit defect can be relieved by cutting the scanning lines on both sides of the short-circuit point. Thus, there is a great effect on the improvement of the yield.

Since the scanning line resistance is reduced, the time constant τ of the scanning line is reduced. Therefore, the rising characteristics of the pixel transistors at the center and the edge of the screen become uniform. as a result,
Flicker or display unevenness can be reduced. Moreover, since it is not necessary to reduce the line capacity of the scanning line,
The retention characteristics of the pixels do not deteriorate. As described above, according to the present invention, a liquid crystal display with extremely little flicker or display unevenness can be realized without lowering the pixel holding characteristics.

For a high-vision TFT, a large TFT panel of about 4 inches has to be produced because a light valve or the like is required in order to constitute a projection type display. When a panel having such a long scanning line is manufactured, the effect of the present invention is further enhanced.

Since the resistance of the scanning line is reduced, it is possible to eliminate an additional pixel holding capacitance line. Therefore, the aperture ratio is improved, and as a result, a very bright liquid crystal display can be realized.

Since it has an offset gate structure,
The pixel retention characteristics are improved. Further, a great effect is expected to reduce current consumption.

The use of the solid phase growth method makes it possible to produce a silicon thin film having excellent crystallinity on an amorphous insulating substrate, which greatly contributes to the development of SOI technology. Reducing the resistance of the gate line has a great effect on maximizing the characteristics of the thin film transistor improved by a method such as solid phase growth and realizing a very excellent liquid crystal display.

When the present invention is applied to a contact type image sensor in which a photoelectric conversion element and its scanning circuit are integrated in the same chip, it is very difficult to increase the reading speed, increase the resolution, and obtain gradation. To produce great effects. When a higher resolution is achieved, application to a contact image sensor for color reading becomes easier. Of course, the effect is great also for reduction of power supply voltage, reduction of current consumption, and improvement of reliability. In addition, since it can be manufactured by a low-temperature process, the length of the contact-type image sensor chip can be increased, and a single chip can realize a reading device for large facsimile such as A4 size or A3 size. Therefore, it is possible to avoid troublesome techniques such as double splicing of sensor chips and unreliable technology, and the mounting yield is improved.

Not only a quartz substrate and a glass substrate, but also a sapphire substrate or MgO.Al ₂ O ₃ , BP, CaF ₂
And other crystalline insulating substrates.

Although a thin film transistor has been described above as an example, a device using a thin film, such as a bipolar transistor or a heterojunction bipolar transistor, can also be used.
The present invention can be applied. Further, the present invention can be applied to an element using the SOI technology such as a three-dimensional device.

The present invention has been described by taking the solid phase growth method as an example.
The present invention can also be applied to the case where a thin-film semiconductor device is manufactured using a poly-Si thin film formed by a VD method or another method, for example, an EB evaporation method, a sputtering method, or an MBE method. Further, it can be applied to a general MOS type semiconductor device.

[Brief description of the drawings]

FIGS. 1A to 1E are process cross-sectional views illustrating a method for manufacturing a thin-film semiconductor device according to a first invention of the present invention.

FIGS. 2A to 2E are process cross-sectional views illustrating a method for manufacturing a thin-film semiconductor device according to a first invention of the present invention. However, FIG. 2A is continued from FIG. 1E.

FIGS. 3A and 3B are process cross-sectional views illustrating a method for manufacturing a thin-film semiconductor device according to a first invention of the present invention. However, FIG. 3A is continued from FIG. 2D.

FIGS. 4A and 4B are process cross-sectional views illustrating a method for manufacturing a thin-film semiconductor device according to a second invention of the present invention. However, FIG. 4A is continued from FIG. 2B.

FIG. 5 is a diagram showing characteristics of an Nch thin film transistor used for a pixel switching thin film transistor according to the present invention.

FIG. 6 is a diagram showing characteristics of an Nch thin film transistor used for a conventional pixel switching thin film transistor.

[Explanation of symbols]

 1-3 Polycrystalline silicon thin film 1-5 Gate electrode 1-10 First interlayer insulating film 1-12 LDD region 1-13 Source region 1-14 Drain region 1-16 Second interlayer insulating film

Continuation of the front page (51) Int.Cl. ⁷ identification symbol FI H01L 27/092 H01L 27/08 321E (58) Investigation field (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 H01L 21 / 8238 H01L 27/08 331 H01L 27/092 G02F 1/1368

Claims (3)

(57) [Claims] 1. A pixel arranged in a matrix, a pixel switching Nch thin film transistor provided for each pixel for selecting the pixel, and a pixel driving circuit composed of an Nch thin film transistor and a Pch thin film transistor are the same. In a method of manufacturing a thin film semiconductor device integrated on an insulating transparent substrate, (1) after forming a thin film semiconductor layer, a gate insulating film and a gate electrode, forming a first resist mask on the Nch thin film transistor; Forming a Pch thin film transistor in a self-aligned manner by ion-implanting a type impurity, (2) removing the first resist mask,
(3) forming a second resist mask on the Pch thin film transistor, ion-implanting an N-type impurity, and forming a source and drain portion of the Nch thin film transistor and L
Simultaneously forming a DD (Lightly Doped Drain) region; (4) removing the second resist mask,
A method of manufacturing a thin-film semiconductor device, comprising at least a step of laminating an interlayer insulating film. 2. A pixel arranged in a matrix, a pixel switching Nch thin film transistor provided for each pixel for selecting the pixel, and a pixel driving circuit composed of an Nch thin film transistor and a Pch thin film transistor are the same. In a method of manufacturing a thin film semiconductor device integrated on an insulating transparent substrate, (1) after forming a thin film semiconductor layer, a gate insulating film and a gate electrode, forming a first resist mask on the Nch thin film transistor; Forming a Pch thin film transistor in a self-aligned manner by ion-implanting a type impurity, (2) removing the first resist mask,
(3) stacking the first interlayer insulating film, ion-implanting an N-type impurity to form a source and a drain of the Nch thin film transistor and an LDD (Lightly Dope);
(d Drain) region; and (4) a step of laminating a second interlayer insulating film after the N-type impurity ions are implanted. 3. The ion implantation amount Np of the P-type impurity is:
3. The method according to claim 2, wherein the ion implantation amount of the N-type impurity is larger than Nn.