JP3347340B2 - Method for manufacturing thin film transistor - Google Patents

Abstract

PURPOSE:To obtain a transistor which has large mobility and is excellent in electric characteristics by using a superior polycrystalline silicon thin film having no defects at a process temperature capable or using a grass substrate, by a method wherein, after a silicon layer stuck and formed on an insulative substrate is irradiated with an energetic beam, said layer is patterned. CONSTITUTION:After a silicon layer 103 is stuck and formed on an insulative substrate 101, the silicon layer 103 is irradiated with an energetic beam 104, and heat treatment is performed, the silicon layer 103 is patterned. An insulative thin film is stuck and formed so as to cover the silicon layer 103. A gate electrode is stuck and formed on the insulative thin film. After impurities are implanted in the silicon thin film 103 through the insulative thin film, a laser beam is applied, thereby activating the impurities. For example, a silicon dioxide film 102 is formed on a glass substrate 101, and the silicon layer 103 is formed on the film 102 by a low pressure CVD method. Next excimer laser is projected and heat treatment is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a thin film transistor applied to an active matrix type liquid crystal display, an image sensor, a liquid crystal shutter array, a three-dimensional integrated device, and the like.

[0002]

2. Description of the Related Art Conventionally, it is known that a semiconductor thin film on an insulating substrate has the following advantages as applied to a picture element of an active matrix type liquid crystal display.

A transistor having uniform characteristics can be formed on a transparent substrate that transmits visible light, which is difficult to realize with a silicon substrate. The stray capacitance can be reduced by reducing the PN junction area.

Further, a thin film transistor is formed on a quartz substrate by applying a bulk semiconductor technique, and a pixel transistor is formed on the same substrate, or a C-MOS circuit using the thin film transistor for driving the pixel on the same substrate. There is also an example that constitutes. However, this C-MOS circuit has 100
Since the gate insulating film formed at a temperature of 0 ° C. or higher and the impurity after ion implantation are activated, the strain point is 800 ° C.
There is a disadvantage that the following inexpensive large-area glass substrates cannot be used.

[0005] In addition, since a single crystal insulating substrate such as sapphire is expensive, an alternative is to use a fused quartz plate or an amorphous SiO ₂ film formed by oxidizing a Si substrate at a temperature of 1000 ° C. or higher. Amorphous Si deposited on Si substrate
A method has been proposed in which an O ₂ film or an amorphous SiN film is used and a semiconductor thin body is formed thereon. However,
Since these SiO ₂ films and SiN films are not single crystals, if a silicon layer is formed thereon and crystallized by a process at a temperature of 1000 ° C. or more, polycrystals grow on the substrate. The grain size of this polycrystal is several tens of nanometers, and even if a MOS transistor is formed thereon, the carrier mobility is about one-seventh of that of a MOS transistor on bulk silicon.

Further, a MOS transistor on an inexpensive glass substrate having a strain point of 850 ° C. or less for an active matrix substrate of a liquid crystal display cannot use a process of 1000 ° C. or more. Even if a silicon layer is deposited by a growth method, since the grain size of the polycrystal is at most several nm, even if a MOS transistor is formed thereon,
The carrier mobility is about one-tenth of the MOS transistor on bulk silicon.

Therefore, recently, a method of scanning a laser thin film, an electron beam or the like on a silicon thin film and melting and re-solidifying the thin film to increase the crystal grain size and to form a single crystal has been studied. According to this method, a high-quality silicon single crystal phase or a high-quality polycrystal can be formed on an insulating substrate, and the characteristics of a device manufactured using the same can be improved, and the characteristics of a device manufactured on bulk silicon can be improved. Improve to a degree. Further, according to this method, the elements can be stacked, and a so-called three-dimensional IC can be realized. Then, a circuit having characteristics such as high density, high speed, and multiple functions can be obtained.

As a first conventional example of applying a laser beam to crystallization of a silicon layer in an active region of a MOS transistor to improve the performance of the MOS transistor, Japanese Patent Application Laid-Open No. 61-78119, "Method of Manufacturing Semiconductor" Is mentioned.

Further, in order to obtain a self-aligned structure for forming a thin film transistor of a three-dimensional element or a liquid crystal display, an impurity is implanted by an ion implantation method, and a source region and a drain of the thin film transistor are irradiated by a laser beam. Attempts have been made to form regions. According to this method, a self-aligned thin film transistor can be formed by a low-temperature process at 600 ° C. or lower.

As a second conventional example in which a laser beam is applied to the activation of impurities implanted in the source / drain regions of a MOS transistor, Extended Abstracts of the
22nd (1990 International) Conference on Solid State
Devices and Materials, Sendai, 1990, pp. 971-974 `` La
rge Area Doping Process for Fabricating of p-SiTF
T's Using Bucket Ion Source and XeCl Excimer Laser
Annealing ".

The above-mentioned first conventional example will be described with reference to FIG. A polycrystalline silicon layer is formed on a heat-resistant glass 601 having a lower melting point than quartz by a CVD method, and is irradiated with a short-wavelength laser 604 as shown in FIG. 6A to crystallize the surface of the polycrystalline silicon layer. As shown in FIG. 6B, the lower region 607 of the laser-irradiated silicon layer is made amorphous by implanting silicon ions 605, and then this silicon layer is subjected to a heat treatment at 600 ° C. for about 15 hours to solidify the amorphous portion. Attempts are made to increase the size 608 of the crystal grains by phase growth. It is a well-known fact that good electrical characteristics with a large effective mobility can be obtained when the thickness of the active region of the thin film transistor is 100 nm or less, particularly 20 to 50 nm. In the conventional example, in order to obtain a thin film silicon layer having a thickness of about several tens nm, the surface of the polycrystalline silicon layer after the solid phase growth step shown above is etched with phosphoric acid as shown in FIG. I am giving. In general, it is known that a polycrystalline silicon layer subjected to solid phase growth can have large crystal grains having a grain size of about several μm when observed by a TEM (electron transmission microscope), but a crystal grain boundary (Glen boundary)
Not only that, there are a very large number of fine defects inside the crystal grains. For this reason, in order to increase the electrical characteristics of the thin film transistor, for example, the effective mobility, the conventional example attempts to hydrogenate the polycrystalline silicon layer after the solid phase growth. In the conventional example, this hydrogenation treatment is carried out in FIG.
At the stage when the above process is completed, an attempt is made to realize a high quality polycrystalline silicon layer.

Further, in the conventional example, the polycrystalline silicon layer manufactured as described above is applied to the formation of a thin film transistor. However, the polycrystalline silicon layer is formed by a self-alignment method using a gate electrode formed of the impurity-doped polycrystalline silicon layer as a mask. A source region and a drain region are formed to form a thin film transistor as shown in FIG. 6G.

However, the above conventional example has the following problems. That is, a short-wavelength laser beam is applied to the polycrystalline silicon layer formed by the CVD method to crystallize only the surface portion, and the lower region of the silicon layer is made amorphous by implantation of silicon ions, and then solid-phased. Attempts have been made to obtain large crystal grains by growth treatment. However, the size of crystal grains of the silicon layer 606 annealed by excimer laser beam annealing is 100 n.
m, and in the step of solid phase growth after ion implantation, since each crystal of the silicon layer 606 becomes a nucleus and the amorphous layer 607 is crystallized, it can be obtained by the conventional solid phase growth. The grain size of the crystal is limited by the size of the silicon layer 606, and the grain size of the crystal obtained by solid phase growth is at most 1
In this case, a crystal having a large grain size, which is intended in the conventional example, cannot be obtained. In addition, since crystals formed by solid phase growth have many fine defects inside, the method according to the conventional example can only provide crystals having a large number of crystal defects inside and having a grain size of 100 nm.

In order to improve the electrical characteristics of the thin film transistor, the silicon layer crystallized by the above-described method is etched with phosphoric acid to be thin, but the etching rate by phosphoric acid is only 0.2 to 0. Therefore, it takes 160 to 400 minutes to set the initial film thickness of 100 nm to 20 nm to 50 nm. 17
Not only is it difficult to control the aging of the state of the phosphoric acid solution at 0 ° C., but also the drawback is that the so-called throughput is extremely low.

Further, since the glass substrate is exposed to a phosphoric acid solution at 170 ° C., constituents of glass, for example, aluminum ions, calcium ions, sodium ions, etc., are dissolved in the phosphoric acid solution from the back surface where the polycrystalline silicon film is not formed. However, there is a problem that the above-mentioned ions adhere to the surface of the polycrystalline silicon film etched with the phosphoric acid, thereby significantly deteriorating the quality of the polycrystalline silicon layer. Therefore, the subthreshold characteristic of the thin film transistor manufactured by applying this method is deteriorated.

After the solid phase growth step shown in FIG. 6D or the polycrystalline silicon layer thinning step with phosphoric acid shown in FIG. 6E is completed, crystal defects occurring at crystal grain boundaries, dangling bonds of silicon atoms, so-called traps After the completion of this step, a gate electrode is formed by impurity-doped polycrystal. The formation of impurity-doped polycrystalline silicon requires a temperature of about 600 ° C., but the heat treatment at a temperature of 450 ° C. or more dissociates hydrogen atoms from silicon atoms. Therefore, in the method of forming a thin film transistor according to the conventional example, since hydrogen atoms in the polycrystalline silicon film escape, the electrical characteristics are extremely high despite attempting to increase the crystal grain size by solid phase growth. There was a problem that the thin film transistor was obtained.

In the second conventional example, an impurity is ion-implanted into the silicon thin film in the source / drain region exposed by stripping the insulating film using a bucket ion source apparatus, and the impurity is activated by beam annealing with an argon laser. To form source / drain regions in a self-aligned manner with respect to the gate electrode. In the ion implantation method, ions implanted in the depth y direction of the silicon thin film perform so-called two-dimensional channeling in which the ions are channeled in a direction inclined with respect to the y-axis. Therefore, as shown in FIG. Impurities are also implanted at the boundary between the source region and the channel region, and also at the boundary between the drain region and the channel region. However, as in the second embodiment, the impurity implanted into the silicon layer is irradiated with a laser beam. When activated, the impurities in the boundary region described above are not activated,
As shown in FIG. 7B, the impurity is not activated, and a region 710 having a defect remains. Therefore, the thin film transistor manufactured according to the second conventional example has a problem that the leak current between the source and the drain becomes large when the gate voltage is off due to a defect at the boundary between the drain region and the channel region below the gate electrode. There was a point.

[0018]

SUMMARY OF THE INVENTION In view of the above, the present invention provides a method of manufacturing a thin film transistor in which a source region and a drain region are formed in a self-aligned manner with respect to a gate electrode at a process temperature at which an inexpensive glass substrate can be used. It provides a method. Another object of the present invention is to provide a method of manufacturing a thin film transistor in which a source region and a drain region are uniformly formed over the entire surface of a substrate in a self-aligned manner. Another object of the present invention is to provide a method for manufacturing a thin film transistor having high mobility and excellent electrical characteristics by using a high-quality polycrystalline silicon thin film having no defect. Another object of the present invention is to provide a method of manufacturing a self-aligned thin film transistor which has a small generation of a leak current between a source and a drain at a process temperature at which an inexpensive glass substrate can be used.

[0019]

According to the present invention, there is provided a method of manufacturing a thin film transistor, comprising the steps of: forming a silicon layer on a substrate; irradiating the silicon layer with an energy beam to crystallize the silicon layer; Performing a heat treatment of the silicon layer after the step of performing the energy beam irradiation.
It is characterized by being carried out at ^-5 mmHg or less.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments. FIGS. 1 and 2 explain the core part of the embodiment of the present invention. FIGS. 3, 4 and 5 show first, second and third thin film transistors to which the method of FIGS. 1 and 2 is applied. Examples of the production method of the present invention will be shown.

FIG. 1 is a cross-sectional view showing a manufacturing process of a polycrystalline silicon layer of a thin film transistor according to the present invention. FIG.
As shown in FIG.
For example, a silicon dioxide film 102 is formed on a transparent glass substrate by atmospheric pressure chemical vapor deposition at a substrate temperature of 200 to 350 ° C. to a thickness of 200 nm.

Next, a silicon layer 103 having a film thickness of 10 nm to 50 nm is formed at a substrate temperature of 550 to 650 ° C. by, for example, a low pressure chemical vapor deposition method. In order to control the threshold value of the thin film transistor, an impurity may be introduced into the silicon layer 103 by an ion implantation method or the like.

Next, as shown in FIG. 1b, the silicon layer is irradiated with an energy beam. An example of the energy beam is a XeCl excimer laser having a wavelength of 308 nm. The beam annealing conditions for the silicon layer formed by the low pressure chemical vapor deposition method are as follows. The pulse width of the pulse laser is 50 nsec.
Energy intensity of the individual pulses of the pulse laser immediately preceding 3 is 200~700mJcm ^-2, a more appropriate strength is 300~600mJcm ^-2. The number of pulses applied to the same portion of the silicon layer 103 may be plural. When performing beam annealing,
The partial pressure of oxygen around the silicon layer 103 is 10 ⁻⁵ mmH
g or less.

This is because, if oxygen exists on the surface of the silicon layer 103 or in the vicinity thereof, when the temperature of the silicon layer 103 is increased by beam annealing, oxygen or nitrogen reacts and is taken into the silicon layer as an impurity. No silicon layer can be obtained. Therefore, when annealing the silicon layer, it is preferable to anneal in a vacuum or an inert gas atmosphere as much as possible. However, when the surface of the silicon layer crystallized with hydrofluoric acid or the like after laser annealing is removed, beam annealing can be performed in an oxygen atmosphere, a nitrogen atmosphere, or the air.

The laser beam 104 is not limited to the XeCl excimer laser, but may be an ArF excimer laser, a KrF excimer laser, a YAG laser, or the like.

By the beam annealing, the silicon layer becomes a polycrystalline silicon layer 105 having a chevron structure as shown in FIG. 1C.

Since the potential barrier at the interface between the silicon layer and the silicon dioxide is about 3.1 eV, when the energy beam at the time of beam annealing is ultraviolet light such as an excimer laser having a wavelength of 308 nm, electrons in the silicon layer are Injected into the silicon dioxide film 102, a positive charge is held at the interface of the silicon layer opposite to the silicon dioxide interface. Therefore, as long as the positive charges are not eliminated, the characteristics of the drain current with respect to the gate voltage of the completed thin film transistor tend to be depleted. Therefore, when ultraviolet light is used as the energy beam, it is necessary to eliminate the holes in the silicon. Irradiation of ultraviolet light to a silicon layer deposited on silicon nitride or silicon nitride oxide instead of silicon dioxide, or a silicon layer deposited directly on a glass substrate causes the same phenomenon. For this reason, it is necessary to eliminate holes generated in silicon.

Next, the stress remaining in the polycrystalline silicon layer, the polycrystalline silicon layer 105 and the silicon dioxide film 10
In order to reduce or eliminate a large number of mismatches existing between the two, and mismatches existing at grain boundaries of crystal grains constituting the polysilicon layer, and point defects and holes existing in the polysilicon grains. And heat treatment. The conditions of the heat treatment are, for example, a temperature of 300 to 650 ° C., a time of 10 minutes to 20 hours, and an atmosphere around the sample is in a nitrogen gas, an inert gas, or an inert gas containing hydrogen. If the substrate has no problem such as expansion and contraction or warpage, the time may be longer than 20 hours. Or 700-800
The rapid thermal annealing method at a temperature of 5 ° C. for 5 to 10 minutes has a sufficient effect, and an inexpensive glass substrate can be used under the above conditions. By this heat treatment, the polycrystalline silicon layer 105 has almost no crystal defects, and a high-quality polycrystalline silicon layer 106 having excellent crystal grain boundaries and electrical characteristics with little inconsistency between the silicon layer and silicon dioxide can be obtained. it can.

Next, after the step of implanting impurities into the silicon layer in a self-aligned manner with respect to the gate electrode is completed, the impurities in the silicon layer are activated by a laser beam, and the two-dimensionally channeled impurities are removed by heat treatment. FIG. 2 shows the second invention of this patent relating to the activation step.
This will be described with reference to FIG.

As shown in FIG. 2A, impurities are ion-implanted into the silicon layer 203 through the insulating film 204 in a self-aligned manner with respect to the gate electrode 205. For example, silicon layer 2
03 has a thickness of 50 nm and the insulating film 204 has a thickness of 150 nm.
In the case of nm and the impurity is phosphorus, ion implantation conditions are as follows: ion implantation amount is 3 × 10 ¹⁵ cm ⁻² , and acceleration voltage is 120 KeV.

By the above-described ion implantation, regions 207 and 208 into which impurities are implanted are formed as shown in FIG. 2B. The region 208 is a region in which an impurity causes a channel in an oblique direction and is ion-implanted below the gate electrode.

Next, a laser beam 209 is irradiated from the side of the substrate on which the gate electrode is formed as shown in FIG. 5C to activate the ion-implanted impurities. Irradiation of the laser beam activates the impurities in the region 207 and forms impurity-doped polycrystalline silicon 210.
The impurity in the region 208 below the gate electrode is not irradiated with a laser beam, and the region 208
Since the heat conduction to the region 208 is also insufficient, the impurities in the region 208 are not activated or are in an insufficiently activated state. When the region 208 where the impurity is not activated is present, the region 208 becomes a resistor, so that the on-state current of the thin film transistor is reduced. In addition, since the drain region has a large number of defects at the boundary of the channel region, the gate region is formed. There is a problem in that the source / drain leakage current becomes extremely large in the voltage off region.

Then, a heat treatment step is performed to activate the impurities in the region 208. The conditions of the heat treatment step are a temperature of 300 to 650 ° C., a time of 10 minutes to 20 hours, and an atmosphere around the sample is in a nitrogen gas, an inert gas, or an inert gas containing hydrogen. If there is no problem such as expansion and contraction or warpage of the substrate, the heat treatment may be performed for a time longer than 20 hours. Or 700-800
The rapid thermal annealing method at a temperature of 5 ° C. for 5 to 10 minutes has a sufficient effect, and an inexpensive glass substrate can be used under the above conditions. By this heat treatment, impurities in the region 208 are activated, and a high-quality silicon layer with extremely few crystal defects can be obtained. As a result, according to the present invention, it is possible to manufacture a thin film transistor which has a high on-current and a small leak current of a source / drain in an off region of a gate voltage and has excellent electric characteristics.

Since the crystal in the region 210 crystallized by the laser beam becomes a nucleus for crystallization, it is practically 30 nuclei.
At a temperature of 0 to 650 ° C., a time of 10 minutes to several hours is sufficient.

Next, a method of manufacturing a thin film transistor using the above-described steps will be described.

FIG. 3 shows an embodiment of the first method of manufacturing a thin film transistor. FIG. 4 shows an embodiment of the second manufacturing method of the thin film transistor. FIG. 5 shows an embodiment of the third manufacturing method of the thin film transistor.

FIGS. 3A to 3I are sectional views showing the steps of manufacturing a thin film transistor according to the present invention. As shown in FIG. 3A, a silicon dioxide film 302 is formed on a pre-cleaned insulating substrate 301, for example, on a transparent glass substrate by a normal pressure chemical vapor deposition method at a substrate temperature of 200 to 350 ° C.
It is deposited to a thickness of nm.

Next, an n-type silicon layer having a film thickness of 150 nm is deposited at a substrate temperature of 550 to 650 ° C. by, for example, a low pressure chemical vapor deposition method. Examples of the impurities contained in the n-type silicon layer include phosphorus, arsenic, and antimony. Then, the n-type silicon layer is patterned to form regions 303 and 304 on the islands which will be the source and drain regions of the thin film transistor.

The source region 303 and the drain region 3
The method for forming 04 is not limited to the above.
Decompress the i-type silicon layer on silicon dioxide film 302
For example, at a substrate temperature of 450 to 650 ° C.,
It is deposited to a thickness of 150 nm. The above-mentioned i-type silico
SiH as the source gas for forming the_FourOr Si_Two
H_FourOr SiH_FourAnd Si_TwoH_FourMixed gas can be used
You. Then, ion implantation is performed in the i-type silicon layer.
For example, at an acceleration voltage of 120 keV, 10 ^Fifteen-10¹⁶
cm^-2Impurities are introduced at a concentration of. Then, the above silico
In order to activate impurities implanted during implantation,
Thermal annealing for 2 hours in a nitrogen atmosphere at a plate temperature of 600 ° C
I do. The impurities implanted into the i-type silicon are
Activated by energy beam such as laser beam
You can also. Then, pattern the silicon layer
To form a source region 303 and a drain region 304
You. When forming a p-type thin film transistor,
In the process of ion implantation, instead of n-type impurities,
P-type impurities such as boron are ion-implanted into the source region.
303 and the drain region 304 may be formed.

Next, for example, a weight concentration of 3 diluted with pure water
The native oxide film formed on the surfaces of the source region and the drain region is removed by using a HF solution of%.

Next, a silicon layer to be an active region of the thin film transistor is formed by, for example, a low pressure chemical vapor deposition method at a substrate temperature of 600 ° C. and a thickness of, for example, 15 nm to 70 nm on which the source region 303 and the drain region 304 are formed. It is formed so as to cover. As a source gas for forming the silicon layer, SiH ₄ , Si ₂ H ₄ ,
Alternatively, a mixed gas of SiH ₄ and Si ₂ H ₄ can be used.

The method of forming the silicon layer 305 is not limited to the above-described low pressure chemical vapor deposition method, but includes a hydrogen-containing amorphous silicon layer formed by decomposition of monosilane by glow discharge, or a sputtering method. The present invention can be applied to a silicon layer.

In order to control the threshold value of the thin film transistor manufactured in this embodiment, after forming the silicon layer, a necessary amount of impurity is implanted by, for example, ion implantation.

Next, the silicon layer is added to the source region 303.
Then, a silicon layer 305 is formed by patterning on the island as shown in FIG. Next, as shown in FIG. 3C, the silicon layer 305 is irradiated with a laser beam 306 to be crystallized. As the laser beam 306, a XeCl excimer pulse laser having a wavelength of 308 nm is used. The beam annealing conditions for a silicon layer formed by low pressure chemical vapor deposition are as follows:
The pulse width of the pulse laser is 50 nsec, the energy intensity of each pulse of the pulse laser immediately before the silicon layer 305 is 200 to 600 mJcm ⁻² ,
A more appropriate strength is 300 to 500 mJcm ^-2 . The number of pulses applied to the same portion of the silicon layer 305 may be plural. During the beam annealing, the partial pressure of oxygen around the silicon layer 305 is 10 ⁻⁵ mmHg or less.

This is because if oxygen exists on the surface of the silicon layer 305 or in the vicinity thereof, when the temperature of the silicon layer 305 is increased by beam annealing, oxygen or nitrogen reacts and is taken into the silicon layer 305 as an impurity. A good silicon layer cannot be obtained. Therefore,
When annealing the silicon layer, it is preferable to anneal in a vacuum or an inert gas atmosphere as much as possible. However, when removing the surface of the silicon layer 305 crystallized with hydrofluoric acid or the like after laser annealing, beam annealing can be performed in an oxygen atmosphere, a nitrogen atmosphere, or even in the air.

The laser beam 306 is not limited to a XeCl excimer laser, but may be an ArF excimer laser, a KrF excimer laser, a YAG laser, or the like.

By the beam annealing, the silicon layer 307 becomes the polycrystalline silicon layer 306 as shown in FIG. 3D.

Next, the stress remaining in polycrystalline silicon layer 306, the number of mismatches existing between polycrystalline silicon layer 306 and silicon dioxide film 302, and the crystal grains forming polycrystalline silicon layer Inconsistency existing at grain boundaries,
In addition, heat treatment is performed to reduce or eliminate point defects and holes present in the polycrystalline silicon particles. The heat treatment may be performed under the conditions described with reference to FIG.

Next, as shown in FIG. 3E, a gate insulating film 308 is formed to cover the source region 303, the drain region 304 and the polycrystalline silicon layer 307 by, for example, a normal pressure chemical vapor deposition method. Substrate temperature 300
At 150 ° C., a silicon dioxide film having a thickness of, for example, 150 nm is deposited. The method and material for forming the gate insulating film 308 are not limited to the above. For example, even if SiO ₂ is deposited and formed by the electron cyclotron resonance CVD method, it can be used as the gate insulating film 308. Further, first, the SiO by the electron cyclotron resonance method (ECR method) is used.
₂ is formed so as to cover the source region 303, the drain region 304, and the polycrystalline silicon film 307, and SiO ₂ is formed by atmospheric pressure chemical vapor deposition. A film may be used. Also, E
One layer of SiO ₂ by the CR method may be used as the gate insulating film 308. Next, as shown in FIG.
To form For example, a silicon thin film into which an impurity has been introduced is formed so as to cover the gate insulating film 308, and then patterned. Examples of the silicon layer into which the impurities are introduced include a silicon layer formed by a low-pressure chemical vapor deposition method using phosphorus as an impurity, an amorphous silicon layer containing phosphorus, and a microcrystalline silicon layer formed by a PECVD method. There is. The thickness of the gate electrode is 300 to 400 n
m. As shown in FIG. 3F, the gate electrode 309 and the source region 303 have a so-called offset structure that does not overlap in the laminating direction of the thin film. Similarly, the gate electrode and the i-drain region 304 have an offset structure.

Next, as shown in FIG. 3G, ions are implanted 330 into the offset structure portion of the polycrystalline silicon layer 307 through the gate insulating film 308 in a self-aligned manner with respect to the gate electrode 309. When the thin film transistor to be manufactured is an n-type, there is phosphorus or the like as an ion species. For example, in the case of phosphorus, when the thickness of the gate insulating film 306 is 150 nm, the conditions for ion implantation are an acceleration voltage of 120 keV and an ion implantation amount of 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻³ .
When the thin film transistor to be manufactured is a p-type, boron or the like is used as an ion species to be ion-implanted. For example, in the case of boron, the conditions for ion implantation are acceleration voltage 4
At 0 keV, the ion implantation amount is 1 × 10 ¹⁵ to 1 × 10 ¹⁶ c
m ^-3 . As shown in FIG. 3G, regions 311 and 312 in which impurities are implanted in a self-aligned manner with respect to the gate electrode 309 are formed.

Next, the impurities contained in the regions 311 and 312 are activated.

The offset regions 311 and 311
When the thickness of the 12 silicon layer is about 25 nm, activation of the implanted impurities by thermal annealing is performed, for example, in a nitrogen atmosphere under the above-described ion implantation conditions.
Annealing conditions of 60 ° C. or more at 700 ° C. or 2 hours at 700 ° C. are required. Under these annealing conditions, even if the impurity is implanted in a self-aligned manner with respect to the gate electrode, the diffusion of the impurity in the lateral direction of the channel becomes large, and eventually, between the gate electrode and the source electrode and between the gate electrode and the drain electrode. Parasitic capacitance occurs. In order to fabricate a thin film transistor on an inexpensive glass substrate having a strain point of around 600 ° C., the activation conditions by the thermal annealing are not appropriate.

As shown in FIG. 3H, the impurities implanted in the regions 311 and 312 are activated by a laser beam. The laser beam conditions are as follows: a XeCl excimer laser having a wavelength of 308 nm and a half width of 50 ns is 300 to 6
The substrate is irradiated in the air with a beam energy intensity of 00 mJcm ^-2 . The number of laser beam pulses applied to the thin film transistor may be appropriately plural.
The 309 and 3 activated by a laser beam
The sheet resistance of No. 10 is 0.01 to 0.05 Ωcm ^−1, which is a resistance value that can be sufficiently used as a thin film transistor. The laser beam is not limited to the above-described XeCl excimer laser, but may be an ArF excimer laser, a KrF excimer laser, or a harmonic of a YAG laser having a wavelength in the same region as ultraviolet rays, for example, for activating impurities. By the irradiation of the laser beam, the regions 311 and 31
2 denotes polycrystalline silicon films 314 and 315 containing impurities.
become.

Further, by the irradiation of the laser beam for activating the impurity, the gate electrode formed by the silicon layer containing the impurity is also annealed at the same time, and the resistance is reduced. Since the thickness of the gate electrode formed of the silicon layer is about 300 nm, the laser beam energy does not reach the silicon layer in the active region.

Next, heat treatment is performed by the method shown in FIG. By this heat treatment, impurities channeled obliquely below the gate electrode are also activated, and a high-quality silicon layer with extremely few crystal defects can be obtained. As a result, according to the present invention, it is possible to manufacture a thin film transistor which has a high on-current and a small leak current of a source / drain in an off region of a gate voltage and has excellent electric characteristics.

Since the source / drain region has already been crystallized by the laser beam, and this becomes a crystal growth nucleus, the temperature is practically 300 to 650 ° C. and the time is 1 hour.
A heat treatment of 0 minutes to several hours is sufficient.

Next, an interlayer insulating film 316 is formed on the gate electrode 30.
9 is formed on the substrate on which is formed. As a material for the interlayer insulating film, for example, there is SiO ₂ having a thickness of, for example, 500 nm formed by a normal pressure chemical vapor deposition method. Further, SiO ₂ , PSG, or SiN _x formed by an electron cyclotron resonance method, a sputtering method, a low pressure chemical vapor deposition method, or the like may be used as the interlayer insulating film 316.

Next, as shown in FIG.
03 and the interlayer insulating film 316 in the drain region 304.
Then, a contact window portion is provided so as to penetrate the gate insulating film 308, and then a metal thin film serving as an electrode, for example, an aluminum thin film is deposited and patterned, and the source electrode
And a drain electrode 318 are formed. In the case where the thin film transistor is used as a picture element of an active matrix type liquid crystal display, a constituent material of the drain electrode 318 is, for example, indium-tin oxide (IT
A transparent electrode made of O) can be used. The I
A TO thin film is formed by sputtering and pattern etching is performed, and then an aluminum thin film as a source electrode material is formed by sputtering and a source electrode is formed by pattern etching.

Next, a passivation film 319, for example, a 50 nm-thick nitride film is formed so as to cover the substrate on which the source electrode 317 and the drain electrode 318 are formed. The passivation film is not limited to a single layer, and may be formed by stacking a plurality of layers of thin films made of different materials. For example, first, a thickness of 20
It is also possible to deposit 0 nm of SiO ₂ so as to cover the source electrode 317 and the drain electrode 312, and then deposit an organic polymer film and use it as a passivation film. In order to prevent contamination of the thin film transistor from the outside, the passivation film 313 further applies a DC voltage generated by the thin film transistor to the liquid crystal molecules when the thin film transistor is used as a picture element of an active matrix type liquid crystal display. There is a purpose to reduce.

Next, a heat treatment is performed in a gas containing hydrogen at, for example, 300 ° C. for 1 hour to obtain a target thin film transistor as shown in FIG. 3I. However, when an organic polymer film that decomposes at 300 ° C. is used as the passivation film, it is necessary to perform the above-described hydrogen treatment before forming the organic polymer film.

The above embodiment is an example of manufacturing a self-aligned thin film transistor.
A C-MOS circuit can be formed by forming thin film transistors of the same type on the same substrate and wiring and connecting the gate electrode and the source electrode or the drain electrode of each thin film transistor with an appropriate wiring material.

FIGS. 4A to 4I are sectional views showing steps of a second method for manufacturing a thin film transistor according to the present invention. FIG.
On the insulating substrate 401 previously cleaned as shown in FIG.
For example, a silicon dioxide film 402 is formed on a transparent glass substrate by, for example, an atmospheric pressure chemical vapor deposition method, for example, at a substrate temperature of 200.
It is deposited at a temperature of about 350 ° C. and a thickness of, for example, 200 nm.

Next, a silicon layer 403 is formed, for example, by a low pressure chemical vapor deposition method so as to cover the silicon dioxide film 402 at a substrate temperature of 450 to 650 ° C. and a film thickness of, for example, 15 nm to 70 nm. As a source gas for forming the silicon layer 403, SiH ₄ , Si ₂ H ₄ , or a mixed gas of SiH ₄ and Si ₂ H ₄ can be used.

The method of forming the silicon layer 403 is not limited to the above-described low pressure chemical vapor deposition method, but includes a hydrogen-containing amorphous silicon layer formed by decomposition of monosilane by glow discharge, or a sputtering method. The present invention can be applied to a silicon layer.

Next, as shown in FIG. 4B, the silicon layer 403 is irradiated with a laser beam 404 to be crystallized.
The laser beam 404 has Xe-
A Cl excimer pulse laser is used. The beam annealing conditions for the silicon layer formed by the low pressure chemical vapor deposition method are as follows: the pulse width of the pulse laser is 50 nsec, and the energy intensity of each pulse of the pulse laser immediately before the silicon layer 403 is 200 to 600 mJcm.
^-2 , more suitable strength is 300-500mJ
cm ^-2 . The number of pulses applied to the same portion of the silicon layer 403 may be plural. For the same reason as in the first embodiment, during beam annealing, the partial pressure of oxygen around the silicon layer 403 is 10 ⁻⁵ mmHg or less. The silicon layer 40 during the beam annealing
The partial pressure of oxygen on and around the surface of No. 3 is 10 ⁻⁵ mmHg or less.

The laser beam 404 is not limited to the XeCl excimer laser, but may be an ArF excimer laser, a KrF excimer laser, a YAG laser, or the like.

After the beam annealing, patterning is performed in an island shape to form a polycrystalline silicon layer 405 as shown in FIG. 4C. In this embodiment, the silicon layer 403 is patterned after being subjected to the beam annealing. However, after the silicon layer is patterned in an island shape in advance, the polycrystalline silicon layer 405 is formed by performing the beam annealing as described above. Can also.

Next, heat treatment is performed by the method shown in FIG. 1 to improve the quality of the silicon layer 405.

Next, as shown in FIG. 4C, a gate insulating film 406 is formed so as to cover the polycrystalline silicon layer 405 by, for example, normal pressure chemical vapor deposition, for example, at a substrate temperature of 30 ° C.
At 0 ° C., a silicon dioxide film having a thickness of, for example, 150 nm is deposited. The method and material for forming the gate insulating film 406 are not limited to the above. For example, even if SiO ₂ is formed by electron cyclotron resonance CVD, it can be used as the gate insulating film 408. The gate insulating film 40 is composed of one layer of silicon dioxide film formed by the ECR method.
8 may be formed.

Next, as shown in FIG.
7 is formed. For example, a silicon thin film into which an impurity has been introduced is deposited so as to cover the gate insulating film 408, and then patterned. Examples of the silicon layer into which the impurity is introduced include a silicon layer formed by a low-pressure chemical vapor deposition method using phosphorus as an impurity and an amorphous silicon layer containing phosphorus formed by a PECVD method. The thickness of the gate electrode is 300 to 400 nm.

Next, as shown in FIG.
Is ion-implanted 408 through the gate insulating film 406 in a self-aligned manner. When the thin film transistor to be manufactured is an n-type, there is phosphorus or the like as an ion species. For example,
In the case of phosphorus, the thickness of the gate insulating film 406 is 150 nm.
In this case, the conditions for ion implantation are as follows: the acceleration voltage is 120 keV and the ion implantation amount is 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻³ .
When the thin film transistor to be manufactured is a p-type,
Examples of ion species to be ion-implanted include boron. For example, in the case of boron, the conditions for ion implantation are an acceleration voltage of 40 keV and an ion implantation amount of 1 × 10 ¹⁵ to 1 × 10 ^16.
cm ^-3 . As shown in FIG.
Then, regions 409 and 410 into which impurities are implanted in a self-aligning manner are formed.

Next, the impurities contained in the regions 409 and 410 are activated.

When the thickness of the silicon layers of the ion-implanted regions 409 and 410 is about 25 nm,
In order to activate the implanted impurities by thermal annealing, it is necessary to perform annealing at 600 ° C. for 60 hours or more or 700 ° C. for 2 hours in a nitrogen atmosphere under the above-described ion implantation conditions, for example. In order to manufacture a thin film transistor on an inexpensive glass substrate having a strain point of about 600 ° C., activation by thermal annealing is not appropriate.

As shown in FIG. 4G, the impurities implanted in the regions 409 and 410 are activated by the laser beam. The laser beam conditions were as follows: a XeCl excimer laser having a wavelength of 308 nm and a half-value width of 50 ns,
The substrate is irradiated in the air with a beam energy intensity of 00 mJcm ^-2 . The number of laser beam pulses applied to the thin film transistor may be appropriately plural.
The 409 and 4 activated by a laser beam
The sheet resistance of No. 10 is 0.01 to 0.05 Ωcm ^−1, which is a resistance value that can be sufficiently used as a thin film transistor. The laser beam is not limited to the above-described XeCl excimer laser, but may be an ArF excimer laser, a KrF excimer laser, or a harmonic of a YAG laser having a wavelength in the same region as ultraviolet rays, for example, for activating impurities. By the irradiation of the laser beam, regions 409 and 41
0 becomes a source region 412 and a drain region 413 formed of a polycrystalline silicon film containing impurities.

Next, a heat treatment is performed by the method described with reference to FIG. 2 in order to activate the impurities implanted in the silicon layer in the active region below the gate electrode by obliquely channeling.

Further, by the irradiation of the laser beam for activating the impurity, the gate electrode formed by the silicon layer containing the impurity is also annealed at the same time, and the resistance is reduced. Since the thickness of the gate electrode formed of the silicon layer is about 300 nm, the laser beam energy does not reach the active silicon layer.

Next, an interlayer insulating film 414 is formed on the gate electrode 40.
7 is formed on the substrate on which is formed. As a material for the interlayer insulating film, for example, there is SiO ₂ having a thickness of, for example, 500 nm formed by a normal pressure chemical vapor deposition method. Further, the interlayer insulating film 414 may be formed of SiO ₂ , PSG, or SiN _x formed by an electron cyclotron resonance method, a sputtering method, a low pressure chemical vapor deposition method, or the like.

Next, as shown in FIG.
12 and the interlayer insulating film 414 on the drain region 413.
Then, a contact window is provided so as to penetrate the gate insulating film 405, and then a metal thin film serving as an electrode, for example, an aluminum thin film is deposited and patterned, and the source electrode 415 is formed.
And a drain electrode 416 are formed. In the case where the thin film transistor is used as a picture element of an active matrix type liquid crystal display, a constituent material of the drain electrode 416 is, for example, indium-tin oxide (IT
A transparent electrode made of O) can be used. The I
A TO thin film is formed by sputtering and pattern etching is performed, and then an aluminum thin film as a source electrode material is formed by sputtering and a source electrode is formed by pattern etching.

Next, a passivation film 417, for example, a 50 nm nitride film is formed so as to cover the substrate on which the source electrode 415 and the drain electrode 416 are formed. The passivation film is not limited to a single layer, and may be formed by stacking a plurality of layers of thin films made of different materials. For example, first, a thickness of 20
0 nm of SiO ₂ may be formed so as to cover the source electrode 415 and the drain electrode 416, and then an organic polymer film may be formed and used as a passivation film. In order to prevent contamination of the thin film transistor from outside, the passivation film 417 further applies a DC voltage generated by the thin film transistor to the liquid crystal molecules when the thin film transistor is used as a picture element of an active matrix type liquid crystal display. There is a purpose to reduce.

Next, a heat treatment is performed in a gas containing hydrogen at, for example, 300 ° C. for 1 hour to obtain a target thin film transistor as shown in FIG. 4H. However, when an organic polymer film that decomposes at 300 ° C. is used as the passivation film, it is necessary to perform the above-described hydrogen treatment before forming the organic polymer film.

The above embodiment is an example of manufacturing a self-aligned thin film transistor.
A C-MOS circuit can be formed by forming thin film transistors of the same type on the same substrate and wiring and connecting the gate electrode and the source electrode or the drain electrode of each thin film transistor with an appropriate wiring material.

FIGS. 5A to 5H are sectional views showing steps of a third method for manufacturing a thin film transistor according to the present invention.

FIGS. 5A to 5D of the third embodiment of the manufacturing process of the thin film transistor of the present invention are the same as FIGS. 4A to 4D of the second embodiment of the manufacturing process of the thin film transistor.

Hereinafter, a third embodiment of the present invention will be described with reference to FIG. 5E.

As shown in FIG. 5E, a gate electrode 507 is formed. For example, a metal thin film such as Cr is formed by sputtering or vapor deposition so as to cover the gate insulating film, and then patterned. When the tensile internal force of the metal thin film is large, for example, in the case of Cr, the thickness is 3
A thin film having a thickness of 00 nm has a large tensile stress and causes problems such as disconnection at a step portion. Therefore, in the case of such a gate electrode, it is necessary to appropriately reduce the thickness. For example, in the case of a gate electrode made of Cr, the thickness may be set to about 150 nm. However, ions cannot be sufficiently prevented in the next ion implantation step of FIG. 5F. For this reason, the resist 508 on the gate electrode is left after patterning. The thickness of the remaining resist is 500 nm or more, which is a sufficient mask for ion implantation.

Next, as shown in FIG.
Is ion-implanted 509 through the gate insulating film 506 in a self-aligned manner. When the thin film transistor to be manufactured is an n-type, there is phosphorus or the like as an ion species. For example,
In the case of phosphorus, the thickness of the gate insulating film 506 is 150 nm.
In this case, the conditions for ion implantation are as follows: the acceleration voltage is 120 keV and the ion implantation amount is 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻³ .
When the thin film transistor to be manufactured is a p-type,
Examples of ion species to be ion-implanted include boron. For example, in the case of boron, the conditions for ion implantation are an acceleration voltage of 40 keV and an ion implantation amount of 1 × 10 ¹⁵ to 1 × 10 ^16.
cm ^-3 . As shown in FIG.
Then, regions 510 and 511 in which impurities are implanted in a self-aligning manner are formed.

Next, a resist 5 on the gate electrode 507 is formed.
08 is peeled off. Next, the impurities implanted into the regions 510 and 511 are activated.

When the thickness of the silicon layers of the ion-implanted regions 510 and 511 is about 25 nm,
In order to activate the implanted impurities by thermal annealing, it is necessary to perform annealing at 600 ° C. for 60 hours or more or 700 ° C. for 2 hours in a nitrogen atmosphere under the above-described ion implantation conditions, for example. In order to manufacture a thin film transistor on an inexpensive glass substrate having a strain point of about 600 ° C., the activation by the thermal annealing is not appropriate.

As shown in FIG.
2 activates the impurities implanted in the regions 510 and 511. The beam annealing conditions are 308 n wavelength.
m, XeCl excimer laser with half width at 50 ns
The substrate is irradiated with a beam energy intensity of 00 to 600 mJcm ⁻² . When a gate electrode is made of a material that reacts with gas molecules in the atmosphere by irradiation with the laser beam 512, the substrate is irradiated with the laser beam in a vacuum or in an inert gas. The number of pulses of the laser beam 512 applied to the thin film transistor may be appropriately plural. The sheet resistance of the 510 and 511 activated by the laser beam 512 is
It is 0.01 to 0.05 Ωcm ^−1, which is a resistance value that can be sufficiently used as a thin film transistor. The laser beam is not limited to the XeCl excimer laser described above, but an ArF excimer laser, a KrF excimer laser, a YAG laser having a wavelength in the same region as ultraviolet rays, or the like can be used for activating impurities. By the irradiation of the laser beam, the regions 510 and 511 become a source region 313 and a drain region 514 formed of a polycrystalline silicon film containing impurities.

Next, the impurities which are obliquely channeled in the silicon layer below the gate electrode are activated by the heat treatment method shown in FIG. 2 to eliminate crystal defects in the silicon layer below the gate electrode. .

Next, an interlayer insulating film 515 is formed on the gate electrode 50.
7 is formed on the substrate on which is formed. As a material for the interlayer insulating film, for example, there is SiO ₂ having a thickness of, for example, 500 nm formed by a normal pressure chemical vapor deposition method. Further, the interlayer insulating film 515 may be formed of SiO ₂ , PSG, or SiN _x formed by an electron cyclotron resonance method, a sputtering method, a low pressure chemical vapor deposition method, or the like.

Next, as shown in FIG.
13 and the interlayer insulating film 515 in the drain region 514.
Then, a contact window is provided so as to penetrate the gate insulating film 507, and then a metal thin film serving as an electrode, for example, an aluminum thin film is formed and patterned, and the source electrode 515 is formed.
And a drain electrode 516 are formed. When the thin film transistor is used as a picture element of an active matrix type liquid crystal display, a constituent material of the drain electrode 517 is, for example, indium-tin oxide (IT
A transparent electrode made of O) can be used. The I
A TO thin film is formed by sputtering and pattern etching is performed, and then an aluminum thin film as a source electrode material is formed by sputtering and a source electrode is formed by pattern etching.

Next, a passivation film 518, for example, a 50-nm nitride film is formed so as to cover the substrate on which the source electrode 516 and the drain electrode 517 are formed. The passivation film is not limited to a single layer, and may be formed by stacking a plurality of layers of thin films made of different materials. For example, first, a thickness of 20
It is also possible to deposit 0 nm of SiO ₂ so as to cover the source electrode 516 and the drain electrode 517, and then deposit an organic polymer film to use as a passivation film. In order to prevent contamination of the thin film transistor from the outside, the passivation film 518 further applies a DC voltage generated by the thin film transistor to the liquid crystal molecules when the thin film transistor is used for a picture element of an active matrix type liquid crystal display. There is a purpose to reduce.

Next, a heat treatment is performed in a hydrogen-containing gas at, for example, 300 ° C. for 1 hour to obtain a target thin film transistor as shown in FIG. 5H. However, when an organic polymer film that decomposes at 300 ° C. is used as the passivation film, it is necessary to perform hydrogen treatment before forming the organic polymer film.

Although the third embodiment is an example of manufacturing a self-aligned thin film transistor, an n-type thin film transistor and a p-type thin film transistor are formed on the same substrate, and a gate electrode and a source electrode or a drain electrode of each thin film transistor are formed. By wiring and connecting the electrodes with an appropriate wiring material, a C-MOS circuit can be formed.

[0096]

As described above, in the method of manufacturing a thin film transistor according to the present invention, defects in the silicon layer can be eliminated by performing a heat treatment after crystallization of the silicon layer by irradiation with an energy beam. For,
Since a thin film transistor having excellent subthreshold characteristics can be manufactured, a high-speed C-MOS circuit can be formed using the thin film transistor. As a result, the drive circuit of the active matrix type liquid crystal display can be formed on the same inexpensive glass substrate as the picture element, so that a high definition liquid crystal display can be manufactured at low cost. In addition, since the step of irradiating the energy beam is performed at a partial pressure of oxygen of 10 −5 mmHg or less, even if the temperature of the silicon layer is increased by beam annealing, oxygen or nitrogen reacts and is taken into the silicon layer as impurities. Can be prevented.

[0097]

[0098]

[0099]

[0100]

[0101]

Further, the present invention is applicable to the production of high-performance three-dimensional elements.

[Brief description of the drawings]

FIG. 1 is a diagram showing an invention relating to improving the quality of a silicon layer by a heat treatment process after crystallization of the silicon layer by irradiation with an energy beam according to the present invention.

FIG. 2 is a diagram showing an invention relating to activation of an impurity channeled in an oblique direction by a heat treatment step after activating an impurity in a silicon layer by laser beam irradiation according to the present invention.

FIG. 3 is a process chart of a first embodiment for realizing the method of manufacturing a thin film transistor according to the present invention.

FIG. 4 is a process chart of a second embodiment for realizing the method of manufacturing a thin film transistor according to the present invention.

FIG. 5 is a process chart of a third embodiment for realizing the method of manufacturing a thin film transistor according to the present invention.

FIG. 6 is a cross-sectional view illustrating a method of manufacturing a conventional thin film transistor.

FIG. 7 is a view showing a problem of activation of impurities by a laser beam after ion implantation in a conventional example.

[Explanation of symbols]

101, 201, 301, 401, 501 Insulating substrate 102, 202, 302, 402, 502 Silicon dioxide film 103, 305, 403, 503 Silicon layer 104, 206, 209, 306, 313, 404, 411, 504, 512 Laser Beam 105, 203, 307, 405, 505 Polycrystalline silicon layer 106 Improved polycrystalline silicon layer 204, 308, 406, 506 Gate insulating film 205, 309, 407, 507 Gate electrode 207, 311, 312, 409, 410 510, 511 Impurity-implanted region 208 Impurity-implanted channel in the oblique direction 210 Impurity-activated region 211 Impurity-activated region 303, 412, 513 Source region 304, 413, 514 Drain region 314, 315 Polycrystalline silicon film containing impurities 316, 414, 518 Interlayer insulating film 317, 415, 516 Source electrode 318, 416, 516 Drain electrode 319, 417, 518 Passivation film

Claims (1)

(57) [Claims] A step of forming a silicon layer on a substrate, a step of irradiating the silicon layer with an energy beam to crystallize the silicon layer, and a step of heat-treating the silicon layer after the step of irradiating the energy beam. And irradiating the energy beam with a partial pressure of oxygen of 10%.
^A method for producing a thin film transistor, wherein the method is performed at ^-5 mmHg or less.