JPH0832074A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a manufacturing method capable of forming crystalline silicon film in high quality having higher liquid crystallizability than the crystallizability obtained by ordinary solid growing method in excellent productivity as well as keeping the clean state of a semiconductor layer and an insulating film interface thereon furthermore using a low cost glass substrate represented by a coning 7059 glass. CONSTITUTION:In the shielded state from outside air, an amorphous silicon film 102 and an insulating thin film 103 e.g. silicon oxide film, etc., are successively formed on a glass substrate 101 and later, a catalyst element assisting the crystallization of the amorphous silicon film 102 is led in the amorphous silicon film 102 by ion implanting method through the intermediary of the insulating film 103 so that the amorphous silicon film 102 with the catalyst element led therein may be crystallized by a heating method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a crystalline silicon film obtained by crystallizing an amorphous silicon film as an active region and a manufacturing method thereof. In particular, the present invention is effective for a semiconductor device having a TFT (thin film transistor) provided on an insulating substrate, and can be applied to an active matrix type liquid crystal display device, a contact image sensor, a three-dimensional IC and the like.

[0002]

2. Description of the Related Art In recent years, large-sized, high-resolution liquid crystal display devices,
High-speed, high-resolution contact image sensor, three-dimensional IC
In order to realize the above, an attempt has been made to form a high-performance semiconductor element on an insulating substrate such as glass or on an insulating film. A thin film silicon semiconductor layer is generally used for a semiconductor element used in these devices.

The thin-film silicon semiconductor layer is roughly classified into two, that is, an amorphous silicon semiconductor (a-Si) and a crystalline silicon semiconductor. Amorphous silicon semiconductors are the most commonly used because they have a low fabrication temperature, can be fabricated relatively easily by the vapor phase method, and have high mass productivity. It is inferior to the silicon semiconductors it has. Therefore, in order to obtain higher speed characteristics in the future, there is a strong demand for establishment of a method for manufacturing a semiconductor device made of a crystalline silicon semiconductor. Known crystalline silicon semiconductors include polycrystalline silicon, microcrystalline silicon, amorphous silicon containing a crystalline component, and semi-amorphous silicon having an intermediate state between crystalline and amorphous.

As a method for obtaining these thin film silicon semiconductor layers having crystallinity, (1) a semiconductor film is formed while the semiconductor film has crystallinity (2) an amorphous semiconductor A film is formed, and then the semiconductor film is made crystalline by the energy of laser light. (3) An amorphous semiconductor film is formed, and then thermal energy is applied to the semiconductor film. To have crystallinity,
Such methods are known.

However, in the method (1), crystallization progresses at the same time as the film forming step. Therefore, in order to obtain crystalline silicon having a large grain size, it is indispensable to increase the thickness of the silicon film. It is technically difficult to uniformly form a film having a film on the entire surface of the substrate. Further, in this method, since the film forming temperature is as high as 600 ° C. or higher, there is a cost problem that an inexpensive glass substrate cannot be used.

Further, in the method (2), since the crystallization phenomenon in the melting and solidification process is utilized, the grain boundaries are favorably processed with a small grain size, and a high quality crystalline silicon film can be obtained. Taking the most commonly used excimer laser as an example, there is a problem that the irradiation area of laser light is small and throughput is low. In addition, the crystallization treatment with laser light is not sufficient in the stability of the laser for uniformly treating the entire surface of a large-area substrate, and is strongly regarded as a next-generation technology.

The method (3) has an advantage that it can be applied to a large area as compared with the methods (1) and (2), but heat treatment for several tens of hours at a high temperature of 600 ° C. or more is required for crystallization. is necessary. On the other hand, considering the use of an inexpensive glass substrate and the improvement of throughput, it is necessary to lower the heating temperature and crystallize it in a shorter time. Therefore, in the method (3), it is necessary to simultaneously solve the above-mentioned conflicting problems.

Further, in the method (3), since the solid phase crystallization phenomenon is utilized, the crystal grains spread parallel to the substrate surface and are several μm.
Although even those with a grain size of 1 appear, the grown crystal grains collide with each other to form a grain boundary, and the grain boundary acts as a trap level for carriers, which is a major cause of lowering the mobility of the TFT. Will end up.

A method for solving the above-mentioned problem of grain boundaries by utilizing the method (3) is disclosed in Japanese Patent Laid-Open No. 5-55142.
Japanese Patent Laid-Open Publication No. 5-136048. In these methods, a foreign particle serving as a nucleus for crystal growth is introduced into the amorphous silicon film, and then a heat treatment is performed to obtain a large-grain crystalline silicon film having the foreign particle as a nucleus.

In the former case, silicon (Si ⁺ ) is introduced into the amorphous silicon film by an ion implantation method, and then a heat treatment is performed to obtain a polycrystalline silicon film having crystal grains with a grain size of several μm.
In the latter, Si particles having a particle diameter of 10 to 100 nm are blown onto the amorphous silicon film together with a high pressure nitrogen gas to form a growth nucleus. It is the same in both cases that a semiconductor element is formed using a high-quality crystalline silicon film in which a foreign substance is selectively introduced into an amorphous silicon film and crystal growth is performed using the foreign substance as a nucleus.

Further, in order to realize a high-performance MOS transistor, not only the quality of the above-mentioned crystalline silicon film, which is the active region, is improved, but also the quality of the gate insulating film is improved, and further, the active region. It is essential to improve the quality of the interface between the semiconductor thin film and the gate insulating film.

In a MOS transistor manufactured on a Si substrate by a conventional IC process, the surface of the Si substrate is thermally oxidized and the thermally oxidized silicon film is used as a gate insulating film. Therefore, the interface between the active layer and the gate insulating film is kept clean, and a very high quality silicon oxide film can be obtained as the gate insulating film.

However, the thermal oxidation step is 100
It requires a high temperature of 0 ° C. or higher, and cannot be applied to a TFT manufactured on an inexpensive glass substrate. Further, even if a thermal oxide film is formed using a substrate having high heat resistance such as a quartz substrate, the original silicon film is not a single crystal silicon but a crystalline silicon film. The insulating property of the silicon film is so poor that it cannot be used as a gate insulating film.

Therefore, in a semiconductor device using a crystalline silicon film formed on an insulating substrate, it is necessary to separately form a gate insulating film by a low temperature film forming method such as a CVD method. For example, in Japanese Unexamined Patent Publication (Kokai) No. 3-4564, a semiconductor layer (amorphous silicon film) and a gate insulating film are continuously formed by a low temperature film forming method, and then a heat treatment for solid phase crystallization is performed to obtain a semiconductor. A high-performance T that keeps the interface between the layer and the gate insulating film (hereinafter referred to as the semiconductor layer / gate insulating film interface) clean.
Realize FT.

[0015]

By the way, when a semiconductor element such as a TFT is manufactured by utilizing a crystalline silicon film on a substrate having an insulating property, the most serious problem is that the active region as described above is used. The crystallinity of the crystalline silicon film and the state of the interface between the semiconductor layer and the gate insulating film.

First, regarding the gate insulating film, when the gate insulating film is formed by the low temperature film forming method, the film quality is inferior to that of the gate insulating film formed by the high temperature oxidation method, and the high performance TF is obtained.
There was a problem that T could not be realized. This is because a defect level due to residual stress, dangling bonds, impurities, etc. in the gate insulating film exists at the semiconductor layer / gate insulating film interface and the depletion layer does not spread. This problem can be almost solved by keeping the interface between the semiconductor layer and the gate insulating film clean, and the technique described in JP-A-3-4564 is effective.

However, regarding the method for producing the crystalline silicon film to be the active region, considering the large area substrate, the crystallinity in the substrate is stable to some extent, and the solid phase crystal described in (3) above is used. Although it is most preferable at present to use the crystallization method, the crystalline silicon film produced by the conventional solid phase crystallization method as disclosed in Japanese Patent Laid-Open No. 3-4564 has a crystal grain boundary of It has a large effect and shows a twin structure with many crystal defects even within a single crystal grain. Therefore, in the method proposed in Japanese Patent Laid-Open No. 3-4564, since the semiconductor layer has a twin structure with many crystal defects, when the semiconductor layer and the gate insulating film are continuously formed, Reflecting poor crystallinity, the defect level at the semiconductor layer / gate insulating film interface cannot be reduced as much as when an insulating thin film is continuously formed on a single crystal silicon film, and the semiconductor layer / gate insulating film interface is cleaned. The effect obtained by keeping at. Therefore, in order to improve the performance of the semiconductor device, it is necessary not only to continuously form the semiconductor layer and the gate insulating film in a state where the outside air is shut off, but also to improve the quality of the crystalline silicon film which becomes the active region.

In the technique disclosed in Japanese Patent Application Laid-Open No. 5-55142 or Japanese Patent Application Laid-Open No. 5-136048, which is proposed for the purpose of improving the quality of the crystalline silicon film, Si ⁺ ions and Si are selectively supplied through the injection window. The particles are introduced into the amorphous silicon film to form nuclei for crystal growth. However, the number of crystal nuclei generated inside the injection window is not one, and a large number of crystal nuclei are generated, resulting in individual crystal growth. Crystal growth occurs from the nuclei. Therefore, in reality, a single crystal grain centering on one injection window of Si ⁺ ions or Si particles cannot be formed,
A large number of nuclei generated in the injection window form grain boundaries.

Therefore, it is impossible to actually control the crystal grain boundaries in JP-A-5-55142 or JP-A-5-136048. Furthermore, since an implantation mask is required when selectively introducing Si ⁺ ions or Si particles that become crystal nuclei, an extra step that is not directly related to the original semiconductor device manufacturing process will be added. Therefore, there is a large demerit in terms of productivity, resulting in higher cost of the product.

Furthermore, when an inexpensive glass substrate is used, shrinkage of the substrate in the heat treatment step for crystallization,
Problems such as warpage occur. For example, Corning 7 commonly used for active matrix type liquid crystal display devices.
059 glass (trade name of Corning) has a glass strain point of 5
The temperature is 93 ° C., and in consideration of increasing the area of the substrate, there is a problem in heating at a temperature higher than this.

On the other hand, when the conventional solid-phase crystallization method is used, it depends on the forming method and conditions of the starting a-Si film, but the heat treatment is performed at a heating temperature of at least 600 ° C. for 20 hours or more. is necessary. In Japanese Patent Laid-Open No. 3-4564, 500
Although it is described that annealing is performed at a temperature of up to 700 ° C. for a long time, in the solid phase crystallization of the a-Si film described in the example, in practice, a heating temperature of at least 600 ° C.
It seems that an annealing time of 0 hours or more is necessary. Further, in the technique described in JP-A-5-55142, crystallization is performed by heat treatment at a temperature of 600 ° C. for 40 hours. Further, in the case of Japanese Patent Laid-Open No. 5-136048,
Heat treatment is performed at a heating temperature of 650 ° C. or higher. therefore,
These techniques are effective techniques for SOI substrates and SOS substrates, but it has been difficult to form a crystalline silicon film on an inexpensive glass substrate to form a semiconductor element by using these techniques.

Further, in the MOS type transistor, the characteristics of the interface between the semiconductor layer for channeling and the gate insulating film are very important factors as described above. The interface state on the side facing the interface of the gate insulating film is also particularly important. That is, when the transistor is in the OFF state, a back channel is formed at the interface facing the gate insulating film with the semiconductor layer interposed therebetween, which causes an increase in leak current. Therefore, in a pixel switching element of an active matrix substrate, a TFT such as a memory element, which particularly needs a charge retention characteristic, in order to prevent a leak current due to a back channel effect, it is possible to maintain good interface characteristics of an interface facing a gate insulating film. It was essential.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to produce a high-quality crystalline silicon film having crystallinity higher than that obtained by a usual solid phase growth method with high productivity. In addition to being formed, the semiconductor layer / insulating film interface can be kept in a clean state, and the heating temperature required for crystallization at this time is 580 ° C. or lower.
It is an object of the present invention to obtain a semiconductor device and a method for manufacturing the same that can use an inexpensive glass substrate represented by glass.

[0024]

Means for Solving the Problems Accordingly, the present inventors have:
As a result of earnest research to achieve the above object, a small amount of a metal element such as nickel, palladium, and lead is introduced into the surface of the amorphous silicon film, and then heat treatment is performed at 550 ° C. for about 4 hours. It was found that the amorphous silicon film can be crystallized in the processing time of.

This mechanism is based on the assumption that crystal nucleation with a metal element as a nucleus occurs at an early stage of the heat treatment, and then the metal element serves as a catalyst to promote crystal growth and crystallization rapidly progresses. To be understood. In that sense, these metal elements are called catalyst elements. In the crystal grains of the crystalline silicon film that has been crystal-grown by promoting crystallization by these catalytic elements, the crystal grains grown from one crystal nucleus by the usual solid phase growth method have a twin structure. The needle-like crystals or columnar crystals are woven into each other, and the inside of each needle-like crystal or columnar crystal is in an ideal single crystal state.

When a TFT is manufactured by using such a crystalline silicon film in the active region, the field effect mobility is 1.2 times as compared with the case of using the crystalline silicon film formed by the usual solid phase growth method. Improve. After crystallization by heat treatment, the crystallized silicon film is irradiated with laser light or strong light, so that the field effect mobility of the one using the catalytic element for crystallization and the one using the solid phase growth method The difference becomes even more pronounced.

That is, when the crystalline silicon film is irradiated with laser light or intense light, the grain boundary portions are intensively processed due to the difference in melting point between the crystalline silicon film and the amorphous silicon film. However, in the crystalline silicon film formed by the usual solid phase growth method, since the crystal structure is in a twin state, twin crystal defects remain inside the crystal grain boundaries even after laser light irradiation. In comparison, the crystalline silicon film crystallized by introducing the catalytic element,
It is formed of needle crystals or columnar crystals, and since the inside is almost single crystal state, the crystal grain boundary part is processed by irradiation of laser light or strong light, and further the crystallinity in the crystal grains is promoted. As a result, a crystalline silicon film having very good crystallinity over the entire surface of the substrate can be obtained.

By the way, especially among the semiconductor elements, the TFT
In order to improve the stability of the MOS type transistor device such as, and to improve its performance, a technique for keeping the semiconductor layer / gate insulating film interface clean as described above, that is, the semiconductor layer /
A technique for continuously forming a gate insulating film in a vacuum is essential. Furthermore, in order to reduce the leak current of the TFT and improve the charge retention characteristics, it is necessary to have a technique for keeping the interface facing the gate insulating film across the semiconductor layer clean. It is more desirable to continuously form three layers of the gate insulating film.

The semiconductor layer crystallized using the above catalyst is
Since it is formed of needle-like crystals or columnar crystals, and the inside thereof is in a substantially single crystal state, when a semiconductor layer and a gate insulating film are continuously formed, a conventional crystalline silicon film having a twin crystal structure with many crystal defects The interface characteristics can be greatly improved as compared with the case where is used for the semiconductor layer.

However, in the above-described method for producing a crystalline silicon film found by the present inventors, a step of adding a catalytic element to the semiconductor layer is required. Therefore, compared with the conventional solid phase growth method, the semiconductor layer / gate It was difficult to continuously form an insulating film, and further to continuously form a base insulating film / semiconductor layer / gate insulating film.

The present inventors added the above-mentioned catalytic element to
In a TFT process using a crystalline silicon film crystallized by low-temperature annealing at 80 ° C. or less in an active region, a semiconductor layer / gate insulating film is continuously formed, and further, a base insulating film / semiconductor layer / gate insulating film is continuously formed. I researched a process that makes it possible.

As a result, after the semiconductor layer / gate insulating film is continuously formed, the catalytic element is introduced into the semiconductor layer through the gate insulating film by the ion implantation method, and crystallized by heat treatment.
Alternatively, it was discovered that the object of the present invention can be achieved by subsequently irradiating with laser light or intense light.

As another method, the same crystallization effect can be obtained by adding a catalytic element to the lower region of the semiconductor layer.
It was also discovered that it is possible to continuously form the semiconductor layer / gate insulating film, but this method involves adding a catalytic element to the surface of the base film before the semiconductor layer is formed, so that the catalyst can be formed in the base film. The element diffuses, and the concentration of the catalyst element added to the semiconductor layer cannot be controlled properly. Further, in this method, it is structurally impossible to continuously form the three layers of the base insulating film / semiconductor layer / gate insulating film because it is necessary to implant the catalytic element into the base insulating film. Therefore, the above-mentioned ion implantation method is the only method for continuously forming three layers of the base insulating film / semiconductor layer / gate insulating film and introducing the catalytic element. Further, the TFT manufactured by continuously forming the semiconductor layer / gate insulating film by using the method of adding the catalytic element to the underlying insulating film did not show the expected high performance characteristics.

Here, the lower the concentration of the catalytic element introduced into the amorphous silicon film, the better, but if it is too low, it does not function to promote crystallization of the amorphous silicon film. As a result of examination by the present inventors, the minimum concentration of the catalytic element causing crystallization is 1 × 10 ¹⁶ atoms / cm ³ ,
At concentrations lower than this, crystal growth due to the catalytic element does not occur.

Further, if the concentration of the catalytic element is high, the influence on the device becomes a problem. The phenomenon that occurs when the catalytic element is high is mainly an increase in leak current in the off region of the TFT. It is understood that this is due to the influence of the impurity level formed by the catalytic element in the silicon film and the tunnel current through the level. As a result of examination by the present inventors, the maximum concentration of the catalytic element to the extent that the element is not affected is 1 × 10 5.
^{It is 19} atoms / cm ³ . Therefore, the concentration of the catalytic element in the film is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atoms / cm ^3.
If so, the catalytic element functions most effectively.

Further, in the TFT, the thickness of the active layer is appropriately 20 to 150 nm. That is, the film thickness 20
If the thickness is less than nm, good crystallinity cannot be obtained, and the film thickness is
If the thickness is equal to or greater than nm, there is a high possibility that the wiring will be disconnected at the edge portion of the active region. Generally, a film thickness of about 100 nm is suitable, and in order to introduce the catalytic element into the a-Si film having this film thickness at a concentration within the above range, the dose amount in the ion implantation step is 1 ×. 10 ¹¹ to 1 × 10 ¹⁴ at
It should be within the range of oms / cm ² .

Further, the crystallization method using the above catalyst element can obtain the most remarkable effect when Ni is used as the catalyst element. Other types of catalyst elements that can be used include Co, Pd, Pt, Cu, Ag, Au, and I.
Examples include n, Sn, Al, and Sb. One or more elements selected from these elements have a crystallization-promoting effect even with a small amount (concentration in the film of 1 × 10 ¹⁶ atoms / cm ³ or more), so there is no problem on the semiconductor element. .

The present invention was obtained as a result of such earnest research by the present inventors.

(1) A semiconductor device according to the present invention has a substrate having an insulating surface, an active region made of a crystalline silicon film formed on the insulating surface of the substrate, and an active region on the active region. The insulating thin film thus formed is provided, and the active region has a structure containing a catalytic element that promotes crystallization of the amorphous silicon film by heat treatment, whereby the above object is achieved.

(2) A semiconductor device according to the present invention has a substrate having an insulating surface, an active region made of a crystalline silicon film formed on the insulating surface of the substrate, and an active region on the active region. The insulating thin film formed is provided, and the active region has a structure in which the crystal grains in this region are substantially in a single crystal state and contains a catalytic element that promotes crystallization of the amorphous silicon film by heat treatment. Therefore, the above object is achieved.

(3) The present invention provides the above semiconductor device,
A MOS type transistor is provided, and its gate insulating film is composed of the insulating thin film.

(4) In a semiconductor device according to the present invention, an active region composed of a first insulating thin film formed on a substrate and a crystalline silicon film formed on the first insulating thin film. And a second insulating thin film formed on the active region, and the active region has a structure containing a catalytic element that promotes crystallization of the amorphous silicon film by heat treatment. The above object is achieved.

(5) The semiconductor device according to the present invention has an active region composed of a first insulating thin film formed on a substrate and a crystalline silicon film formed on the first insulating thin film. And a second insulating thin film formed on the active region, wherein the active region has a crystal grain in a substantially single crystal state, and the amorphous silicon film is crystallized by heat treatment. The structure has a catalytic element that promotes chemical conversion, and thereby the above-mentioned object is achieved.

(6) According to the present invention, in the above semiconductor device, a MOS type transistor is provided, and a gate insulating film thereof is formed of the second insulating thin film.

(7) In the present invention, preferably, the concentration of the catalyst element in the active region in the film is 1 × 10 ¹⁶ -1.
× 10 ¹⁹ atoms / cm ³ .

(8) In the present invention, preferably, the active region contains Ni, Co, Pd, Pt, and
It contains one or more kinds of elements among Cu, Ag, Au, In, Sn, Al and Sb.

(9) In the method for manufacturing a semiconductor device according to the present invention, an insulating thin film such as an amorphous silicon film and a silicon oxide film is provided on a substrate whose surface region has an insulating property in a state where the outside air is shut off. And a catalyst element that promotes crystallization of the amorphous silicon film,
The method includes an ion implantation method of introducing it through the insulating thin film and a step of crystallizing the amorphous silicon film introduced with the catalytic element by heating, whereby the above object is achieved.

(10) In the method of manufacturing a semiconductor device according to the present invention, an insulating thin film such as an amorphous silicon film and a silicon oxide film is provided on a substrate whose surface region has an insulating property in a state where the outside air is shut off. And a step of introducing into the amorphous silicon film a catalyst element that promotes crystallization of the amorphous silicon film through the insulating thin film by an ion implantation method, and the catalyst element It includes a step of crystallizing the introduced amorphous silicon film by heating and a step of irradiating the crystallized silicon film with laser light or strong light to treat the crystal, thereby achieving the above object. To be done.

(11) In the present invention, preferably, the method for manufacturing a semiconductor device includes a step of forming a gate insulating film of a MOS transistor from the insulating thin film.

(12) In the method of manufacturing a semiconductor device according to the present invention, three layers of the first insulating thin film, the amorphous silicon film, and the second insulating thin film are formed on the substrate with the outside air shut off. A step of continuously forming, a step of introducing a catalyst element that promotes crystallization of the amorphous silicon film into the amorphous silicon film through the second insulating thin film by an ion implantation method, and the catalyst And a step of crystallizing the amorphous silicon film into which the element is introduced by heat treatment, whereby the above object is achieved.

(13) In the method of manufacturing a semiconductor device according to the present invention, three layers of the first insulating thin film, the amorphous silicon film, and the second insulating thin film are continuously formed on the substrate while the outside air is shut off. And a step of introducing a catalyst element that promotes crystallization of the amorphous silicon film into the amorphous silicon film through the second insulating thin film by an ion implantation method, and the catalyst element And a step of crystallizing the crystallized amorphous silicon film and irradiating the crystallized silicon film with laser light or strong light to achieve the above object. To be done.

(14) In the present invention, preferably, in the method for manufacturing a semiconductor device described above, the second insulating thin film is formed into an M layer.
It includes a step of forming a gate insulating film of an OS type transistor.

(15) In the present invention, preferably, the dose amount when introducing the catalyst element into the amorphous silicon film by the ion implantation method is 1 × 10 ¹¹ to 1 × 10 ¹⁴ ato.
It is ms / cm ² .

(16) In the present invention, preferably Ni, Co, Pd, Pt, Cu, Ag and A are used as catalyst elements.
One or more kinds of elements selected from u, In, Sn, Al and Sb are used.

[0055]

In the semiconductor device of the present invention, an active region made of a crystalline silicon film formed on the insulating surface of the substrate and an insulating thin film formed on the active region are provided. Since the region has a structure containing a catalytic element that promotes crystallization of the amorphous silicon film by heating, the crystalline silicon film forming the active region is usually obtained by crystallization of the amorphous silicon film. The crystallinity can be higher than that obtained by the solid-phase growth method. Further, since the crystallinity of the active region is good, the defect level at the interface can be effectively reduced by continuously forming the active region and the insulating film on the active region to keep the interface clean. Can be reduced to

Since the crystallization of the amorphous silicon film by heating is promoted by the catalytic element, a high quality crystalline silicon film can be formed with high productivity. Moreover, at this time, the heating temperature required for crystallization is 580 ° C. or lower, so that an inexpensive glass substrate typified by Corning 7059 glass can be used.

In the semiconductor device of the present invention, the first insulating thin film formed on the substrate, the crystalline active region formed on the first insulating thin film, and the active region on the active region are formed. The second insulating thin film formed on the first insulating thin film, the active region having a structure containing a catalytic element that promotes crystallization of the amorphous silicon film by heat treatment. The continuous growth of the region and the second insulating thin film can greatly improve the characteristics of the interface with the insulating thin film above and below the active region.
Further, the crystalline silicon film forming the active region can be formed with high productivity by crystallization of the amorphous silicon film, and the crystallization of the amorphous silicon film is performed at a temperature low enough to use an inexpensive glass substrate. Not to mention that you can do it in.

Further, the crystallinity of the silicon film forming the active region can be further improved by subjecting the crystalline silicon film obtained by the heat treatment of the amorphous silicon film to irradiation of laser light or intense light. Further, the field effect mobility of carriers in the active region can be further improved.

By using the above-mentioned insulating thin film as a gate insulating film of a MOS type transistor, the leak current of the transistor can be reduced.

The concentration of the catalytic element in the film in the active region is set to 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atoms / cm ^3.
By this, the catalytic element can be effectively functioned.

In the semiconductor device manufacturing method of the present invention, the amorphous silicon film and the insulating thin film are successively formed on the substrate whose surface region has an insulating property in a state where the outside air is shut off. The interface of the membrane can be kept clean.

A catalyst element that promotes crystallization of the amorphous silicon film is introduced into the amorphous silicon film through the insulating thin film by an ion implantation method, and then the catalyst element is introduced. Since the crystalline silicon film is crystallized by heating, a high-quality crystalline silicon film having crystallinity higher than that obtained by the usual solid phase growth method can be obtained.
Can be formed with high productivity.

Moreover, at this time, the heating temperature required for crystallization is 5
Since the temperature is 80 ° C. or lower, an inexpensive glass substrate typified by Corning 7059 glass can be used as the substrate.

Further, the amorphous silicon film into which the catalytic element has been introduced is crystallized by heating, and then the crystallized silicon film is irradiated with laser light or strong light for crystal treatment. Further, the crystallinity of the crystalline silicon film forming the active region can be further enhanced, and the field effect mobility of carriers in the active region can be further improved.

In the method of manufacturing a semiconductor device according to the present invention, the first insulating thin film, the amorphous silicon film, and the second insulating thin film are continuously formed in three layers on the substrate while the outside air is shut off. As a result, the characteristics of the interface between the insulating thin film above and below the amorphous silicon film can be greatly improved.

[0066]

[Embodiment 1] FIG. 1 is a cross-sectional view for explaining a thin film transistor and a method of manufacturing the same according to a first embodiment of the present invention, and FIGS. Example TF
The manufacturing method of T is shown in the order of steps.

In the figure, reference numeral 100 denotes a semiconductor device having a thin film transistor (TFT) 10.
Is formed on a glass substrate 101 with an insulating base film 102 such as a silicon oxide film interposed therebetween. The insulating base film 10
An island-shaped crystalline silicon film 103b that forms the TFT is formed on the TFT 2. This crystalline silicon film 103
A central portion of b is a channel region 108, and both side portions thereof are source and drain regions 109 and 110. An aluminum gate electrode 106 is provided on the channel region 108 via a gate insulating film 104. The surface of the gate electrode 106 is covered with an oxide layer 107. The entire surface of the TFT 10 is covered with an interlayer insulating film 111, and a contact hole 111a is formed in a portion of the interlayer insulating film 111 corresponding to the source / drain regions 109 and 110. The source / drain regions 109 and 110 are connected to the electrode wiring 112, through the contact hole 111a.
It is connected to 113.

In this embodiment, the crystalline silicon film 103b contains a catalytic element (Ni) that promotes crystallization of the amorphous silicon film by heat treatment, and the crystal grains in this film are in a substantially single crystal state. Of needle-like crystals or columnar crystals.

Of course, the TFT 10 of this embodiment can be used as an element constituting a driver circuit or a pixel portion of an active matrix type liquid crystal display device.
CPU mounted on the same substrate as these circuits and pixel parts
It can also be used as an element constituting the. In addition, T
The application range of FT is not limited to liquid crystal display devices,
It goes without saying that it can be applied to a thin film integrated circuit generally called.

Next, the manufacturing method will be described. Here, a process of manufacturing an N-type TFT on a glass substrate will be described.

First, a base film 102 of silicon oxide having a thickness of about 200 nm is formed on a glass substrate 101 by, for example, a sputtering method. This silicon oxide film is
It is provided to prevent diffusion of impurities from the glass substrate 101.

Next, as shown in FIG.
An intrinsic (I-type) amorphous silicon film (a-Si film) 103 having a thickness of 100 nm, for example, 80 nm is formed, and a thickness of 20 to 150 is continuously formed on the amorphous silicon film (a-Si film) 103 without being exposed to the atmosphere.
nm, here a 100 nm silicon oxide film is formed as the gate insulating film 104. By thus continuously forming the semiconductor layer and the gate insulating film without exposing them to the atmosphere, the interface between the semiconductor layer and the gate insulating film can be kept clean, and the reliability of the TFT to be completed later can be improved and high. It leads to performance improvement. It is more preferable that the continuous formation of the semiconductor layer and the gate insulating film can be performed without breaking the vacuum.

For example, as a method of continuously forming the semiconductor layer and the insulating film without exposing them to the atmosphere, plasma C
The VD method is generally used, and in addition, there are a sputtering method, a photo CVD method, an electron beam evaporation method, and the like. In this example, the a-Si film and the silicon oxide film were continuously formed by the RF plasma CVD method. To form the a-Si film, silane (SiH ₄ ) gas is used as a raw material, and this is used at a substrate temperature of
Decomposed and deposited at ˜400 ° C., preferably 200 to 300 ° C. In addition, TEOS (Te
tra Ethoxy Silan) as a raw material and decomposed and deposited with oxygen at a substrate temperature of 150 to 600 ° C, preferably 300 to 450 ° C. By the way, the above TEOS contains Si atoms, O
It is an organic material containing atoms and the like that is liquid at room temperature and is used for forming an interlayer insulating film and the like, and an insulating film having excellent step coverage can be obtained.

Next, as shown in FIG. 1B, nickel ions 105 are added to the gate insulating film 1 by an ion implantation method.
It is introduced into the a-Si film 103 through 04. The dose amount of nickel at this time is 1 × 10 ¹¹ to 1 × 10 ¹⁴ atoms.
/ Cm ² In this embodiment, the acceleration voltage of nickel ions is 120 to 200 keV, for example 160.
keV and the dose amount is 1 × 10 ¹³ atoms / cm ²
As a result, nickel ions 105 were introduced into the a-Si film 103. Then, this is annealed in a hydrogen reducing atmosphere or an inert atmosphere at a heating temperature of 520 to 580 ° C. for several hours to several tens of hours, and here, at 550 ° C. for 4 hours to be crystallized. At this time, the nickel ions 105 implanted in the a-Si film serve as nuclei, and then nickel serves as a catalyst to promote crystal growth, and the a-Si film 103 is effectively crystallized. As a result, the a-Si film 103 becomes the crystalline silicon film 103a. At the same time, nickel is uniformly diffused in the film, and the nickel concentration in the crystalline silicon film 103a becomes 1.2 × 10 ¹⁸ atoms / cm ³ .

Next, as shown in FIG. 1 (c), unnecessary portions of the crystalline silicon film 103a are removed to perform element isolation to form active regions (source, drain regions, and channel regions) of the TFT. The island-shaped crystalline silicon film 103b is formed. At this time, the silicon oxide film 104 on the crystalline silicon film 103a is patterned into the same shape as the island-shaped crystalline silicon film 103b.

Subsequently, by the sputtering method,
Aluminum with a thickness of 400-800 nm, for example 600
The film is formed to have a thickness of nm. Then, the aluminum film is patterned to form the gate electrode 106. Further, the surface of the aluminum gate electrode 106 is anodized to form an oxide layer 107 on the surface (FIG. 1).
(D)).

Here, the anodic oxidation is carried out in an ethylene glycol solution containing tartaric acid in an amount of 1 to 5%, the voltage is first raised to 220 V at a constant current, and the state is maintained for 1 hour to complete the oxidation treatment. The thickness of the obtained oxide layer 107 is 200 nm. Since the thickness of the oxide layer 107 will be the length of the offset gate region in the subsequent ion doping process, the length of the offset gate region can be determined by the anodizing process.

Then, an impurity (phosphorus) is implanted into the active region (crystalline silicon film) 103b by ion doping using the gate electrode 106 and the oxide layer 107 around it as a mask. Phosphine (PH ₃ ) is used as a doping gas, the acceleration voltage is 60 to 90 kV, for example 80 kV, and the dose amount is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ^-2 .
For example, it is set to 2 × 10 ¹⁵ cm ⁻² . By this step, the regions 109 and 110 into which the impurities are implanted will be formed in the TFT 10 later.
The source / drain regions of the gate electrode 106 and the region 108 of the oxide layer 107 surrounding the gate electrode 106 where the impurities are not implanted will be the channel region of the TFT 10 later.

Thereafter, as shown in FIG. 1D, annealing is performed by irradiation with laser light 115 to activate the ion-implanted impurities, and at the same time, the crystal of the portion whose crystallinity is deteriorated in the above-mentioned impurity introduction step is performed. Improve sex. At this time, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was used as a laser, and irradiation was performed at an energy density of 150 to 400 mJ / cm ² , preferably 200 to 250 mJ / cm ² . The sheet resistance of the N-type impurity (phosphorus) regions 109 and 110 thus formed was 200 to 800 Ω / □.

Then, a silicon oxide film or a silicon nitride film having a thickness of about 600 nm is formed as an interlayer insulating film 111. When a silicon oxide film is used, if TEOS is used as a raw material and is formed by a plasma CVD method using oxygen and oxygen, or a low pressure CVD method or an atmospheric pressure CVD method using ozone, excellent interlayer insulation with excellent step coverage is obtained. A film is obtained. In addition, if a silicon nitride film formed by plasma CVD using SiH ₄ and NH ₃ as source gases is used, hydrogen atoms are supplied to the interface between the active region and the gate insulating film, and the dangling bond that deteriorates the TFT characteristics. Is effective.

Next, a contact hole 111a is formed in the interlayer insulating film 111, and the electrode wiring 11 of the TFT is formed by a two-layer film of a metal material such as titanium nitride and aluminum.
2, 113 are formed. The titanium nitride film functions as a barrier film for preventing diffusion of aluminum into the source / drain regions. Finally, annealing is performed at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm to complete the TFT 10 shown in FIG.

When the TFT is used as an element for switching the pixel electrode, one of the electrodes 112 and 113 is connected to the pixel electrode made of a transparent conductive film such as ITO, and a signal is input from the other electrode. When the present TFT is used in a thin film integrated circuit, a contact hole may be formed also on the gate electrode 106 and necessary wiring may be provided.

The TFT of this embodiment manufactured in this way
10, the field effect transfer is 60 to 80 cm ² / Vs, S
Good values of 0.6 to 0.8 V / digit and a threshold voltage of 2 to 3 V were shown. The S value is a rise coefficient in the sub-threshold region of the TFT, and in the graph showing the relationship between the gate voltage VG and the drain current ID, the slope of the graph at the point where the drain current ID sharply rises is
The change is shown in the gate voltage when the drain current ID increases by one digit. In addition, the variation of TFT characteristics in the substrate is ± 12% in the field effect movement and ± 8% in the threshold voltage.
It was within.

As described above, in this embodiment, the amorphous silicon film 103 and the insulating thin film 104 are successively formed on the substrate whose surface region has an insulating property in a state where the outside air is shut off. The interface can be kept clean.

A catalytic element (Ni) that promotes crystallization of the amorphous silicon film is introduced into the amorphous silicon film by the ion implantation method through the insulating thin film, and then the catalytic element is added. Since the introduced amorphous silicon film is crystallized by heating, a high-quality crystalline silicon film 103b having crystallinity higher than that obtained by a normal solid phase growth method can be formed with high productivity. it can.

Further, since the crystallinity of the crystalline silicon film 103b is good, by keeping the interface between the amorphous silicon film 103 and the gate insulating film 104 thereabove clean as described above, The defect level at the interface can be effectively reduced.

Moreover, at this time, the heating temperature required for crystallization is 5
Since the temperature is 80 ° C. or lower, an inexpensive glass substrate typified by Corning 7059 glass can be used as the substrate.

Moreover, since the silicon oxide film on the crystalline silicon film 103b is used as the gate insulating film of the MOS type transistor, the leak current of the transistor can be reduced.

The concentration of the catalytic element in the crystalline silicon film in the film is set to 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atoms / cm ^3.
Therefore, the catalytic element can effectively function.

[Embodiment 2] FIG. 2 is a cross-sectional view for explaining a thin film transistor and a method of manufacturing the same according to a second embodiment of the present invention. FIGS. 2 (a) to 2 (e) show the present embodiment. The manufacturing method of the example TFT is shown in the order of steps.

In the figure, reference numeral 200 denotes a semiconductor device of this embodiment, which has a peripheral drive circuit of an active matrix type liquid crystal display device and a circuit 20 of CMOS structure which constitutes a general thin film integrated circuit. This CMOS circuit is
The N-type TFT 21 and the P-type TFT 22 are connected so that they perform complementary operations.

The N-type TFT 21 and the P-type TFT 22 are formed on a glass substrate 201 with an insulating base film 202 such as a silicon oxide film interposed therebetween. The insulating base film 2
On 02, island-shaped crystalline silicon films 203n and 203p forming the TFTs 21 and 22 are formed adjacent to each other. Central portions of the crystalline silicon films 203n and 203p are an N channel region 208 and a P channel region 209, respectively. Both sides of the crystalline silicon film 203n are N-type source / drain regions 20 of an N-type TFT.
9, 210, and both side portions of the crystalline silicon film 203p are P-type source / drain regions 212, 213 of a P-type TFT.
Has become.

Aluminum gate electrodes 206 and 207 are provided on the N channel region 208 and the P channel region 209 with a gate insulating film 204 interposed therebetween.
The entire surface of the TFTs 21 and 22 is the interlayer insulating film 214.
Of the N-type TF of the interlayer insulating film 214.
A contact hole 214n is formed in a portion of the T21 corresponding to the source / drain regions 210 and 211, and a contact hole 214p is formed in a portion of the interlayer insulating film 214 corresponding to the source / drain regions 212 and 213 of the P-type TFT 22. Has been formed. The N-type TFT 21
The source and drain regions 210 and 211 are connected to the electrode wirings 215 and 216 via the contact holes 214n. Further, the source / drain regions 212 and 213 of the P-type TFT 22 have the contact holes 214.
It is connected to the electrode wirings 216 and 217 via p.

In the present embodiment, the crystalline silicon films 203n and 203p contain a catalytic element (Ni) that promotes crystallization of the amorphous silicon film by the heat treatment, and the crystal grains in the film are almost simple. It is composed of needle-like crystals or columnar crystals in a crystalline state.

Next, the manufacturing method will be described. Here, a process of manufacturing a circuit having the above CMOS structure on a glass substrate will be described.

First, a base film 202 made of silicon oxide and having a thickness of about 100 nm is formed on the glass substrate 201 by, for example, a sputtering method. Next, an intrinsic (I-type) amorphous silicon film (a-Si film) 203 having a thickness of 25 to 100 nm, for example 50 nm, is formed by a plasma CVD method,
A silicon oxide film 204 having a thickness of 20 to 150 nm, here 100 nm, is continuously formed (FIG. 2A).

Next, as shown in FIG. 2B, nickel ions 205 are added to the gate insulating film 2 by an ion implantation method.
It is introduced into the a-Si film 203 through 04. At this time, the dose amount of nickel was 5 × 10 ¹² atoms / cm ² , and the acceleration voltage was 140 kev. Then, this is heated under a hydrogen reducing atmosphere or an inert atmosphere at a heating temperature of 520.
~ 580 ℃ for several hours to tens of hours, specifically 550 ℃
Anneal for 6 hours to crystallize.

At this time, the nickel ions 205 implanted in the a-Si film serve as nuclei, and then nickel serves as a catalyst to promote crystal growth, and the a-Si film 203 is effectively crystallized. As a result, the a-Si film 203 becomes a crystalline silicon film 203a. The nickel concentration in the crystalline silicon film 203a is 1 × 10 ¹⁸ atoms / cm ³ .
Subsequently, the crystallinity of the crystalline silicon film 203a is enhanced by irradiating the crystalline silicon film with a laser beam. As the laser light at this time, a XeCl excimer laser (wavelength 308 nm, pulse width 40 nsec) was used. The laser irradiation conditions are as follows:
Heating at 0 to 450 ° C., for example 400 ° C., energy density 200 to 400 mJ / cm ² , for example 300 mJ / c
It was irradiated with m ² .

After that, as shown in FIG.
The crystalline silicon film to be the active regions (element regions) 203n and 203p of the FT is left, and the other regions are removed by etching to perform element isolation. At this time, the silicon oxide film 204 on the crystalline silicon film is the island-shaped crystalline silicon film 203.
Patterned in the same shape as n, 203p.

Subsequently, as shown in FIG. 2D, an aluminum film (containing silicon of 0.1 to 2%) having a thickness of 400 to 800 nm, for example, 500 nm is formed by a sputtering method, and the aluminum film is patterned. Then, the gate electrodes 206 and 207 are formed.

Next, by the ion doping method, impurities (phosphorus) are implanted into the active region 203n using the gate electrode 206 as a mask, and impurities (boron) are implanted into the active region 203p using the gate electrode 207 as a mask. At this time, phosphine (PH ₃ ) is used as a doping gas.
And diborane (B ₂ H ₆ ) are used. In the former case, the acceleration voltage is 60 to 90 kV, for example, 80 kV, and in the latter case, 40 kV to 80 kV, for example, 65 kV, and the dose amount is 1 × 10 ¹⁵ to 8 × 10. ¹⁵ cm ^-2 , for example ² phosphorus
× 10 ¹⁵ cm ^-2 , and boron is 5 × 10 ¹⁵ cm ^-2 .

By this step, the gate electrodes 206, 20
The area which is masked by 7 and is not implanted with impurities is a TFT later.
Of the channel regions 208 and 209. At the time of doping, each element is selectively doped by covering a region where doping is unnecessary with a photoresist. As a result, N-type impurity regions 210 and 211,
P-type impurity regions 212 and 213 are formed, as shown in FIG.
As shown in (d), N-channel type TFT (NTFT) 2
1 and a P-channel type TFT (PTFT) 22 can be formed.

Thereafter, as shown in FIG. 2D, annealing is performed by irradiation with laser light to activate the ion-implanted impurities. As the laser light, an XeCl excimer laser (wavelength 308 nm, pulse width 40 nse
Using c), the irradiation condition of the laser beam was such that the energy density was 250 mJ / cm ² and two shots were irradiated at one location.

Then, as shown in FIG.
A silicon oxide film having a thickness of 00 nm is formed as an interlayer insulating film 214 by a plasma CVD method, contact holes 214n and 214p are formed in the film, and a two-layer film of a metal material such as titanium nitride and aluminum is used to form electrode wiring 215 of the TFT. 216 and 217 are formed. Finally, annealing is performed at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm to complete the N-type and P-type TFTs 21 and 22.

CMOs produced according to the above examples
In the S structure circuit, the field effect mobility of each TFT is 120 to 150 cm ² / Vs for NTFT, and PTFT
Is as high as 100 to 130 cm ² / Vs, and the threshold voltage is NT
The FT showed a very good characteristic of 1.5 to 2V and the PFTT a -2 to -3V.

In the second embodiment having such a structure, the crystalline silicon film obtained by the heat treatment of the amorphous silicon film is irradiated with laser light or strong light. In addition to the effect of the first embodiment, the crystallinity of the silicon film forming the active region can be further improved, and the field effect mobility of the carrier in the active region can be further improved.

[Embodiment 3] FIG. 3 is a cross-sectional view for explaining a thin film transistor and a method of manufacturing the same according to a third embodiment of the present invention, and FIGS. 3 (a) to 3 (e) show the present embodiment. The manufacturing method of the example TFT is shown in the order of steps.

In the figure, reference numeral 300 denotes a semiconductor device having a thin film transistor (TFT) 30.
Is the TFT 10 in the semiconductor device of the first embodiment.
And has the same sectional structure. In this example,
The first embodiment in that the silicon oxide film as the base insulating film 302, the semiconductor layer 303 as the active region, and the silicon oxide film 303 as the gate insulating film are continuously formed without being exposed to the atmosphere. Different from the example. Note that FIG.
In the above, the constituent elements of the present embodiment denoted by the reference numerals in the 300s correspond to the constituent elements denoted by the reference numerals in the 100s of the first embodiment shown in FIG.

Next, the manufacturing method will be described. Also in this embodiment, the process of manufacturing the N-type TFT 30 on the glass substrate will be described as an example.

First, as shown in FIG. 3A, a glass substrate 301 has a thickness of 100 to 300 nm, for example, 200 n.
m of the base film 302 made of silicon oxide and having a thickness of 25
˜100 nm, for example 80 nm, intrinsic (I-type) amorphous silicon film (a-Si film) 303, further thickness 20 to 15
A silicon oxide film having a thickness of 0 nm, here 100 nm, is continuously formed as the gate insulating film 304. This step is performed without exposing it to the atmosphere. By continuously forming the base insulating film / semiconductor layer / gate insulating film as described above, the base insulating film / semiconductor layer interface and the semiconductor layer / gate insulating film interface can be kept clean.

Here, the continuous formation of the semiconductor layer / gate insulating film leads mainly to improvement of ON characteristics such as improvement of reliability and performance of a TFT completed later. Further, the continuous formation of the base insulating film / semiconductor layer can improve the OFF characteristics such as reduction of leak current.

In this example, the silicon oxide film / a-Si film / silicon oxide film was continuously formed by the RF plasma CVD method. For forming the a-Si film, silane (SiH ₄ ) gas is used as a raw material and the substrate temperature is 150 to ₄₀₀ ° C., preferably 2
Decomposed and deposited at 00 to 300 ° C. Moreover, in forming the silicon oxide film, TE is used for both the base insulating film and the gate insulating film.
Substrate temperature of 150-600 with oxygen as a raw material
Decomposed and deposited at ℃, preferably 300-450 ℃. The underlying silicon oxide film 302 also functions as a buffer layer for preventing diffusion of impurities from the glass substrate.

Next, as shown in FIG. 3B, nickel ions 305 are added to the gate insulating film 3 by an ion implantation method.
It is introduced into the a-Si film 303 through 04. The dose amount of nickel at this time is 1 × 10 ¹¹ to 1 × 10 ¹⁴ atoms.
/ Cm ² In this embodiment, the acceleration voltage of nickel ions is 120 to 200 keV, for example 160.
keV and the dose amount is 1 × 10 ¹³ atoms / cm ²
As a result, nickel ions 305 were introduced into the a-Si film 303. Then, this is annealed in a hydrogen reducing atmosphere or an inert atmosphere at a heating temperature of 520 to 580 ° C. for several hours to several tens of hours and at 550 ° C. for 4 hours to be crystallized. At this time, nickel ions 305 implanted in the a-Si film
Becomes a nucleus, and then nickel acts as a catalyst to effectively crystallize the a-Si film 303. As a result, the crystalline silicon film 303a is formed. At the same time, nickel diffuses uniformly into the film, and the nickel concentration in the crystalline silicon film 303a becomes 1.2 × 10 ¹⁸ atoms / cm ³ .

Next, as shown in FIG. 3C, unnecessary portions of the crystalline silicon film 303a are removed to perform element isolation, and later become active regions (source / drain regions, channel regions) of the TFT. An island-shaped crystalline silicon film 303b is formed. At this time, the silicon oxide film 304 on the crystalline silicon film 303a is patterned into the same shape as the island-shaped crystalline silicon film 303b.

Subsequently, by the sputtering method,
An aluminum film having a thickness of 400 to 800 nm, for example 600 nm, is formed. Then, the aluminum film is patterned to form the gate electrode 306. Further, the surface of the aluminum electrode is anodized to form an oxide layer 307 on the surface (FIG. 3D). The anodic oxidation here is performed in an ethylene glycol solution containing tartaric acid in an amount of 1 to 5%, the voltage is first increased to 220 V with a constant current, and the state is maintained for 1 hour to complete the treatment. The thickness of the obtained oxide layer 307 is 200 nm. Since the thickness of the oxide layer 307 becomes the length of the offset gate region in the subsequent ion doping process, the length of the offset gate region can be determined by the anodizing process.

Next, an impurity (phosphorus) is implanted into the active region by ion doping using the gate electrode 306 and the oxide layer 307 around it as a mask. Phosphine (PH ₃ ) is used as the doping gas, the acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose amount is 1 × 10.
^{It is set to 15} to 8 × 10 ¹⁵ cm ^-2 , for example, 2 × 10 ¹⁵ cm ^-2 .

By this step, the regions 309 and 310 into which the impurities are implanted will later become the source and drain regions of the TFT, and the gate electrode 306 and the oxide layer 307 around it will be formed.
The region 308 which is masked by and is not implanted with impurities will later become the channel region of the TFT.

Thereafter, as shown in FIG. 3D, annealing is performed by laser light irradiation to activate the ion-implanted impurities, and at the same time, the crystal of the portion where the crystallinity is deteriorated in the above-mentioned impurity introduction step is performed. Improve sex. On this occasion,
The laser used is a KrF excimer laser (wavelength 248 nm, pulse 20 nsec), energy density 150 to 400 mJ / cm ² , preferably 200.
Irradiation was performed at ˜250 mJ / cm ² . The sheet resistance of the N-type impurity (phosphorus) regions 309 and 310 thus formed was 200 to 800 Ω / □.

Then, a silicon oxide film or a silicon nitride film having a thickness of about 600 nm is formed as an interlayer insulating film 311. When a silicon oxide film is used, if TEOS is used as a raw material and is formed by a plasma CVD method using oxygen and oxygen, or a low pressure CVD method or an atmospheric pressure CVD method using ozone, excellent interlayer insulation with excellent step coverage is obtained. A film is obtained. In addition, if a silicon nitride film formed by plasma CVD using SiH ₄ and NH ₃ as source gases is used, hydrogen atoms are supplied to the interface between the active region and the gate insulating film, and the dangling bond that deteriorates the TFT characteristics. Has the effect of reducing

Next, a contact hole 311a is formed in the interlayer insulating film 311, and the electrode wiring 31 of the TFT is made of a metal material such as a multilayer film of titanium nitride and aluminum.
2, 313 are formed. Finally, annealing is performed at 350 ° C. for 30 minutes in a hydrogen atmosphere at 1 atm, and then, as shown in FIG.
The TFT 30 shown in is completed.

When this TFT is used as an element for switching a pixel electrode, one of electrodes 312 and 313 is connected to a pixel electrode made of a transparent electrode film such as ITO, and a signal is input from the other electrode. When the present TFT is used in a thin film integrated circuit, a contact hole may be formed on the gate electrode 306 and necessary wiring may be provided.

NTF produced according to the above examples
T showed good characteristics such as a field effect mobility of 60 to 80 cm ² / Vs, an S value of 0.6 to 0.8 V / digit, and a threshold voltage of 2 to 3 V. The variation in TFT characteristics within the substrate was within ± 12% in field effect mobility and within ± 8% in threshold voltage. The leakage current in question is 2-6 × 10 ^-12 A /
It was cm ² and could be reduced by a uniform digit as compared with the case where the base insulating film / semiconductor layer was not continuously formed.

Particularly, in the third embodiment, not only the ON characteristics are improved but also the leak current in the OFF region is reduced by continuously forming three layers of the base insulating film / semiconductor layer / gate insulating film. did it.

In the above description, three examples are given as examples of the present invention, but the present invention is not limited to the above examples, and various modifications based on the technical idea of the present invention. Is possible.

For example, in each of the above-mentioned embodiments, nickel was used as the catalyst element for promoting the crystallization of the amorphous silicon film, but in addition to nickel, cobalt, palladium, platinum, copper, silver, gold, indium, The same effect can be obtained by using tin, antimony, or aluminum.

Further, in Example 2, the heating method by excimer laser irradiation which is a pulse laser was used as a means for promoting the crystallinity of the crystalline silicon film, but other lasers (for example, continuous wave Ar laser) are also used. Similar processing is possible.

In the heat treatment, instead of laser light, infrared light, light emitted from a flash lamp (strong light) is used.
Is used to heat the sample by raising it to 1000-1200 ℃ (temperature of silicon monitor) in a short time, so-called RTA (Rapid Thermal Annealing) or RT
A heat treatment called P (rapid thermal process) or the like may be used.

Further, in addition to the active matrix type substrate for the liquid crystal display, the present invention is, for example, a contact type image sensor, a driver built-in type thermal head, an organic type E.
A driver built-in type optical writing element or display element that uses an L (electroluminescence) element or the like as a light emitting element, a three-dimensional I
It is applicable to C etc. Here, the organic EL element is
It is an electroluminescent device using an organic material as a light emitting material. By applying the present invention, high performance such as high speed and high resolution of these elements can be realized.

Furthermore, the present invention is not limited to the thin film transistors described in the above embodiments, but can be widely applied to all semiconductor processes using MOS transistors.

[0130]

As described above, according to the semiconductor device of the present invention, a catalyst that promotes crystallization of the active region formed on the insulating substrate or the insulating thin film by the heat treatment of the amorphous silicon film. Since the structure includes an element, a highly reliable high performance semiconductor device can be realized by a low temperature process of 580 ° C. or lower. That is, a semiconductor device having a high-performance thin film transistor having uniform and stable characteristics on an inexpensive large-area substrate such as a glass substrate can be obtained by a simple manufacturing process. Further, in the three-dimensional IC, it is possible to prevent heat damage to the semiconductor element in the lower layer, and it is possible to simplify the manufacturing process and improve the performance of the element.

Further, according to the method of manufacturing a semiconductor device of the present invention, an amorphous silicon film and an insulating thin film are successively formed on a substrate whose surface region has an insulating property in a state where the outside air is shut off. Therefore, the interface of these films can be kept in a clean state.

Further, a catalyst element that promotes crystallization of the amorphous silicon film is introduced into the amorphous silicon film through the insulating thin film by an ion implantation method, and then the catalyst element is introduced. Since the crystalline silicon film is crystallized by heating, a high-quality crystalline silicon film having crystallinity higher than that obtained by the usual solid phase growth method can be obtained.
Can be formed with high productivity.

At this time, the heating temperature required for crystallization is 5
Since the temperature is 80 ° C. or lower, an inexpensive glass substrate typified by Corning 7059 glass can be used as the substrate.

Further, since the amorphous silicon film having the catalytic element introduced therein is crystallized by heating, the crystallized silicon film is irradiated with laser light or intense light.
The crystallinity of the crystalline silicon film forming the active region can be further improved, and the field effect mobility of carriers in the active region can be further improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a TFT according to a first embodiment of the present invention and a method for manufacturing the TFT.

FIG. 2 is a sectional view illustrating a TFT according to a second embodiment of the present invention and a method for manufacturing the TFT.

FIG. 3 is a sectional view illustrating a TFT according to a third embodiment of the present invention and a method for manufacturing the TFT.

[Explanation of symbols]

10, 21, 30 N-type TFT 20 CMOS circuit 22 P-type TFT 100, 200, 300 Semiconductor device 101, 201, 301 Glass substrate 102, 202, 302 Base insulating film 103, 203, 303 Amorphous silicon film 103a, 203a , 303a crystalline silicon film 103b, 203n, 203p, 303b active region 104, 204, 304 gate insulating film 105, 205, 305 catalyst element 106, 206, 207, 306 gate electrode 107, 307 anodized layer 108, 208, 209 , 308 channel regions 109, 110, 210, 211, 212, 213, 3
09, 310 source / drain regions 111, 214, 311 interlayer insulating layers 111a, 214n, 214p, 311a contact holes 112, 113, 215, 216, 217, 312, 3
13 electrode wiring

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number for FI Technical indication H01L 21/265 21/324 Z 23/15 27/12 R H01L 21/265 Y 23/14 C

Claims (16)

[Claims] 1. A substrate having an insulating surface, an active region made of a crystalline silicon film formed on the insulating surface of the substrate, and an insulating thin film formed on the active region. A semiconductor device in which the active region contains a catalytic element that promotes crystallization of the amorphous silicon film by heat treatment. 2. A substrate having an insulating surface, an active region made of a crystalline silicon film formed on the insulating surface of the substrate, and an insulating thin film formed on the active region. The active region is a semiconductor device in which the crystal grains in this region are substantially in a single crystal state and contains a catalytic element that promotes crystallization of the amorphous silicon film by heat treatment. 3. A MOS type transistor is provided, and its gate insulating film is composed of the insulating thin film.
Alternatively, the semiconductor device according to item 2. 4. A first insulating thin film formed on a substrate, an active region formed on the first insulating thin film and made of a crystalline silicon film, and an active region formed on the active region. A second insulating thin film, wherein the active region contains a catalytic element that promotes crystallization of the amorphous silicon film by heat treatment. 5. A first insulating thin film formed on a substrate, an active region formed on the first insulating thin film and comprising a crystalline silicon film, and an active region formed on the active region. And a second insulating thin film, wherein the active region is such that the crystal grains in this region are in a substantially single crystal state and contains a catalytic element that promotes crystallization of the amorphous silicon film by heat treatment. Semiconductor device. 6. The semiconductor device according to claim 4, further comprising a MOS transistor, the gate insulating film of which is composed of the second insulating thin film. 7. The semiconductor device according to claim 1, wherein the concentration of the catalytic element in the film in the active region is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atoms / cm ^3. . 8. The active region comprises N as a catalytic element.
i, Co, Pd, Pt, Cu, Ag, Au, In, S
The semiconductor device according to claim 1, which contains one or more kinds of elements out of n, Al, and Sb. 9. A step of continuously forming an amorphous silicon film and an insulating thin film on a substrate whose surface region has an insulating property in a state where the outside air is blocked, and the amorphous silicon film, wherein The method includes a step of introducing a catalytic element that promotes crystallization of a silicon film through the insulating thin film by an ion implantation method, and a step of crystallizing an amorphous silicon film introduced with the catalytic element by heat treatment. Manufacturing method of semiconductor device. 10. A step of continuously forming an amorphous silicon film and an insulating thin film on a substrate whose surface region has an insulating property in a state where the outside air is blocked, A step of introducing a catalytic element that promotes crystallization of the silicon film through the insulating thin film by an ion implantation method; a step of crystallizing the amorphous silicon film introduced with the catalytic element by heating; And a step of irradiating the crystallized silicon film with laser light or strong light to treat the crystal. 11. The method of manufacturing a semiconductor device according to claim 9, further comprising the step of forming a gate insulating film of a MOS transistor from the insulating thin film. 12. The first substrate on the substrate in a state where the outside air is shut off.
Forming an insulating thin film, an amorphous silicon film, and a second insulating thin film in three layers in succession; and a catalyst element for promoting crystallization of the amorphous silicon film in the amorphous silicon film, A method of manufacturing a semiconductor device, comprising: a step of introducing it through the second insulating thin film by an ion implantation method; and a step of crystallizing an amorphous silicon film introduced with the catalytic element by heat treatment. 13. The first substrate is provided on the substrate in a state where the outside air is shut off.
Forming an insulating thin film, an amorphous silicon film, and a second insulating thin film in three layers in succession; and a catalyst element for promoting crystallization of the amorphous silicon film in the amorphous silicon film, A step of introducing through the second insulating thin film by an ion implantation method, a step of crystallizing the amorphous silicon film introduced with the catalytic element by a heat treatment, a laser beam or a laser beam applied to the crystallized silicon film. A method of manufacturing a semiconductor device, including the step of irradiating strong light to treat a crystal. 14. The method of manufacturing a semiconductor device according to claim 12, further comprising the step of forming a gate insulating film of a MOS transistor from the second insulating thin film. 15. The dose amount when the catalyst element is introduced into the amorphous silicon film by an ion implantation method is 1 × 10.
¹¹ to 1 × 10 ¹⁴ atoms / cm ² is set.
14. The method for manufacturing a semiconductor device according to 0, 12, or 13. 16. A catalyst element comprising Ni, Co, Pd,
Pt, Cu, Ag, Au, In, Sn, Al and Sb
9. Use of one or more kinds of elements among
14. The method for manufacturing a semiconductor device according to 0, 12, or 13.