JP2002280560A - Manufacturing method for semiconductor element, semiconductor element manufactured by the same manufacturing method, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve an interfacial characteristic between a crystalline silicon semiconductor film and a gate insulation film of a semiconductor element, and to reduce the lowering of mobility, and further, to improve sufficiently a minus shift of a flat band. SOLUTION: Before forming a gate electrode 5 of the semiconductor element, a crystalline silicon semiconductor film 3 and a silicon oxide film 4 are so subjected to steam annealing under a high-pressure condition as to reduce defects and dangling bonds included in them and oxidize a portion of the top-surface side of the crystalline silicon semiconductor film 3 which is contacted with the silicon oxide film 4. Thereby, there is obtained the semiconductor element having a good-quality semiconductor film wherein the interfacial characteristic between the crystalline silicon semiconductor film 3 and the silicon oxide film 4 is made excellent and the defects and the dangling bonds present in an interfacial surface portion are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor element, a semiconductor element and a semiconductor device manufactured by the method, and more particularly, to a method for crystallizing an amorphous silicon semiconductor film. The present invention relates to a method of manufacturing a semiconductor element using a crystalline silicon semiconductor film as an active region, a semiconductor element manufactured by the method, and a semiconductor device.

[0002]

2. Description of the Related Art In recent years, high-performance semiconductor elements have been formed on an insulating substrate such as glass in order to realize a large-sized liquid crystal display device with high resolution, a high-resolution and high-speed contact image sensor, and a three-dimensional IC. Attempts have been made to do so. Such a semiconductor element is generally a thin-film silicon semiconductor, and is roughly classified into an amorphous silicon semiconductor (a-Si) and a crystalline silicon semiconductor.

Since an amorphous silicon semiconductor film has a low manufacturing temperature and can be relatively easily formed by a gas phase method, it is excellent in mass productivity and is generally used more than a crystalline silicon semiconductor film. ing.

However, an amorphous silicon semiconductor film is different from a crystalline silicon semiconductor film in that:
Since physical properties such as conductivity are inferior, establishment of a simple manufacturing method of a thin-film semiconductor element having a crystalline silicon semiconductor film is strongly demanded in order to improve high-speed characteristics and the like of the semiconductor element in the future. . Polycrystalline silicon, microcrystalline silicon, and the like are known as the crystalline silicon semiconductor film.

The following methods (1) to (4) are used to fabricate a thin silicon semiconductor film having such crystallinity.
The method shown in (3) is known. (1) A crystalline silicon semiconductor film is formed directly on an insulating substrate. (2) After the amorphous silicon semiconductor film is formed, the amorphous silicon semiconductor film is irradiated with strong light such as a laser beam, and the amorphous silicon semiconductor film is crystallized into a crystalline silicon semiconductor film by the light energy. (3) After the amorphous silicon semiconductor film is formed, it is heated and the amorphous silicon semiconductor film is crystallized into a crystalline silicon semiconductor film by the heat energy.

However, in the above method (1), crystallization proceeds simultaneously with the film formation step, so that a thick film must be formed in order to obtain a crystalline silicon semiconductor film having a large grain size. Therefore, it is technically difficult to form a film having good semiconductor properties over the entire surface of the substrate. The film formation temperature is as high as 600 ° C. or higher,
There is also a cost problem that an inexpensive glass substrate that cannot withstand a high temperature of 00 ° C. or more cannot be used.

In the above method (2), since the crystallization phenomenon in the melt-solidification process is used, the crystal grains are small, but the grain boundaries formed by collision of the crystal grains are excellent. Thus, a high-quality crystalline silicon semiconductor film can be obtained.
However, for example, when using an excimer laser currently most commonly used as laser light,
Since the stability of laser light is not sufficient, it is not easy to perform uniform processing over the entire surface of a large-sized substrate, and a plurality of crystalline silicon semiconductor films having uniform characteristics are formed on the same substrate. May not be possible. Further, there is also a problem that the laser cannot be manufactured efficiently because the irradiation area of the laser beam is small.

The method (3) is more suitable for forming a large-area crystalline silicon semiconductor film than the methods (1) and (2). However, in order to crystallize an amorphous silicon semiconductor film, heat treatment for a long time under a high temperature condition of 600 ° C. or more is required. For this reason, there is a problem that an inexpensive glass substrate that cannot withstand a high temperature condition of 600 ° C. or more cannot be used, and that the throughput cannot be improved. Further, in the method (3), since the solid-phase crystallization phenomenon is used, the crystal grains become large, the crystal grains having a diameter of several μm spread along the substrate surface, and the grown crystal grains are mutually separated. When a grain boundary is formed by collision, the grain boundary acts as a trap level for carriers, and the mobility of the TFT may be reduced.

A method of producing a high-quality and uniform crystalline silicon semiconductor film by lower-temperature and shorter-time heat treatment using the above method (3) is disclosed in Japanese Patent Laid-Open No. 6-33.
382, JP-A-6-333825, and JP-A-8-33062, respectively.

In the film forming method described in these publications,
After introducing a trace amount of a metal element such as nickel onto the surface of the amorphous silicon semiconductor film, crystallization is performed at a low temperature of 600 ° C. or less and a short processing time of about several hours by performing heat treatment. .

The metal element that promotes crystallization acts as a catalyst in the amorphous silicon semiconductor film, and crystal nuclei having the introduced metal element as nuclei are generated at an early stage. It is considered that crystallization progresses rapidly around the nucleus. For this reason, hereinafter, the metal element used for crystallization of the amorphous silicon semiconductor film is referred to as a catalyst element.

The introduction of such a catalytic element promotes the crystallization of the amorphous silicon semiconductor film. The crystalline silicon semiconductor film obtained by crystal growth has a structure composed of a plurality of columnar crystals, whereas a silicon semiconductor film crystallized by a normal solid-phase growth method has a twin structure. Is in a state close to a single crystal.

However, dangling bonds, defects, and the like are present in the crystalline silicon semiconductor film manufactured by the above-described method for manufacturing a semiconductor film, and these dangling bonds, defects, and the like are present. It acts as a trap level for carriers and causes a decrease in carrier mobility in a manufactured TFT, and also causes a negative shift of a flat band potential due to a positive charge due to a defect.

Further, in a TFT manufactured using such a crystalline silicon semiconductor film, a similar defect exists at the interface between the gate insulating film and the crystalline silicon semiconductor film. , And a negative shift of the flat band potential occurs.

JP-A-7-225079 and JP-A-8-25079
Japanese Patent No. 55858 discloses that the interface between the crystalline silicon semiconductor film and the gate insulating film is modified by using high-pressure steam annealing to neutralize the positive charge due to the defect and to reduce the flat band potential. A method for approaching 0V is disclosed.

In a normal baking furnace, annealing is performed at normal pressure in a nitrogen atmosphere containing a small amount of hydrogen, so that a crystalline silicon semiconductor, a gate insulating film, a crystalline silicon semiconductor film and a gate insulating film are formed. In each of the interfaces, a method for reducing dangling bonds and defects has been proposed.

[0017]

In the method of performing steam annealing under high-pressure conditions, after forming a gate electrode, a crystalline silicon semiconductor film and a gate insulating film are reformed immediately below the gate electrode in order to modify the crystalline silicon semiconductor film and the gate insulating film. Therefore, the crystalline silicon semiconductor film and the gate insulating film in the portion are not sufficiently modified, so that carrier mobility may be reduced due to remaining dangling bonds and defects, and a flat band may cause a negative shift. is there.

Further, in the method of performing the normal pressure annealing in a nitrogen atmosphere containing a small amount of hydrogen, a long time is required for raising and lowering the temperature to raise and lower the temperature. Is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has an object to improve interface characteristics between a crystalline silicon semiconductor film and a gate insulating film, to reduce a decrease in mobility, and to improve a flatness. It is an object of the present invention to provide a method for manufacturing a semiconductor element capable of sufficiently taking measures against band negative shift, a semiconductor element and a semiconductor device manufactured by the method.

[0020]

In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming an amorphous silicon semiconductor film on a substrate having an insulating surface; A step of introducing into the semiconductor film a catalyst element that promotes crystallization of the silicon semiconductor film; a step of heating and crystallizing the amorphous silicon semiconductor film into which the catalyst element is introduced; A step of forming a gate insulating film covering the semiconductor;
And a step of forming a gate electrode on the gate insulating film in a heat treatment at a temperature of 600 ° C. or lower in an atmosphere of an atmospheric pressure or higher.

In the method for manufacturing a semiconductor device according to the present invention, the substrate is preferably a glass substrate.

In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the heat treatment step is performed in a pressure range of 10 to 20 atm.

In the method of manufacturing a semiconductor device according to the present invention, the step of crystallizing the amorphous silicon semiconductor film preferably includes a laser annealing treatment after a heat treatment.

In the method of manufacturing a semiconductor device according to the present invention, the step of crystallizing the amorphous silicon semiconductor film preferably includes a heat treatment in a temperature range of 540 to 600 ° C.

In the method for manufacturing a semiconductor device according to the present invention, the amorphous silicon semiconductor film may have a thickness of 25 to 25.
It is preferable that the film is formed to have a thickness in the range of 80 nm.

In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the catalytic element introduced into the amorphous silicon semiconductor film has a concentration of 1 × 10 ¹⁶ atoms / cm ³ or less.

In the method for manufacturing a semiconductor device according to the present invention, the catalyst element may be one or more of nickel, cobalt, palladium, platinum, copper, silver, indium, tin, aluminum and antimony. preferable.

In the method for manufacturing a semiconductor device according to the present invention, the catalyst element preferably contains at least nickel.

The semiconductor device of the present invention is manufactured by the above-described method of manufacturing a semiconductor device of the present invention.

Further, in the semiconductor device of the present invention, a plurality of the semiconductor elements of the present invention are formed on the same substrate.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

The method of manufacturing a semiconductor device according to the present invention is applied, for example, for manufacturing an N-type TFT on a glass substrate. Such a TFT is applicable to a driver circuit and a pixel portion of an active matrix type, and can also be used as a constituent element of a thin film integrated circuit.

In this embodiment, a method of manufacturing hundreds of thousands to several millions of N-type TFTs to be used as pixel TFTs on an active matrix substrate for a liquid crystal display device will be described.

FIGS. 1A to 1D are cross-sectional views showing steps of manufacturing an N-type TFT as a method of manufacturing a semiconductor device according to the present invention. Active matrix substrates for liquid crystal display devices, which are semiconductor devices, have hundreds of thousands or more of T
Although an FT is provided, a method of manufacturing one TFT will be described to facilitate understanding of the present invention.

First, as shown in FIG. 1A, a plasma CVD method is performed on a glass substrate 1 which is an insulating substrate.
A base film 2 made of silicon oxide is formed to a thickness of 200 nm. Next, an intrinsic amorphous silicon semiconductor film 3 is formed by a plasma CVD method. If the amorphous silicon semiconductor film 3 has a thickness of less than 25 nm, sufficient crystal growth cannot be achieved even by the introduction of a catalyst element described later, and if it exceeds 80 nm, the introduction of the catalyst element in a later step will cause The resulting columnar crystals may have a two-layer structure and the crystallinity may be deteriorated, and the catalytic element may remain. For this reason, the thickness of the amorphous silicon semiconductor film 3 is preferably 25 nm to 80 nm. In this embodiment, the amorphous silicon semiconductor film 3 is formed to a thickness of 40 nm. After the amorphous silicon semiconductor film 3 is formed, an unnecessary portion of the amorphous silicon semiconductor film 3 is removed to separate elements.

This amorphous silicon semiconductor film 3
Is an element formation film that will be a source region, a drain region, and a channel region in a later step, and forms a number of island regions by performing element isolation. In the present embodiment,
Since the present invention is applied to an active matrix type liquid crystal display device, the amorphous silicon semiconductor film 3 has island regions arranged in a matrix.

Next, as shown in FIG. 1B, Ni as a catalyst element is added to the amorphous silicon semiconductor film 3 by a sputtering method. The added catalytic element may remain in the active region of the TFT to be manufactured, causing an increase in leakage current and deterioration of characteristics. Therefore, the surface concentration of the added catalytic element is 1 × 10 ¹⁵ atoms / c.
m ² or less. In the present embodiment, 7
A surface concentration of × 10 ¹³ atoms / cm ² was obtained.
Ni (nickel) as a catalyst element was added.

The catalyst element to be added is Ni
In addition, one or more metals such as cobalt, palladium, platinum, copper, silver, gold, indium, tin, aluminum, and antimony can be used. The crystallization of the silicon semiconductor film 3 can be promoted.

However, since the catalytic element promotes the crystal growth of silicon by being silicided in the amorphous silicon semiconductor film, the lattice constant of the silicide compound of the catalytic element becomes the lattice constant of the crystal structure of single crystal silicon. Preferably, they are similar. NiSi ₂ , a silicide compound of Ni, has the crystal structure most similar to that of single-crystal silicon among the silicide compounds of the catalyst element described above, and its lattice constant is also closest to the lattice constant of silicon. ing. Therefore, NiSi ₂ becomes the most excellent template for crystallization of the amorphous silicon semiconductor film, and crystallization of the amorphous silicon semiconductor film is most promoted. Therefore, Ni is suitable as a catalyst element.

The method of adding the catalytic element is not limited to the above-described sputtering method, but may be performed by using an amorphous silicon semiconductor film 3 using a coating solution composed of a Ni compound.
A method of forming a coating film thereon may be used.

When the catalytic element is added to the amorphous silicon semiconductor film 3, the entire glass substrate 1 is heat-treated in an inert gas atmosphere at a temperature of 540 to 620 ° C. for several hours. The silicon semiconductor film 3 is crystallized. As described above, by performing crystallization with the catalyst metal as a nucleus in a temperature range of 540 to 620 ° C., it is possible to prevent spontaneous generation of a crystal nucleus independent of the catalyst metal in the amorphous silicon semiconductor film 3. it can. In this embodiment, the entire glass substrate 1 is heat-treated at 580 ° C. for 4 hours in a nitrogen atmosphere.

Next, by irradiating the silicon semiconductor film 3 with a laser beam, the crystallization of the silicon semiconductor film 3 is further promoted. In the present embodiment, a KrF excimer laser having a wavelength of 248 nm and a pulse width of 20 nsec is used as laser light to be applied to the silicon semiconductor film 3. However, not limited to such a KrF excimer laser, other laser light may be used.

The conditions for irradiating the silicon semiconductor film 3 with laser light are as follows:
In the range of 00 to 400 mJ / cm ² , for example, 250 mJ
/ Cm ² , and 2 to 10 shots, for example, 2 shots of laser light are irradiated per spot. Simultaneously with the irradiation of the laser beam, the entire glass substrate 1
Heating to about ° C further promotes crystallization of the silicon semiconductor film 3.

Thereafter, a silicon oxide film 4 as a gate insulating film is coated by plasma CVD over the entire glass substrate 1 so as to cover the crystalline silicon semiconductor film 3 in a thickness of 50 to 250 nm, for example, 150 nm.
To a film thickness of

Next, the entire glass substrate 1 is subjected to a heat treatment in an atmosphere containing water vapor under a temperature condition of about 50 to 600 ° C. under a pressure of at least atmospheric pressure. The pressure condition is preferably about 10 to 20 atm, since the temperature can be raised to a predetermined temperature in a short time and the temperature can be lowered to a predetermined temperature in a short time. Also, the heating temperature
By setting the temperature to 600 ° C. or lower, an inexpensive glass substrate 1 can be used. In the present embodiment, 35
Heat treatment was performed for 1 hour at a temperature of 0 ° C. and a pressure of 10 atm.

By performing a heat treatment in such a high-pressure steam atmosphere, the crystalline silicon semiconductor film 3 is formed.
In addition, defects and dangling bonds included in the silicon oxide film 4 serving as a gate insulating film are reduced. In addition, since a part of the upper surface of the crystalline silicon semiconductor film 3 in contact with the silicon oxide film 4 as the gate insulating film is oxidized, the interface characteristics between the crystalline silicon semiconductor film 3 and the silicon oxide film 4 are improved. Improved, and defects and dangling bonds at this interface portion are reduced.

Further, since the heat treatment is carried out under a high pressure condition higher than the atmospheric pressure, the temperature can be raised in a short time and the temperature can be lowered to a predetermined temperature in a short time. As a result, the efficiency of the overheat treatment can be improved, and the productivity of the semiconductor element can be improved.

Then, as shown in FIG. 1C, an aluminum film is formed on the silicon oxide film 4 in a range of 400 to 800 nm, for example, 600 nm by a sputtering method.
The gate electrode 5 is formed at the center of the crystalline silicon semiconductor film 3 by patterning the formed aluminum film into a predetermined shape. Then, the gate electrode 5
An oxide layer 6 is formed by anodizing the surface of the substrate. The anodic oxidation of the gate electrode 5 is performed in an ethylene glycol solution containing tartaric acid at 1 to 5%. This oxide layer 6
The portion of the crystalline silicon semiconductor film 3 covered with is formed by the anodic oxidation step so that the length of the offset gate area is formed in the subsequent ion doping step in order to form an offset gate area that is not ion-doped. Is determined by the thickness of the oxide layer 6. In this embodiment, the thickness of the oxide layer 6 is set to 200 nm.

Next, impurities such as phosphorus or boron are implanted into the crystalline silicon semiconductor film 3 by an ion doping method. In this embodiment, phosphorus is used as an impurity, its acceleration voltage is in the range of 60 to 90 kV, for example, 80 kV, phosphine (PH ₃ ) is used as a doping gas, and the dose of a phosphorus element is 1
The range of × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 2 × 10
^{It was 15} cm ^-2 .

In this step, the gate electrode 5 and the oxide layer 6 formed on the silicon oxide film 4 function as a mask, and the gate electrode 5 and the oxide semiconductor layer 3 on which the oxide layer 6 is not formed are formed. Impurities are implanted into the regions to form source and drain regions 7 and 9 in the TFT through the steps described later (both refer to FIG. 1D).
On the other hand, the region of the crystalline silicon semiconductor layer 3 immediately below the gate electrode 5 is a region into which impurities are not implanted, and is subjected to a channel region 8 (FIG.
Reference).

Note that an N-type TFT and a P-type T
In the case of fabricating a semiconductor device in which the FT and the FT are configured in a complementary manner, a photoresist serving as a mask when each of the N-type or P-type impurities is implanted is formed.
If the respective photoresists are selectively doped with impurities, impurities capable of forming N-type and P-type impurity regions can be respectively introduced, and then introduced in a nitrogen atmosphere at a temperature of 550 ° C. for 4 hours. By performing the heat treatment over a period of time, the ion-implanted impurities are activated.

Next, as shown in FIG. 1D, a silicon oxide film 10 having a thickness of 600 nm is formed as an interlayer insulating film over the entire glass substrate 1 by plasma CVD over the entire surface of the substrate. Contact holes are formed from the silicon oxide film 10 to the source region 7 and the drain region 9 of the silicon semiconductor film 3, respectively. Thereafter, a source electrode 11 and a drain electrode 12 that are conductive to the source region 7 and the drain region 9 of the TFT, respectively, are formed in each of the formed contact holes by a metal material, for example, a multilayer film of titanium nitride and aluminum. Thus, a TFT is formed.

When the formed TFT is used as a pixel switching element of a liquid crystal display device or the like, a pixel electrode made of ITO or the like is formed instead of the source electrode 11 and the drain electrode 12 made of a metal material.

The semiconductor device thus obtained is subjected to steam annealing under high-pressure conditions before forming the gate electrode 5, so that defects contained in the crystalline silicon semiconductor film 3 and the silicon oxide film 4 are removed. And dangling bonds are reduced. Moreover, the crystalline silicon semiconductor film 3
Is partially oxidized on the upper surface side in contact with the silicon oxide film 4 serving as the gate insulating film, thereby improving the interface characteristics between the crystalline silicon semiconductor film 3 and the silicon oxide film 4, and improving defects and defects at this interface portion. A TFT having a high-quality semiconductor film with reduced dangling bonds is obtained.

FIG. 2 shows a semiconductor device of the present invention and a semiconductor device having a semiconductor layer formed by a conventional method without performing steam annealing under high pressure conditions.

According to the table of FIG. 2, the semiconductor device of the present invention is superior to the conventional semiconductor device in both the mobility, the threshold voltage Vth, and the sub-threshold value S, and has a variation in the threshold voltage Vth. The semiconductor device has been reduced and has uniform characteristics on the same substrate.

[0057]

According to the method of manufacturing a semiconductor device of the present invention, since a steam annealing is performed under high pressure conditions before forming a gate electrode, defects and dangling contained in a crystalline silicon semiconductor film and a gate insulating film are reduced. The number of ring bonds is reduced, and a part of the upper surface of the crystalline silicon semiconductor film which is in contact with the gate insulating film is oxidized. This allows
A semiconductor element having a high-quality semiconductor film having excellent interface characteristics between a crystalline silicon semiconductor film and a gate insulating film and having reduced defects and dangling bonds at the interface can be obtained.

The semiconductor device manufactured by the method of manufacturing a semiconductor device according to the present invention is excellent in the interface characteristics between the crystalline silicon semiconductor film and the gate insulating film of each semiconductor device. It is excellent for each of the voltage and the sub-threshold characteristic value. Further, in a semiconductor device in which a plurality of such semiconductor elements are formed on the same substrate, variations in threshold voltage between the semiconductor elements are reduced.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention for each process.

FIG. 2 is a table comparing the mobility, the threshold voltage, the sub-threshold characteristic value, and the variation in the threshold voltage between a semiconductor device having a semiconductor element of the present invention and a semiconductor device having a conventional semiconductor element.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Underlayer 3 Silicon semiconductor film 4 Silicon oxide film 5 Gate electrode 6 Oxide layer 7 Source region 8 Channel region 9 Drain region 10 Silicon oxide film 11 Source electrode 12 Drain electrode

 ──────────────────────────────────────────────────続 き Continued from the front page F term (reference) GG02 GG13 GG25 GG35 GG45 HJ01 HJ04 HJ12 HJ23 HL01 HL03 HL07 HL11 HM14 NN04 NN23 NN35 NN72 PP01 PP03 PP05 PP10 PP13 PP29 PP34 QQ11

Claims (11)

[Claims] A step of forming an amorphous silicon semiconductor film on a substrate having an insulating surface; and a step of introducing a catalytic element that promotes crystallization of the silicon semiconductor film into the amorphous silicon semiconductor film. A step of heating and crystallizing the amorphous silicon semiconductor film into which the catalytic element has been introduced, a step of forming a gate insulating film covering the crystalline silicon semiconductor, and a substrate on which the gate insulating film is formed A heat treatment at a temperature of 600 ° C. or less in an atmosphere of 1 atm or more containing water vapor, and a step of forming a gate electrode on the gate insulating film. Method. 2. The method according to claim 1, wherein the substrate is a glass substrate. 3. The heat treatment step is performed at 10 to 20 atm.
The method for manufacturing a semiconductor device according to claim 1, wherein the method is performed in a pressure range of: 4. The method according to claim 3, wherein the step of crystallizing the amorphous silicon semiconductor film includes a laser annealing process after a heat treatment. 5. The method according to claim 1, wherein the step of crystallizing the amorphous silicon semiconductor film includes a heat treatment in a temperature range of 540 to 600 ° C. 6. The method according to claim 1, wherein the amorphous silicon semiconductor film is formed to a thickness in a range of 25 to 80 nm. 7. The catalyst element introduced into the amorphous silicon semiconductor film is 1 × 10 ¹⁶ atoms / cm.
^The method for manufacturing a semiconductor device according to claim 1, wherein the concentration is ³ or less. 8. The catalyst element is nickel, cobalt,
The method for manufacturing a semiconductor device according to claim 1, wherein the method is one or more of palladium, platinum, copper, silver, indium, tin, aluminum, and antimony. 9. The method according to claim 8, wherein the catalytic element contains at least nickel. 10. A semiconductor device manufactured by the manufacturing method according to claim 1. 11. A semiconductor device wherein a plurality of the semiconductor elements according to claim 10 are formed on the same substrate.