JP3107345B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates relates to a method of manufacturing a semiconductor equipment and, more particularly, to a method of manufacturing a semiconductor equipment which the crystalline silicon film amorphous silicon film is crystallized with the active region. In particular, the present invention is effective for a semiconductor device having a TFT (thin film transistor) provided on an insulating substrate, and can be applied to an active matrix liquid crystal display device, a contact image sensor, a three-dimensional IC, and the like.

[0002]

2. Description of the Related Art In recent years, large and high resolution liquid crystal display devices have been developed.
High-speed, high-resolution contact image sensor, 3D IC
In order to realize such a technique, attempts have been made to form a high-performance semiconductor element on an insulating substrate such as glass or an insulating film. In general, a thin-film silicon semiconductor layer is used for a semiconductor element used in these devices.

[0003] The silicon semiconductor layer in the form of a thin film is roughly classified into two types: a layer composed of an amorphous silicon semiconductor (a-Si) and a layer composed of a crystalline silicon semiconductor. Amorphous silicon semiconductors are most commonly used because they have a low production temperature, can be relatively easily produced by a gas phase method, and have high mass productivity. Inferior to silicon semiconductors. Therefore, in order to obtain higher-speed characteristics in the future, it is strongly required to establish a method for manufacturing a semiconductor device made of a crystalline silicon semiconductor. Note that as the silicon semiconductor having crystallinity, polycrystalline silicon, microcrystalline silicon, amorphous silicon containing a crystal component, semi-amorphous silicon having an intermediate state between crystalline and amorphous, and the like are known.

As a method for obtaining a silicon semiconductor layer in the form of a thin film having crystallinity, (1) a semiconductor film is formed while imparting crystallinity to the semiconductor film, and (2) an amorphous semiconductor film is formed. Forming a film and then making the semiconductor film crystalline by the energy of laser light. (3) forming an amorphous semiconductor film and then applying heat energy to the semiconductor film Has crystallinity,
Such a method is known.

However, in the method (1), the crystallization proceeds simultaneously with the film formation step, so that it is necessary to increase the thickness of the silicon film in order to obtain crystalline silicon having a large grain size. It is technically difficult to uniformly form a film having the above on the substrate over the entire surface. Further, in this method, since the film forming temperature is as high as 600 ° C. or more, there is a problem in terms of cost that an inexpensive glass substrate cannot be used.

In the method (2), the crystallization phenomenon in the melting and solidification process is used, so that the grain boundaries are satisfactorily processed in spite of the small grain size, and a high-quality crystalline silicon film can be obtained. Taking an excimer laser, which is most commonly used, as an example, the first problem is that the laser light irradiation area is small and the throughput is low. In addition, the crystallization treatment using laser light does not have sufficient laser stability to uniformly treat the entire surface of a large-area substrate, and has a strong sense of a next-generation technology.

The method (3) has an advantage that it can cope with a large area as compared with the methods (1) and (2). However, the crystallization requires a heat treatment at a high temperature of 600 ° C. or more for several tens of hours. is necessary. On the other hand, considering the use of an inexpensive glass substrate and the improvement of throughput, it is necessary to lower the heating temperature and crystallize in a shorter time. Therefore, in the method (3), it is necessary to simultaneously solve the above conflicting problems.

In the method (3), since the solid phase crystallization phenomenon is used, the crystal grains spread in parallel to the substrate surface and have a size of several μm.
However, since the grown crystal grains collide with each other to form a grain boundary, the grain boundary acts as a trap level for carriers, which is a major cause of lowering the mobility of the TFT. Would.

A method for solving the above-mentioned problem of the crystal grain boundary by using the above method (3) is disclosed in Japanese Patent Application Laid-Open No. 5-55142.
Or Japanese Patent Application Laid-Open No. 5-136048. In these methods, a foreign substance serving as a nucleus for crystal growth is introduced into an amorphous silicon film, and then a heat treatment is performed to obtain a crystalline silicon film having a large particle diameter using the foreign substance as a nucleus.

In the former, silicon (Si.sup. ⁺ ) Is introduced into an amorphous silicon film by an ion implantation method, and then a polycrystalline silicon film having crystal grains having a grain size of several .mu.m is obtained by heat treatment.
In the latter, growth nuclei are formed by blowing Si particles having a particle size of 10 to 100 nm together with high-pressure nitrogen gas onto an amorphous silicon film. In both cases, a semiconductor element is formed using a high-quality crystalline silicon film obtained by selectively introducing foreign matter into an amorphous silicon film and using the nucleus as a nucleus to grow a crystal.

In order to realize a high-performance MOS transistor, not only the quality of the above-mentioned crystalline silicon film as an active region but also the quality of a gate insulating film and the active region are improved. It is essential to improve the quality of the interface between the semiconductor thin film and the gate insulating film.

In a MOS transistor manufactured on a Si substrate by a conventional IC process, the surface of the Si substrate is thermally oxidized, and the thermally oxidized silicon film is used as a gate insulating film. Therefore, the interface between the active layer and the gate insulating film is kept clean, and a very high-quality silicon oxide film can be obtained as the gate insulating film.

However, this thermal oxidation step requires 100
Since a high temperature of 0 ° C. or higher is required, it cannot be applied to a TFT manufactured on an inexpensive glass substrate. Also, even if a thermal oxide film is formed using a substrate having high heat resistance such as a quartz substrate, the underlying silicon film is not a single crystal silicon but a crystalline silicon film. The insulating properties of a silicon film are poor and cannot be used as a gate insulating film.

Therefore, in a semiconductor device using a crystalline silicon film formed on an insulating substrate, it is necessary to separately form a gate insulating film by a low-temperature film forming method such as a CVD method. For example, in Japanese Patent Application Laid-Open No. 3-4564, a semiconductor layer (amorphous silicon film) and a gate insulating film are continuously formed by a low-temperature film forming method, and then a heat treatment for solid-phase crystallization is performed. The interface between the layer and the gate insulating film (hereinafter, referred to as a semiconductor layer / gate insulating film interface) is kept clean and has a high performance T.
FT is realized.

[0015]

When a semiconductor device such as a TFT is formed on a substrate having an insulating property by using a crystalline silicon film, the most problematic is the active region as described above. And the state of the interface between the semiconductor layer and the gate insulating film.

First, as for the gate insulating film, when the gate insulating film is formed by the low-temperature film forming method, the film quality is inferior to that of the gate insulating film formed by the high-temperature oxidation method, and the high-performance TF
There is a problem that T cannot be realized. This is because defect levels due to residual stress, dangling bonds, impurities, and the like in the gate insulating film exist at the interface between the semiconductor layer and the gate insulating film, and the depletion layer does not spread. This problem can be almost solved by keeping the interface between the semiconductor layer and the gate insulating film clean, and the technique described in JP-A-3-4564 is effective.

However, with regard to the method of producing a crystalline silicon film to be an active region, considering a large-area substrate, the solid-phase crystal described in the above (3), in which the crystallinity within the substrate is somewhat stable, is considered. Although it is currently most preferable to use the crystallization method, the crystalline silicon film produced by the conventional solid-phase crystallization method as disclosed in JP-A-3-4564 has a The influence is large, and a single crystal grain also shows a twin structure with many crystal defects. For this reason, in the method proposed in Japanese Patent Application Laid-Open No. 3-4564, since the semiconductor layer has a twin structure with many crystal defects, when the semiconductor layer and the gate insulating film are continuously formed, the lower semiconductor layer is formed. The defect level at the interface between the semiconductor layer and the gate insulating film cannot be reduced as much as when the insulating thin film is continuously formed on the single crystal silicon film, reflecting the poor crystallinity, and the interface between the semiconductor layer and the gate insulating film is cleaned. The effect obtained by keeping at is diminished. Therefore, in order to improve the performance of a semiconductor device, it is necessary not only to continuously form a semiconductor layer and a gate insulating film in a state where external air is shut off, but also to improve the quality of a crystalline silicon film to be an active region.

In the technique disclosed in Japanese Patent Application Laid-Open Nos. 5-55142 and 5-136048 for the purpose of improving the quality of the crystalline silicon film, Si ⁺ ions or Si ⁺ ions are selectively passed through an implantation window. The grains are introduced into the amorphous silicon film to form crystal growth nuclei, but the number of crystal nuclei generated in the injection window is not one, but a number of crystal nuclei are generated, and individual crystal growth Crystal growth takes place from the nucleus of. Therefore, a single crystal grain centered on one implantation window of Si ⁺ ions or Si particles cannot actually be formed,
Grain boundaries are formed by a large number of nuclei generated in the injection window.

Therefore, in JP-A-5-55142 or JP-A-5-136048, it is impossible to actually control the grain boundaries. Further, since an implantation mask is required when selectively introducing Si ⁺ ions or Si particles serving as crystal nuclei, extra steps that are not directly related to the original semiconductor device manufacturing process are added. Therefore, there is a great disadvantage in productivity, and as a result, the cost of the product is increased.

Further, when an inexpensive glass substrate is used, shrinkage of the substrate in a heat treatment step for crystallization,
Problems such as warpage occur. For example, Corning 7 commonly used in active matrix type liquid crystal display devices
059 glass (Corning's trade name) has a glass strain point of 5
At 93 ° C., there is a problem in heating at a temperature higher than 93 ° C. in consideration of increasing the area of the substrate.

On the other hand, when the conventional solid-phase crystallization method is used, the heat treatment is performed at a heating temperature of at least 600 ° C. for 20 hours or more, depending on the method and conditions for forming the starting a-Si film. is necessary. In Japanese Patent Application Laid-Open No. 3-4564, 500
Although it is described that annealing is performed for a long time at a temperature of 700 ° C. to 700 ° C., in the solid-phase crystallization of the a-Si film described in the example, actually, a heating temperature of at least 600 ° C.
It seems that an annealing time of 0 hour or more is required. In the technique described in JP-A-5-55142, crystallization is performed by a heat treatment at a temperature of 600 ° C. for 40 hours. Also, in Japanese Unexamined Patent Publication No. Hei 5-136048,
Heat treatment at a heating temperature of 650 ° C. or higher is performed. therefore,
These techniques are effective for SOI substrates and SOS substrates, but it has been difficult to form a crystalline silicon film on an inexpensive glass substrate to form a semiconductor element using these techniques.

Further, as described above, the characteristics of the interface between the semiconductor layer for channeling and the gate insulating film are very important factors in the MOS transistor, but in the case of a thin film transistor, the characteristics of the semiconductor layer / The state of the interface facing the gate insulating film interface is also particularly important. That is, when the transistor is in an OFF state, a back channel is formed at an interface facing the gate insulating film with the semiconductor layer interposed therebetween, which causes an increase in leakage current. Therefore, in the case of a TFT that requires a particularly high charge retention characteristic, such as a pixel switching element or a memory element of an active matrix substrate, it is necessary to maintain good interface characteristics at the interface facing the gate insulating film in order to prevent leakage current due to the back channel effect. Was indispensable.

The present invention has been made in order to solve the above-mentioned problems, and provides a high-quality crystalline silicon film having higher crystallinity than that obtained by a normal solid-phase growth method with good productivity. In addition, the interface between the semiconductor layer and the insulating film can be kept clean, and at this time, the heating temperature required for crystallization is set to 580 ° C. or less, and Corning 7059 is used.
To obtain a manufacturing method of the semiconductor equipment to an inexpensive glass substrate typified by glass can be available is an object of the present invention.

[0024]

Means for Solving the Problems Accordingly, the present inventors have:
As a result of diligent research to achieve the above object, a minute amount of a metal element such as nickel, palladium, or lead was introduced into the surface of the amorphous silicon film, and then heat treatment was performed at about 550 ° C. for about 4 hours. It has been found that the amorphous silicon film can be crystallized in the above processing time.

This mechanism is based on the assumption that crystal nucleus generation with a metal element as a nucleus occurs at an early stage of the heat treatment, and then the metal element acts as a catalyst to promote crystal growth, and crystallization proceeds rapidly. Understood. In such a sense, these metal elements are called catalyst elements. The crystal grains grown from one crystal nucleus by the ordinary solid phase growth method have a twin structure in the crystal grains of the crystalline silicon film grown by the crystallization promoted by these catalyst elements. Further, many needle-like crystals or columnar crystals are woven, and the inside of each needle-like crystal or columnar crystal is in an ideal single crystal state.

When a TFT is manufactured using such a crystalline silicon film as an active region, the field-effect mobility is 1.2 times higher than that of a case using a crystalline silicon film formed by a usual solid phase growth method. To a degree. After crystallization by heat treatment, the crystallized silicon film is irradiated with laser light or intense light to irradiate the crystallized silicon film with a catalytic element for crystallization and the solid-phase growth method for the field-effect mobility. The difference becomes even more pronounced.

That is, when the crystalline silicon film is irradiated with laser light or strong light, the crystal grain boundary is intensively treated due to the difference in melting point between the crystalline silicon film and the amorphous silicon film. However, in a crystalline silicon film formed by an ordinary solid-phase growth method, since the crystal structure is in a twin state, the inside of a crystal grain boundary remains as a twin defect even after laser irradiation. In comparison, a crystalline silicon film crystallized by introducing a catalytic element,
It is formed of needle-like crystals or columnar crystals, and its inside is almost a single crystal, so the crystal grain boundary is treated by laser light or strong light irradiation, and the crystallinity in the crystal grains is further promoted. Thus, a crystalline silicon film exhibiting very good crystallinity over the entire surface of the substrate can be obtained.

By the way, among the semiconductor elements, especially TFTs
In order to improve the stability of a MOS transistor device such as a MOS transistor device and improve its performance, a technique for keeping the interface between the semiconductor layer and the gate insulating film clean as described above, that is, the semiconductor layer /
A technique for continuously forming a gate insulating film in a vacuum is indispensable. Further, in order to reduce the leak current of the TFT and improve the charge retention characteristics, a technique for keeping the interface facing the gate insulating film with the semiconductor layer in between is necessary, and the underlying insulating film / semiconductor layer / It is more desirable to continuously form three layers of the gate insulating film.

The semiconductor layer crystallized using the above catalyst is
It is formed of a needle-like crystal or a columnar crystal, and its interior is almost a single crystal. Therefore, when a semiconductor layer and a gate insulating film are continuously formed, a conventional crystalline silicon film having a twin structure with many crystal defects is formed. The interface characteristics can be greatly improved as compared with the case where is used for the semiconductor layer.

However, the above-described method for producing a crystalline silicon film, which the present inventors have found, requires a step of adding a catalytic element to the semiconductor layer. It has been difficult to form an insulating film continuously, and further to form a base insulating film / semiconductor layer / gate insulating film continuously.

The present inventors added the above-mentioned catalyst element and added
In a TFT process in which a crystalline silicon film crystallized by low-temperature annealing at 80 ° C. or lower is used for an active region, a semiconductor layer / gate insulating film is continuously formed, and further, a base insulating film / semiconductor layer / gate insulating film is continuously formed in three layers. The process that makes it possible is studied.

As a result, after the semiconductor layer / gate insulating film is continuously formed, a catalytic element is introduced into the semiconductor layer through the gate insulating film by an ion implantation method, and crystallized by heat treatment.
Alternatively, it has been discovered that the object of the present invention can be achieved by irradiating laser light or strong light thereafter.

As another method, the same crystallization effect can be obtained by adding a catalytic element to the region below the semiconductor layer.
We have also discovered that it is possible to continuously form a semiconductor layer / gate insulating film. However, in this method, a catalyst element is added to the surface of the underlying film before the semiconductor layer is formed, and the catalyst is also added to the underlying film. The elements diffuse, and the concentration of the catalytic element added to the semiconductor layer cannot be properly controlled. Further, in this method, since it is necessary to implant a catalytic element into the base insulating film, it is structurally impossible to continuously form three layers of the base insulating film / semiconductor layer / gate insulating film. Therefore, there is only the above-described ion implantation method as a method of continuously forming three layers of a base insulating film / semiconductor layer / gate insulating film and introducing a catalytic element. In addition, a TFT manufactured by continuously forming a semiconductor layer / gate insulating film by using a method of adding a catalytic element to the base insulating film did not exhibit the expected high-performance characteristics.

Here, the lower the concentration of the catalytic element to be introduced into the amorphous silicon film, the better, but if it is too low, it does not function to promote crystallization of the amorphous silicon film. As a result of investigations by the present inventors, the minimum concentration of a catalyst element at which crystallization occurs is 1 × 10 ¹⁶ atoms / cm ³ ,
At a concentration lower than this, crystal growth by the catalytic element does not occur.

If the concentration of the catalytic element is high, the effect on the device becomes a problem. A phenomenon that occurs when the catalytic element is high is an increase in leakage current mainly in the off region of the TFT. This is understood to be due to the influence of the impurity level formed in the silicon film by the catalytic element, which is caused by the tunnel current through the level. As a result of investigations by the present inventors, the maximum concentration of the catalytic element that does not affect the device is 1 × 10
¹⁹ atoms / cm ³ . Therefore, the concentration of the catalyst element in the film is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atoms / cm ^3.
Then, the catalyst element functions most effectively.

Further, in a TFT, the thickness of the active layer is suitably from 20 to 150 nm. That is, the film thickness 20
If it is less than nm, good crystallinity cannot be obtained,
Above nm, the possibility of disconnection of the wiring at the edge of the active region increases. Generally, a film thickness of about 100 nm is considered appropriate. In order to introduce a catalytic element into the a-Si film having this thickness at a concentration within the above range, the dose amount in the ion implantation step is set to 1 ×. 10 ¹¹ to 1 × 10 ¹⁴ at
oms / cm ² .

The crystallization method using the above catalyst element can obtain the most remarkable effects when Ni is used as the catalyst element. Other types of usable catalyst elements include Co, Pd, Pt, Cu, Ag, Au, and I.
n, Sn, Al, and Sb. One or a plurality of elements selected from these elements have the effect of promoting crystallization in a very small amount (concentration in the film of 1 × 10 ¹⁶ atoms / cm ³ or more), and thus have no problem on the semiconductor element. .

The present invention has been obtained as a result of such intensive studies by the present inventors.

[0039]

[0040]

[0041]

[0042]

[0043]

[0044]

[0045]

[0046]

(1) In the method of manufacturing a semiconductor device according to the present invention, an insulating thin film such as an amorphous silicon film and a silicon oxide film is formed on a substrate having a surface region having an insulating property in a state where the outside air is shut off. And forming a catalyst element for promoting crystallization of the amorphous silicon film,
The method includes a step of introducing the catalyst element through the insulating thin film by an ion implantation method and a step of crystallizing the amorphous silicon film into which the catalyst element has been introduced by heating, thereby achieving the above object.

(2) In the method of manufacturing a semiconductor device according to the present invention, an insulating thin film such as an amorphous silicon film and a silicon oxide film may be formed on a substrate having a surface region having an insulating property in a state where outside air is shut off. And forming a catalyst element for promoting crystallization of the amorphous silicon film,
A step of introducing the catalyst element through the insulating thin film by ion implantation, a step of crystallizing the amorphous silicon film into which the catalyst element is introduced by heating, and irradiating the crystallized silicon film with laser light or strong light. And treating the crystal by the above process, thereby achieving the above object.

(3) Preferably, in the present invention, the method for manufacturing a semiconductor device includes a step of forming a gate insulating film of a MOS transistor from the insulating thin film.

(4) In the method of manufacturing a semiconductor device according to the present invention, three layers of the first insulating thin film, the amorphous silicon film, and the second insulating thin film are formed on the substrate in a state where the outside air is shut off. A step of continuously forming, a step of introducing a catalyst element for promoting crystallization of the amorphous silicon film into the amorphous silicon film through the second insulating thin film by an ion implantation method, Crystallizing the amorphous silicon film into which the element is introduced by heat treatment, thereby achieving the above object.

(5) In the method of manufacturing a semiconductor device according to the present invention, three layers of the first insulating thin film, the amorphous silicon film, and the second insulating thin film are continuously formed on the substrate in a state where the outside air is shut off. Forming a catalyst element that promotes crystallization of the amorphous silicon film into the amorphous silicon film via the second insulating thin film by an ion implantation method; The step of crystallizing the amorphous silicon film into which is introduced, and the step of irradiating the crystallized silicon film with laser light or strong light to perform crystal treatment, thereby achieving the above object. Is done.

(6) Preferably, in the present invention, the method for manufacturing a semiconductor device includes the step of:
Forming a gate insulating film of the S-type transistor.

(7) Preferably, in the present invention, the dose at the time of introducing the catalyst element into the amorphous silicon film by an ion implantation method is 1 × 10 ¹¹ to 1 × 10 ¹⁴ atom.
s / cm ² .

(8) In the present invention, Ni, Co, Pd, Pt, Cu, Ag, and A are preferably used as the catalyst element.
One or more of u, In, Sn, Al and Sb are used.

[0055]

According to the method of manufacturing a semiconductor device of the present invention ,
In a state where the air is shut off, the surface
Continuous formation of amorphous silicon film and insulating thin film on board
Therefore, the interface of these films can be kept clean.
it can.

[0056]

[0057]

[0058]

[0059]

[0060]

[0061]

A catalyst element for promoting crystallization of the amorphous silicon film is introduced into the amorphous silicon film via the insulating thin film by an ion implantation method. Since the crystalline silicon film is crystallized by heating, a high-quality crystalline silicon film having higher crystallinity than the crystallinity obtained by the ordinary solid phase growth method,
It can be formed with high productivity.

In this case, the heating temperature required for crystallization is 5
The temperature is 80 ° C. or lower, and an inexpensive glass substrate typified by Corning 7059 glass can be used as the substrate.

Further, after the amorphous silicon film into which the catalytic element has been introduced is crystallized by heating, the crystallized silicon film is irradiated with laser light or strong light to perform crystal processing. Further, the crystallinity of the crystalline silicon film forming the active region can be further increased, and the field effect mobility of carriers in the active region can be further improved.

In the method of manufacturing a semiconductor device according to the present invention, three layers of a first insulating thin film, an amorphous silicon film, and a second insulating thin film are successively formed on a substrate in a state where the outside air is shut off. Therefore, the characteristics of the interface between the amorphous silicon film and the insulating thin film above and below the amorphous silicon film can be greatly improved.

[0066]

EXAMPLES Example 1] FIG. 1 is a sectional view for explaining a first method of <br/> manufacturing a thin film transistor capacitor according to an embodiment of the present invention, FIGS. 1 (a) through 1 ( 3E shows a method of manufacturing the TFT of this embodiment in the order of steps.

In the figure, reference numeral 100 denotes a semiconductor device having a thin film transistor (TFT) 10.
Is formed on a glass substrate 101 via an insulating base film 102 such as a silicon oxide film. The insulating base film 10
On 2, an island-shaped crystalline silicon film 103 b constituting the TFT is formed. This crystalline silicon film 103
The central portion of b is a channel region 108, and the two side portions are source and drain regions 109 and 110. An aluminum gate electrode 106 is provided on the channel region 108 via a gate insulating film 104. The surface of the gate electrode 106 is covered with an oxide layer 107. The entire surface of the TFT 10 is covered with an interlayer insulating film 111, and contact holes 111a are formed in portions of the interlayer insulating film 111 corresponding to the source / drain regions 109 and 110. The source / drain regions 109 and 110 are connected to the electrode wiring 112, via the contact hole 111a.
113.

In this embodiment, the crystalline silicon film 103b contains a catalytic element (Ni) that promotes crystallization of the amorphous silicon film by heat treatment, and the crystal grains in this film are substantially in a single crystal state. Are made of needle-like crystals or columnar crystals.

The TFT 10 of this embodiment can of course be used as an element constituting a driver circuit or a pixel portion of an active matrix type liquid crystal display device.
CPU mounted on the same substrate as these circuits and pixel parts
Can also be used as an element constituting. Note that T
The application range of FT is not limited to liquid crystal display devices,
Needless to say, it can be used for a thin film integrated circuit generally called.

Next, the manufacturing method will be described. Here, a process of manufacturing an N-type TFT on a glass substrate will be described.

First, a base film 102 made of silicon oxide having a thickness of about 200 nm is formed on a glass substrate 101 by, for example, a sputtering method. This silicon oxide film is
It is provided to prevent diffusion of impurities from the glass substrate 101.

Next, as shown in FIG.
An intrinsic (I-type) amorphous silicon film (a-Si film) 103 having a thickness of 100 nm, for example, 80 nm is formed, and a thickness of 20 to 150 is continuously formed thereon without being exposed to the air.
A silicon oxide film having a thickness of 100 nm in this case is formed as the gate insulating film 104. By continuously forming the semiconductor layer and the gate insulating film without exposing the semiconductor layer to the air in this manner, the interface between the semiconductor layer and the gate insulating film can be kept clean. It leads to performance improvement. It is more preferable that the continuous formation of the semiconductor layer and the gate insulating film can be performed without breaking vacuum.

For example, as a method for continuously forming a semiconductor layer and an insulating film without taking them out to the atmosphere, a plasma C
The VD method is generally used, and other examples include a sputtering method, a photo CVD method, and an electron beam evaporation method. In this embodiment, the a-Si film and the silicon oxide film are continuously formed by the RF plasma CVD method. For the formation of the a-Si film, silane (SiH ₄ ) gas is used as a raw material,
Decomposed and deposited at 400 to 400 ° C, preferably 200 to 300 ° C. In addition, TEOS (Te
tra Ethoxy Silan) was used as a raw material, and was decomposed and deposited together with oxygen at a substrate temperature of 150 to 600C, preferably 300 to 450C. Incidentally, the above TEOS is composed of Si atoms, O
It is an organic material that is liquid at room temperature and contains atoms and the like, and is used for forming an interlayer insulating film and the like, and can provide an insulating film having excellent step coverage.

Next, as shown in FIG. 1B, nickel ions 105 were implanted into the gate insulating film 1 by ion implantation.
04 is introduced into the a-Si film 103. The dose of nickel at this time is 1 × 10 ¹¹ to 1 × 10 ¹⁴ atoms.
/ Cm ² . In this embodiment, the accelerating voltage of nickel ions is set to 120 to 200 keV, for example, 160
keV and a dose of 1 × 10 ¹³ atoms / cm ²
As a result, nickel ions 105 were introduced into the a-Si film 103. Then, this is annealed in a hydrogen reducing atmosphere or an inert atmosphere at a heating temperature of 520 to 580 ° C. for several hours to several tens of hours, here at 550 ° C. for 4 hours for crystallization. At this time, the nickel ions 105 implanted into the a-Si film become nuclei, and then nickel serves as a catalyst to promote crystal growth, whereby the a-Si film 103 is effectively crystallized. Thereby, the a-Si film 103 becomes the crystalline silicon film 103a. At the same time, nickel is uniformly diffused in the film, and the nickel concentration in the crystalline silicon film 103a becomes 1.2 × 10 ¹⁸ atoms / cm ³ .

Next, as shown in FIG. 1 (c), unnecessary portions of the crystalline silicon film 103a are removed to perform element isolation, and the active region (source, drain region, and channel region) of the TFT is removed. An island-shaped crystalline silicon film 103b is formed. At this time, the silicon oxide film 104 on the crystalline silicon film 103a is patterned into the same shape as the island-shaped crystalline silicon film 103b.

Subsequently, by the sputtering method,
Aluminum having a thickness of 400 to 800 nm, for example, 600
The film is formed to have a thickness of nm. Then, the gate electrode 106 is formed by patterning the aluminum film. Further, the surface of the aluminum gate electrode 106 is anodized to form an oxide layer 107 on the surface.
(D)).

Here, the anodic oxidation is performed in an ethylene glycol solution containing tartaric acid at 1 to 5%, and the voltage is first increased to 220 V with a constant current, and the state is maintained for one hour to finish the oxidation treatment. The thickness of the obtained oxide layer 107 is 200 nm. Note that the thickness of the oxide layer 107 becomes the length of the offset gate region in a later ion doping process, and thus the length of the offset gate region can be determined in the above anodic oxidation process.

Next, an impurity (phosphorus) is implanted into the active region (crystalline silicon film) 103b by ion doping using the gate electrode 106 and the surrounding oxide layer 107 as a mask. Phosphine (PH ₃ ) is used as the doping gas, the acceleration voltage is 60 to 90 kV, for example, 80 kV, the dose is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² ,
For example, 2 × 10 ¹⁵ cm ⁻² . By this step, the regions 109 and 110 into which the impurities are implanted are formed later by the TFT 10.
And the region 108 into which the impurity masked by the gate electrode 106 and the surrounding oxide layer 107 is not implanted becomes a channel region of the TFT 10 later.

Thereafter, as shown in FIG. 1D, annealing is performed by irradiating a laser beam 115 to activate the ion-implanted impurities, and at the same time, a portion where the crystallinity is degraded in the above-described impurity introducing step is reduced. Improves crystallinity. At this time, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was used as a laser to be used.
Irradiation was performed at an energy density of 150 to 400 mJ / cm ² , preferably 200 to 250 mJ / cm ² . N-type impurity (phosphorus) regions 109, 110 thus formed
Had a sheet resistance of 200 to 800 Ω / □.

Subsequently, a silicon oxide film or a silicon nitride film having a thickness of about 600 nm is formed as the interlayer insulating film 111. When a silicon oxide film is used, if TEOS is used as a raw material and formed by plasma CVD with oxygen, reduced pressure CVD with ozone, or normal pressure CVD, good interlayer insulation with excellent step coverage can be obtained. A film is obtained. In addition, when a silicon nitride film formed by a plasma CVD method using SiH ₄ and NH ₃ as a source gas is used, hydrogen atoms are supplied to the interface between the active region and the gate insulating film, and the dangling bond that deteriorates TFT characteristics is supplied. This has the effect of reducing

Next, a contact hole 111a is formed in the interlayer insulating film 111, and a metal material, for example, a two-layer film of titanium nitride and aluminum is used to form a TFT electrode wiring 11a.
2 and 113 are formed. The titanium nitride film functions as a barrier film for preventing diffusion of aluminum into the source and drain regions. Finally, annealing is performed at 350 ° C. for 30 minutes in a hydrogen atmosphere at 1 atm to complete the TFT 10 shown in FIG.

When the present TFT is used as an element for switching a pixel electrode, one of the electrodes 112 and 113 is connected to a pixel electrode made of a transparent conductive film such as ITO, and a signal is input from the other electrode. When the present TFT is used for a thin film integrated circuit, a contact hole may be formed also on the gate electrode 106 and a necessary wiring may be provided.

The TFT of this embodiment manufactured in this manner
At 10, the field effect transfer is 60-80 cm ² / Vs, S
The values exhibited good characteristics of 0.6 to 0.8 V / digit and a threshold voltage of 2 to 3 V. The S value is a rise coefficient in a sub-threshold region of the TFT. In a graph showing a relationship between the gate voltage VG and the drain current ID, a slope of the graph at a point where the drain current ID rises steeply is expressed by:
This is shown by the change in the gate voltage when the drain current ID increases by one digit. The variation in TFT characteristics within the substrate is ± 12% for the field effect movement and ± 8% for the threshold voltage.
Was within.

As described above, in this embodiment, the amorphous silicon film 103 and the insulating thin film 104 are successively formed on a substrate having a surface region having an insulating property in a state where the outside air is shut off. Can be kept in a clean state.

In addition, a catalyst element (Ni) for promoting crystallization of the amorphous silicon film is introduced into the amorphous silicon film via the insulating thin film by an ion implantation method. Since the introduced amorphous silicon film is crystallized by heating, a high-quality crystalline silicon film 103b having higher crystallinity than that obtained by a normal solid-phase growth method can be formed with good productivity. it can.

Since the crystallinity of the crystalline silicon film 103b is good, the interface between the amorphous silicon film 103 and the gate insulating film 104 thereon is kept clean as described above. Defect levels at the interface can be effectively reduced.

In this case, the heating temperature required for crystallization is 5
The temperature is 80 ° C. or lower, and an inexpensive glass substrate typified by Corning 7059 glass can be used as the substrate.

Further, since the silicon oxide film on the crystalline silicon film 103b is used as the gate insulating film of the MOS transistor, the leakage current of the transistor can be reduced.

Further, the concentration of the catalyst element in the crystalline silicon film in the film is set to 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atoms / cm ^3.
Therefore, the catalytic element can function effectively.

[0090] [Embodiment 2] FIG 2 is a sectional view for explaining a second method of <br/> manufacturing a thin film transistor capacitor according to an embodiment of the present invention, FIG. 2 (a) to FIG. 2 (e The parentheses indicate the method of manufacturing the TFT of this example in the order of steps.

In the figure, reference numeral 200 denotes a semiconductor device of the present embodiment, which has a peripheral drive circuit of an active matrix type liquid crystal display device and a CMOS circuit 20 constituting a general thin film integrated circuit. The circuit of this CMOS configuration is
An N-type TFT 21 and a P-type TFT 22 are connected so that they perform complementary operations.

The N-type TFT 21 and the P-type TFT 22 are each formed on a glass substrate 201 via an insulating base film 202 such as a silicon oxide film. The insulating base film 2
On island 02, island-shaped crystalline silicon films 203n and 203p constituting each of the TFTs 21 and 22 are formed adjacent to each other. The central portions of the crystalline silicon films 203n and 203p are an N channel region 208 and a P channel region 209, respectively. Both sides of the crystalline silicon film 203n are N-type source / drain regions 21 of an N-type TFT.
0,211 and both sides of the crystalline silicon film 203p are P-type source / drain regions 212,213 of a P-type TFT.
It has become.

On the N channel region 208 and the P channel region 209, aluminum gate electrodes 206 and 207 are provided via a gate insulating film 204.
The entire surface of the TFTs 21 and 22 is an interlayer insulating film 214.
N-type TF of the interlayer insulating film 214
A contact hole 214n is formed in a portion corresponding to the source and drain regions 210 and 211 of T21, and a contact hole 214p is formed in a portion of the interlayer insulating film 214 corresponding to the source and drain regions 212 and 213 of the P-type TFT 22. Is formed. And the N-type TFT 21
Are connected to the electrode wirings 215 and 216 through the contact holes 214n. The source / drain regions 212 and 213 of the P-type TFT 22 are connected to the contact holes 214.
They are connected to the electrode wirings 216 and 217 via p.

In this embodiment, the crystalline silicon films 203n and 203p contain a catalyst element (Ni) that promotes crystallization of the amorphous silicon film by heat treatment, and the crystal grains in the films are substantially single. It is made of a needle-like crystal or a columnar crystal in a crystalline state.

Next, the manufacturing method will be described. Here, a process for manufacturing a circuit having the above CMOS structure on a glass substrate will be described.

First, a base film 202 made of silicon oxide having a thickness of about 100 nm is formed on a glass substrate 201 by, for example, a sputtering method. Next, by plasma CVD, an intrinsic (I-type) amorphous silicon film (a-Si film) 203 having a thickness of 25 to 100 nm, for example, 50 nm,
A silicon oxide film 204 having a thickness of 20 to 150 nm, here 100 nm, is continuously formed (FIG. 2A).

Next, as shown in FIG. 2B, nickel ions 205 were implanted into the gate insulating film 2 by ion implantation.
04 is introduced into the a-Si film 203. At this time, the dose of nickel was 5 × 10 ¹² atoms / cm ² , and the acceleration voltage was 140 keV. Then, this is heated at a heating temperature of 520 under a hydrogen reducing atmosphere or an inert atmosphere.
~ 580 ° C for several hours to tens of hours, specifically 550 ° C
For 6 hours for crystallization.

At this time, nickel ions 205 implanted in the a-Si film become nuclei, and then nickel acts as a catalyst to promote crystal growth, whereby the a-Si film 203 is effectively crystallized. Thus, the a-Si film 203 becomes a crystalline silicon film 203a. The nickel concentration in the crystalline silicon film 203a is 1 × 10 ¹⁸ atoms / cm ³ .
Subsequently, the crystalline silicon film 203a is irradiated with a laser beam to increase the crystallinity of the crystalline silicon film 203a. At this time, a XeCl excimer laser (wavelength 308 nm, pulse width 40 nsec) was used as the laser light. The irradiation conditions of the laser beam are as follows.
0 to 450 ° C, for example, 400 ° C, and an energy density of 200 to 400 mJ / cm ² , for example, 300 mJ / c.
Irradiation at m ² .

Thereafter, as shown in FIG.
The crystalline silicon film to be the active regions (element regions) 203n and 203p of the FT is left, and the other regions are removed by etching to perform element isolation. At this time, the silicon oxide film 204 on the crystalline silicon film becomes an island-like crystalline silicon film 203.
It is patterned into the same shape as n, 203p.

Subsequently, as shown in FIG. 2D, an aluminum (containing 0.1 to 2% silicon) having a thickness of 400 to 800 nm, for example, 500 nm is formed by a sputtering method, and the aluminum film is patterned. Thus, gate electrodes 206 and 207 are formed.

Next, an impurity (phosphorus) is implanted into the active region 203n using the gate electrode 206 as a mask, and an impurity (boron) is implanted into the active region 203p using the gate electrode 207 as a mask by ion doping. At this time, phosphine (PH ₃ ) is used as a doping gas.
And using diborane (B ₂ H _6), in the former case, the acceleration voltage of 60～90KV, for example, a 80 kV, in the latter case 40KV～80kV, for example, a 65 kV, the dose is 1 × 10 ¹⁵ ~8 × 10 ¹⁵ cm ^-2 , eg phosphorus 2
× 10 ¹⁵ cm ^-2 and boron is 5 × 10 ¹⁵ cm ^-2 .

By this step, the gate electrodes 206 and 20
The region masked by the mask 7 and not doped with impurities is
Channel regions 208 and 209. At the time of doping, each element is selectively doped by covering a region not requiring doping with a photoresist. As a result, the N-type impurity regions 210 and 211,
P-type impurity regions 212 and 213 are formed, and FIG.
As shown in (d), an N-channel type TFT (NTFT) 2
1 and a P-channel TFT (PTFT) 22 can be formed.

Thereafter, as shown in FIG. 2D, annealing is performed by irradiating a laser beam to activate the ion-implanted impurities. As a laser beam, a XeCl excimer laser (wavelength 308 nm, pulse width 40 ns)
Using c), the laser beam was irradiated at an energy density of 250 mJ / cm ² for two shots per location.

Subsequently, as shown in FIG.
A silicon oxide film having a thickness of 00 nm is formed as an interlayer insulating film 214 by a plasma CVD method, and contact holes 214n and 214p are formed therein. 216 and 217 are formed. Finally, annealing is performed at 350 ° C. for 30 minutes under a hydrogen atmosphere at 1 atm to complete the N-type and P-type TFTs 21 and 22.

The CMO fabricated according to the above embodiment
In the S structure circuit, the field effect mobility of each TFT is 120 to 150 cm ² / Vs for NTFT, and PTFT
Is as high as 100 to 130 cm ² / Vs, and the threshold voltage is NT.
The FT showed very good characteristics of 1.5 to 2 V and the PTFT of -2 to -3 V.

In the second embodiment having such a structure, the crystalline silicon film obtained by the heat treatment of the amorphous silicon film is irradiated with a laser beam or an intense light. In addition to the effects of the first embodiment, the crystallinity of the silicon film constituting the active region can be further improved, and the field effect mobility of the carrier in the active region can be further improved.

[0107] [Embodiment 3] FIG. 3 is a sectional view for explaining a third method of <br/> manufacturing a thin film transistor capacitor according to an embodiment of the present invention, FIGS. 3 (a) to FIG. 3 (e The parentheses indicate the method of manufacturing the TFT of this example in the order of steps.

In the figure, reference numeral 300 denotes a semiconductor device having a thin film transistor (TFT) 30.
Is the TFT 10 in the semiconductor device of the first embodiment.
It has exactly the same cross-sectional structure. In this example,
The first embodiment is characterized in that the silicon oxide film as the base insulating film 302, the semiconductor layer 303 as the active region, and the silicon oxide film 304 as the gate insulating film are formed continuously without being exposed to the air. It is different from the example. Note that FIG.
In this embodiment, the components of this embodiment with reference numerals in the 300's correspond to the components with reference numerals in the 100's in the first embodiment shown in FIG.

Next, the manufacturing method will be described. Also in the present embodiment, a process for manufacturing an N-type TFT 30 on a glass substrate will be described as an example.

First, as shown in FIG. 3A, a thickness of 100 to 300 nm, for example, 200 n
m of silicon oxide, and a thickness of 25
An intrinsic (I-type) amorphous silicon film (a-Si film) 303 having a thickness of 20 to 15 nm, for example, 80 nm;
A silicon oxide film with a thickness of 0 nm, here 100 nm, is continuously formed as the gate insulating film 304. This step is performed without exposing to the atmosphere. By continuously forming the base insulating film / semiconductor layer / gate insulating film in this manner, the interface between the base insulating film / semiconductor layer and the interface between the semiconductor layer / gate insulating film can be kept clean.

Here, the continuous formation of the semiconductor layer / gate insulating film mainly leads to improvement of ON characteristics such as improvement of reliability and performance of a TFT completed later. Further, by continuously forming the base insulating film / semiconductor layer, it is possible to improve the OFF characteristics such as a reduction in leak current.

In this example, the silicon oxide film / a-Si film / silicon oxide film was continuously formed by RF plasma CVD. For forming the a-Si film, a silane (SiH ₄ ) gas is used as a raw material, and the substrate temperature is 150 to ₄₀₀ ° C., preferably 2
Decomposed and deposited at 00 to 300 ° C. In forming the silicon oxide film, both the base insulating film and the gate insulating film are made of TE.
Substrate temperature 150 to 600 with OS as raw material together with oxygen
° C, preferably 300 to 450 ° C. The underlying silicon oxide film 302 also functions as a buffer layer for preventing diffusion of impurities from the glass substrate.

Next, as shown in FIG. 3 (b), nickel ions 305 are deposited on the gate insulating film 3 by ion implantation.
04 is introduced into the a-Si film 303. The dose of nickel at this time is 1 × 10 ¹¹ to 1 × 10 ¹⁴ atoms.
/ Cm ² . In this embodiment, the accelerating voltage of nickel ions is set to 120 to 200 keV, for example, 160
keV and a dose of 1 × 10 ¹³ atoms / cm ²
As a result, nickel ions 305 were introduced into the a-Si film 303. Then, this is annealed in a hydrogen reducing atmosphere or an inert atmosphere at a heating temperature of 520 to 580 ° C. for several hours to several tens of hours, and at 550 ° C. for 4 hours for crystallization. At this time, the nickel ions 305 implanted into the a-Si film
Becomes a nucleus, and then nickel acts as a catalyst to effectively crystallize the a-Si film 303. Thereby, a crystalline silicon film 303a is formed. At the same time, nickel is diffused uniformly in the film, and the nickel concentration in the crystalline silicon film 303a becomes 1.2 × 10 ¹⁸ atoms / cm ³ .

Next, as shown in FIG. 3C, an unnecessary portion of the crystalline silicon film 303a is removed to perform element isolation, and later to become an active region (source / drain region, channel region) of the TFT. An island-shaped crystalline silicon film 303b is formed. At this time, the silicon oxide film 304 on the crystalline silicon film 303a is patterned into the same shape as the island-shaped crystalline silicon film 303b.

Subsequently, by a sputtering method,
An aluminum film having a thickness of 400 to 800 nm, for example, 600 nm is formed. Then, the gate electrode 306 is formed by patterning the aluminum film. Further, the surface of the aluminum electrode is anodized to form an oxide layer 307 on the surface (FIG. 3D). The anodic oxidation here is performed in an ethylene glycol solution containing tartaric acid at 1 to 5%. The voltage is first increased to 220 V at a constant current, and the state is maintained for 1 hour, thereby completing the process. The thickness of the obtained oxide layer 307 is 200 nm. Note that the thickness of the oxide layer 307 becomes the length of the offset gate region in a later ion doping process, and thus the length of the offset gate region can be determined in the anodic oxidation process.

Next, impurities (phosphorus) are implanted into the active region by ion doping using the gate electrode 306 and the oxide layer 307 around the gate electrode 306 as a mask. Phosphine (PH ₃ ) is used as the doping gas, the acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose is 1 × 10
¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 2 × 10 ¹⁵ cm ⁻² .

In this step, the regions 309 and 310 into which the impurities are implanted later become the source and drain regions of the TFT, and the gate electrode 306 and the oxide layer 307 around it are formed.
The region 308 which is masked and is not implanted with impurities becomes a channel region of the TFT later.

Thereafter, as shown in FIG. 3D, annealing is performed by irradiating a laser beam to activate the ion-implanted impurities and, at the same time, to crystallize the portion where the crystallinity has deteriorated in the above-described impurity introducing step. Improve sex. On this occasion,
As a laser to be used, a KrF excimer laser (wavelength: 248 nm, pulse: 20 nsec) is used, and the energy density is 150 to 400 mJ / cm ² , preferably 200.
Irradiation was performed at ２５０250 mJ / cm ² . The sheet resistance of the N-type impurity (phosphorus) regions 309 and 310 thus formed was 200 to 800 Ω / □.

Subsequently, a silicon oxide film or a silicon nitride film having a thickness of about 600 nm is formed as the interlayer insulating film 311. When a silicon oxide film is used, if TEOS is used as a raw material and formed by plasma CVD with oxygen, reduced pressure CVD with ozone, or normal pressure CVD, good interlayer insulation with excellent step coverage can be obtained. A film is obtained. In addition, when a silicon nitride film formed by a plasma CVD method using SiH ₄ and NH ₃ as a source gas is used, hydrogen atoms are supplied to the interface between the active region and the gate insulating film, and the dangling bond that deteriorates TFT characteristics is supplied. Has the effect of reducing

Next, a contact hole 311 a is formed in the interlayer insulating film 311, and the electrode wiring 31 of the TFT is formed of a metal material, for example, a multilayer film of titanium nitride and aluminum.
2, 313 are formed. Finally, annealing is performed at 350 ° C. for 30 minutes in a hydrogen atmosphere at 1 atm, and FIG.
Is completed.

When the present TFT is used as an element for switching a pixel electrode, one of the electrodes 312 and 313 is connected to a pixel electrode made of a transparent electrode film such as ITO, and a signal is input from the other electrode. When the present TFT is used for a thin film integrated circuit, a contact hole may be formed also on the gate electrode 306 and a necessary wiring may be provided.

The NTF manufactured according to the above embodiment
T exhibited good characteristics such as a field effect mobility of 60 to 80 cm ² / Vs, an S value of 0.6 to 0.8 V / digit, and a threshold voltage of 2 to 3 V. The variation in TFT characteristics within the substrate was within ± 12% in field effect mobility and within ± 8% in threshold voltage. The leakage current in question is 2-6 × 10 ^-12 A /
cm ² , which was a uniform digit reduction compared to the case where the base insulating film / semiconductor layer was not continuously formed.

In particular, in the third embodiment, by continuously forming three layers of the base insulating film / semiconductor layer / gate insulating film, it is possible not only to improve the ON characteristics but also to reduce the leak current in the OFF region. did it.

In the above description, three embodiments have been described as embodiments of the present invention. However, the present invention is not limited to the above embodiments, and various modifications based on the technical idea of the present invention are possible. Is possible.

For example, in each of the above embodiments, nickel was used as a catalyst element for promoting crystallization of the amorphous silicon film. However, in addition to nickel, cobalt, palladium, platinum, copper, silver, gold, indium, Similar effects can be obtained by using tin, antimony, or aluminum.

Further, in the second embodiment, as a means for promoting the crystallinity of the crystalline silicon film, a heating method by irradiating an excimer laser which is a pulse laser is used, but other lasers (for example, a continuous oscillation Ar laser) may be used. Similar processing is possible.

In the heat treatment, infrared light or light emitted from a flash lamp (strong light) is used instead of laser light.
So-called RTA (Rapid Thermal Annealing) or RT, in which the sample is heated to 1000 to 1200 ° C. (temperature of the silicon monitor) in a short time to heat the sample.
Heat treatment called P (rapid thermal process) may be used.

Further, according to the present invention, in addition to the active matrix type substrate for liquid crystal display, for example, a contact type image sensor, a thermal head having a built-in driver, an organic
Optical writing element and display element with built-in driver using L (Electroluminescence) element as light emitting element, 3D I
C is applicable. Here, the organic EL element is
An electroluminescent device using an organic material as a light emitting material. By applying the present invention, high performance such as high speed and high resolution of these elements is realized.

Further, the present invention is not limited to the thin film transistors described in the above embodiments, but is widely applicable to all semiconductor processes using MOS transistors.

[0130]

As described above, in the semiconductor device according to the present invention,
According to the manufacturing method, the surface area is
Silicon film and insulating film on substrate with insulating region
Since thin films are formed successively, clean the interface between these films.
Can be kept in a state.

[0131]

A catalyst element for promoting crystallization of the amorphous silicon film is introduced into the amorphous silicon film through the insulating thin film by an ion implantation method. Since the crystalline silicon film is crystallized by heating, a high-quality crystalline silicon film having higher crystallinity than the crystallinity obtained by the ordinary solid phase growth method,
It can be formed with high productivity.

At this time, the heating temperature required for crystallization is 5
The temperature is 80 ° C. or lower, and an inexpensive glass substrate typified by Corning 7059 glass can be used as the substrate.

Further, since the amorphous silicon film into which the catalytic element is introduced is crystallized by heating, the crystallized silicon film is irradiated with laser light or strong light.
The crystallinity of the crystalline silicon film forming the active region can be further increased, and the field effect mobility of carriers in the active region can be further improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a TFT according to a first embodiment of the present invention and a method for manufacturing the same.

FIG. 2 is a cross-sectional view illustrating a TFT according to a second embodiment of the present invention and a method for manufacturing the same.

FIG. 3 is a cross-sectional view illustrating a TFT according to a third embodiment of the present invention and a method for manufacturing the same.

[Explanation of symbols]

10, 21, 30 N-type TFT 20 CMOS circuit 22 P-type TFT 100, 200, 300 Semiconductor device 101, 201, 301 Glass substrate 102, 202, 302 Base insulating film 103, 203, 303 Amorphous silicon film 103a, 203a , 303a Crystalline silicon film 103b, 203n, 203p, 303b Active region 104, 204, 304 Gate insulating film 105, 205, 305 Catalyst element 106, 206, 207, 306 Gate electrode 107, 307 Anodized layer 108, 208, 209 , 308 Channel regions 109, 110, 210, 211, 212, 213, 3
09, 310 Source / drain regions 111, 214, 311 Interlayer insulating layers 111a, 214n, 214p, 311a Contact holes 112, 113, 215, 216, 217, 312, 3
13 electrode wiring

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/20 H01L 21/265 H01L 21/324 H01L 21/336

Claims (8)

(57) [Claims] In a state in which 1. A blocked outside air, and a step in which the surface region is formed by continuing the amorphous silicon film and an insulating thin film on a substrate having an insulating property, the amorphous silicon film, amorphous A step of introducing a catalyst element for promoting crystallization of the silicon film through the insulating thin film by an ion implantation method, and a step of crystallizing the amorphous silicon film into which the catalyst element has been introduced by heat treatment. A method for manufacturing a semiconductor device. 2. A step of continuously forming an amorphous silicon film and an insulating thin film on a substrate having a surface region having an insulating property in a state in which outside air is blocked; Introducing a catalyst element that promotes crystallization of the silicon film through the insulating thin film by an ion implantation method, crystallizing the amorphous silicon film into which the catalyst element has been introduced by heating, Irradiating the converted silicon film with laser light or intense light to perform crystal processing. 3. A process according to claim 1 or 2 comprising the step of forming a gate insulating film of the MOS transistor from said insulating thin film
The manufacturing method of the semiconductor device described in the above. 4. A step of forming three successive layers of a first insulating thin film, an amorphous silicon film, and a second insulating thin film on a substrate in a state in which outside air is shut off; Introducing a catalyst element that promotes crystallization of the amorphous silicon film through the second insulating thin film by an ion implantation method; and heat-treating the amorphous silicon film into which the catalyst element has been introduced. And a step of crystallizing the semiconductor device. 5. A step of continuously forming three layers of a first insulating thin film, an amorphous silicon film, and a second insulating thin film on a substrate in a state in which outside air is shut off; Introducing a catalyst element that promotes crystallization of the amorphous silicon film through the second insulating thin film by an ion implantation method; and heat-treating the amorphous silicon film into which the catalyst element has been introduced. A method of manufacturing a semiconductor device, comprising: crystallizing a silicon film by irradiating the crystallized silicon film with laser light or strong light. 6. The method of claim 4 including forming a gate insulating film of the MOS transistor from said second insulating film
Or the method of manufacturing a semiconductor device according to 5 . 7. A dose for introducing said catalyst element into said amorphous silicon film by ion implantation is 1 × 10 ^11.
Claims 1 and 2, which are 1 × 10 ¹⁴ atoms / cm ² .
6. The method for manufacturing a semiconductor device according to any one of 4 and 5. 8. Ni, Co, Pd, P as a catalyst element
3. The method according to claim 1, wherein one or more of t, Cu, Ag, Au, In, Sn, Al and Sb are used.
6. The method for manufacturing a semiconductor device according to any one of 4 and 5.