KR100256912B1 - Semiconductor circuit, semiconductor device and manufacturing method thereof - Google Patents

Abstract

The semiconductor circuit of the present invention has a CMOS structure including an n-channel transistor and a p-channel transistor each having an active region formed of a crystalline silicon film on a substrate having an insulating surface. The n-channel transistor and the p-channel transistor have complementary CMOS structures. The p-channel transistor includes a catalytic element for improving the crystallinity of the amorphous film in the active region, and the concentration of the catalytic element in the active region of the n-channel transistor is lower than that in the active region of the p-channel transistor.

Description

Semiconductor circuit, semiconductor device and manufacturing method thereof

FIG. 1 is a plan view for explaining an outline of a manufacturing process of a TFT of the first embodiment; FIG.

2A to 2F are sectional views taken on line A-A 'of FIG. 1 for explaining a manufacturing process of the TFT of the first embodiment.

FIG. 3 is a plan view for explaining an outline of a manufacturing process of the TFT of the second embodiment; FIG.

4A to 4E are sectional views taken along the line B-B 'in FIG. 3 for explaining a manufacturing process of the TFT of the second embodiment.

FIG. 5 is a plan view for explaining the outline of a manufacturing process of the TFT of the third embodiment; FIG.

6A to 6E are cross-sectional views taken along line C-C 'of FIG. 5 for explaining a manufacturing process of the TFT of the third embodiment.

7A and 7B are graphs showing the relationship between the gate voltage and the drain current of the TFT of the present invention.

FIG. 8 is a view for explaining an inverter circuit used in the present invention; FIG.

9A and 9B are graphs showing the relationship between the gate voltage and the drain current of a conventional TFT.

DESCRIPTION OF THE REFERENCE NUMERALS

101: glass organ 102: bottom membrane

103: a-Si film 104: mask film

105: catalytic element 107: laser light

108: gate insulating film 109n, 109p: gate electrode

110n, 110p: oxide layer 111n, 111p: channel region

116: interlayer insulating film 117: electrode

The present invention relates to a semiconductor circuit composed of a MOS transistor such as a thin film transistor (hereinafter referred to as TFT) provided on a substrate having an insulating surface, and a manufacturing method thereof. The semiconductor circuit of the present invention can be employed in a semiconductor device such as a thin film integrated circuit and a three-dimensional integrated circuit using a TFT applicable to a driver, an image sensor, etc. of an active matrix liquid crystal display device. The present invention also relates to a semiconductor device including such a semiconductor circuit and a manufacturing method thereof.

In recent years, in order to realize an active matrix liquid crystal display device, a high-speed and high-resolution close-contact type image sensor, or a three-dimensional IC, attempts have been made to form a high-performance semiconductor device on an insulating substrate such as glass or on an insulating film. Particularly, in the active matrix liquid crystal display device, driver monolithic technology is actively developed. According to this driver monolithic technology, a driver as a semiconductor element for driving a matrix portion including a plurality of pixels constituting a display portion is formed on the same substrate as the matrix portion.

A thin film of silicon is generally used for a semiconductor layer of a semiconductor circuit included in the semiconductor device. Thin-film silicon semiconductors are generally classified into two types, those formed from amorphous silicon (hereinafter referred to as a-Si) and those formed from silicon with crystallinity. Polysilicon, microcrystalline silicon, and the like are known as silicon having crystallinity.

The a-Si semiconductor is most commonly used because it can be produced at a low temperature and can be produced relatively easily by the vapor phase method and is excellent in mass productivity. However, the a-Si semiconductor has a problem of lower conductivity than a silicon semiconductor having crystallinity. For this reason, in order to obtain high-speed characteristics, it is strongly desired to establish a manufacturing method of a semiconductor circuit formed of crystalline silicon.

As the method for obtaining the silicon semiconductor, the following three methods are known.

(1) The first method is a method of directly forming a film having crystallinity at the time of film formation.

(2) In the second method, the amorphous film is formed first, and then the film is made crystalline by laser energy.

(3) The third method is to first form an amorphous film and then to apply heat energy to the film so that the film has crystallinity.

However, according to the first method, crystallization progresses at the same time as the film forming step, so that it is inevitable to form a silicon film having a large thickness in order to obtain crystalline silicon having a large grain size. Therefore, it is technically difficult to uniformly form a film having satisfactory semiconductor characteristics over the entire substrate. In addition, since the film-forming temperature is as high as 600 DEG C or more, an inexpensive glass substrate having a low glass distortion point can not be used, which is disadvantageous in cost.

For this reason, research and development on the second and third methods are currently focused. In the second method, for example, as described in Japanese Patent Application Laid-Open No. 6-252398, an XeCl excimer laser light having a wavelength of 308 nm is irradiated to an a-Si film to melt only the silicon film in a short time without damaging the glass substrate , Which crystallizes in the course of its solidification. In particular, in Japanese Patent Application Laid-Open No. 6-252398, it is noted that the optimum value of the irradiation laser energy is different between the n-channel TFT and the p-channel TFT. By separating the laser irradiation process for each TFT, Energy. That is, since one TFT is irradiated while masking the regions of the TFTs of different types, one laser irradiation step is required for each of the TFTs.

The third method is advantageous in that the semiconductor is relatively easily formed on the substrate having a larger area than the first and second methods. However, this third method requires heat treatment at a high temperature of 600 DEG C or more over several tens of hours for crystallization. Therefore, in the third method, it is necessary to solve the conflicting problem of lowering the heat treatment temperature and crystallizing in a short time in order to use an inexpensive glass substrate and to improve the throughput.

Methods for solving the problem of heat treatment using the third method are described in Japanese Patent Laid-Open Nos. 6-244103 and 6-244104. According to these methods, by using the catalytic element for promoting the crystallization of the a-Si film, the heating temperature is lowered and the processing time is shortened. Specifically, a small amount of a metal element such as nickel, palladium, or lead is introduced into the surface of the a-Si film. Thereafter, the a-Si film is heat-treated at 550 DEG C for about 4 hours to complete the crystallization of the a-Si film. Currently, CORNING 7059 glass manufactured by Corning Inc. used in an active matrix liquid crystal display device has a glass distortion point of 593 캜. Therefore, in consideration of the large-sized substrate, the above-mentioned Japanese Patent Application Laid-Open No. 6-244103 is very effective.

The crystallization mechanism at low temperature is as follows. First, the generation of crystal nuclei in the nucleus of a nitrogen element occurs early. Thereafter, the metal element acts as a catalyst to promote crystal growth, and the crystallization proceeds rapidly. In this sense, these metal elements are referred to as catalytic elements. The crystalline silicon film obtained by crystallizing the a-Si film by a conventional solid-phase growth method has a twin crystal structure. On the other hand, the crystalline silicon film obtained by promoting crystallization by the catalytic element is composed of a plurality of columnar crystals, and the inside of each columnar crystal is in an ideal single crystal state.

Further, in Japanese Patent Application Laid-Open No. 6-244104, a catalyst element is selectively introduced into a part of the a-Si film and heated. As a result, only the region into which the catalytic element is introduced is selectively crystallized, leaving the other portion of the a-Si film in the amorphous state. Further, by extending the heating time, crystal growth is performed in the lateral direction (direction parallel to the substrate) from the region where the catalytic element is selectively introduced. In the transverse direction crystal growth region, columnar crystals having almost the same growth direction are adjacent to each other. Accordingly, the regions have more satisfactory crystallinity as compared with a region where crystal nuclei are randomly generated by directly introducing the catalytic element. Therefore, by using the crystalline silicon film obtained by the lateral crystal growth as the active region of the semiconductor device, the semiconductor can have higher performance.

However, various methods for producing a crystalline silicon film have been invented and studied, but all of the above requirements are unsatisfactory. For example, in a driver monolithic active matrix type liquid crystal display device, when the driver is composed of a single channel structure including only an n-channel TFT, the power consumption and the heat generation amount corresponding thereto increase. Therefore, it is effective to construct a driver with CMOS to reduce power consumption and heat generation.

However, in the p-channel TFT and the n-channel TFT constituting the CMOS circuit, the p-channel TFT has a much poorer performance than the n-channel TFT. Further, as compared with the MOS transistor formed on the semiconductor substrate, the channel region in the TFT is formed of an incomplete crystalline silicon film, so that the performance difference between the p-channel TFT and the n-channel TFT becomes more remarkable. Particularly notable is the difference between the field effect mobility and the threshold voltage, which causes problems. Conventionally, when the n-channel TFT is formed of the same material as the p-channel TFT, the p-channel TFT can attain about 1/3 of the field effect mobility of the n-channel TFT. Further, for the threshold voltage, the n-channel TFT is stabilized at about 2V to 3V. On the other hand, the p-channel TFT is stabilized at -7 V to -12 V, which is extremely large in absolute value and does not stabilize.

In such a case, the problems that may occur in the semiconductor circuit can be considered by taking an inverter having the simplest CMOS configuration as an example. 8 shows a circuit of the inverter. When a high output signal (hereinafter referred to as H signal) is inputted to the input terminal 803, the n-channel TFT 801 is turned on and a low output signal (hereinafter referred to as L signal) from the ground 806 And is output from the output terminal 804. When the L signal is input to the input terminal 803, the p-channel TFT 802 is turned on, and the H signal from the V _DD 805 is outputted from the output terminal 804.

Next, Figs. 9A and 9B show the relationship between the gate voltage V _G and the drain current I _D in general n-channel TFT and p-channel TFT. The drain current I _{D on the} vertical axis is indicated on a log scale. The threshold voltage V _TH of the n-channel TFT shown in Fig. 9A is about 2V, while the threshold voltage V _TH of the p-channel TFT shown in Fig. 9B is about -8V. Particularly, it is noticed that the gate voltage V _G of each TFT rises in the OFF region. This is because the channel layer of the TFT is formed of an incompletely crystalline silicon film, and when the gate voltage V _G is turned off and the voltage is concentrated at the junction at the drain end, the annealing of the carrier through the crystal defect (trap level) Is understood to occur. Therefore, in the TFT including the channel layer formed of the crystalline silicon film on the insulating substrate, the increase of the leakage current in the OFF region is inevitable to some extent.

When the inverter of Fig. 8 is composed of n-channel and p-channel TFTs having the TFT characteristics shown in Figs. 9A and 9B, the gate voltage for driving the TFT, that is, the input voltage to the input terminal 803, The voltage V _H for driving and the voltage V _L for driving the p-channel TFT are expressed by the following equations.

(N) represents the n-channel TFT side, and (P) represents the p-channel TFT side.

ΔV _TH representing the TFT between the V _H non-uniformity, in the n-channel TFT 1V, the p-channel TFT in a 3V, and when the V _ON margin of the n-channel and p-channel TFT both to 3V, V _H = 6V and V _L Is -14V, which are very large values. As shown in Fig. 9, an inverter formed of a typical CMOS TFT having TFT characteristics has a large V _L due to a characteristic defect of a p-channel TFT, thereby increasing power consumption. As a result, the advantage of the CMOS is reduced, and when V _L is input to the input terminal 803, a large negative voltage is applied to the gate electrode of the n-channel TFT 801, thereby increasing the leakage current. Although the field effect mobility in the above circuit is not considered, when the field effect mobility is insufficient, the TFT speed becomes low at a high frequency, and high frequency driving can not be performed.

In the above-mentioned Japanese Patent Application Laid-Open No. 6-252398, the n-channel TFT and the p-channel TFT have different optimal irradiation energy and are crystallized separately by the laser annealing method. However, the performance of the p-channel TFT can not be greatly improved, and this technique can not realize a CMOS circuit having sufficient characteristics without combining other technologies. This is because the above-mentioned Japanese Patent Application Laid-Open No. 6-252398 focuses on only the field effect mobility, which is one of the TFT characteristics, and the irradiation energy of the laser light is set to obtain the maximum value. Since the maximum value is different between the p-channel TFT and the n-channel TFT, a separate laser annealing process is required. However, another important point, namely the reduction of the threshold voltage of the p-channel TFT, is not considered in this technique. Further, according to the experiment of the inventors of the present invention, when the laser annealing changes the power to some extent, the field effect mobility of the TFT largely changes but the threshold voltage hardly changes. As apparent from these results, Japanese Patent Application Laid-Open No. 6-252398 has realized the optimization of the n-channel TFT and the p-channel TFT in terms of the field effect mobility. However, in all aspects, the semiconductor circuit having the high- I could not.

According to one aspect of the present invention, a semiconductor circuit has a CMOS structure including an n-channel transistor and a p-channel transistor each having an active region formed of a crystalline silicon film on a substrate having an insulating surface. The n-channel transistor and the p-channel transistor have complementary CMOS structures. Wherein the p-channel transistor includes a catalytic element for improving the crystallinity of the amorphous film in the active region, and the concentration of the catalytic element in the active region of the n-channel transistor is higher than that in the active region of the p- low.

In one embodiment of the present invention, the concentration of the catalytic element in the active region of the p-channel transistor is about 1 × 10 ¹⁵ atom / cm 3 to 1 × 10 ¹⁹ atom / cm 3.

In another embodiment of the present invention, the concentration of the catalytic element in the active region of the p-channel transistor is about 1 x 10 ¹⁶ atoms / cm 3 to 1 x 10 ¹⁸ atoms / cm 3.

In another embodiment of the present invention, the concentration of the catalytic element in the active region of the n-channel transistor is less than 1 x 10 ¹⁵ atoms / cm 3.

In another embodiment of the present invention, the concentration of the catalytic element is defined as the minimum value obtained by two-way on-mass spectrometry.

According to another aspect of the present invention, a semiconductor circuit includes an n-channel transistor and a p-channel transistor each having an active region formed of a crystalline silicon film on a substrate having an insulating surface. Wherein the active region of the p-channel transistor is formed of a crystalline silicon film that is crystallized by a catalytic element, and the active region of the n-channel transistor is a crystalline silicon that is crystallized by solid- Film.

According to another aspect of the present invention, a semiconductor circuit includes an n-channel transistor and a p-channel transistor, each of which has an active region formed of a silicon film having crystallinity on a substrate having an insulating surface. The active region of the p-channel transistor is formed of a crystalline silicon film that is crystallized by a catalytic element, and the active region of the n-channel transistor is formed of a crystalline silicon film that is crystallized by laser light or strong light irradiation .

In one embodiment of the present invention, the catalytic element includes at least one element selected from the group consisting of Ni, Co, Fe, Pd, Pt, Cu, Ag, Au, In, Sn, .

In another embodiment of the present invention, the semiconductor device comprises any one of the semiconductor circuits.

A method of manufacturing a semiconductor circuit according to another aspect of the present invention includes the steps of forming an amorphous silicon film on a substrate having an insulating surface, selectively introducing a catalyst element for promoting crystallization of the amorphous silicon film into the amorphous silicon film A step of forming an amorphous silicon film region into which the catalytic element is introduced by performing an annealing process to obtain a crystalline silicon film region; a step of forming a p-channel transistor using the crystalline silicon film region; And forming an n-channel transistor using the region.

A method of manufacturing a semiconductor circuit according to another aspect of the present invention includes the steps of forming an amorphous silicon film on a substrate having an insulating surface, selectively introducing a catalyst element for promoting crystallization of the amorphous silicon film into the amorphous silicon film And the amorphous silicon film in the periphery of the crystallized amorphous silicon film region is subjected to crystal growth in a direction substantially parallel to the surface of the substrate, A step of obtaining a silicon film region, a step of forming a p-channel transistor using the crystalline silicon film region, and a step of forming an n-channel transistor using an area not crystallized by the catalytic element.

In one embodiment of the present invention, a method of manufacturing a semiconductor circuit is characterized in that after the annealing process is performed to obtain the crystalline silicon film region, another annealing process is performed at a high temperature to form a region which is not crystallized by the catalytic element Forming a p-channel transistor by using the crystalline silicon film region obtained by performing the annealing process; forming a p-channel transistor by nucleating a region not crystallized by the catalytic element and using the solid-phase crystallized region Thereby forming an n-channel transistor.

In another embodiment of the present invention, a method of manufacturing a semiconductor circuit includes the steps of: performing the annealing process to obtain the crystalline silicon film region; thereafter irradiating laser light or strong light to crystallize a region not crystallized by the catalytic element A step of forming a p-channel transistor using the crystalline silicon film region obtained by performing the annealing process, a step of forming a p-channel transistor by using a region crystallized by irradiating laser light or strong light to a region not crystallized by the catalytic element, And forming a channel transistor.

In another embodiment of the present invention, a method of manufacturing a semiconductor circuit includes the steps of: selectively crystallizing a region containing the catalytic element; spontaneously nucleating a region where the crystallization by the catalytic element is insufficient; And irradiating the crystallized region with laser light or strong light to improve the crystallinity of the crystallized region.

In another embodiment of the present invention, a method of manufacturing a semiconductor device is provided.

Accordingly, the present invention provides: (1) a semiconductor circuit and a semiconductor device including a p-channel transistor which can use an inexpensive glass substrate, improve the throughput, and significantly improve the performance of the n-channel transistor, (2) A method of manufacturing such a semiconductor circuit and a semiconductor device.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

According to the present invention, a semiconductor device or a semiconductor circuit includes an n-channel transistor and a p-channel transistor on an insulating substrate. Wherein the active region of the p-channel transistor includes a predetermined amount of catalytic element for promoting crystallization of the a-Si film, and the concentration of the catalytic element in the active region of the n-channel transistor is larger than the concentration of the catalytic element in the active region of the p- It is higher than the concentration of element.

The present inventor has also developed a crystallization technique for the a-Si film described in Japanese Patent Application Laid-Open Nos. 6-244103 and 6-244104. As a result, it has been found that the effect is greatly different between the n-channel TFT and the p-channel TFT. 7A and 8B show the relationship between the gate voltage and the drain current of the TFT manufactured according to various aspects of the present invention and the conventional process by the present inventors. Fig. 7A is a graph of an n-channel TFT and Fig. 7B is a graph of a p-channel TFT. The solid line shows the characteristics of a TFT including an active region formed of a crystalline silicon film crystallized using a catalytic element. The dotted line shows the characteristics of a TFT including an active region formed of a crystalline silicon film crystallized by a conventional solid phase crystallization without using a catalytic element. Both of these films are crystallized in a solid state, and then the entire film is irradiated with a low-power excimer laser light to improve the crystallinity. The drain current I _{D on the} vertical axis is indicated by a logarithmic scale.

In the n-channel TFT of Fig. 7A, the characteristics of the TFT crystallized by the conventional process indicated by the dotted line are changed to the characteristics indicated by the solid line by introducing the catalytic element for crystallization. To be more specific, the field effect mobility is enhanced in approximately 120㎠ / Vs to about 140㎠ / Vs, the threshold voltage V _TH is reduced to from about 2V~3V 1V~2V. However, the rise of the drain current I _D at the negative voltage of V _G , that is, the OFF voltage of the n-channel TFT, tends to increase when the catalytic element is used.

On the other hand, in the p-channel TFT of Fig. 7D, the ON characteristic of the TFT manufactured using the catalytic element for crystallization was remarkably improved as compared with the TFT manufactured in the conventional solid-phase crystallization process. Specifically, the field effect mobility was improved from about 40 cm 2 / Vs to about 90 cm 2 / Vs, and the magnitude of the threshold voltage V _TH was reduced from about -8 V to -10 V to about -3 V to-4 V. It is not clear why the effect of the p-channel TFT is larger than that of the n-channel TFT, but one of the reasons is that the stress in the crystal of the silicon film crystallized by using the catalytic element is more magnetic than that of the silicon film crystallized by other methods do. Another reason is that the crystal orientation of the silicon film crystallized by using the catalytic element is (110) dominant, which is more influential on the hole than electrons. However, the OFF characteristic deteriorates not only in the n-channel TFT but also in the p-channel TFT.

A serious problem of other techniques described in Japanese Patent Application Laid-Open Nos. 6-244103 and 6-244104 is an increase in leakage current in the OFF region of the TFT. This is caused by the catalytic element remaining in the crystalline silicon film which remains after the crystallization and is unevenly distributed in the crystal grain boundaries. Particularly, an element which effectively acts as a catalyst for promoting crystallization of an amorphous silicon film such as nickel or palladium forms an impurity level in the vicinity of the bandgap center in silicon. Therefore, in the TFT, an increase in leakage current in the OFF region is remarkable due to these catalytic elements.

According to the present invention, in a semiconductor device and a semiconductor circuit having a plurality of TFTs on a substrate, a catalytic element is introduced into all of the TFT regions and crystallized, and in particular, only the region of the p-channel TFT is positively crystallized . Therefore, the ON characteristics of the TFT obtained by the crystallization process using the conventional method are sufficient for the n-channel TFT, and the ON characteristic is improved by only turning off the OFF characteristic of the p-channel TFT without damaging the OFF characteristic thereof. As a result, the V _TH of the p-channel TFT in question is lowered and the field effect mobility is improved. As a result, the resulting CMOS circuit is capable of high frequency driving, realizing a low driving voltage and a low power consumption.

In the present invention, the leakage current in the TFT off region increases in the p-channel TFT obtained using the catalytic element. For example, when driving the inverter shown in Fig. 8, since the threshold voltage V _TH of the n-channel TFT is low, the voltage V _TH is not so large. Thus, it is not necessary to apply a large OFF current to the p-channel TFT. Therefore, in practical use, the leakage current of the p-channel TFT is not a serious problem. The problem is the leakage current in the OFF region of the n-channel TFT, rather than the p-channel TFT. Since the threshold voltage V _TH of the p-channel TFT is large, the voltage V _L for driving the inverter shown in Fig. 8 has a large amplitude. Next, a large OFF current applied to the n-channel TFT becomes large. Therefore, it is necessary to prevent the rise of the leakage current in the OFF region, especially the rise of the leakage current in the V _G -I _D characteristic in the n-channel TFT, rather than the p-channel TFT. Therefore, when the CMOS circuit is composed of an n-channel TFT and a p-channel TFT, which are formed of a crystalline silicon film which is crystallized using a catalytic element, the leakage current increases in the n-channel TFT. As a result, a high-performance CMOS circuit can not be obtained.

The present invention is particularly effective for a semiconductor circuit including an n-channel TFT and a p-channel TFT or a circuit having a CMOS structure such as an inverter in a semiconductor device as described above. The concentration of the catalytic element in the active region of the TFT is defined as the maximum value obtained by the two-way on-mass spectrometry. When the concentration of the catalytic element of the p-channel TFT is 1 x 10 ¹⁵ atoms / cm 3 to about 1 x 10 ¹⁹ atoms / cm 3, the catalyst can function to promote the crystallization of the a-Si film as its starting material. When the concentration of the catalytic element in the active region is about 1 x 10 ¹⁶ atoms / cm 3 to about 1 x 10 ¹⁸ atoms / cm 3, the catalyst can function most efficiently. In the present invention, the concentration of the catalytic element in the active region of the p-channel TFT is the most preferable in the above range. On the other hand, when the concentration of the catalytic element in the active region of the TFT is less than about 1 x 10 ¹⁵ atoms / cm 3, the catalytic element does not act and accordingly, the increase in the leakage current in the OFF region caused by the catalytic element No adverse effects occur. Therefore, the concentration of the catalytic element in the active region of the n-channel TFT is preferably less than about 1 x 10 ¹⁵ atoms / cm 3.

In the present invention, it is important that the p-channel TFT is formed of a crystalline silicon film whose active region is crystallized using a catalytic element. On the other hand, in the n-channel TFT, it is preferable that the active region is formed by the crystalline silicon film crystallized by the spontaneous solid-phase crystallization process without using the catalytic element, and the simplicity of the process and the uniformity of the plurality of TFTs on the substrate . In this case, the catalytic element is selectively introduced, crystallized selectively by the annealing treatment, and then the annealing treatment is continued to spontaneously generate nuclei in other regions to solid-phase crystallize. Thereafter, laser light or strong light is irradiated to the entire surface of the substrate to promote the crystallinity of the polycrystallized region. This procedure is particularly effective for improving the ON characteristic of the TFT.

Further, in the present invention, forming the active region of the n-channel TFT from a crystalline silicon film crystallized by irradiation with laser light or strong light is effective for shortening the process and improving the throughput. That is, the catalytic element is selectively introduced and crystallized selectively by heat treatment. Then, by irradiating the entire surface of the substrate with laser light or strong light, the region remaining in the amorphous state is crystallized, and the region first crystallized by the catalytic element is The crystallinity is improved. Therefore, the above-described two steps of crystallization and crystal orientation can be performed in one step.

Further, in the region where the p-channel TFT is formed, not the region into which the direct catalytic element is introduced (hereinafter referred to as the introduction region) but the introduction region thereof is used as a seed, and in the peripheral portion thereof, Direction) is used, higher performance can be achieved. This is because, as described above, although the crystal growth is randomly performed in the above-described introduction region, the periphery thereof is formed of an extremely high-quality crystalline silicon film with uniform growth direction.

In the present invention, other element such as Co, Fe, Pd, Pt, Cu, Ag, Au, In, Sn, Al and Sb may be used as the catalyst element. Any one or more elements selected from the group consisting of the above-mentioned elements can also improve the crystallinity.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[Example 1]

The semiconductor circuit of the first embodiment of the present invention will be described. In this embodiment, a semiconductor circuit having a CMOS structure is fabricated on a glass substrate. The semiconductor having this CMOS structure is composed of an n-channel TFT and a p-channel TFT having a complementary function. This CMOS configuration is used for a peripheral driver of an active matrix liquid crystal display device, a part of a general thin film integrated circuit, and the like. In this embodiment, such a manufacturing process of the semiconductor circuit is described.

1 is a plan view for explaining an outline of a manufacturing process of a TFT of this embodiment. Sectional view taken along the line A-A 'in Figs. 2A to 2F. This process proceeds from FIG. 2A to FIG. 2F.

As shown in Fig. 2A, a lower film 102 is formed on the glass substrate 101 by, for example, sputtering with silicon oxide to a thickness of about 300 nm. The silicon oxide film 102 is formed to prevent impurities from diffusing from the glass substrate. Next, an intrinsic (I-type) a-Si film 103 having a film thickness of 80 nm is formed thereon by a low-pressure CVD method or a plasma CVD method. The thickness of the a-Si film 103 may be in the range of 25 to 100 nm.

Next, a silicon oxide film is formed on the a-Si film 103, and a through hole is provided in a predetermined region 100 of the silicon oxide film to form a mask film 104. [ The a-Si film 103 is exposed through the through-hole in the region 100, for example. Specifically, the a-Si film 103 is exposed in the region 100 and the other portion is masked by the silicon oxide film 104, as shown in Fig. 1 showing the top surface of the state of Fig. 2A.

Next, as shown in Fig. 2A, the substrate 101 is held so that the surface of the a-Si film 103 is in contact with the aqueous solution 105 containing nickel. In this example, nickel acetate is used as the solution and the concentration of nickel in the aqueous solution is 10 ppm. Thereafter, the aqueous solution 105 is uniformly coated on the substrate 101 by a spinner and dried.

Next, the substrate 101 is crystallized by a reducing reaction gas or an inert gas at a heating temperature of 550 DEG C for 4 hours. The annealing temperature may range from 520 ° C to 580 ° C and the annealing time may be from hours to tens of hours. At this time, the nickel applied to the surface acts as a nucleus for crystallization, and the crystal grains of the a-Si film 103 are vertically grown to selectively form a crystalline silicon film 103a as shown in FIG. 2B . The a-Si film 103 in the region masked by the mask film 104 and not in contact with the nickel solution 105 is not crystallized but remains in an amorphous state as the a-Si region 103c. The nickel applied to the surface diffuses to the entirety of the crystalline silicon film 103a. The nickel concentration of the crystalline silicon film 103a, which is measured by two-way on-mass spectrometry (SIMS), is typically about 5 x 10 ¹⁷ atoms / cm 3.

Next, after the mask film 104 is removed, the entire substrate 101 is irradiated with the laser beam 107 as shown in Fig. 2C. Thus, the a-Si film 103c is crystallized to form a crystalline silicon region. At this time, the crystallinity of the crystalline silicon region 103a is further improved. As the laser beam at this time, an XeCl excimer laser having a wavelength of 308 nm and a pulse width of 40 nsec is used. The irradiation conditions of the laser beam were such that the substrate was heated to 150 to 450 캜, for example 400 캜, and irradiated at an energy density of 200 mJ / cm 2 to 400 mJ / cm 2, for example, 250 mJ / cm 2 at the time of irradiation.

Next, as shown in Fig. 2D, an unnecessary portion of the crystalline silicon film is etched away for element isolation to form an island-shaped crystalline silicon film 103n (serving as a source / drain region and a channel region) , And 103p. The crystalline silicon film 103n is obtained as a result of crystallization by laser irradiation. In order to improve the crystallinity of the crystallized film, the crystalline silicon film 103p is irradiated with laser light using nickel as a catalyst, And solid-phase crystallization.

Next, as the gate insulating film 108, a silicon oxide film is deposited to a thickness of 100 nm to cover the crystalline silicon films 103n and 103p serving as active regions. The thickness of the gate insulating film 108 may be in the range of 20 nm to 150 nm. The silicon oxide film decomposes the gases by RF plasma CVD at a substrate temperature of 150 to 600 ° C, preferably 300 to 600 ° C, using TEOS (Tetra Ethoxy Ortho Silicate) together with oxygen gas as raw materials, Silicon oxide was deposited thereon. Alternatively, silicon oxide may be formed by low-pressure CVD or atmospheric pressure CVD with the use of TEOS gas as a raw material and ozone gas at a substrate temperature of 350 ° C to 600 ° C, preferably 400 ° C to 550 ° C. Next, in order to improve the bulk characteristics of the gate insulating film 108 and the interfacial characteristics between the crystalline silicon films 103n and 103p and the gate insulating film 108 after the deposition, the substrate is etched under an inert gas atmosphere for about 30 to 60 minutes at 400 Lt; 0 > C to 600 < 0 > C.

An aluminum film is deposited by sputtering to a thickness of 400 nm to 800 nm, for example, 600 nm, and then patterned to form gate electrodes 109n and 109p. In addition, the gate electrodes 109n and 109p are anodized to form oxide layers 110n and 110p on the substrate as shown in FIG. 2E. This anodic oxidation is performed by immersing the substrate 101 in an ethylene glycol solution containing 1 to 5% of tartaric acid and applying a voltage of 220 V. Next, the substrate 101 is held under this condition for 1 hour. The obtained oxide layers 110n and 110p have a thickness of about 200 nm. The thickness of the oxide layers 110n and 110p defines the size of the offset gate region in a later ion doping process. Accordingly, the size of the offset gate region can be determined in the anodic oxidation process.

Impurities (phosphorus and boron) are then implanted into the crystalline silicon films 103n and 103p using the gate electrodes 109n and 109p and the oxide layers 110n and 110p around them as a mask by ion doping . Phosphine (PH ₃ ) and diboron (B ₂ H ₆ ) are used as the doping gas. The accelerating voltage for phosphorus is about 60 kV to 90 kV, for example 80 kV, and the acceleration voltage for boron is about 40 kV to 80 kV, for example 65 kV. The dose is about 1 × 10 ¹⁵ cm ^{-2 to} 8 × 10 ¹⁵ cm ^-2 for phosphorus, for example about 2 × 10 ¹⁵ cm ^-2 for phosphorus, and about 5 × 10 ¹⁵ cm ^-2 for boron. In this process, the regions where no impurity is implanted are formed in the channel regions 111n and 111p of the TFT, respectively, because of the mask formed by the gate electrode 109n, the oxide layer 110n, the gate electrode 110p and the oxide layer 110p. . When doping is performed, regions that do not need to be doped are coated with photoresist so that doping can be selectively performed for each element. Specifically, at the time of doping phosphorus, the active region 114p for serving as a p-channel TFT is masked with a photoresist, and when boron is doped, an active region 114n for serving as an n- . As a result, n-type impurity regions 112n and 113n and p-type impurity regions 112p and 113p are formed, thereby forming an n-channel TFT (hereinafter referred to as NTFT) and a p- , PTFT) is formed.

Thereafter, as shown in FIG. 2E, annealing is performed by irradiating the laser beam 115 to activate the doped impurity, and at the same time, the crystallinity of the portion where crystallinity deteriorates in the impurity implantation step is improved. At this time, an XeCl laser (having a wavelength of 308 nm and a pulse width of 40 nsec) is used as the laser light. The substrate was irradiated with an energy density of about 150 mJ / cm 2 to 400 mJ / cm 2, preferably 200 mJ / cm 2 to 250 mJ / cm 2. The sheet resistance of the n-type impurity (phosphorus) regions 112n and 113n thus formed is about 200Ω / cm2 to 400Ω / cm2 and the sheet resistance of the p-type impurity (boron) regions 112p and 113p is about 500Ω / / Cm < 2 >.

Next, a silicon oxide film or a silicon nitride film having a thickness of about 600 nm is formed by an interlayer insulating film 116. [ When the above-described silicon oxide film is formed by plasma CVD method with oxygen gas, or by using low pressure CVD or atmospheric pressure CVD method using TEOS as a raw material together with ozone, an interlayer insulating film excellent in step coverage can be obtained. When a silicon nitride film formed by using SiH ₄ or NH ₃ as a source gas by plasma CVD is used as an interlayer insulating film, hydrogen atoms are supplied to the interface between the active region and the gate insulating film, .

Next, contact holes are formed in the interlayer insulating film, and electrode wirings 117, 118, and 119 of the TFT are formed by a two-layer film of a metal material such as titanium nitride and aluminum. The titanium nitride film is provided as a barrier for preventing aluminum from diffusing into the semiconductor layer.

Finally, annealing is performed at about 350 DEG C for about 30 minutes in a 1 atm hydrogen gas atmosphere to obtain the TFT shown in Fig. 2F.

The NTFT thus produced has a field effect mobility μ of about 80 cm 2 / Vs to 100 cm 2 / Vs, a threshold voltage V _TH of about 2 V to 3 V, and a leakage current 1 _OFF in an OFF region of about a few Pa. On the other hand, the PTFT has a field effect mobility μ of about 60 cm 2 / Vs to 70 cm 2 / Vs, a threshold voltage V _TH of about -3 V to -4 V, satisfying the PTFT characteristic, and the leakage current 1 _OFF is about ten Pa. Therefore, in this embodiment, the characteristics of the PTFT are mainly improved. As a result, a semiconductor circuit of a CMOS structure having excellent characteristics can be obtained as a CMOS structure constituted of TFTs formed on a glass substrate.

[Example 2]

A second embodiment of the present invention will be described below with reference to the accompanying drawings. In this embodiment, a semiconductor having a CMOS structure formed of NTFT and PTFT formed on a glass substrate will be described.

3 is a plan view for explaining the outline of a manufacturing process of the TFT of this embodiment. 4A to 4E are sectional views taken along line B-B 'of FIG. 3, and the process proceeds from FIG. 4A to FIG. 4E.

As shown in Fig. 4A, the lower film 202 is formed of silicon oxide with a thickness of 100 nm on the glass substrate 201 by sputtering, for example. Next, an intrinsic (I-type) a-Si film 203 having a film thickness of 50 nm is formed thereon by a low-pressure CVD method. The thickness of the a-Si film 203 may be in the range of 25 to 100 nm.

Next, a photosensitive resin (for example, photoresist) is applied to the a-Si film 203, exposed and developed to form a mask film 204. The a-Si film 203 is exposed in the mask film 204, that is, in the region 200 through a through hole in the form of a slit. More specifically, as shown in FIG. 3 showing the top surface of the state of FIG. 4A, the a-Si film 203 is exposed in the region 200 and the other portion is masked by the silicon oxide film 104.

After the mask is prepared, a nickel thin film 205 is deposited on the surface of the substrate 201 as shown in FIG. 4A. In this embodiment, the distance between the deposition source and the substrate is larger than usual in order to lower the deposition rate so that the thickness of the nickel thin film 205 is 1 nm to 2 nm. The surface density of the nickel thin film 205 on the substrate 201 was measured by an experimental test, and the result was about 4 × 10 ¹³ atoms / cm 2.

Next, as shown in FIG. 4B, the mask film 204 is etched away to lift off the nickel thin film 205 on the mask film 204. As a result, a small amount of nickel in the nickel thin film 205 in the region 200 is selectively added. Next, the a-Si film 203 is crystallized by performing annealing in an inert gas at an annealing temperature of, for example, about 550 DEG C for about 16 hours.

In this case, the crystal grain of the a-Si film 203 with respect to the substrate 201 having nickel added to the surface of the a-Si film 203 as nuclei for crystallization in the region 200 It grows vertically. As a result, a crystalline silicon film 203a is formed in the periphery of the region 200 as indicated by the arrow 206 in Fig. 4B. Crystal growth progresses from the region 200 in the lateral direction (i.e., parallel to the substrate), and the crystalline silicon film 203b is formed as a result of the growth of the colon in the sulfur direction. The other region of the a-Si film 203 remains in the amorphous state as the a-Si region 203c. The nickel concentration of the crystalline silicon film 203b is about 8 × 10 ¹⁶ atoms / cm 3. In the crystal growth, the distance of crystal growth in a direction parallel to the substrate indicated by arrow 206 is about 80 mu m.

Next, as shown in Fig. 4B, the entire surface of the substrate is irradiated with the laser beam 207. [ As a result, the crystal grains of the a-Si film 203c are grown. At this time, crystallinity of the crystalline silicon region 203b is improved. As the laser beam at this time, a XeCl excimer laser (having a wavelength of 308 nm and a pulse width of 40 nsec) was used and the substrate was heated to 400 ° C and laser light was irradiated at an energy density of 250 mJ / cm 2.

Thereafter, as shown in Fig. 4C, the crystalline silicon film in the region serving as the active region (that is, the device region) 203n and 203p is etched and removed without etching, . The crystalline silicon film 203n is obtained as a result of crystallization only by laser irradiation. On the other hand, the crystalline silicon film 203p is directionally controlled at a low temperature by the catalytic action of nickel to solid-phase crystallize, and then its crystallinity is improved by laser light irradiation.

Next, a silicon oxide film as a gate insulating film 208 is deposited to a thickness of about 100 nm to cover the crystalline silicon films 203n and 203p serving as an active region. The gate insulating film 208 decomposes the gas by RF plasma CVD at a substrate temperature of 350 占 폚 with TEOS as a raw material together with oxygen gas, and deposits silicon oxide thereon.

4D, an aluminum film (containing about 0.1 to 2% of silicon) is deposited by sputtering to a thickness of 400 nm to 800 nm, for example, 500 nm, and then patterned to form gate electrodes 209n and 209p ).

Next, impurity ions (phosphorus and boron) are implanted into the crystalline silicon films 203n and 203p using the gate electrodes 209n and 209p as masks by the ion doping method. Phosphine (PH ₃ ) and diboron (B ₂ H ₆ ) are used as the doping gas. The doping conditions are the same as those in the first embodiment. In this process, the region where the impurity is not implanted is caused by the mask formed by the gate electrodes 209n and 209p so that the TFT functions as the channel regions 211n and 211p. When doping is performed, regions that do not need to be doped are coated with photoresist so that doping can be selectively performed for each element. As a result, n-type impurity regions 212n and 213n and p-type impurity regions 212p and 213p are formed. Thus, as shown in FIG. 3, an n-channel TFT (NTFT) ).

Thereafter, as shown in FIG. 4D, laser light 215 is irradiated to perform annealing to activate the doped impurity. At this time, as the laser light, an XeCl excimer laser (having a wavelength of 308 nm and a pulse width of 40 nsec) is used. The substrate was irradiated with about 20 shots at an energy density of about 250 mJ / cm 2 per one place.

4E, a silicon oxide film having a thickness of 600 nm is formed as an interlayer insulating film 216 by a plasma CVD method. A contact hole is formed in the interlayer insulating film 216, and electrode wirings 217, 218 and 219 of the TFT are formed by a two-layer film of a metal material such as titanium nitride and aluminum. Finally, annealing is performed at 350 DEG C for about 30 minutes in a 1 atm hydrogen gas atmosphere to obtain a TFT.

In a CMOS circuit thus fabricated, the NTFT has a field effect mobility μ of about 80 cm 2 / Vs to 100 cm 2 / Vs and a threshold voltage V _TH of about 2V to 3V. On the other hand, the PTFT exhibits a field effect mobility μ of about 80 cm 2 / Vs to 100 cm 2 / Vs higher than that of NTFT and a threshold voltage V _TH of about -3 V to -4 V, satisfying these characteristics. In the OFF region of leakage current 1 _OFF , the NTFT has a leakage current of several pA, while the PTFT has a leakage current of about 10Pa, which is less than 1/2 of that of the PTFT fabricated in the first embodiment.

[Example 3]

A third embodiment of the present invention will be described below with reference to the accompanying drawings. In this embodiment, a semiconductor having a CMOS structure formed of NTFT and PTFT formed on a glass substrate will be described.

5 is a plan view for explaining an outline of a manufacturing process of the TFT of this embodiment. 6A to 6E are sectional views taken along line C-C 'of FIG. The process proceeds from FIG. 6A to FIG. 6E.

As shown in FIG. 4A, the lower film 302 is formed of silicon oxide with a thickness of 300 nm on the glass substrate 301.

Next, an intrinsic (I-type) a-Si film 303 having a film thickness of about 50 nm is formed thereon by a plasma CVD method. The thickness of the a-Si film 203 may be in the range of 25 to 100 nm.

Next, a photosensitive resin (photoresist) is applied to the a-Si film 303, exposed and developed to form a mask film 304. The a-Si film 303 is exposed to the mask film 304, that is, the region 300 in the form of a slit through a through hole. 5, which illustrates the top surface of the state of FIG. 6A, the a-Si film 303 is exposed in the region 300 and the other portion is masked by the photoresist.

After the mask 304 is prepared, a nickel thin film 305 having a thickness of about 1 nm to 2 nm is deposited on the surface of the substrate 301 on the surface of the substrate 301, as shown in Fig. 6A. 6B, the mask film 304 is etched away to lift off the nickel thin film 305 on the mask film 304. Then, as shown in FIG. As a result, a small amount of nickel in the nickel thin film 305 is selectively added to the a-Si film 303 in the region 300. Next, the a-Si film 303 is annealed by annealing at an annealing temperature of 600 캜 for about 20 hours in an inert gas atmosphere.

In this case, in the region 300, crystal grains of the a-Si film 303 are grown using nickel added to the surface of the a-Si film 303 as nuclei for crystallization. As a result, a crystalline silicon film 303a is formed in the periphery of the region 300 as indicated by an arrow 306 in Fig. 6B. Crystal growth proceeds from the region 300 in the lateral direction (i.e., parallel to the substrate) and the crystalline silicon film 303b is formed as a result of the growth of the crystals in the lateral direction. At an annealing temperature of 600 占 폚, natural nuclei are generated in the other regions of the a-Si film 303 which do not undergo crystal growth in the transverse direction due to the influence of nickel. The crystal growth in the lateral direction is inhibited by the generation of the natural nuclei, and is constrained by collision with new crystal grains. The region of the a-Si film 303 which does not undergo crystal growth in the lateral direction is filled with crystal grains grown by the natural nucleation to form a normal solid-phase crystallization region 303d. The nickel concentration of the crystalline silicon film 303b obtained by crystal growth in the transverse direction is about 5 x 10 < ¹⁶ > atoms / cm < 3 >. In the crystal growth, a distance of crystal growth in a direction parallel to the substrate indicated by an arrow 306 is about 140 mu m.

Next, as shown in Fig. 6B, the entire surface of the substrate is irradiated with the laser beam 307. [ As a result, the crystallinity of the crystalline silicon region 303b obtained by the crystal growth in the lateral direction and the a-Si film 303d obtained by the normal solid-phase crystallization by the nickel of the nickel thin film 305 is further improved do. As the laser beam at this time, an XeCl excimer laser (having a wavelength of 308 nm and a pulse width of 40 nsec) was used, and the substrate was heated to about 400 ° C and irradiated with laser light at an energy density of 250 mJ / cm 2.

Thereafter, as shown in FIG. 6C, the crystalline silicon film in the other region is etched away without etching away the crystalline silicon film in the region serving as the active region (that is, the element region) 303n and 303p, Separation is performed. The crystalline silicon film 303n is obtained by performing normal solid-phase crystallization by natural nucleation and irradiating laser light to improve its crystallinity. On the other hand, the crystalline silicon film 303p is controlled in direction at a low temperature by the catalytic action of nickel to crystallize, and then its crystallinity is improved by laser light irradiation.

Thereafter, the crystalline silicon film 303n is used as the active region of the NTFT, and the crystalline silicon film 303p is used as the active region of the PTFT. Accordingly, the semiconductor circuit of the CMOS structure is manufactured in the same manner as in Embodiments 1 and 2.

In this embodiment, an NTFT of a further improved characteristic can be obtained as compared with the NTFT produced in the second embodiment. In the CMOS circuit of the CMOS structure manufactured by this embodiment, the PTFT has a field effect mobility μ of about 80 cm 2 / Vs to 100 cm 2 / Vs and a threshold voltage V _TH of about -3 V to -4 V, As shown in Fig. In addition, the NTFT exhibits satisfactory characteristics with a field effect mobility of about 120 cm 2 / Vs to 150 cm 2 / Vs and a threshold voltage V _TH of about 2V to 3V.

Although the above-described three embodiments have been described according to the present invention, the present invention is not limited to these embodiments, and various modifications may be made without departing from the spirit and scope of the present invention.

For example, in the above embodiment, in order to introduce nickel, a small amount of nickel is added by a method of applying an aqueous solution of a nickel salt dissolved in the surface of the aSi film or a method of forming a nickel thin film by a vapor deposition method, Method. However, before growth of the first amorphous silicon film, nickel may be introduced into the surface of the lower film to diffuse nickel from the lower layer of the aSi film to cause crystal growth. That is, the crystal growth may be performed from the upper surface side of the amorphous silicon film or from the lower surface side. Also, various other techniques can be used for the introduction of nickel. For example, as a solvent for dissolving a nickel salt, a method of diffusing nickel from an SiO ₂ film using a SOG (Spin On Glass) material as a solvent is also effective, and a method of forming a thin film by a sputtering method or a plating method, A method of directly introducing it into the apparatus can be used. As the impurity metal element promoting crystallization, the same effect can be obtained by using one or more elements selected from cobalt, iron, palladium, platinum, copper, silver, gold, indium, tin, aluminum and antimony in addition to nickel have.

In the above-mentioned three embodiments, a method of crystallizing the amorphous silicon film or improving the crystallinity of the crystalline silicon film by excimer irradiation which is a pulse laser was used. Particularly, in a method for promoting the crystallinity of a crystalline silicon film by a catalytic element, defects and displacements in the crystal grains are effectively treated while maintaining good crystallinity of the crystalline silicon film crystallized by the catalytic element, A silicon film is obtained. As the heating means at this time, in addition to the excimer laser used in the present embodiment, the same processing can be performed by using another kind of laser such as continuous oscillation Ar laser. It is also called a rapid thermal annealing (RTP) method in which the sample is heated by raising the temperature to about 1000 ° C to 1200 ° C (silicon molder's temperature) in a short time using infrared light and flash lamp instead of laser light ) Can be used.

In addition to the active matrix type substrate for liquid crystal displays, the application of the present invention can be applied to various types of applications such as a built-in type image sensor, a driver built-in type thermal head, a driver incorporated type driver incorporating a light emitting element, Are considered. By using the present invention, high performance such as high speed and high resolution of these elements can be realized. Further, the present invention is not limited to the MOS transistor described in the above embodiment, but can be applied to a general semiconductor process including a bipolar transistor or a correction induction transistor using a crystalline semiconductor as a material of a device.

As described above, in the semiconductor device and the semiconductor circuit having the n-channel type TFT or the p-channel type TFT, which are formed on the insulating substrate and the use of the inexpensive glass substrate and the improvement of the throughput, , the OFF characteristic of the n-channel TFT is not undermined, and the ON characteristic of the p-channel TFT which is a current problem is greatly improved. Thus, a high-performance semiconductor circuit, in particular, a CMOS structure circuit can be obtained by a simple process. Particularly, in a liquid crystal display device, a driver monolithic active matrix substrate having an active matrix portion and a peripheral circuit portion on the same substrate, which satisfies the high performance and high integration required of the TFTs constituting the peripheral drive circuit portion, Compact, high-performance, and low-cost.

Various modifications may be easily made by those skilled in the art without departing from the scope and spirit of the present invention. Accordingly, the claims of the present invention should not be construed as limited to what is described herein, but rather should be construed broadly.

Claims (22)

Channel transistor and a p-channel transistor each having an active region formed of a crystalline silicon film on a substrate having an insulating surface, wherein the n-channel transistor and the p- Channel transistor, wherein the p-channel transistor includes a catalytic element for improving the crystallinity of the amorphous film in the active region, and the concentration of the catalytic element in the active region of the n- Is lower than the concentration in the active region of the semiconductor circuit. The semiconductor circuit according to claim 1, wherein the concentration of the catalytic element in the active region of the p-channel transistor is about 1 x 10 ¹⁵ atoms / cm 3 to 1 x 10 ¹⁹ atoms / cm 3. The semiconductor circuit according to claim 1, wherein a concentration of the catalytic element in the active region of the p-channel transistor is about 1 x 10 ¹⁶ atoms / cm 3 to 1 x 10 ¹⁸ atoms / cm 3. The semiconductor circuit according to claim 1, wherein a concentration of the catalytic element in the active region of the n-channel transistor is less than about 1 x 10 ¹⁵ atoms / cm 3. 2. The semiconductor circuit according to claim 1, wherein the concentration of the catalytic element is defined as a minimum value obtained by two-way on-mass analysis. A semiconductor circuit comprising an n-channel transistor and a p-channel transistor each having an active region formed of a crystalline silicon film on a substrate having an insulating surface, wherein the active region of the p- Wherein the active region of the n-channel transistor is formed of a crystalline silicon film which is crystallized by solid-phase crystallization without using a catalytic element. A semiconductor circuit comprising an n-channel transistor and a p-channel transistor each having an active region formed of a crystalline silicon film on a substrate having an insulating surface, wherein the active region of the p- Wherein the active region of the n-channel transistor is formed of a crystalline silicon film which is crystallized by irradiation with laser light or strong light. The semiconductor circuit according to claim 1, wherein the catalytic element comprises at least one element selected from the group consisting of Ni, Co, Fe, Pd, Pt, Cu, Ag, Au, In, Sn, Al and Sb. The semiconductor circuit according to claim 6, wherein the catalytic element comprises at least one element selected from the group consisting of Ni, Co, Fe, Pd, Pt, Cu, Ag, Au, In, Sn, Al and Sb. The semiconductor circuit according to claim 7, wherein the catalytic element comprises at least one element selected from the group consisting of Ni, Co, Fe, Pd, Pt, Cu, Ag, Au, In, Sn, Al and Sb. A semiconductor device comprising the semiconductor circuit according to claim 1. Forming an amorphous silicon film on a substrate having an insulating surface, selectively introducing a catalyst element for promoting crystallization of the amorphous silicon film into the amorphous silicon film, annealing the amorphous silicon film to form an amorphous silicon film Forming a p-channel transistor using the crystalline silicon film region, and forming an n-channel transistor using a region outside the crystalline silicon film, A method of manufacturing a semiconductor circuit. Forming an amorphous silicon film on a substrate having an insulating surface, selectively introducing a catalyst element for promoting crystallization of the amorphous silicon film into the amorphous silicon film, annealing the amorphous silicon film to form an amorphous silicon film Crystallizing the amorphous silicon film and crystallizing the amorphous silicon film in a direction substantially parallel to the surface of the amorphous silicon film existing in the periphery of the crystallized amorphous silicon film region to obtain a crystalline silicon film region; And forming an n-channel transistor by using a region which is not crystallized by the catalytic element. The method according to claim 12, further comprising the steps of: performing the annealing treatment to obtain the crystalline silicon film region, then performing another annealing treatment at a high temperature to nucleate a region not crystallized by the catalytic element to solid- A step of forming a p-channel transistor by using the crystalline silicon film region obtained by performing the processing and a step of forming an n-channel transistor by using a solid-phase crystallized region by generating a nucleus in an area not crystallized by the catalytic element Wherein the step of forming the semiconductor circuit comprises the steps of: 14. The method according to claim 13, further comprising the steps of: performing the annealing treatment to obtain the crystalline silicon film region, then performing another annealing treatment at a high temperature to nucleate a region not crystallized by the catalytic element to solid- And forming a p-channel transistor using the crystalline silicon film region obtained by performing the crystallization of the n-channel transistor, and a step of forming an n-channel transistor using the solid-phase crystallized region by nucleating a region where crystallization by the catalytic element is not performed Of the semiconductor circuit. The method according to claim 12, further comprising the steps of: performing the annealing treatment to obtain the crystalline silicon film region, then irradiating laser light or strong light to crystallize a region not crystallized by the catalytic element; A step of forming a p-channel transistor using the region of the silicon film to be formed, and a step of forming an n-channel transistor using a region crystallized by irradiating laser light or strong light to a region where crystallization by the catalytic element is not performed A method of manufacturing a semiconductor circuit. 14. The method according to claim 13, further comprising the steps of: performing the annealing treatment to obtain the crystalline silicon film region; thereafter irradiating laser light or strong light to crystallize a region not crystallized by the catalytic element; A step of forming a p-channel transistor using the region of the silicon film to be formed, and a step of forming an n-channel transistor using a region crystallized by irradiating laser light or strong light to a region where crystallization by the catalytic element is not performed A method of manufacturing a semiconductor circuit. 15. The method of claim 14, further comprising the steps of: selectively crystallizing a region containing the catalytic element; spontaneously nucleating a region not crystallized by the catalytic element to cause solid-phase crystallization; To thereby improve the crystallinity of the crystallized region. The semiconductor device according to claim 12, wherein the catalytic element comprises at least one element selected from the group consisting of Ni, Co, Fe, Pd, Pt, Cu, Ag, Au, In, Sn, Gt; 14. The semiconductor circuit according to claim 13, wherein the catalytic element comprises at least one element selected from the group consisting of Ni, Co, Fe, Pd, Pt, Cu, Ag, Au, In, Sn, Gt; A method of manufacturing a semiconductor device comprising the semiconductor circuit according to claim 12. A method of manufacturing a semiconductor device comprising the semiconductor circuit according to claim 13.