JP2000031057A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a catalyst element in a crystal silicon film by opening an insulating thin film, exposing an amorphous silicon film, adding the catalyst element promoting the crystallization of the amorphous silicon film, selectively leaving it only in an opening, and obtaining the crystal silicon film in crystal growth from the opening to a periphery. SOLUTION: An insulating thin film 104 is installed on an amorphous silicon film 103 formed on a substrate 101. The opening 100 is formed in the prescribed area of the insulating thin film 104 and a part of the amorphous silicon film 103 is exposed. A catalyst element 105 promoting the crystallization of the amorphous silicon film 103 is added on a surface. Then, only the catalyst element existing on the insulating thin film 104 is selectively removed. The amorphous silicon film 103 is crystal-grown from the opening 100 to the peripheral area, namely, in a direction parallel to the surface of the substrate 101 by heating it so as to obtain a crystal silicon film 103b. The active area (element area) of a semiconductor device is formed in the area of the crystal silicon film 103b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using a crystalline silicon film obtained by crystallization of an amorphous silicon film as an active region. About. The present invention is particularly effective for manufacturing a semiconductor device using a field effect thin film transistor (TFT) provided on a substrate having an insulating surface, and specifically, an active matrix liquid crystal display device, a contact image sensor, It can be applied to the manufacture of three-dimensional ICs and the like.

[0002]

2. Description of the Related Art In recent years, large-scale, high-resolution liquid crystal display devices, high-speed, high-resolution contact image sensors, or high-performance three-dimensional ICs have been developed. In addition, attempts have been made to form high-performance semiconductor devices. Conventionally, a thin film silicon semiconductor is generally used as a semiconductor element used in these devices. The thin-film silicon semiconductor includes two types of amorphous silicon semiconductor (a-Si) and crystalline silicon semiconductor.
It is roughly divided into two.

Of these, amorphous silicon semiconductors are:
It is most commonly used because it has a low production temperature, can be produced relatively easily by a gas phase method, and has high mass productivity. However, physical properties such as conductivity of an amorphous silicon semiconductor are inferior to those of a crystalline silicon semiconductor. Therefore, in order to form a semiconductor device that can operate at higher speed in the future, it is strongly required to establish a method for manufacturing a semiconductor device made of a crystalline silicon semiconductor.

Polycrystalline silicon, microcrystalline silicon, and the like are known as silicon semiconductors having crystallinity. As a method for obtaining a thin film silicon semiconductor having such crystallinity, (1) a film having crystallinity is directly formed at the time of film formation, (2) an amorphous semiconductor film is formed first, Irradiation of light (for example, laser light) to give crystallinity by its energy, (3) First, an amorphous semiconductor film is formed, and thermal energy is applied thereto to give crystallinity. Methods are known.

However, in the method (1), the crystallization proceeds simultaneously with the film formation step, so that it is necessary to increase the thickness of the silicon film in order to obtain crystalline silicon having a large grain size. It is technically difficult to form a film having physical properties uniformly over the entire surface of the substrate. Further, since the film forming temperature of the crystalline film is as high as about 600 ° C. or more, there is a cost problem that an inexpensive glass substrate cannot be used.

In the method (2), a grain boundary is favorably treated in spite of a small grain size in order to utilize a product-solidification phenomenon in a melt-solidification process, and a high-quality crystalline silicon film is obtained. However, taking an excimer laser, which is most commonly used at present, for this method as an example, there is a problem that the irradiation area of the laser beam is small and the throughput is low. Further, as a more serious problem, in order to uniformly treat the entire surface of a large-area substrate, laser stability is not sufficient, and it is difficult to obtain a silicon film having uniform crystallinity. Therefore, it is difficult to form a plurality of semiconductor elements having uniform characteristics on the same substrate.

Further, the method (3) has an advantage that it can be applied to a substrate having a larger area than the method (1) or (2). However, in crystallization, about 6
It is necessary to perform heat treatment at a high temperature of 00 ° C. or more for several tens of hours. Therefore, in order to use an inexpensive glass substrate and to improve the throughput, it is necessary to lower the heating temperature. However, in order to realize crystallization in a shorter time, conflicting problems must be solved simultaneously. Need to be resolved. In the method (3), since the solid phase crystallization phenomenon is used, the crystal grains spread in parallel to the substrate surface, and even those having a particle size of several μm appear. However, in the process, the grown crystal grains collide with each other to form grain boundaries. The formed grain boundary acts as a trap level for carriers, and is a major cause of lowering the mobility of a formed semiconductor device (for example, a TFT).

A method of producing a silicon film having high quality and uniform crystallinity by heating at a lower temperature and for a shorter time by applying the above method (3) is disclosed in Japanese Patent Application Laid-Open No. 9-171964. It is proposed in Japanese Unexamined Patent Publication No. 9-313259.

In the methods disclosed therein, a minute amount of a metal element such as nickel is introduced onto the surface of the amorphous silicon film, and thereafter, the treatment is performed at a low temperature of about 600 ° C. or less for about several hours. In time, crystallization is realized. This mechanism is such that crystal nuclei having a metal element as a nucleus occur early, and then the metal element acts as a catalyst to promote crystal growth, whereby crystallization proceeds rapidly. In that sense, a metal element having such an action is referred to as a “catalytic element” in the present specification. Whereas the amorphous silicon film crystallized by the ordinary solid phase growth method has a twin structure, the crystalline silicon film grown by the crystallization promoted by these catalytic elements has many columnar structures. It is composed of crystals, and the inside of each columnar crystal is in a state close to a single crystal.

Further, by selectively introducing such a catalytic element into a part of the amorphous silicon film and heating it, the catalytic element can be removed while leaving the other part in an amorphous silicon film state. Only the introduced region can be selectively crystallized. Further, if the heating time is further extended, crystal growth can be performed in a lateral direction (that is, in a direction parallel to the substrate surface) from the selective introduction region. In other words, in this method, the direction of crystal growth and the state of the crystal grain boundaries are controlled by selectively introducing a catalytic element.

Within such a lateral crystal growth region, columnar crystals whose growth directions are substantially aligned in one direction are closely adjacent to each other, and the catalyst element is directly introduced to randomly generate crystal nuclei. This is a region having good crystallinity as compared with the region where the occurrence has occurred. Then, a high-performance semiconductor device can be obtained by using the silicon film in such a lateral crystal growth region having good crystallinity as an active region.

Here, as a selective introduction method of the catalyst element,
In Japanese Patent Application Laid-Open No. 9-171964, after forming a mask film for selective introduction on an amorphous silicon film, an aqueous solution in which a salt of a catalyst element is dissolved is applied to the substrate surface, and then spin-dried. Thus, selective introduction of the catalyst element is performed.
After that, the mask film is removed, and heat treatment for crystallization is performed. In Japanese Patent Application Laid-Open No. 9-313259, similarly to Japanese Patent Application Laid-Open No. 9-171964, an aqueous solution in which a mask film for performing selective introduction on an amorphous silicon film and a salt of a catalyst element are dissolved is formed. Is applied to the substrate surface and then spin-dried to selectively introduce a catalyst element. However, unlike JP-A-9-171964, the mask film is not removed thereafter, and crystallization is performed as it is. Heat treatment.

[0013]

However, although the above-described method of crystallizing a silicon film using a catalytic element is very effective, the following problems remain.

[0014] The catalyst element greatly contributes to the crystallization of the amorphous silicon film, but after the crystallization, it remains mainly in the crystal grain boundary and remains in the crystalline silicon film. The presence of a large amount of these catalytic elements in the crystalline silicon film that constitutes the active region (element region) of a semiconductor device impairs the reliability and electrical stability of an electronic device using these semiconductor devices. It is an inhibitor and of course not preferred.

In particular, elements such as nickel, cobalt, and platinum, which efficiently act as catalysts for promoting crystallization of an amorphous silicon film, form impurity levels near the center of the band gap in silicon. Therefore, when a TFT is manufactured using a silicon film crystallized using these catalyst elements, the effect of the catalyst element remaining in the crystallized silicon film is mainly due to the leakage current during the OFF operation of the TFT. Phenomena such as increase in reliability and decrease in reliability appear. That is, the above-described catalyst element improves the current driving capability such as the field-effect mobility, the on-current, or the on-current rise coefficient (S coefficient) in the TFT element to be formed by improving the crystallinity of the channel region. However, as a cost, the off characteristic and the reliability are deteriorated.

Here, the method using a catalyst element is roughly classified into two types. One is to add a catalytic element to the entire surface of the amorphous silicon film to grow crystals, and the other is to selectively add the catalytic element to the amorphous silicon film and First, after crystallizing into a seed region, a peripheral portion of the seed region is laterally crystal-grown.

In the former case, crystallization proceeds due to random nucleation by the catalytic element, and the catalytic element used for crystallization remains in the crystal grain boundary. For this reason, the concentration of the catalyst element in the obtained silicon film necessarily increases. In the latter case, on the other hand, if the catalytic element acts efficiently, the catalytic element promotes crystallization in a state of being unevenly distributed at the growth tip, so that the catalytic element ideally exists in the region after crystallization. do not do. Actually, the catalytic element is also detected from the silicon film region where the crystal grows in the lateral direction, but the concentration is at least one digit lower than that of the silicon film obtained by the former method.

Therefore, considering the reduction of the concentration of the catalyst element in the silicon film, the latter method (selective introduction method) of laterally growing the crystal after the selective introduction of the catalyst element is very effective. The above-mentioned Japanese Patent Application Laid-Open Nos. 9-171964 and 9-313259 both use this selective introduction method. As described above, the selective introduction of the catalyst element is performed using a mask film. Have gone.

Here, in Japanese Patent Application Laid-Open No. 9-171964, an aqueous solution containing a salt of a catalytic element is applied on a mask film,
After removing the mask film, heat treatment is performed. However, the catalyst element in the state where the aqueous solution is applied and spin-dried is not sufficiently adsorbed on the substrate surface, and is removed only by the subsequent water washing. That is, regardless of the material of the mask film (whether a photoresist mask film or a silicon oxide mask film), in the mask film removing step, the catalyst element that should have been added is also removed. For this reason, it is actually difficult to perform crystallization by the method described in JP-A-9-171964.

In order to solve the above problems, it is possible to add a catalytic element by using a thin film forming method such as sputtering or vapor deposition. However, when a resist mask film is used, the surface of the silicon film may be added. Can directly attach resist and cause undesirable contamination. Further, since the heat treatment is performed in a state where the surface of the active region is exposed, the possibility that the active region is contaminated in the heat treatment step is increased. In a general coplanar field-effect transistor device, the surface of the silicon film is very important because the surface of the silicon film serves as a channel surface that plays an important role in driving the transistor. Need to keep.

On the other hand, according to the method disclosed in JP-A-9-313259, after an aqueous solution of a catalyst element is applied and dried,
Since the heat treatment is performed while a mask film such as a silicon oxide film is left, surface contamination of the active region is reduced. However, the catalyst element in the silicon film grown in the lateral direction obtained in this state is still at a relatively high concentration, and sufficient device characteristics cannot be obtained.

In addition, as described above, in order to improve the performance of the device and obtain stable and highly reliable device characteristics, the surface of the active region is kept clean and actually becomes the channel interface of the field effect transistor. It is very important to improve the characteristics of the interface between the silicon film and the gate insulating film in the active region. In a conventional general field effect transistor device having a coplanar structure, in order to easily achieve this purpose, a method of continuously forming a silicon film and a gate insulating film in an active region without exposing the film to the air is used. It is valid. However, when a crystallization method using a catalyst element as described above is employed, a catalyst element introduction step is necessary,
It is difficult in principle to form a silicon film and a gate insulating film continuously, and it cannot be realized by conventional techniques.

The present invention has been made in order to overcome the problems that occur when crystallizing a silicon film using the above-described catalytic element. A method of manufacturing a semiconductor device capable of realizing a reduction in the concentration of a catalytic element of the above, securing a clean active region surface and good channel interface characteristics, and the like. It is an object of the present invention to provide a method for manufacturing a semiconductor device which can be manufactured with high yield on a substrate having a surface.

[0024]

According to a method of manufacturing a semiconductor device of the present invention, a step of forming an amorphous silicon film on a substrate having an insulating surface and a step of depositing an insulating thin film on the amorphous silicon film Forming an opening in a predetermined region of the insulating thin film and exposing a part of the amorphous silicon film through the opening; and forming a catalyst element for promoting crystallization of the amorphous silicon film. A step of adding on the insulating thin film and the amorphous silicon film, a step of selectively removing only a catalyst element present on the insulating thin film among the added catalyst elements, and a heat treatment. The crystal growth of the amorphous silicon film,
From the region where the catalytic element is added and introduced to the peripheral region, in a lateral direction parallel to the surface of the substrate,
The method includes the steps of obtaining a crystalline silicon film region and forming an active region of a semiconductor device using the crystalline silicon film region, thereby achieving the above object.

Preferably, the insulating thin film is formed after lateral crystal growth of the amorphous silicon film by the heat treatment.
It is used as a gate insulating film of a semiconductor device to be formed.

Preferably, the amorphous silicon film and the insulating thin film formed thereon are continuously formed without being exposed to the air.

Preferably, the step of selectively removing only the catalyst element present on the insulating thin film includes a step of light etching a surface of the insulating thin film to remove the catalyst element by lift-off.

In one embodiment, a material that etches only the insulating thin film without substantially etching the silicon film and the catalyst element is used as an etchant during the light etching of the surface of the insulating thin film. .

For example, a silicon oxide film or a silicon nitride film can be used as the insulating thin film, and low-concentration hydrofluoric acid can be used as an etchant for the light etching.

Ni, Co, Pd, Pt, Cu, A are used as the catalyst element for promoting crystallization of the amorphous silicon film.
At least one element selected from the group consisting of g, Au, In, Sn, Al, and Sb can be used.

Preferably, the step of adding the catalyst element on the insulating thin film and the amorphous silicon film is performed by forming a thin film in a state where the catalyst element is in a metal state.

Preferably, the surface concentration of the added catalyst element is determined to be about 1 × 10 ¹³ by total reflection X-ray fluorescence analysis.
Control is performed within the range of atoms / cm ² to about 2 × 10 ¹⁴ atoms / cm ² .

Preferably, the active region is formed such that the direction of the lateral crystal growth is substantially parallel to the direction of carrier movement in the formed semiconductor device.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to the description of a specific embodiment of the present invention, first, the results of a study conducted by the inventors of the present invention in the process leading to the present invention will be described.

According to the present invention, an insulating thin film is provided on an amorphous silicon film formed on an insulating substrate such as glass, and a predetermined region of the insulating thin film is opened to form an amorphous silicon film. After partially exposing, a catalytic element that promotes crystallization of the amorphous silicon film is added onto the insulating thin film and the amorphous silicon film. Thereafter, only the catalyst element existing on the insulating thin film is selectively removed. Then, a heat treatment is performed to grow the amorphous silicon film in a lateral direction (that is, in a direction parallel to the substrate surface) from the region where the catalytic element is added and introduced to the peripheral region. An active region (element region) of the semiconductor device is formed using the silicon film in the lateral crystal growth region obtained as described above. By doing so, the catalytic element in the silicon film in the region where the crystal has grown in the lateral direction is greatly reduced, and the surface of the silicon film in the lateral growth region that is to be the active region is also kept clean. The reason will be described below.

According to the study by the inventors of the present invention, the reason why the catalyst element concentration of the silicon film in the lateral growth region cannot be reduced is as follows.
It has been found that the catalytic element is also present in the region beyond the tip of the lateral growth region of the silicon film (that is, in the amorphous region that has not been grown by the catalytic element).

In the conventional method for introducing a catalyst element, Japanese Patent Application Laid-Open No.
As described in Japanese Patent No. 312259, a catalytic element is introduced over the entire surface of a substrate mainly using a silicon oxide film as a mask film, and then a heat treatment for crystallization is performed. At this time,
This will be described with reference to FIGS. In the figure, 5
01 is a substrate, 502 is an amorphous silicon film, 503 is a mask film of silicon oxide, and 504 is a catalytic element added to the surface. FIG. 5A shows a state immediately before heat treatment for crystallization, and FIG. 5B shows a state during heat treatment for crystallization of the silicon film 502.

At the time of the heat treatment, an introduction region of the amorphous silicon film 502 where the catalyst element 504 is in contact (a region corresponding to the opening 500 of the mask film 503 in the amorphous silicon film 502) is first crystallized. The seed region 502
a. Further, crystal growth proceeds in the lateral direction (the direction of arrow 505) from seed region 502a, and lateral crystal growth region 502b is formed.

On the other hand, the catalyst element 504 existing on the mask film (silicon oxide film) 503 diffuses through the silicon oxide film 503 as shown by an arrow 506, and
2 has been reached. At this time, originally, the silicon oxide film 50
3, the value of the diffusion coefficient of the catalytic element is
02, which is very small compared to the diffusion coefficient value. However, in actuality, the diffusion of the catalytic element into the silicon oxide film 503, which cannot be considered from the value of the diffusion coefficient, occurs.
b and the surface of the region 502c where the crystal growth is not reached. As a result, the catalyst element 504 also exists in a region where the catalyst element 504 does not originally exist (should not exist). If this occurs, the effect of introducing the catalyst element 504 selectively and growing in the lateral direction and its effectiveness will be greatly impaired.

Therefore, in the present invention, the catalytic element present on the mask film for selective introduction is removed before the heat treatment for crystallization. As a result, the phenomenon that the catalytic element diffuses from the mask film does not occur. Therefore, the concentration of the catalyst element in the silicon film in the lateral growth region serving as the active region is reduced. Furthermore, since the surface of the silicon film serving as an active region is covered and subjected to heat treatment in a clean state in which no catalytic element is present even in a film such as a silicon oxide film used as a mask film, the surface state of the active region Can also be kept in good condition without contamination. Also,
Since the total amount of the catalytic element on the substrate to be put into the heat treatment furnace during the heat treatment can be greatly reduced, the contamination of the heat treatment furnace by the catalyst element can also be reduced.

Therefore, by using the present invention, contamination in the crystallization step and occurrence of defective device characteristics due to catalytic elements are greatly reduced, and the production yield is greatly improved.
Further, the performance of the semiconductor device to be formed can be improved, and the reliability thereof can be greatly improved.

The insulating thin film used as a mask film for selective introduction of a catalytic element is preferably used as it is as a gate insulating film of a thin film transistor after a heat treatment step for crystallization of a silicon film. In the present invention, unlike the method of the prior art, the catalytic element does not exist on the insulating thin film used as the mask film for introducing the catalytic element in the crystallization step, and the catalytic element is introduced into the insulating thin film during the heat treatment step. No diffusion occurs. Therefore, even after the crystallization step, no catalytic element is present in the insulating thin film, and the insulating thin film is in a clean state. Therefore, the insulating thin film can be used as it is as a gate insulating film of a thin film transistor. As a result, the number of times the silicon film surface serving as the active region is exposed to the air is reduced, and the contamination is reduced.
A mask film removing process, an active region surface cleaning process, or a new gate insulating film forming process is omitted or shortened,
The manufacturing process is simplified. In addition, during the heat treatment process for crystallization, the insulating thin film is also tightened, resulting in a dense and good insulating film with a low fixed charge density. It can be obtained without adding.

Further, when the insulating thin film used as the mask film is used as it is as the gate insulating film, the amorphous silicon film and the insulating thin film are continuously exposed without being exposed to the air. It is more desirable to form the film by using the above method. In other words, the amorphous silicon film that will later become the active region and the insulating thin film that will later become the gate insulating film are continuously formed without being exposed to the air, and are the most important interfaces for the field effect transistor. The channel interface between the active layer and the gate insulating film can be obtained in an ideal interface state which is very clean and has a low interface state density. As a result, the transistor characteristics can be improved and stabilized, and the reliability can be greatly improved.

In the step of selectively removing only the catalyst element present on the insulating thin film, it is desirable to perform light etching on the surface of the insulating thin film and remove the catalyst element by lift-off. When the catalytic element is removed by a method such as etching the catalytic element itself, not only the catalytic element present on the insulating thin film but also the amorphous silicon film that is present in contact with the amorphous silicon film at the selective introduction part is required. Even catalytic elements can be removed together. On the other hand, when an etchant for etching the catalyst element itself is used, the catalyst element actually present on the insulating thin film is not entirely removed, and a certain amount of the catalyst element may remain as an etching residue.

In order to sufficiently obtain the effects of the present invention, the catalytic element added to the substrate surface must be almost completely removed only on the insulating thin film.
It is very effective to light-etch the surface of the insulating thin film thereunder after adding the catalytic element. As a result, only the catalyst element present on the insulating thin film can be efficiently and reliably removed by so-called lift-off.

At this time, it is important to appropriately select an etchant for lightly etching the surface of the insulating thin film. Specifically, it is necessary to use, as the etchant, a material that etches only the insulating thin film without etching the silicon film and the catalyst element. By using such an etchant, only the catalyst element on the insulating thin film can be almost completely removed together with the insulating thin film, while leaving the catalyst element present on the silicon film in the selective introduction part.

More specifically, it is desirable to use a silicon oxide film or a silicon nitride film as the insulating thin film and to use low-concentration hydrofluoric acid as an etchant for light-etching the surface.

Taking nickel, which is a typical catalytic element, as an example, hydrofluoric acid is soluble and etched in a silicide compound state, but is present in a metal state (atomic state). Is not etched. Other catalyst elements show almost the same tendency. On the other hand, in the present invention, the catalyst element on the insulating thin film is removed without any heat treatment step after the addition of the catalyst element. Therefore, when the removal step (light etching step) is performed, the catalyst element is completely silicide. It has not been converted and exists in an atomic state. Therefore, when hydrofluoric acid is used as an etchant in the light etching step, the added catalytic element is not etched. Further, the silicon film itself has a strong etching resistance to hydrofluoric acid and is hardly etched. On the other hand, when a silicon oxide film or a silicon nitride film is used as an insulating thin film as a mask film, they are etched against hydrofluoric acid and have the least effect on a silicon film as a semiconductor. I'm done.

Here, the silicon oxide film has a very large etching rate with respect to hydrofluoric acid. In the present invention, a heat treatment step is performed while lightly etching the surface of the insulating thin film to leave the insulating thin film, and the insulating thin film is further used as a gate insulating film. The surface roughness of the gate insulating film may become so large that the mask film (insulating thin film) that should ultimately function as a gate insulating film may disappear. Therefore, especially when a silicon oxide film is used, the etching rate of the silicon oxide film is about 10 n using low concentration hydrofluoric acid.
m / min or less. Specifically, it is preferable to use hydrofluoric acid in which the concentration of hydrogen fluoride in the liquid is about 1% or less.

Ni, C is used as a catalyst element in the present invention.
o, Pd, Pt, Cu, Ag, Au, In, Sn, A
1 or Sb can be used. One or a plurality of elements selected from these elements have a trace effect to promote crystallization.

Particularly, when Ni is used as a catalyst element
The most remarkable effect can be obtained. For this reason
Then, the following model can be considered. The catalyst element is simple
It does not act alone, it combines with the silicon film and turns into silicide
This has an effect on crystal growth. The crystal structure at that time is non-
Acts like a template when crystallizing a crystalline silicon film.
Therefore, it is considered that the crystallization of the amorphous silicon film is promoted. this
Sometimes, Ni combines with two Sis to form NiSi_TwoIs represented
Is formed. This NiSi_TwoIs a fluorite-shaped knot
Shows a single crystal silicon structure.
The structure is very similar to the diamond structure
You. Moreover, NiSi _TwoHas a lattice constant of 5.406Å
And the lattice in the diamond structure of crystalline silicon
It has a value very close to the constant 5.430 °. Therefore, Ni
Si_TwoIs a mold for crystallizing the amorphous silicon film
Is the most suitable for the catalyst element of the present invention.
In particular, it is most preferable to use Ni.

The step of adding these catalyst elements typified by nickel onto the insulating thin film and the amorphous silicon film is performed in a state where these catalyst elements are not in the silicide compound or salt state but in the metal state. It is desirable to carry out by forming. This is for the following reason.

In the present invention, as described above, it is optimal to use a silicon oxide film as the insulating thin film and use low-concentration hydrofluoric acid as an etchant for light-etching the surface. At this time, the silicide compound is removed by etching with hydrofluoric acid. Further, in the method of applying and drying an aqueous solution of a salt of a catalyst element on the substrate surface as disclosed in Japanese Patent Application Laid-Open No. 9-313259, since the catalyst element is simply present in a salt state deposited on the substrate surface. It is removed not only by hydrofluoric acid cleaning but also by water cleaning alone. Therefore, these techniques cannot be applied to the present invention. In the present invention, at the time of light etching of the insulating thin film, it is necessary that the catalytic element added to the silicon film at the introduction portion is securely adsorbed on the silicon film surface without being removed. It is desirable to form the thin film on the insulating thin film and the amorphous silicon film in a state where the catalytic element represented by nickel is in a metallic state as described above, and to thereby add the catalytic element.

At this time, the concentration of the catalyst element added to the substrate surface was determined to be about 1 × 10 ¹³ atoms by total reflection X-ray fluorescence analysis.
It is desirable to control within the range of s / cm ² to about 2 × 10 ¹⁴ atoms / cm ² . In general, the method of introducing a catalyst element by forming a thin film is more effective than the method of introducing an aqueous solution of a salt of a catalyst element onto a substrate surface by drying it, as in JP-A-9-313259. It is difficult to control the amount to a very small amount. On the other hand, the total reflection X-ray fluorescence analysis can analyze only the substrate surface without destruction with high sensitivity (the lower limit of detection is about 1 × 10 ¹⁰ atoms / cm ² or less). It is the best way to manage the quantity. Then, the surface element addition amount of the catalyst element is set to about 1 × 10 ¹³ atoms / cm ² to about 2 × 10 ¹⁴ ato as described above.
By controlling within the range of ms / cm ² , sufficient lateral crystal growth of the amorphous silicon film is performed, and in a semiconductor device formed using the same, a remarkable increase in leakage current due to a catalytic element is performed. And no adverse effects such as reduced reliability.

Further, in the present invention, in order to realize a semiconductor device having higher mobility and higher performance,
The semiconductor device is configured such that the crystal growth direction of the silicon film by the catalytic element and the carrier movement direction in the semiconductor device are substantially parallel (specifically, the channel region and the source / drain region in the active region are arranged. Is desirable. With such a configuration, a crystal grain boundary serving as a trap when carriers move is theoretically not present in the moving direction, so that a semiconductor device having higher mobility can be obtained. Actually, a certain amount of bending or branching of the columnar product occurs in the lateral crystal growth region, but by adopting the above-described configuration, the trap amount such as the crystal grain boundary in the carrier moving direction can be ensured. To decrease.

In the following, some specific embodiments of the present invention achieved based on the above-described examination results are described.
This will be described with reference to the accompanying drawings.

(First Embodiment) In a first embodiment of the present invention, a plurality of n-channel TFTs (n
The present invention is applied to a process of manufacturing a TFT. The n-type TFT of the present embodiment can be used not only as a driver circuit and a pixel portion of an active matrix liquid crystal display device but also as an element constituting a general thin film integrated circuit. In the following description of the present embodiment, as a representative thereof, for driving a pixel of an active matrix substrate for a liquid crystal display device, it is necessary to particularly uniformly manufacture hundreds of thousands to millions of n-type TFTs on a substrate. The description will be made by taking the n-type TFT 120 as an example.

FIGS. 1A to 1E are plan views showing an outline of a process of manufacturing a pixel TFT on an active matrix substrate described in the present embodiment. Actually, hundreds of thousands or more TFTs are configured as described above, but in the present embodiment,
The description will be simplified to 12 TFTs in 3 rows × 4 columns. 2A to 2F are cross-sectional views illustrating a manufacturing process of an arbitrary one of the twelve TFTs 120 shown in FIG. 1, in which order from (a) to (f). , The manufacturing process proceeds sequentially. In FIG. 2, the positional relationship between the catalytic element introduction portion 100 and the arrangement direction of the active region (channel region and source / drain region) of the TFT 120 differs from the arrangement direction of the TFT 120 in FIG. 1 by 90 degrees. However, this is for ease of explanation, and the effect of the present invention is not impaired by this positional relationship.

In the manufacturing method of this embodiment, first, FIG.
As shown in FIG. 1A, a base film 102 made of silicon oxide and having a thickness of about 300 nm is formed on a glass substrate 101 by, for example, a sputtering method. The silicon oxide film 102 is provided to prevent diffusion of impurities from the glass substrate 101. Next, by a low pressure CVD method or a plasma CVD method, the thickness is about 25 nm to about 100 nm,
For example, an intrinsic (I-type) amorphous silicon film (a-
A (Si film) 103 is formed on the base film 102. Further thereon, an insulating thin film 104 made of a silicon oxide film or a silicon nitride film is deposited.

In the present invention, the insulating thin film 104
Functions as a mask film and a gate insulating film of a TFT when a catalytic element is introduced later. In the present embodiment, the insulating thin film 104 is a silicon oxide film, specifically, TEOS (TetraEthoxy Ortho).
(Silicate) as a raw material together with oxygen to be decomposed and deposited by an RF plasma CVD method. Further, in the present embodiment, the a-Si film 1 described above is used without exposing the substrate 101 to the atmosphere using a multi-chamber plasma CVD apparatus.
03 and the silicon oxide film 104 are continuously formed.

The thickness of the silicon oxide film (mask film) 104 is preferably about 10 nm to about 50 nm. If the silicon oxide film 104 is thinner than the above range, in the step of introducing the catalyst element, the introduced catalyst element diffuses and passes through the silicon oxide film (mask film) 104 and is undesirable in the lower silicon film 103. There is a possibility to reach the area. On the other hand, from the above range, the silicon oxide film 104
If it is thick, it will be difficult to use it later as a gate insulating film. In the present embodiment, the thickness of the silicon oxide film 104 is about 30 nm.

Next, the silicon oxide film (mask film) 104 on the a-Si film 103 is patterned to form an opening (through hole) 100 to obtain a predetermined mask pattern. Here, as shown in FIG.
The a-Si film 103 is exposed in the form of a slit through the opening (through hole) 100. This state is referred to as multiple T
When viewed generally from the top with respect to the FT, the a-Si film 10
Reference numeral 3 denotes a slit exposed at the bottom of a plurality of through holes (openings) 100 provided in the mask film 104.
Other portions of the a-Si film 103 are masked.

Thereafter, as shown in FIG. 2A, a nickel film (nickel thin film) is formed on the upper surface of the structure obtained above.
105 is formed by a sputtering method. In the opening 100 of the mask film 104, the nickel film 105 is formed on the surface of the a-Si film 103 exposed at the bottom thereof and comes into contact with the a-Si film 103 (reference numeral 1).
05a). At this time, the surface concentration (the surface concentration of the added nickel) of the nickel film 105 (105a) formed on the substrate surface is managed by total reflection X-ray fluorescence analysis, and is preferably about 1 × 10 ¹³ atoms / cm ^2. ~ About 2 × 10 ¹⁴ atoms / c
controlled within a range of m ^2. In this embodiment, the surface concentration of the nickel film 105 is typically set to about 5 × 10 ¹³ atoms / cm ² by setting the pressure during sputtering higher than usual and controlling the DC power extremely low. . In this state, the nickel film 105 formed on the substrate surface has a density of a monoatomic layer or less, and is hardly a film.

Next, the substrate 101 is immersed in low-concentration hydrofluoric acid, and the surface of the mask film 104 is lightly etched.
In the present embodiment, the above-described light etching treatment is performed by immersion in about 0.5% hydrofluoric acid for about 30 seconds. By this light etching process, the mask film 104 is formed.
Is etched by about 5 nm, and accordingly, the nickel film 105 existing on the mask film 104 is lifted off and completely removed. On the other hand, the nickel film 105a existing in contact with the silicon film 103 in the region 100
Is not removed by this light etching process,
As shown in FIG. 2B, the nickel film 105a is selectively present only on the portion of the a-Si film 103 exposed in the region 100 on the substrate 101.

Thereafter, the substrate 101 on which the selective introduction of nickel (selective formation of the nickel film 105a) has been performed is subjected to an inert atmosphere, for example, a nitrogen atmosphere at about 540 ° C. The heat treatment is performed at a temperature of about 620 ° C. for several hours to several tens hours. In this embodiment, as an example, the heat treatment is performed at about 580 ° C. for about 6 hours. In this heat treatment, random crystal nuclei with nickel as nuclei occur in the a-Si film 103 in the region 100 in contact with the nickel film 105a, and crystallization proceeds, and the crystalline silicon film 103a as a seed region is formed. Is formed (see FIG. 2C). Thereafter, crystal growth is performed in a lateral direction (a direction parallel to the surface of the substrate 101) from the crystalline silicon film 103a in the region 100 (that is, the seed region 103a) to a peripheral region thereof, as indicated by an arrow 106. . At this time, since there is no nickel on the mask film 104, the lateral crystal growth indicated by the arrow 106 is not caused by nickel caused by diffusion through the mask film 104. This is performed based on only the nickel from the nickel film 105a formed in the region 100. In addition, during the above-described heat treatment step, the lateral crystal growth region 103 serving as a later channel surface is formed.
The surface of b is a clean silicon oxide film 1 containing no nickel.
04 is always covered, and contamination of the active region can be prevented as much as possible.

Here, referring to FIG. 1A, in a region sandwiched between linear regions (introduction regions) 100 (seed regions 103a) into which nickel has been selectively introduced, as shown by an arrow 106, a lateral direction crystal is formed. Although the grown crystalline silicon film 103b is formed, the laterally grown crystalline silicon films 103b grown from the separate introduction regions 100 finally collide with each other to form a crystal grain boundary 103d. The same lateral crystal growth occurs from the outermost linear introduction region 100 to the outside, but the region where the growth does not reach remains as the amorphous silicon film region 103c. That is, if FIG. 1 and FIG.
The TFT 120 formed in FIG.
1 corresponds to one of the TFTs in the column drawn on the rightmost side, and the introduction region 100 in FIG.
It corresponds to the line drawn on the rightmost side in (a).
Therefore, in FIG. 2, another introduction region and a crystalline region that grows laterally from the introduction region actually exist on the left side of the drawing, but other introduction regions exist on the right side. Absent.

The concentration of nickel in the lateral growth region 103b where an active region is to be formed later is typically about 5 × 10 ¹⁶ atoms / cm ³ according to SIMS measurement. This value is sufficiently lower than the value obtained by the prior art.

Next, unnecessary portions of the silicon film 103 are removed to perform element isolation. At this time, the silicon oxide film 104 on the silicon film 103 used as the mask film is also left as it is. That is, thereby, the island-shaped crystalline silicon film 103i which will be the active region (source / drain region and channel region) of the TFT 120 later is formed using the lateral crystallization region 103b, and the silicon oxide film 104 is similarly formed. By patterning, a first gate insulating film 104i is formed (see FIGS. 1B and 1C and FIG. 2D).

Here, the channel interface of the later TFT 120 is formed by a high-quality lateral crystal growth silicon film 103i (103).
It is formed as an interface between b) and the silicon oxide film 104i used as the mask film. In other words, the channel interface in the present embodiment is a film formed continuously without any exposure to the air, and is subjected to a high-temperature heat treatment for crystallization, so that the interface is clean and excellent. Has characteristics. In addition, the first gate insulating film 104i is also densified by heat treatment, and has very good bulk characteristics.

Next, an oxidized film having a thickness of about 20 nm to about 130 nm, typically about 70 nm, is formed so as to cover the island-shaped crystalline silicon film 103i serving as an active region and the island-shaped first gate insulating film 104i. A silicon film is formed on the second gate insulating film 10
7 is formed. The silicon oxide film 107 is made of, for example, TE
Using OS as a raw material, substrate temperature is about 150 ° C with oxygen.
At about 600C, preferably about 300C to about 450C, R
Decompose and deposit by F plasma CVD method. Or,
Using TEOS as a raw material, the substrate temperature is set to about 350 ° C. to about 600 ° C., preferably about 400 ° C. to about 5 ° C., together with ozone gas.
It may be formed at 50 ° C. by a low pressure CVD method or a normal pressure CVD method. The second gate insulating film 107 is provided for preventing leakage between the side surface of the silicon film 103i and a gate line to be formed later. The thickness of the gate insulating film 104i (for example, about 25 nm = about 5 nm by light etching)
of the second gate insulating film 107 (for example, about 70 nm) (about 95 nm in the above example).
nm).

Subsequently, by a sputtering method,
Thickness of about 400 nm to about 800 nm, for example about 600 nm
Is formed. Then, the aluminum film is patterned to form a gate electrode 108. Further, the gate electrode 108 made of aluminum is used.
Is anodized to form an oxide layer 109 on the surface (see FIG. 2E). The gate electrode 108 simultaneously constitutes the gate bus line 118 in plan view,
When this state is viewed in a plan view, the state is as shown in FIG.

Anodization is typically carried out with tartaric acid at about 1%
The operation is performed in an ethylene glycol solution containing about 5%. At first, the applied voltage is increased to about 220 V while the current is kept constant, and the state is maintained for about 1 hour to end the operation. The resulting oxide layer 109 has a thickness of about 200 nm.
It is. Note that the thickness of the oxide layer 109 corresponds to the thickness of an offset gate region formed in a later ion doping step, and the length of the offset gate region can be determined in the above-described anodic oxidation step. it can.

Next, an impurity (phosphorus) is implanted into the active region 103i by ion doping using the gate electrode 108 and the surrounding oxide layer 109 as a mask.
Specifically, phosphine (PH) is used as a doping gas.
₃ ), the acceleration voltage is about 60 kV to about 90 kV, for example, about 80 kV, and the dose is about 1 × 10 ¹⁵ cm ⁻² to about 8 × 1.
0 ¹⁵ cm ^-2 , for example, about 2 × 10 ¹⁵ cm ^-2 . By this step, the regions 111 and 112 into which the impurities are implanted in the active region 103i become source / drain regions of the TFT 120 later. On the other hand, a region 110 which is masked by the gate electrode 108 and the surrounding oxide layer 109 and into which impurities are not implanted becomes a channel region of the TFT 120 later.

After that, as shown in FIG. 2E, annealing is performed by irradiation with a laser beam 113 to activate the ion-implanted impurities, and at the same time, a portion where the crystallinity is deteriorated in the above-described impurity introducing step. Improves crystallinity. Specifically, for example, a XeC1 excimer laser (wavelength 308n)
m, a pulse width of about 40 nsec) and an energy density of about 150 J / cm ² to about 400 J / cm ² , preferably about 20 J / cm ^2.
As 0 J / cm ² ~ about 300 J / cm ^2, each with respect to one place 10
Irradiate each time. The sheet resistance of the n-type impurity (phosphorus) regions 111 and 112 thus formed is typically about 200 Ω / □ to about 800 Ω / □.

Subsequently, a silicon oxide film or a silicon nitride film having a thickness of about 600 nm is formed as the interlayer insulating film 114. When a silicon oxide film is used, TEOS is used as a raw material, and plasma CVD of TEOS and oxygen or TOS
When formed by low-pressure CVD or normal-pressure CVD of EOS and ozone, a good interlayer insulating film 114 having excellent step coverage can be obtained. Further, when a silicon nitride film formed by a plasma CVD method using SiH ₄ and NH ₃ as source gases is used, hydrogen atoms are supplied to the interface between the active region 103i and the gate insulating film 104i, and the TFT characteristics are reduced. Has the effect of reducing dangling bonds that degrade.

Next, a contact hole is formed in the interlayer insulating film 114, and a source electrode / wiring 115 of the TFT 120 is formed using a metal material, for example, a two-layer film of titanium nitride and aluminum. The titanium nitride film is provided as a barrier film for preventing diffusion of aluminum into the semiconductor layer. Since the TFT 120 in this embodiment is assumed to be an element for switching a pixel electrode, the other drain electrode is provided with a pixel electrode 116 made of a transparent conductive film such as ITO. That is, in FIG.
A video signal is supplied via the source bus line 115, and based on the gate signal of the gate bus line 118,
The necessary charges are written to the pixel electrodes 116.

Finally, a hydrogen atmosphere of about 1 atm.
Annealing is performed at about 30 ° C. for about 30 minutes to complete the TFT 120 shown in FIG. In addition, if necessary,
For the purpose of protecting the TFT 120, a protective film made of a silicon nitride film or the like may be provided on the TFT 120.

The n-type T of this embodiment manufactured as described above
FT 120 typically has a field effect mobility of about 100
Despite the extremely high performance of cm ^-2 / Vs and the threshold voltage of about 2.5 V, even if the durability test is performed by repeated measurement, bias application, temperature stress, etc., almost no characteristic deterioration is observed. Very reliable compared to conventional ones. In addition, the leakage current in the TFT off region where the catalytic element is particularly problematic is about 5 pA, which is the same as when no catalytic element is used, as compared with the conventional value of about 10 pA to about 15 pA.
It was reduced to about pA, and the production yield was able to be greatly improved. Then, when an active matrix substrate for liquid crystal display formed using the n-type TFT 120 manufactured according to the present embodiment was actually evaluated for lighting, a high-definition liquid crystal having very few pixel defects and a high contrast ratio was obtained. A panel was obtained.

In this embodiment, the n-type TFT 120
Is described using the pixel electrode of the active matrix substrate as an example.
0 can be easily applied to a thin film integrated circuit and the like. For example, in that case, a contact hole may be formed also on the gate electrode 108 and a necessary wiring may be provided.

(Second Embodiment) In a second embodiment of the present invention, a plurality of n-channel TFTs are formed on a glass substrate.
The present invention is applied to a process of manufacturing a CMOS circuit in which an (n-type TFT) and a p-channel type TFT (p-type TFT) are configured to be complementary. The n-type TFT and the p-type TFT constituting the CMOS circuit of this embodiment can be used not only as a peripheral driving circuit of an active matrix type liquid crystal display device but also as an element constituting a general thin film integrated circuit. In the following description of the present embodiment, an n-type TFT and a p-type TFT forming a CMOS circuit for a peripheral drive circuit of an active matrix substrate for a liquid crystal display device are representative thereof.
The description will be made using FT as an example.

FIG. 3 is a plan view showing the outline of the manufacturing process of the n-type TFT 221 and the p-type TFT 222 constituting the CMOS circuit described in this embodiment. FIG. 4 (a)
4F are cross-sectional views taken along line 4-4 in FIG.
The manufacturing process of the n-type TFT 221 and the p-type TFT 222 sequentially proceeds in the order from (a) to (f).

In the manufacturing method of this embodiment, first, FIG.
As shown in FIG. 1A, a base film 202 made of silicon oxide having a thickness of about 300 nm is formed on a glass substrate 201 by, for example, a CVD method or a PVD method. This silicon oxide film 202 is provided to prevent diffusion of impurities from the glass substrate 201. Next, using a multi-chamber type plasma CVD apparatus, the thickness is about 25 nm to about 100 n.
An intrinsic (I-type) amorphous silicon film (a-Si film) 203 of m, for example, about 35 nm is formed on the base film 202. Further, without exposing the substrate to the atmosphere,
A silicon oxide film 204 is formed continuously by the plasma CVD method. At this time, plasma CVD
As a film forming gas in the process, typically, a-
SiH ₄ gas is used for depositing the Si film 203, and a mixed gas of SiH ₄ gas and N ₂ O gas is used for depositing the silicon oxide film 204.

Next, the silicon oxide film 204 is patterned to provide openings (through holes) 200 to obtain a predetermined mask pattern. Here, as shown in FIG. 4A, the a-Si film 203 is exposed in a slit shape through the opening (through hole) 200 of the mask film 204.
When this state is viewed from above, the a-Si film 203 has a through hole (opening) 200 provided in the mask film 204.
Is exposed in a slit shape at the bottom of the a-Si film 203.
Other parts of are masked.

Thereafter, as shown in FIG. 4A, a nickel film (nickel thin film) is formed on the upper surface of the structure obtained above.
205 is thin film deposited. The nickel film 205 is formed on the surface of the a-Si film 203 exposed at the bottom of the opening 200 of the mask film 204, and
3 (reference number 205a).

In the nickel deposition process, the thickness of the nickel film 205 is controlled by making the distance between the deposition source and the substrate larger than usual and lowering the deposition rate. Specifically, by total reflection X-ray fluorescence analysis,
The surface concentration (the surface concentration of nickel to be added) of the formed nickel film 205 (205a) is about 1 × 10 ¹³ atom
s / cm ² to about 2 × 10 ¹⁴ atoms / cm ² , for example, about 3 ×
It is controlled to be 10 ¹³ atoms / cm ² .

Next, the substrate 201 is immersed in low-concentration hydrofluoric acid, and the surface of the mask film 204 is lightly etched.
In the present embodiment, the above-described light etching treatment is performed by immersion in about 0.5% hydrofluoric acid for about 30 seconds. By this light etching process, the mask film 204 is formed.
Is etched by about 5 nm, and accordingly, the nickel film 205 existing on the mask film 204 is lifted off and completely removed. On the other hand, the nickel film 205a existing in contact with the silicon film 203 in the region 200
Is not removed by this light etching process,
As shown in FIG. 4B, the nickel film 205a is selectively present only on the portion of the a-Si film 203 that is exposed in the region 200 on the substrate 201.

Thereafter, the substrate 201 on which the selective introduction of nickel (selective formation of the nickel film 205a) has been performed is subjected to a temperature of about 540 ° C. in an inert atmosphere, for example, a nitrogen atmosphere. The heat treatment is performed at a temperature of about 620 ° C. for several hours to several tens hours. In this embodiment, as an example, the heat treatment is performed at about 580 ° C. for about 5 hours. In this heat treatment, in the a-Si film 203 in the region 200 in contact with the nickel film 205a, the a-Si film 2
03 with the nickel added to the surface of the substrate 20
The crystallization of the a-Si film 203 proceeds in a direction perpendicular to 1;
A crystalline silicon film 203a is formed as a seed region (see FIG. 4C). Thereafter, as shown by an arrow 206, crystal growth is performed in a lateral direction (a direction parallel to the surface of the substrate 201) from the crystalline silicon film 203a (that is, the seed region 203a) in the region 200 to the peripheral region. . At this time, since no nickel is present on the mask film 204, the arrow 206
Is performed not based on nickel caused by diffusion through the mask film 204, but based only on nickel from the nickel film 205a formed in the region 200. In addition, during the above-mentioned heat treatment step, the lateral crystal growth region 20 which will be a later channel surface is formed.
The surface of 3b is always covered with a clean silicon oxide film 204 containing no nickel, so that contamination of the active region can be prevented as much as possible.

Here, referring to FIG. 3, in a region around a linear region (introduction region) 200 (seed region 203 a) into which nickel is selectively introduced, crystallinity that has grown in the lateral direction as indicated by an arrow 206. Although the silicon film 203b is formed, the region where the growth does not reach remains as the amorphous silicon film region 203c.

The growth distance of the lateral crystal growth in this embodiment (growth distance on line 4-4 'in FIG. 3)
Is about 60 μm. The nickel element concentration in the lateral growth region 203b where an active region is to be formed later is:
According to SIMS measurements, typically about 5 × 10 ¹⁶ atoms /
cm ^3. This value is sufficiently lower than the value obtained by the prior art.

Next, unnecessary portions of the silicon film 203 are removed to perform element isolation. At this time, the silicon oxide film 204 on the silicon film 203 used as the mask film is also left as it is. That is, thereby, island-shaped crystalline silicon films 203n and 203p which become active regions (source / drain regions and channel regions) of the n-type TFT 221 and the p-type TFT 222 later are formed using the lateral crystallization region 203b. The silicon oxide film 204 is similarly patterned to form first gate insulating films 204n and 204p as shown in FIG.

Here, the later-described n-type TFT 221 and p-type TFT
The channel interface of the FT 222 is formed as an interface between the high-quality lateral crystal growth silicon film 203n or 203p and the silicon oxide film 204n or 204p used as a mask film. In other words, the channel interface in the present embodiment is a film formed continuously without any exposure to the air, and is subjected to a high-temperature heat treatment for crystallization, so that the interface is clean and excellent. Has characteristics.
The first gate insulating films 204n and 204p are also densified by heat treatment, and have very good bulk characteristics.

Next, a thickness of about 20 nm to cover the island-shaped crystalline silicon films 203n and 203p serving as active regions and the island-shaped first gate insulating films 204n and 204p.
A silicon oxide film with a thickness of about 130 nm, typically about 40 nm, is formed as the second gate insulating film 207. The silicon oxide film 207 is decomposed and deposited by RF plasma CVD at a substrate temperature of about 150 ° C. to about 600 ° C., preferably about 300 ° C. to about 450 ° C., for example, using TEOS as a raw material together with oxygen. Alternatively, using TEOS as a raw material, the substrate temperature is set to about 350 ° C. to about 600 ° C. together with ozone gas,
Preferably, it may be formed at about 400 ° C. to about 550 ° C. by a low pressure CVD method or a normal pressure CVD method. The second gate insulating film 207 includes silicon films 203n and 203p
In order to prevent a leak between the side surface of the semiconductor device and a gate line to be formed later.

The total thickness of the gate insulating film finally becomes the thickness of the first gate insulating film 204n or 204p (for example, about 15 nm = about 5 nm by light etching).
of the second gate insulating film 207 (for example, about 40 nm) (about 55 nm in the above example).
nm).

Subsequently, by the sputtering method,
Thickness of about 400 nm to about 800 nm, for example about 500 nm
Of an aluminum film (containing about 0.1% to about 2% silicon) is formed. Then, this aluminum film is patterned to form a gate electrode 208 as shown in FIG.
n and 208p are formed.

Next, the gate is formed by an ion doping method.
Active regions using the electrodes 208n and 208p as masks.
Impurities (phosphorus and boron) are added to 203n and 203p.
Inject each. Specifically, the doping gas
OSPHIN (PH_Three) And diborane (B_TwoH₆)
When doping with phosphorus, the accelerating voltage is about 60 kV to about 9 kV.
0 kV, for example, about 80 kV, and the dose amount is about 1 × 10^Fifteencm
^-2~ 8 × 10^Fifteencm^-2For example, about 2 × 10^Fifteencm^-2age,
When boron is doped, the acceleration voltage is set to about 40 kV to about 80 kV.
kV, for example, about 65 kV, and the dose amount is about 1 × 10^Fifteencm^-2
~ 8 × 10^Fifteencm ^-2For example, about 5 × 10^Fifteencm^-2And
By this step, the active regions 203n and 203p
211n and 212n and 21n,
1p and 212p are later referred to as TFTs 221 and 222.
It becomes a source / drain region. On the other hand, the gate electrode 208
n and 208p are masked by regions where impurities are not implanted.
Regions 210n and 210p are later referred to as TFTs 221 and 22p.
2 channel region.

In this embodiment, as can be seen from FIG. 3, the crystal growth direction 206 of the silicon film and the TFT 221 are different.
And 222 (in the source region 2)
TF so that their directions (from 11n or 211p to the drain region 212n or 212p) are parallel to each other.
Each region included in the active region of T221 and T221 is arranged. This reduces the trap density of defects or crystal grain boundaries in the silicon film with respect to carriers, so that TFTs 221 and 222 having higher mobility can be obtained.

Then, as shown in FIG. 4E, annealing is performed by irradiation with a laser beam 213 to activate the ion-implanted impurities and, at the same time, to remove the portions whose crystallinity has deteriorated in the impurity introduction step. Improves crystallinity. Specifically, for example, a XeCl excimer laser (wavelength 308n)
m, a pulse width of about 40 nsec) and an energy density of about 150 J / cm ² to about 400 J / cm ² , preferably about 20 J / cm ^2.
Irradiation is performed 10 times at one location, each at 0 J / cm ² to about 300 J / cm ² , typically about 250 J / cm ² .

Subsequently, as shown in FIG.
A silicon oxide film of about 00 nm is formed by plasma CVD, for example.
It is formed as an interlayer insulating film 214 by a method. Next, a contact hole is formed in the interlayer insulating film 214, and source electrodes / wirings 217, 218, and 219 of the TFT are formed using a metal material, for example, a two-layer film of titanium nitride and aluminum. Finally, annealing is performed at about 350 ° C. for about 30 minutes in a hydrogen atmosphere of about 1 atm.
The TFTs 221 and 222 shown in FIG. Further, if necessary, a protective film made of a silicon nitride film or the like may be provided on the TFTs 221 and 222 for the purpose of protecting the TFTs 221 and 222.

The CMOS manufactured according to the above embodiment
N-type TFT 221 and p-type TFT 222 constituting a circuit
Typically have a field effect mobility of about 130 cm ⁻² / Vs to about 160 cm ⁻² / V in the n-type TFT 221.
s, the threshold voltage is about 1V to about 2V, while the p-type TFT 22
2 has a field effect mobility of about 90 cm ⁻² / Vs to about 1
20 cm ^-2 / Vs and a threshold voltage of about ^-2 V to about -3 V, showing very good characteristics. Further, the n-type TFT 22
Although the 1-type and p-type TFTs 222 have such high performance, there is almost no deterioration in characteristics even after repeated measurement, durability test by bias application or temperature stress. Highly reliable. In addition, the leakage current in the TFT off region where the catalytic element is particularly problematic is about 5 pA for the n-type TFT 221 and about 5 pA for the p-type TFT in comparison with the conventional value of about 10 pA to about 15 pA.
222 was reduced to about 3 pA, and the manufacturing yield was able to be greatly improved.

Although the two embodiments based on the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications based on the technical idea of the present invention are possible. It is.

For example, in the above two embodiments, the silicon oxide film serving as the mask film is used as it is as the gate insulating film of the TFT. However, after the crystallization step, the mask film is removed and a new gate insulating film is formed. Even if the film is re-formed, there is no diffusion of nickel from above the mask film during the crystallization step, and contamination of the silicon film surface is suppressed, so that the effects of the present invention can be obtained. Also, as the mask film,
Similar effects can be obtained by using a silicon nitride film in addition to the silicon oxide film. Further, the same effect can be obtained by using cobalt, palladium, platinum, copper, silver, gold, indium, tin, aluminum, or antimony in addition to nickel as the impurity metal element that promotes crystallization.

The present invention is applied to, for example, a contact-type image sensor, a thermal head with a built-in driver, a light with a built-in driver using an organic EL as a light emitting element, in addition to the active matrix type substrate for liquid crystal display. A writing element, a display element, and a three-dimensional IC can be considered.
By applying the present invention to these elements, higher performance such as higher speed and higher resolution can be realized.

Further, the present invention is not limited to the MOS transistors described in the above embodiments, but is widely applied to all semiconductor processes including bipolar transistors and electrostatic induction transistors using a crystalline semiconductor as an element constituting material. Can be.

[0104]

As described above, according to the present invention, it is possible to realize a high-performance semiconductor device having a stable characteristic with a small leakage current. A semiconductor device can be obtained by a simple manufacturing process. In addition, the non-defective product rate in the manufacturing process is greatly improved, and the cost of the product can be reduced.

In particular, in a liquid crystal display device, a pixel switching TFT required for an active matrix substrate is used.
The active matrix section and the peripheral drive circuit section are formed on the same substrate, simultaneously satisfying the requirements of the improvement of the switching characteristics of the TFT or the high performance and the high integration required for the TFT constituting the peripheral drive circuit section. The driver monolithic type active matrix substrate described above can be realized. As a result, downsizing, higher performance, lower cost, and the like of the module are realized.

[Brief description of the drawings]

FIGS. 1A to 1E are plan views schematically showing a manufacturing process of an n-type TFT according to a first embodiment of the present invention.

FIGS. 2A to 2F are cross-sectional views sequentially illustrating a manufacturing process of an n-type TFT according to the first embodiment of the present invention.

FIG. 3 is a plan view schematically showing a manufacturing process of n-type and p-type TFTs constituting a CMOS circuit according to a second embodiment of the present invention.

4 (a) to 4 (f) are cross-sectional views taken along line 4-4 in FIG. 3 and show a CMO according to a second embodiment of the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing steps of the n-type and p-type TFTs constituting the S circuit in order.

FIGS. 5A and 5B are schematic cross-sectional views for explaining a problem of a conventional crystallization method using a catalytic element.

[Explanation of symbols]

 100, 200 Opening (through-hole) 101, 201 Substrate 102, 202 Underlayer 103, 203 Silicon film 103a, 203a Seed region 103b, 203b Lateral crystal growth region 104, 204 Mask film (first gate insulating film) 105 , 205 Nickel film (catalytic element film) 106, 206 Crystal growth direction 107, 207 Second gate insulating film 108, 208n, 208p Gate electrode 109 Anodized layer 110, 210n, 210p Channel region 111, 211n, 211p Source region 112 , 212n, 212p Drain region 113, 213 Laser light 114, 214 Interlayer insulating film 115 Source electrode 116 Pixel electrode 118 Gate bus line 125 Source bus line 120 N-channel TFT (n-type TFT) 217, 218 219 electrodes and wiring 221 n-channel type TFT (n-type TFT) 222 p-channel type TFT (p-type TFT)

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masao Moriguchi 22-22, Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (72) Inventor Hiromi Sakamoto 22-22, Nagaikecho, Abeno-ku, Osaka-shi, Osaka F-term (for reference) 5F052 AA11 DA02 EA03 EA15 FA06 GB05

Claims (10)

[Claims] A step of forming an amorphous silicon film on a substrate having an insulating surface, depositing an insulating thin film on the amorphous silicon film, and forming an opening in a predetermined region of the insulating thin film. Forming and exposing a portion of the amorphous silicon film through the opening; and adding a catalyst element that promotes crystallization of the amorphous silicon film to the insulating thin film and the amorphous silicon film. A step of selectively removing only the catalyst element present on the insulating thin film out of the added catalyst elements; and performing a heat treatment to increase the crystal growth of the amorphous silicon film. From the region where the catalytic element is added and introduced toward the peripheral region, in a lateral direction parallel to the surface of the substrate to obtain a crystalline silicon film region, and using the crystalline silicon film region Forming an active region of a semiconductor device. Manufacturing method of the device. 2. The method according to claim 1, wherein the insulating thin film is used as a gate insulating film of a semiconductor device formed after laterally growing the amorphous silicon film by the heat treatment.
13. The method for manufacturing a semiconductor device according to item 5. 3. The semiconductor device according to claim 1, wherein the amorphous silicon film and the insulating thin film formed thereon are continuously formed without being exposed to the air. Manufacturing method. 4. The step of selectively removing only the catalyst element present on the insulating thin film includes a step of light etching a surface of the insulating thin film to remove the catalyst element by lift-off. Item 4. The method for manufacturing a semiconductor device according to any one of Items 1 to 3. 5. A material that etches only the insulating thin film without substantially etching the silicon film and the catalyst element as an etchant during the light etching of the surface of the insulating thin film. 5. The method for manufacturing a semiconductor device according to item 4. 6. The method according to claim 4, wherein a silicon oxide film or a silicon nitride film is used as the insulating thin film, and low concentration hydrofluoric acid is used as an etchant at the time of the light etching.
Alternatively, the method of manufacturing a semiconductor device according to 5. 7. The catalyst element that promotes crystallization of the amorphous silicon film includes Ni, Co, Pd, Pt, Cu,
The method of manufacturing a semiconductor device according to claim 1, wherein at least one element selected from the group consisting of Ag, Au, In, Sn, Al, and Sb is used. 8. The method according to claim 1, wherein the step of adding the catalyst element on the insulating thin film and the amorphous silicon film is performed by forming a thin film in a state where the catalyst element is in a metal state. 13. The method of manufacturing a semiconductor device according to claim 1. 9. The surface concentration of the added catalyst element is defined as
Approximately 1 × 10 ¹³ atoms / cm ² by total reflection X-ray fluorescence analysis
9. The method according to claim 1, wherein the control is performed within a range of about 2 × 10 ¹⁴ atoms / cm ² . 10. The active region is formed so that a direction of the lateral crystal growth and a moving direction of carriers in a semiconductor device to be formed are substantially parallel to each other.
13. The method of manufacturing a semiconductor device according to claim 1.