JPH07297122A - Semiconductor device and production thereof - Google Patents

Abstract

PURPOSE:To introduce a minimum quantity of catalyst element uniformly onto the surface of a substrate by introducing a catalyst element for accelerating the crystallization, through deposition, to an amorphous silicon film in an active region and growing crystals on the amorphous silicon film through heating and irradiation of laser light or intensive light. CONSTITUTION:An amorphous silicon film 103 is deposited by low pressure CVD or plasma CVD, followed by deposition of a quite thin film 105 by vacuum deposition. It is then annealed under hydrogen reducing atmosphere or inert atmosphere and crystallized. In this regard, the nickel 105 deposited on the surface serves as a nucleus for crystallizing the amorphous silicon film 103 in the direction vertical to a substrate 101 thus depositing a crystal silicon film 103a. Nickel is diffused uniformly into the film simultaneously with the crystallization.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which can be used in an active matrix type liquid crystal display device using a TFT (thin film transistor) provided on an insulating substrate such as glass, and a manufacturing method thereof. The present invention relates to a semiconductor device in which a crystalline silicon film obtained by crystallizing an amorphous silicon film is formed as an active region on a substrate having an insulating surface, and a manufacturing method thereof.

[0002]

2. Description of the Related Art As a semiconductor device having TFTs on an insulating substrate such as glass, an active matrix type liquid crystal display device using these TFTs for driving pixels, an image sensor and the like are known. A thin film silicon semiconductor is generally used for the active region of the TFT used in these devices. The thin film silicon semiconductor is roughly classified into two types, that is, an amorphous silicon (a-Si) semiconductor and a crystalline silicon semiconductor.

The former amorphous silicon semiconductor is most commonly used because it has a low production temperature, can be produced relatively easily by a vapor phase method, and is highly producible in mass production. However, since an amorphous silicon semiconductor is inferior in physical properties such as conductivity to a silicon semiconductor having crystallinity, in order to obtain higher speed characteristics in the future, a method for manufacturing a TFT made of a silicon semiconductor having crystallinity There was a strong demand for the establishment of. on the other hand,
As the latter silicon semiconductor having crystallinity, polycrystalline silicon, microcrystalline silicon, amorphous silicon containing a crystalline component, semi-amorphous silicon having an intermediate state between crystalline and amorphous are known. There is.

The following methods are known as conventional methods for obtaining a thin film silicon semiconductor having crystallinity.

(1) A method of directly forming a crystalline silicon semiconductor film at the time of film formation (2) A method of forming an amorphous silicon semiconductor film and making it crystalline by the energy of laser light (3) Method of Forming Amorphous Silicon Semiconductor Film and Making Crystallinity by Applying Thermal Energy However, these methods have the following problems.

In the case of the above method (1), crystallization progresses at the same time as the film forming step. Therefore, in order to obtain crystalline silicon having a large particle size, it is indispensable to make the silicon film thick. However, it is technically difficult to uniformly form a film having good semiconductor physical properties over the entire surface of the substrate. Also,
Since the film forming temperature is as high as 600 ° C. or higher, there is a cost problem that an inexpensive glass substrate cannot be used.

In the case of the above method (2),
Since the crystallization phenomenon of the melting and solidification process is used, the grain boundaries are well processed despite the small grain size, and high quality crystals can be obtained.
Taking the most commonly used excimer laser as an example, the throughput is low due to the small irradiation area of the laser beam, and the stability of the laser is not sufficient to uniformly process the entire surface of a large area substrate. There is a problem.
Therefore, there is a strong sense of next-generation technology.

The method (3) has an advantage of being able to deal with a large area as compared with the methods (1) and (2), but has a high temperature of 600 ° C. or higher for tens of hours for crystallization. There is a problem that a heat treatment for a long time is required. That is, in consideration of the use of an inexpensive glass substrate and the improvement of throughput, there is a problem that it is necessary to simultaneously solve the conflicts of lowering the heating temperature and crystallization in a short time. In addition, since this method utilizes the solid-phase crystallization phenomenon, some crystal grains spread parallel to the substrate surface and have a grain size of several μm, but the grown crystal grains collide with each other to form grain boundaries. Is formed and its grain boundaries act as trap levels for carriers,
This is a major cause of lowering the mobility of the TFT.

Therefore, two methods have been proposed for solving the above-mentioned problems of the grain boundaries by utilizing the method (3) (Japanese Patent Laid-Open Nos. 5-55142 and 5-136).
048).

In these proposed methods, a foreign particle which becomes a nucleus of crystal growth is introduced into the amorphous silicon film, and then a heat treatment is carried out to obtain a large grain size crystalline silicon film having the foreign particle as a nucleus. ing. More specifically, the former (JP-A-5-5514)
In the method of No. 2), impurities such as silicon (Si ⁺ ) are introduced into the amorphous silicon film by the ion implantation method, and heat treatment is performed to obtain a polycrystalline silicon film having crystal grains with a grain size of several μm. On the other hand, in the latter method (Japanese Patent Laid-Open No. 5-136048), Si particles having a particle diameter of 10 to 100 nm are blown together with high-pressure nitrogen gas onto the amorphous silicon film to form growth nuclei. Thus, both of them form a semiconductor element by using a high-quality crystalline silicon film in which a foreign substance is selectively introduced into an amorphous silicon film and crystal growth is performed by using the foreign substance as a nucleus.

However, in the two methods proposed above,
Since the introduced foreign matter acts only as growth nuclei, it is effective in controlling nucleation and crystal growth direction during crystal growth, but there are still problems with the heat treatment process for crystallization. There is. For example, in the method of JP-A-5-55142, crystallization is performed by heat treatment at a temperature of 600 ° C. for 40 hours. Further, in the method of Japanese Patent Laid-Open No. 5-136048, heat treatment is performed at a heating temperature of 650 ° C or higher. Therefore, these methods are based on SOI (Semiconductor on Insu
However, it is difficult to form a crystalline silicon film on an inexpensive glass substrate to form a semiconductor element. For example, Corning 7059 glass or the like is used for an active matrix type liquid crystal display device, which has a glass strain point of 593 ° C.
There is a problem with heating above 0 ° C.

In order to solve the above-mentioned various problems, the inventors of the present invention have made it possible to reduce the temperature required for crystallization and to shorten the processing time, and further, to minimize the influence of grain boundaries. A method for producing a crystalline silicon thin film was found.

According to the research conducted by the inventors of the present application, when a trace amount of a metal element such as nickel, palladium or lead is introduced into the surface of an amorphous silicon film and heated, crystallization is performed by heat treatment at 550 ° C. for about 4 hours. It turns out to be possible. It is considered that this mechanism is that crystal nucleation with a metal element as a nucleus occurs at an early stage, and then the metal element serves as a catalyst to promote crystal growth and crystallization rapidly progresses. From this point of view, these metal elements are hereinafter referred to as catalyst elements.

By the way, in the crystalline silicon film which is crystallized by promoting crystallization by these catalytic elements, the crystalline silicon film obtained by crystallizing the amorphous silicon film by a usual solid phase growth method has a twin structure. On the other hand, it is composed of many needle-like crystals or columnar crystals, and the inside of each needle-like crystal or columnar crystal is in an ideal single crystal state.

When a TFT is manufactured by using such a crystalline silicon film as an active region, the field effect mobility is 1.2 compared with the case where a crystalline silicon film formed by a usual solid phase growth method is used. The difference can be made more remarkable by irradiating laser light or intense light to promote its crystallinity. The reason for this is considered as follows. That is, when the crystalline silicon film is irradiated with laser light or intense light, the grain boundary parts are intensively processed due to the difference in melting points between the crystalline silicon film and the amorphous silicon film. Since the crystalline silicon film formed by the solid-phase growth method of 1) has a twin crystal structure, twin crystal defects are left inside the crystal grain boundaries even after irradiation with laser light or intense light. On the other hand, the crystalline silicon film crystallized by introducing the catalytic element is composed of needle-like crystals or columnar crystals, and since the inside is in a single crystal state, it is crystallized by laser light or intense light irradiation. This is because when the boundary portion is processed, a crystalline silicon film that is almost in a single crystal state is obtained over the entire surface of the substrate.

In order to introduce a small amount of the catalytic element as described above, plasma treatment, ion implantation, or a method of applying a solution or compound containing the catalytic element can be used. Note that plasma treatment is a treatment in which a material containing a catalytic element is used as an electrode of a plasma CVD apparatus and plasma is generated in an atmosphere such as nitrogen or hydrogen to add the catalytic element to the amorphous silicon film. is there.

[0017]

However, the presence of a large amount of the above catalytic element such as nickel in a semiconductor unfavorably impairs the reliability and electrical stability of a device using these semiconductors. . That is, the catalyst element such as nickel that promotes the crystallization is necessary when crystallizing the amorphous silicon, but it is desirable that the crystallized silicon film is not contained as much as possible. .

Therefore, it is necessary to select a catalyst element that has a strong tendency to be inactive in crystalline silicon and at the same time reduce the amount of the catalyst element necessary for crystallization as much as possible to perform crystallization in the minimum amount. There is. For this purpose, it is necessary to precisely control the amount of the catalyst element added, and
It is essential to ensure the uniformity of the amount of the catalyst element added in the processing method within the substrate and the stability (reproducibility) between the substrates.

When nickel is used as the catalytic element, nickel is added by the above-mentioned plasma treatment after the formation of the amorphous silicon film to form a crystalline silicon film, and the crystallization process is examined in detail. The following matters were found.

(1) When nickel was introduced into the amorphous silicon film by the plasma treatment, nickel had already penetrated to a considerable depth in the amorphous silicon film before the heat treatment.

(2) In crystallization, the initial generation of crystal nuclei starts from the surface on which nickel is introduced.

(3) When the crystalline silicon film obtained by crystallizing the amorphous silicon film into which nickel was introduced by the plasma treatment was irradiated with laser light, excessive nickel was deposited on the surface of the crystalline silicon film.

From the above, it can be concluded that all the nickel introduced by the plasma treatment is not functioning effectively. That is, it is considered that there is nickel that does not function sufficiently even if a large amount of nickel is introduced. Furthermore, from this, it is considered that the point or plane where nickel and silicon are in contact functions during the low temperature crystallization. Therefore, it can be concluded that nickel must be dispersed as finely as possible in atomic form. That is, it can be concluded that it is necessary to disperse nickel as atomically as possible in the vicinity of the surface of the amorphous silicon film within a range where low temperature crystallization is possible, in a dispersed state.

By the way, as a method of introducing a very small amount of nickel (catalyst element) near the surface of the amorphous silicon film,
There is a method of applying a solution of a catalytic element in a solvent or a compound to an amorphous silicon film. With this method, by controlling the nickel concentration in the solution or compound, the amount of nickel introduced into the amorphous silicon film can be easily controlled, and the minimum amount necessary for crystallization is required. It becomes possible to add the catalytic element in an amount of Further, when a crystalline silicon film crystallized by introducing a catalytic element by this method is irradiated with laser light, nickel is not deposited and high-quality crystalline silicon is obtained.

However, the method of coating the amorphous silicon film with the catalyst element dissolved in the solvent or compound has a problem that the uniformity in the substrate is not good. That is,
Various methods such as a method of uniformly applying with a spinner and drying, and a method of dipping the substrate directly into the solution and then drying with an air knife were tried.
A variation in the amount of added nickel of ± 10 to 20% was observed on the square substrate. In addition, if the amount of added nickel is highly non-uniform in the substrate, a region where crystal growth does not occur locally due to an insufficient amount of nickel, or a region where nickel is present in a large amount so as to adversely affect the semiconductor element, occur. Therefore, it is difficult to form hundreds of thousands of TFTs on one substrate with good uniformity, like an active matrix substrate of a liquid crystal display device. Further, in recent years, in response to the demand for cost reduction and large area of the device, a semiconductor device having excellent uniformity and stability enough to handle a glass substrate of 400 nm square or more and a manufacturing method thereof are required.

The present invention has been made in order to solve the problems of the prior art as described above, and can perform heat treatment at a temperature of 600 ° C. or less for a short time, and a catalytic element can be uniformly deposited on a substrate surface with a minimum amount. An object of the present invention is to provide a high-performance semiconductor device which can be applied to a large-area substrate by introduction, has high stability and productivity, and which can obtain crystallinity higher than that obtained by heat treatment, and a manufacturing method thereof. And

[0027]

The semiconductor device of the present invention comprises:
What is claimed is: 1. A semiconductor device comprising an active region made of a crystalline silicon film formed on a substrate having an insulating surface, the active region being formed by vapor deposition of a catalytic element for promoting crystallization on an amorphous silicon film. The amorphous silicon film is crystal-grown by performing heat treatment and laser light or intense light irradiation on the amorphous silicon film, whereby the above object is achieved.

The semiconductor device of the present invention is a semiconductor device in which an active region made of a crystalline silicon film is formed on a substrate having an insulating surface, and the active region is an amorphous silicon film. A region in which the catalytic element is selectively introduced by selectively introducing a catalytic element that promotes crystallization by a vapor deposition method and performing heat treatment and laser light or intense light irradiation on the amorphous silicon film. The crystal growth is performed in the peripheral portion of the substrate in a direction substantially parallel to the surface of the substrate, thereby achieving the above object.

The catalyst elements are Ni, Co, Pd and P.
It can be one or more kinds of elements selected from t, Cu, Ag, Au, In, Sn, P, As, Sb and Al.

The concentration of the catalytic element in the active region is 1 × 10 ¹⁶ atoms / cm ³ to 1 × 10 ¹⁹ at.
It is preferably oms / cm ³ .

A method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device in which an active region made of a crystalline silicon film is formed on a substrate having an insulating surface, and is amorphous on the substrate. A step of forming a porous silicon film, and a step of depositing a thin film containing a catalytic element that promotes crystallization of the amorphous silicon film before or after the step of forming the amorphous silicon film; The method includes the steps of crystallizing the silicon film by heating, and the step of irradiating the crystallized silicon film with laser light or strong light to promote crystallinity, whereby the above object is achieved.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which an active region made of a crystalline silicon film is formed on a substrate having an insulating surface, and is amorphous on the substrate. Before and after the step of forming a porous silicon film and the step of forming the amorphous silicon film, a thin film containing a catalytic element that promotes crystallization of the amorphous silicon film is in contact with the amorphous silicon film. And the step of selectively vapor-depositing the amorphous silicon film and heating the amorphous silicon film so that the amorphous silicon film is substantially parallel to the substrate surface at the periphery of the region in contact with the thin film containing the catalytic element. Direction and the crystallinity of the region where crystal growth is performed in a direction substantially parallel to the substrate surface by irradiating the silicon film crystallized by heating with laser light or strong light. Including the step of promoting The above-mentioned object can be achieved by the.

When depositing a thin film containing a catalytic element that promotes crystallization of the amorphous silicon film, it is desirable that the distance between the deposition source containing the catalytic element and the substrate is 20 cm or more. .

When depositing a thin film containing a catalytic element that promotes crystallization of the amorphous silicon film, a large amount of deposition on the substrate is suppressed between the deposition source containing the catalytic element and the substrate. It is desirable to provide a threshold plate for vapor deposition.

As the catalyst element, Ni, Co, P
d, Pt, Cu, Ag, Au, In, Sn, P, As,
One or more elements selected from Sb and Al can be used.

[0036]

In the present invention, a thin film containing a catalytic element is formed on the surface of the amorphous silicon film by vapor deposition as a method of introducing the catalytic element that promotes crystallization of the amorphous silicon film. In this method, the catalytic element is introduced in contact with the surface of the amorphous silicon film and does not penetrate deeply into the film unlike the plasma treatment method, so that the catalytic element is prevented from existing in a state where it does not contribute to crystallization. be able to. Therefore, when the catalyst element is introduced by the vapor deposition method, deposition of the catalyst element does not occur even if irradiation with laser light or intense light is performed.

Since the catalyst element is introduced into the amorphous silicon film by forming a thin film containing the catalyst element,
Compared with the method of applying a solution or compound in which the catalytic element is dissolved, the variation in the amount of catalytic element added in the substrate can be made smaller, and in the experiments conducted by the inventors of the present invention, it was within ± 5% for a 127 mm square substrate. confirmed. Further, even when the substrate has a large area, it can be dealt with by enlarging the vapor deposition apparatus, and it is considered that the substantial variation in the amount of the catalytic element added at that time is not much different from that of the 127 mm square substrate. Therefore, the catalytic element can be uniformly introduced over the entire surface of the substrate, and a semiconductor device excellent in uniformity and stability can be manufactured on a large-area substrate.

When a heat treatment is carried out by selectively introducing a catalyst element that promotes crystallization into a part of the amorphous silicon film,
Crystal growth occurs laterally (direction substantially parallel to the substrate surface) from the introduced region. Inside this region, needle-like crystals or columnar crystals with the growth direction aligned in one direction (horizontal direction) are crowded together, and compared with the region where the crystal growth nuclei randomly occur due to the direct introduction of the catalytic element. This is a region where the crystallinity is remarkably good. When laser light or intense light is irradiated to the region where crystal growth has occurred in the lateral direction, the crystal grain boundaries between needle-like crystals or columnar crystals are processed, and a crystalline silicon film close to a single crystal can be obtained. it can.

At this time, if the vapor deposition method is used as the method of introducing the catalyst element, the lateral crystal growth can be efficiently performed. The catalytic element that contributes to crystallization exists at the tip of the needle crystal or columnar crystal, that is, the tip of crystal growth. Therefore, if the catalytic element efficiently functions for crystallization, the catalytic element exists only in the crystal growth portion where crystallization is performed and does not exist in the already crystallized lateral crystal growth region. According to the experiments conducted by the inventors of the present application, when nickel is introduced as a catalytic element, the nickel concentration in the lateral crystal growth region is 1 × 1 when the plasma treatment method is used.
While it was 0 ^{18 to} 5 × 10 ¹⁸ atoms / cm ^3, it was 5 × 10 ¹⁶ to 1 × 10 ¹⁷ a when the vapor deposition method was used.
The value was as small as one digit or more, toms / cm ³ .

The lower the concentration of the catalyst element introduced into the amorphous silicon film is, the more preferable it is. However, if the concentration is too low, the function of promoting the crystallization of the amorphous silicon film does not work. According to the investigation by the inventors of the present application, the minimum concentration of the catalyst element causing crystallization was 1 × 10 ¹⁶ atoms / cm ³ , and at the concentration below this, crystal growth by the catalyst element did not occur. On the other hand, if the concentration of the catalytic element is too high, the semiconductor element is adversely affected. A phenomenon that can be considered when the concentration of the catalytic element is high is mainly an increase in leak current in the off region of the TFT. It is considered that this is because the catalytic element is due to the impurity level formed in the silicon film, and a tunnel current is generated through the level. As a result of examination by the inventors of the present application, the maximum concentration at which the catalytic element does not adversely affect the semiconductor element was 1 × 10 ¹⁹ atoms / cm ³ . Therefore, the concentration of the catalytic element in the film is 1 × 10 ¹⁶ to 1 ×
If it is 10 ¹⁹ atoms / cm ³ , the catalytic element functions most effectively.

When the catalytic element is introduced in the above concentration range,
It is necessary to devise the vapor deposition method in order to introduce it with good controllability by the vapor deposition method. In order to control such a minute vapor deposition amount, it is difficult to control by the film formation time. The inventors of the present application used nickel as a vapor deposition source (catalyst element) and tried adding a small amount by increasing the distance between the vapor deposition source and the substrate. At that time, the vapor deposition time was fixed at 5 seconds in consideration of the limit of time control. The reason for this is that if the vapor deposition time is shorter than that, there is a problem in reproducibility, and it is considered difficult to employ it in the actual manufacturing process. As a result, the amount of vapor deposition (the amount of nickel introduced) is inversely proportional to the square of the distance between the vapor deposition source and the substrate, and the surface distribution of nickel is 1 × 10 ¹⁴ atoms / cm 2 at the position where the distance between the vapor deposition source and the substrate is 20 cm. ^{Was 3} . When this nickel is uniformly diffused into the amorphous silicon film having a thickness of 100 nm, the nickel concentration in the film is 1 × 10 ^19.
It becomes atoms / cm ³ . Therefore, by setting the distance between the vapor deposition source and the substrate to be 20 cm or more, it is possible to introduce the catalyst element at a concentration in the amorphous silicon film of 1 × 10 ¹⁹ atoms / cm ³ or less.

As a method of introducing a trace amount of the catalytic element by the vapor deposition method, a method of providing a threshold plate between the vapor deposition source and the substrate for suppressing a large amount of vapor deposition is also effective. in this way,
By devising the shape of the threshold plate, it is possible to control the amount of vapor deposition desired. The inventors of the present application have confirmed that nickel can be introduced into the amorphous silicon film at 1 × 10 ¹⁹ atoms / cm ³ or less with good control by using a SUS mesh-like threshold plate.

When Ni is used as the above-mentioned catalyst element, the most remarkable effect can be obtained.
o, Pd, Pt, Cu, Ag, Au, In, Sn, P,
As, Sb and Al can be used. One or more kinds of elements selected from these catalytic elements have an effect of promoting crystallization even in a small amount (1 × 10 ¹⁶ atoms / cm ³ or more), so that there is no possibility of adversely affecting the semiconductor element.

The substrate having an insulative surface mentioned here is an insulative substrate itself or a substrate having an insulative film on the surface regardless of the presence or absence of insulative property.

[0045]

Embodiments of the present invention will be described below with reference to the drawings. The TFTs obtained in the following examples
Can be used not only in a driver circuit and a pixel portion of an active matrix type liquid crystal display device but also in an element in which a CPU is formed on the same substrate. Also, the application range of these TFTs is not limited to liquid crystal display devices,
It can be used for all semiconductor devices generally called thin film integrated circuits.

(Example 1) In this example, a case where the present invention is applied to an N-type TFT formed on a glass substrate will be described.

FIG. 1E shows a sectional view of the TFT of this embodiment. In this TFT, a base film 102 made of silicon oxide is formed on a glass substrate 101 in order to prevent diffusion of impurities from the substrate, and source / drain regions 111 and 112 and a channel region 11 are formed thereon.
An active region 103n made of crystalline silicon having 0 is formed, and a gate insulating film 10 made of silicon oxide is formed thereon.
7 are formed. A gate electrode 108 made of an aluminum film is formed thereon so as to face the channel region 110.
Is formed, and an oxide layer 109 formed by anodizing the gate electrode is formed on the surface thereof. An interlayer insulating film 113 made of silicon oxide or silicon nitride is formed so as to cover it, and further, electrodes and wirings 114, 115 of the TFT made of a two-layer film of a metal material such as titanium nitride and aluminum are formed thereon. The gate insulating film 107 and the interlayer insulating film 113 are electrically connected to the source / drain regions 111 and 112 through the contact holes.

This TFT can be manufactured as follows. FIG. 1 is a cross-sectional view showing the outline of the manufacturing process of the TFT of this embodiment, and the process proceeds in the order of (A) → (E).

First, as shown in FIG. 1A, a glass substrate 101 having a thickness of 20 is formed by, for example, a sputtering method.
A base film 102 of about 0 nm made of silicon oxide is formed. A first intrinsic (I-type) amorphous silicon film 103 having a thickness of 25 to 100 nm, for example 80 nm, is formed thereon by a low pressure CVD method or a plasma CVD method.

Next, an extremely thin film 105 of nickel is formed by the vacuum evaporation method. At this time, the surface density of nickel on the substrate was set to 1 × 10 ¹¹ to 1 × 10 ¹⁴ atoms / cm ³ . In this example, a mesh sill plate made of SUS was installed between the vapor deposition source (nickel) and the substrate, the degree of vacuum during vapor deposition was 1 × 10 ⁻⁴ Pa, and the distance between the vapor deposition source and the substrate was set. Was set to 20 cm and vapor deposition was performed for 5 seconds. The area density of nickel at this time was about 1 × 10 ¹² atoms / cm ³ .

Here, strictly speaking, the reference plane of the substrate when the distance is 20 cm is strictly the amorphous silicon film 1 on the substrate 101.
However, since the underlayer film 102 and the amorphous silicon film 103 are thin, they may be the surface of the substrate 101. In addition, the conditions for setting the distance to 20 cm are:
This is in the above-described processing state, and may be changed to some extent depending on the type of catalyst element, the threshold plate, the degree of vacuum, the processing time, and the like.

This is heated under a hydrogen reducing atmosphere or an inert atmosphere at a heating temperature of 520 to 580 ° C. for several hours to several tens hours,
For example, it is annealed at 550 ° C. for 8 hours to be crystallized. At this time, the nickel 105 deposited on the surface serves as a nucleus,
Crystallization of the amorphous silicon film 103 occurs in the direction perpendicular to the substrate 101 to form a crystalline silicon film 103a. Further, at the same time as crystallization, nickel is uniformly diffused in the film, and the nickel concentration in the crystalline silicon film 103a is 6 ×.
It was 10 ¹⁷ atoms / cm ³ .

Subsequently, as shown in FIG. 1B, laser light is irradiated to promote the crystallinity of the crystalline silicon film 103a. Although a XeCl excimer laser (wavelength 308 nm, pulse width 40 nsec) was used as the laser here, other lasers may be used. Laser light irradiation conditions are energy density of 200 to 400 mJ / cm
² , for example, 300 mJ / cm ² and the substrate is 20 at the time of irradiation.
It was heated to 0 to 450 ° C, for example 400 ° C.

Next, as shown in FIG. 1C, the crystalline silicon film 103a in an unnecessary portion is removed to perform element isolation, and the active region (source / drain region 11) of the TFT is later formed.
1, 112, the island-shaped crystalline silicon film 103n to be the channel region 110) is formed.

Next, as shown in FIG. 1D, a thickness of 20 to 70 is formed so as to cover the crystalline silicon film 103n which becomes the active region.
A gate insulating film 107 made of a silicon oxide film having a thickness of 150 nm, for example, 100 nm is formed. Here, the substrate temperature is 150 to 600 ° C., preferably 300 to 450, together with oxygen, by the RF plasma CVD method using TEOS as a raw material.
Decomposed and deposited at ℃. As another method, TEOS may be used as a raw material and formed at a substrate temperature of 350 to 600 ° C., preferably 400 to 550 ° C. by a low pressure plasma CVD method or an atmospheric pressure CVD method together with ozone gas.

Next, after the film formation, in order to improve the bulk characteristics of the gate insulating film itself and the interface characteristics between the crystalline silicon film and the gate insulating film, 400 to 400 nm in an inert gas atmosphere.
Annealing was performed at 600 ° C. for 30 to 60 minutes.

Subsequently, an aluminum film having a thickness of 400 to 800 nm, for example 600 nm, is formed by the sputtering method. This aluminum film is patterned to form a gate electrode 108, and the surface thereof is further anodized to form an oxide layer 109 on the surface. This anodization is
The reaction was terminated by carrying out in an ethylene glycol solution containing tartaric acid in an amount of 1 to 5%, initially increasing the voltage to 220 V with a constant current, and maintaining the state for 1 hour. The thickness of the obtained oxide layer 109 was 200 nm. Here, since the thickness of the oxide layer 109 forms the offset gate region in the subsequent ion doping process, the length of the offset gate region can be determined by this anodic oxidation process. Further, by forming the oxide layer 109, it is possible to prevent hillocks from being generated in the aluminum film which forms the gate electrode 108 in a later step.

Then, an impurity (phosphorus) is implanted into the active region 103n by ion doping using the gate electrode 108 and the oxide layer 109 around it as a mask. Phosphine (PH ₃ ) is used as a doping gas,
The acceleration voltage is 60 to 90 keV, for example 80 keV,
The dose amount is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 2 ×
It is 10 ¹⁵ cm ^-2 . By this step, the regions 111 and 112 into which the impurities are implanted will later become the source / drain regions 111 and 112 of the TFT, and the regions which are masked by the gate electrode 108 and the oxide layer 109 and into which the impurities are not implanted will be the TFTs later. Of the channel region 110.

After that, annealing is performed by laser light irradiation to activate the ion-implanted impurities, and at the same time, the crystallinity of a portion of the active region 103n whose crystallinity is deteriorated in the impurity-implantation step is improved. Here, as a laser, a XeCl excimer laser (wavelength 308 nm,
A pulse width of 40 nsec) was used, but another laser may be used. The irradiation condition of the laser light is such that the energy density is 150 to 400 mJ / cm ² , and preferably 200 to ²
It is 50 mJ / cm ² . N formed in this way
The sheet resistance of the type impurity (phosphorus) regions 111 and 112 is 2
It was 00 to 800 Ω / □.

Subsequently, an interlayer insulating film 113 made of a silicon oxide film or a silicon nitride film having a thickness of about 600 nm is formed by the plasma CVD method. Here, in the case of forming a silicon oxide film, TEOS is used as a raw material and is decomposed / deposited with RF by an RF plasma CVD method, or TEOS is used as a raw material and is decomposed with ozone gas by a low pressure plasma CVD method or an atmospheric pressure CVD method. When formed by the deposition method, a good interlayer insulating film having excellent step coverage can be obtained. When forming a silicon nitride film,
Forming a film by plasma CVD using SiH ₄ and NH ₃ as source gases has the effect of reducing dangling bonds in the crystalline silicon film and can improve TFT characteristics.

Next, as shown in FIG. 1E, a contact hole is formed in the interlayer insulating film 113, and a TFT is formed by a two-layer film of a metal material such as titanium nitride and aluminum.
Electrodes / wirings 114 and 115 are formed and connected to the source / drain regions 111 and 112. Finally, anneal at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm to complete the TFT.
To complete.

The obtained TFT can be used in a peripheral driver circuit of an active matrix type liquid crystal display device, a switching element of a pixel portion, or a thin film integrated circuit including a CPU. When used as a switching element for a pixel electrode, the electrode 114 or 115 is used as an IT element.
It is connected to a pixel electrode made of a transparent conductive film such as O, and a signal is input from the other electrode. When used in a thin film integrated circuit such as a CPU, a contact hole is formed also on the gate electrode 108, and a necessary wiring is formed to be connected to the gate electrode 108.

The N-type TFT thus obtained has good characteristics of field effect mobility of 120 to 150 cm ² / Vs, S value of 0.2 to 0.4 V / digit, and threshold voltage of 2 to 3 V. Indicated. Variations in TFT characteristics within the substrate were within ± 12% in field-effect mobility and within ± 8% in threshold voltage, and it was possible to manufacture with good uniformity and stability.

(Embodiment 2) In this embodiment, a case where the present invention is applied to a P-type TFT formed on a glass substrate will be described.

FIG. 3F shows a sectional view of the TFT of this embodiment. In this TFT, a base film 202 made of silicon oxide is formed on a glass substrate 201 in order to prevent diffusion of impurities from the substrate, and source / drain regions 211 and 212 and a channel region 21 are formed thereon.
An active region 203p made of crystalline silicon having 0 is formed, and a gate insulating film 20 made of silicon oxide is formed thereon.
7 are formed. A gate electrode 208 made of an aluminum film is formed thereon so as to face the channel region 210.
Is formed, and an interlayer insulating film 213 made of silicon oxide or silicon nitride is formed so as to cover it. Further thereon, electrodes / wirings 214 and 215 of a TFT made of a two-layer film of a metal material such as titanium nitride and aluminum.
Are formed, the gate insulating film 207 and the interlayer insulating film 2 are formed.
The source / drain regions 211 and 212 are electrically connected to each other through the contact holes formed at 13.

This TFT can be manufactured as follows. FIG. 2A is a plan view showing the outline of the manufacturing process of the TFT of this embodiment. FIG. 3 is a sectional view taken along the line AA ′ of FIG. 2A, and the process proceeds in the order of (A) → (F).

First, as shown in FIG. 3A, a glass substrate 201 having a thickness of 20 is formed by, for example, a sputtering method.
A base film 202 of about 0 nm made of silicon oxide is formed. A first intrinsic (I-type) amorphous silicon film 203 having a thickness of 25 to 100 nm, for example 80 nm, is formed thereon by a low pressure CVD method or a plasma CVD method.

Next, the mask 204 is formed of an insulating thin film such as a silicon oxide film or a silicon nitride film having a thickness of about 50 nm, and the mask 204 is selectively removed to form the slit-shaped opening 20.
0 is set. Seeing this state from the top of the board,
As shown in (A), the amorphous silicon film 203 is exposed in a slit shape in the region 200 where the opening is provided, and the other part is masked. In FIG. 2A, a cross section taken along line AA ′ corresponds to FIG. 3E or 3F. In this embodiment, the TFT is manufactured with the arrangement shown in FIG. 2A, but the TFT can be manufactured with no problem by the same method even with the arrangement shown in FIG. 2B. In addition, in FIGS. 2 (A) and (B), 21
Reference numerals 1 and 212 are the source / drain regions of the TFT, 210 is the channel region, and 206 is the crystal growth direction.

After forming the mask 204, as shown in FIG. 3B, an ultrathin nickel film 205 is formed by a vacuum evaporation method.
To form. At this time, the surface density of nickel on the substrate is 5
It was set to be 10 ^{10 to} 5 × 10 ¹³ atoms / cm ³ . In this embodiment, the degree of vacuum during vapor deposition is 1 × 10 ⁻⁴ P.
a, vapor deposition was performed for 5 seconds with the distance between the vapor deposition source and the substrate being 40 cm. The area density of nickel at this time is 2 × 1
It was about 0 ¹³ atoms / cm ³ . At the portion of the region 200 where the slit-shaped opening is provided, the vapor-deposited nickel thin film 205 is in contact with the amorphous silicon film 203, which means that the trace amount of nickel was selectively added.

Next, this is annealed in a hydrogen reducing atmosphere or an inert atmosphere at a heating temperature of 550 ° C. for 16 hours to be crystallized. At this time, in the region 200 where the trace amount of nickel is selectively added, crystallization of the amorphous silicon film 203 occurs in the direction perpendicular to the substrate 201,
The crystalline silicon film 203a is formed. Further, at the same time as crystallization, nickel is uniformly diffused in the film, and the nickel concentration in the crystalline silicon film 203a is 4 × 10 ¹⁸ atoms /
It became cm ³ . On the other hand, in the peripheral region of the region 200, crystal growth occurs in the lateral direction (the direction parallel to the substrate 201) from the region 200, as shown by an arrow 206 in FIG.
A crystalline silicon film 203b is formed which is laterally grown. In the other regions, the amorphous silicon film is left as it is as the amorphous silicon film 203. The concentration of nickel in the crystalline silicon film 203b grown in the lateral direction is 2 ×
The value is about 10 ¹⁷ atoms / cm ^3, which is about an order of magnitude smaller than that of the crystalline silicon film 203 a which is crystal-grown by directly adding nickel. In the above crystal growth,
The crystal growth distance in the direction parallel to the substrate indicated by the arrow 206 was about 80 μm.

After that, the mask 204 is removed and laser light is irradiated to promote the crystallinity of the crystalline silicon film 203b. Here, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) is used as the laser, and the irradiation conditions are as follows: the substrate is heated to 200 to 450 ° C., for example 350 ° C., and the energy density is 200 to 400 mJ / cm ² ,
For example, irradiation was performed at 250 mJ / cm ² .

Next, as shown in FIG. 3D, unnecessary portions of the crystalline silicon film 203 are removed to perform element isolation, and the active regions (source / drain regions 21) of the TFT are later removed.
1, 212, an island-shaped crystalline silicon film 203p to be the channel region 210) is formed.

After that, as shown in FIG. 3E, a thickness of 20 is formed so as to cover the crystalline silicon film 203p which will be the active region.
A gate insulating film 207 made of a silicon oxide film having a thickness of 150 nm, for example 100 nm, is formed. Here, the gate insulating film 207 is formed by a sputtering method. Silicon oxide is used as a target, and the substrate temperature is 200 to 40.
It is heated to 0 ° C., for example 350, and the sputtering atmosphere uses oxygen and argon, and argon / oxygen = 0 to 0.
5, for example, 0.1 or less.

Subsequently, a 400 nm-thickness aluminum film is formed by a sputtering method, and this is patterned to form a gate electrode 208.

Then, an impurity (boron) is implanted into the active region 203p by ion doping using the gate electrode 208 as a mask. Diborane (B ₂ H ₆ ) is used as a doping gas, the acceleration voltage is 40 to 80 keV,
For example, it is set to 65 keV and the dose amount is 1 × 10 ¹⁵ to 8 × 1.
It is set to 0 ¹⁵ cm ^-2 , for example, 5 × 10 ¹⁵ cm ^-2 . By this step, the regions 211 and 212 into which the impurities are implanted are
The source / drain regions 211 and 212 of the TFT will be formed later, and the regions masked by the gate electrode 208 and not implanted with impurities will be the channel regions 210 of the TFT later.

After that, annealing is performed by laser light irradiation to activate the ion-implanted impurities, and at the same time, the crystallinity of a portion of the active region 203p where the crystallinity is deteriorated in the impurity-implantation step is improved. Here, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) is used as the laser, and the energy density is 200 to
400 mJ / cm ^2, was irradiated with for example 250 mJ / cm ^2. The sheet resistance of the N-type impurity (phosphorus) regions 211 and 212 thus formed was 500 to 900 Ω / □.

Subsequently, an interlayer insulating film 213 made of a silicon oxide film having a thickness of about 600 nm is formed by the plasma CVD method. Here, the silicon oxide film is decomposed / deposited by a RF plasma CVD method with TEOS as a raw material or oxygen, or by a low pressure plasma CVD method or an atmospheric pressure CVD method with TEOS as a raw material together with ozone gas. When formed, a good interlayer insulating film having excellent step coverage can be obtained.

Next, as shown in FIG. 3F, a contact hole is formed in the interlayer insulating film 213, and a TFT is formed by a two-layer film of a metal material such as titanium nitride and aluminum.
Electrodes / wirings 214 and 215 are formed and connected to the source / drain regions 211 and 212. Finally, anneal at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm to complete the TFT.
To complete.

When this TFT is used as a switching element of a pixel electrode, the electrode 214 or 215 is used as an IT element.
It is connected to a pixel electrode made of a transparent conductive film such as O, and a signal is input from the other electrode. When used in a thin film integrated circuit such as a CPU, a contact hole is formed also on the gate electrode 208, and a necessary wiring is formed to be connected to the gate electrode 208.

The P-type TFT thus obtained has good field effect mobility of 120 to 140 cm ² / Vs, S value of 0.3 to 0.5 V / digit, and threshold voltage of −2 to −3 V. Characterized. The variation in TFT characteristics within the substrate was within ± 10% in field effect mobility and within ± 5% in threshold voltage, and it was possible to manufacture with good uniformity and stability.

(Embodiment 3) In this embodiment, an N-type TFT and a P-type TFT, which are used in a peripheral drive circuit of an active matrix type liquid crystal display device or a general thin film integrated circuit, are formed in a complementary type on a glass substrate. A case in which the present invention is applied to a circuit having the above CMOS structure will be described.

FIG. 5E shows a sectional view of a circuit having a CMOS structure of this embodiment. In this circuit, in order to prevent diffusion of impurities from the substrate on the glass substrate 301,
A base film 302 made of silicon oxide is formed. N-type T made of crystalline silicon having source / drain regions 312, 313 and a channel region 310 thereon.
FT active region 303n and source / drain region 31
4, 315, and an active region 303p of an N-type TFT made of crystalline silicon having a channel region 311 are formed.

A gate insulating film 307 made of silicon oxide is formed thereon, and gate electrodes 308, 30 made of an aluminum film are formed so as to face the channel regions of the respective TFTs.
9 is formed. An interlayer insulating film 316 made of silicon oxide is formed so as to cover it, and TFT electrodes / wirings 317, 318, 319 made of a two-layer film of a metal material such as titanium nitride and aluminum are further formed thereon. Through the contact hole formed through the gate insulating film 307 and the interlayer insulating film 316.
The drain regions 312, 313, 314, and 315 are electrically connected.

This CMOS structure circuit can be manufactured as follows. FIG. 4 shows the CMO of this embodiment.
It is a top view which shows the outline of the manufacturing process of S structure circuit. Figure 5
4B is a sectional view taken along the line BB ′ of FIG. 4, and the process proceeds in the order of (A) → (E).

First, as shown in FIG. 5A, a glass substrate 301 having a thickness of 10 is formed by, for example, a sputtering method.
A base film 302 made of silicon oxide having a thickness of about 0 nm is formed. On top of that, a thickness of 25 to 100 is formed by a low pressure CVD method.
nm (eg, 50 nm) intrinsic (I-type) amorphous silicon film 3
03 is deposited.

Next, a mask 304 is formed of an insulating thin film such as a silicon oxide film or a silicon nitride film having a thickness of about 50 nm, and the mask 304 is selectively removed to remove the catalyst element injection port 300.
Open. When this state is viewed from the upper surface of the substrate, as shown in FIG. 4, the amorphous silicon film 303 is exposed through the catalytic element injection port 300, and the other portions are masked.

After the mask 304 is provided, FIG.
As shown in FIG.
5 is formed. At this time, the surface density of nickel on the substrate is
It was set to be 5 × 10 ^{10 to} 5 × 10 ¹³ atoms / cm ³ . In this embodiment, the degree of vacuum during vapor deposition is 1 × 10 ⁻⁴ P.
a, vapor deposition was performed for 5 seconds with the distance between the vapor deposition source and the substrate being 60 cm. The surface density of nickel at this time is 1 × 1
It was about 0 ¹³ atoms / cm ³ . In the region 300 where the catalyst element injection port is provided, the deposited nickel thin film 305 is in contact with the amorphous silicon film 303,
This means that the trace amount of nickel was selectively added to this portion. In a hydrogen reducing atmosphere or an inert atmosphere,
For example, it is annealed at a heating temperature of 550 ° C. for 16 hours to be crystallized.

At this time, in the region 300 where the small amount of nickel is selectively added, the amorphous silicon film 303 is crystallized in the direction perpendicular to the substrate 301 to form the crystalline silicon film 303a. . Further, at the same time as crystallization, nickel is uniformly diffused in the film, and the crystalline silicon film 303
The nickel concentration in a was 2 × 10 ¹⁸ atoms / cm ³ . On the other hand, in the peripheral area of the area 300, FIG.
As indicated by an arrow 306, crystal growth occurs in the lateral direction (direction parallel to the substrate 301) from the region 300, and a crystalline silicon film 303b crystallized in the lateral direction is formed. In the other regions, the amorphous silicon film is left as it is as the amorphous silicon film 303. The concentration of nickel in the crystalline silicon film 303b laterally grown is 1 × 10 ¹⁷ a
The value is about toms / cm ^3, which is about an order of magnitude smaller than that of the crystalline silicon film 303a crystallized by directly adding nickel. During the crystal growth, the arrow 30
The crystal growth distance in the direction parallel to the substrate indicated by 6 is 8
It was about 0 μm.

After that, the mask 304 is removed and a laser beam is irradiated to promote the crystallinity of the crystalline silicon film 303b. Here, a XeCl excimer laser (wavelength 308 nm, pulse width 40 nsec) was used as the laser light. The laser light irradiation condition is an energy density of 200-
The irradiation was performed at 400 mJ / cm ² , for example 300 mJ / cm ^2, and the substrate was heated to 200 to 450 ° C., for example 400 ° C., during irradiation.

Next, as shown in FIG. 5C, the crystalline silicon films to be the active regions (element regions) 303n and 303p of the TFT are left and the other regions are removed by etching.
Isolate between elements.

Next, as shown in FIG. 5D, the gate insulating film 3 made of a silicon oxide film having a thickness of 100 nm is formed so as to cover the crystalline silicon films 303n and 303p to be the active regions.
07 is formed into a film. Here, the substrate temperature is set to 350 by using the TEOS as a raw material together with oxygen by the RF plasma CVD method.
Decomposed and deposited at ℃.

Subsequently, aluminum (containing 0.1 to 2% of silicon) having a thickness of 400 to 800 nm, for example 600 nm, was formed by a sputtering method and patterned to form gate electrodes 308 and 309.

Then, the active region 303 is formed by ion doping using the gate electrodes 308 and 309 as masks.
Impurity (phosphorus) is implanted into n, and impurity (boron) is implanted into the active region 303p. Phosphine (PH ₃ ) and diborane (B ₂ H ₆ ) are used as the doping gas,
The former has an acceleration voltage of 60 to 90 keV, for example 80 keV.
And the latter has an acceleration voltage of 40 to 80 keV, for example 65
keV. Dose amount is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm
^-2 , for example, phosphorus 2 × 10 ¹⁵ cm ^-2 , boron 5 × 10
¹⁵ cm ^-2 . By this step, the regions 312, 313, 314, and 315, into which the impurities are implanted, will later become the source / drain regions of the TFT, and the gate electrodes 308 and 30.
The regions masked by 9 and not doped with impurities will later become channel regions 310 and 311 of the TFT. At the time of the above-mentioned doping, each element can be selectively doped by covering a region where doping is unnecessary with a photoresist. As a result, the N-type impurity regions 312 and 313, the P-type impurity region region 314,
314 are formed, and an N-channel TFT and a P-channel TFT can be formed as shown in FIG.

After that, as shown in FIG. 5D, annealing is performed by laser light irradiation to activate the ion-implanted impurities. Here, XeCl is used as laser light.
Excimer laser (wavelength 308 nm, pulse width 40 ns
ec) and the irradiation condition is an energy density of 250 mJ /
Irradiation with 2 shots per cm ² was performed.

Then, as shown in FIG.
Interlayer insulating film 316 made of a silicon oxide film having a thickness of about 00 nm
Are formed by a plasma CVD method. A contact hole is formed in this, and the electrode / wiring 317 of the TFT is made of a two-layer film of a metal material such as titanium nitride and aluminum.
318 and 319 are formed, and the source / drain regions 31 are formed.
2, 313, 314, and 315 are connected. Finally, anneal at 350 ° C for 30 minutes in a hydrogen plasma atmosphere,
Complete the TFT.

In the circuit having the CMOS structure thus obtained, the field effect mobility of the N-type TFT is 150 to 1
80 cm ² / Vs, the field effect mobility of P-type TFT is 12
It showed a high value of 0 to 140 cm ² / Vs. Also,
The threshold voltage is 1.5 to 2V for N-type TFT and − for P-type TFT.
It showed a very good characteristic of 2-3V. The variation in TFT characteristics within the substrate was within ± 12% for the field effect mobility and within ± 8% for the threshold voltage, and it was possible to manufacture with good uniformity and stability.

The embodiments of the present invention have been specifically described above, but the present invention is not limited to the above embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, in Examples 1 to 3 described above, as a method of introducing nickel, a very small amount of nickel is selectively added by forming an extremely thin nickel film on the surface of an amorphous silicon film by vapor deposition. The method of growing crystals from the part was adopted. However, a method of adding a small amount of nickel to the surface of the base film by vapor deposition before forming the amorphous silicon film may be used. That is, the trace amount of nickel may be added to the upper surface or the lower surface of the amorphous silicon film, and the crystal growth may be performed from the upper surface side or the lower surface side of the amorphous silicon film.

When nickel is used as the catalyst element for promoting crystallization, the most remarkable effect can be obtained, but in addition, cobalt, palladium, platinum, copper, silver,
Similar effects can be obtained by using metal elements such as gold, indium, tin, phosphorus, arsenic, antimony, and aluminum. If it is one or more kinds of elements selected from these catalytic elements, a trace amount (1 × 10 ¹⁶ atoms /
(about cm ³ ) also has the effect of promoting crystallization,
There is no risk of adversely affecting semiconductor elements.

In the above embodiment, heating was performed by irradiation of an excimer laser which is a pulse laser in order to promote the crystallinity of the crystalline silicon film, but other lasers (for example, an Ar laser which is a continuous wave laser) are used. The same processing can be performed by using it. Further, instead of the laser, strong light equivalent to laser light, for example, infrared light, flash lamp, etc., is used in a short time of 1000 to 1200.
A so-called RTA (also called rapid thermal anneal, or RTP (rapid thermal process)) that heats the sample by raising the temperature to ℃ (silicon monitor temperature) may be used.

Further, the present invention can be applied to other than the active matrix substrate for liquid crystal display. For example,
Examples include contact-type image sensers, thermal heads with built-in drivers, optical writing elements and display elements with built-in drivers that use organic EL, etc. as light emitting elements, and semiconductor devices such as three-dimensional ICs. As a result, it is possible to realize high performance such as high speed and high resolution of these elements. Further, the MOS described in the above embodiment
Not only the type transistor, but also a wide range of semiconductor processes and semiconductor devices including a bipolar transistor and a static induction transistor using a crystalline semiconductor as an element material.

[0102]

As is apparent from the above description, according to the present invention, a large area substrate is provided in a semiconductor device in which an active region made of a crystalline silicon film is formed on a substrate having an insulating surface. A high-performance TFT having uniform and stable characteristics can be formed by a simple manufacturing process. Particularly in a liquid crystal display device, the characteristics of the pixel switching TFT required for the active matrix substrate can be made uniform, and the high performance required for the TFT constituting the peripheral drive circuit section can be satisfied at the same time. A driver monolithic active matrix substrate in which an active matrix portion (display portion) and a peripheral drive circuit portion are formed on the substrate can be realized, and the module can be made compact, high performance, and cost can be reduced. .

[Brief description of drawings]

1A to 1E are process diagrams (cross-sectional views) showing a method for manufacturing a semiconductor device according to a first embodiment.

2A and 2B are plan views showing an outline of a manufacturing process of a semiconductor device according to a second embodiment.

3A to 3F are process diagrams (cross-sectional views) taken along the line AA ′ in FIG.

FIG. 4 is a plan view showing an outline of a manufacturing process of a semiconductor device of Example 3;

5A to 5E are process diagrams (cross-sectional views) taken along the line BB ′ of FIG.

[Explanation of symbols]

101, 201, 301 Glass substrate 102, 202, 302 Underlayer film 103, 203, 303 Amorphous silicon film 103a, 203a, 303a Crystalline silicon film 203b, 303b Crystalline silicon film 103n, 203p, 303n, 303p Active region 204 , 304 mask 206, 306 crystal growth direction 107, 207, 307 gate insulating film 108, 208, 308, 309 gate electrode 109 oxide layer (anodized layer) 110, 210, 310, 311 channel region 111, 112, 211, 212, 312, 313, 3
14, 315 Source / drain regions 113, 213, 316 Inter-layer insulating film 114, 115, 214, 215, 317, 318, 3
19 electrodes and wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/336

Claims (9)

[Claims] 1. A semiconductor device having an active region made of a crystalline silicon film formed on a substrate having an insulating surface, the active region promoting crystallization of an amorphous silicon film. A semiconductor device comprising a crystal element grown by introducing a catalytic element by a vapor deposition method and subjecting the amorphous silicon film to heat treatment and laser light or intense light irradiation. 2. A semiconductor device in which an active region made of a crystalline silicon film is formed on a substrate having an insulating surface, wherein the active region is crystallized in a part of an amorphous silicon film. Around the region where the catalytic element is selectively introduced by subjecting the amorphous silicon film to heat treatment and laser light or intense light irradiation by selectively introducing a catalytic element that promotes A semiconductor device comprising a crystal grown in a portion in a direction substantially parallel to the substrate surface. 3. The catalyst element is Ni, Co, Pd, P
The semiconductor device according to claim 1, which is one or more kinds of elements selected from t, Cu, Ag, Au, In, Sn, P, As, Sb, and Al. 4. The concentration of the catalytic element in the active region is 1 × 10 ¹⁶ atoms / cm ³ to 1 × 10 ¹⁹ at.
The semiconductor device according to claim 1, wherein the semiconductor device has oms / cm ³ . 5. A method of manufacturing a semiconductor device in which an active region made of a crystalline silicon film is formed on a substrate having an insulating surface, the method comprising forming an amorphous silicon film on the substrate. Before or after the step of forming the amorphous silicon film, a step of depositing a thin film containing a catalytic element that promotes crystallization of the amorphous silicon film, and crystallization of the amorphous silicon film by heating. And a step of irradiating a silicon film crystallized by heating with laser light or intense light to promote crystallinity. 6. A method of manufacturing a semiconductor device in which an active region made of a crystalline silicon film is formed on a substrate having an insulating surface, the method comprising: forming an amorphous silicon film on the substrate. Before or after the step of forming the amorphous silicon film, a thin film containing a catalytic element that promotes crystallization of the amorphous silicon film is selectively contacted with a part of the amorphous silicon film. A step of vapor deposition, and heating the amorphous silicon film, in the peripheral part of the region in contact with the thin film containing the catalytic element in the amorphous silicon film,
The process of crystal growth in a direction substantially parallel to the substrate surface, and irradiating laser light or intense light to the silicon film crystallized by heating to cause crystal growth in a direction substantially parallel to the substrate surface. And a step of promoting crystallinity of the formed region, a method of manufacturing a semiconductor device. 7. When depositing a thin film containing a catalytic element that promotes crystallization of the amorphous silicon film, the vapor deposition is performed with a distance of 20 cm or more between the deposition source containing the catalytic element and the substrate. A method of manufacturing a semiconductor device according to claim 5 or 6. 8. When depositing a thin film containing a catalytic element that promotes crystallization of the amorphous silicon film, a large amount of vapor is deposited on the substrate between the deposition source containing the catalytic element and the substrate. The method for manufacturing a semiconductor device according to claim 5, wherein a threshold plate is provided to suppress vapor deposition. 9. Ni, Co, P as the catalyst element
d, Pt, Cu, Ag, Au, In, Sn, P, As,
The method for manufacturing a semiconductor device according to claim 5, wherein one or more kinds of elements selected from Sb and Al are used.