JPH09148245A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having very high performance and high reliability. SOLUTION: In a semiconductor device in which films 2 being an active area are stacked on a substrate 1 having an insulation face, the films 2 being the active area are crystallized with the use of an amorphous silicon film as a base and composed of crystalline silicon films in substantially a monocrystal state that respective pillar crystals in crystal particles are coupled to each other. Since the films 2 being the active area are in the monocrystal state, a movement speed of carriers can be made faster, etc., and characteristics are enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a film to be an active region is laminated on a substrate having an insulating surface, and a manufacturing method thereof. In particular, the present invention is effective for a semiconductor device including a thin film transistor (hereinafter abbreviated as TFT), and can be used for, for example, an active matrix type liquid crystal display device, a contact image sensor, a three-dimensional IC and the like.

[0002]

2. Description of the Related Art In recent years, in order to realize a high resolution liquid crystal display device, a high speed and high resolution contact type image sensor, a three-dimensional IC, etc., high performance has been achieved on an insulating substrate such as glass or an insulating film. Attempts have been made to form semiconductor devices. In the semiconductor element used in these devices, a thin film silicon semiconductor is generally used. The thin film silicon semiconductor is roughly classified into two types, that is, an amorphous silicon semiconductor (α-Si) and a crystalline silicon semiconductor.

The former amorphous silicon semiconductor is most commonly used because it has a low production temperature, can be produced relatively easily by a vapor phase method, and is highly mass producible. Are inferior in physical properties to a silicon semiconductor having crystallinity.
Therefore, in order to obtain higher speed characteristics in the future, it is strongly required to establish a method for manufacturing a semiconductor device made of a crystalline silicon semiconductor.

The latter crystalline silicon semiconductors are known to be polycrystalline silicon, microcrystalline silicon, amorphous silicon containing crystalline components, semi-amorphous silicon having an intermediate state between crystalline and amorphous. ing.

The following three methods are known as methods for obtaining the above-mentioned crystalline silicon semiconductor film.

(1) A film having crystallinity is directly formed at the time of film formation.

(2) An amorphous semiconductor film is formed in advance,
It has crystallinity due to the energy of laser light.

(3) An amorphous semiconductor film is formed in advance,
It is made crystalline by applying heat energy.

However, in the method (1), crystallization progresses at the same time as the film forming step. Therefore, in order to obtain crystalline silicon having a large grain size, it is indispensable to increase the thickness of the silicon film. It is technically difficult to uniformly form the film having the above-mentioned structure over the entire surface of the substrate having the insulating surface.

In the method (2), when the excimer laser most commonly used at present is taken as an example, there is a problem that the irradiation area of the laser beam is small and the throughput is low, and the entire surface of the substrate is uniform. The stability of the laser is not enough to process it, and there is a strong sense that it is a next-generation technology.

The method (3) is more advantageous than the methods (1) and (2) in terms of uniformity and stability in the substrate, and is used for an ultra-compact high definition liquid crystal panel using a quartz substrate. Has been done. However, in this case, heat treatment is performed at a temperature of about 600 ° C. for several tens of hours, and then heat treatment for promoting crystallinity is further performed at a temperature higher than the heat treatment, for example, at 1000 ° C. for several tens of minutes to several hours. ing. That is, there is a problem that the processing time is long and the throughput is low.

For these methods, Japanese Patent Laid-Open No. 6-244
No. 103 and Japanese Patent Laid-Open No. 6-244104. These methods solve the above-mentioned problem of processing time by utilizing the method (3). That is, a catalytic element that promotes crystallization of the amorphous silicon film is used, and thereby the heating temperature is lowered and the processing time is shortened. Specifically, a trace amount of a metal element such as nickel, palladium, or lead is introduced onto the surface of the amorphous silicon film, and then heated. According to this, the heating temperature is 550 ° C. and the processing time is about 4 hours.

The mechanism of this low-temperature crystallization is that crystal nuclei centering on a metal element occur at an early stage, and then the metal element acts as a catalyst to promote crystal growth and the crystallization rapidly progresses. To be understood. In that sense, these metal elements are hereinafter referred to as catalyst elements. The crystalline silicon film in which crystal growth is promoted by crystallization by these catalytic elements has a network structure of many columnar crystals within the grains, and each columnar crystal has an ideal single crystal state. Has become. By the way, in the crystalline silicon film crystallized by the usual solid phase growth method, one grain has a twin structure.

Further, in Japanese Patent Application Laid-Open No. 6-244104, a catalyst element is selectively introduced into a part of the amorphous silicon film and heated to leave the other part in the state of the amorphous silicon film. By selectively crystallizing only the region into which the catalytic element is introduced, and further extending the heating time, crystal growth is performed in the lateral direction (direction parallel to the substrate) from the introduced region. Inside this lateral crystal growth region, columnar crystals with the growth direction aligned in one direction are crowded together, and the crystallinity is further improved in comparison with the region where the catalytic elements are directly introduced and the generation of crystal nuclei occurs randomly. It is a good area. Therefore, by using the crystalline silicon film in the lateral crystal growth region for the active region of the semiconductor device, the performance of the semiconductor device can be improved.

[0015]

By the way, the above-mentioned JP-A-6-244103 and JP-A-6-2441.
The technique disclosed in Japanese Patent Publication No. 04 has been proposed mainly for lowering the crystallization temperature, and is very effective. However, its crystallinity and the characteristics of semiconductor devices when it is used are not yet sufficient.

According to an experiment conducted by the present inventor, individual crystal grains in the crystalline silicon film crystallized by the catalytic element have an angular distribution of about 10 degrees as a whole. Therefore, even if the crystallinity of each columnar crystal is good, the whole grain contains crystal defects (dislocations) of a considerably high density. Since the crystal grain size is as large as about 30 μm, the characteristics are almost determined by the crystallinity in the grain, and the channel in the active region of the semiconductor device has approximately one crystal orientation.
Although relatively high mobility is obtained, it means that the threshold voltage and the leak current are hard to decrease because the defect density is high.

When a TFT is manufactured using a crystalline silicon film that is actually crystallized using a catalytic element, a field effect mobility of about 60 to 80 cm ² / Vs is obtained. This value is about 1.2 times higher than that of a crystalline silicon film that is solid-phase crystallized at 600 ° C. However, considering the application to a thin film integrated circuit, at least 150 cm ² / m of the NMOS type. A field effect mobility of Vs or higher is required. On the other hand, a method is adopted in which the crystalline silicon film crystallized by the catalytic element is further irradiated with laser light or the like to promote its crystallinity. But,
When such a method is adopted, the laser annealing technique itself has poor uniformity and stability, and on the contrary, good uniformity due to solid-phase crystallization often results.

As another problem, it is pointed out that the catalyst element used for crystallization of the amorphous silicon film remains ununiformly distributed at the crystal grain boundaries in the film. That is, if a large amount of a catalytic element is present in the crystalline silicon film that constitutes the active region (element region) of the semiconductor device, the electrical stability of the semiconductor device will be impaired, and the reliability will decrease. Will be forced to.

In particular, nickel, palladium, etc., which act efficiently as a catalyst element for crystallization of the amorphous silicon film, form an impurity level in the vicinity of the center of the band gap in silicon, so that these elements do not remain. In the semiconductor device, it causes a phenomenon such as an increase in leak current in an off region, a shift in threshold voltage, and deterioration over time.

Therefore, the above-mentioned catalytic element for promoting crystallization of nickel or the like is necessary when crystallizing amorphous silicon, but it should be contained as little as possible in the crystallized silicon. Can be said to be desirable. Considering this,
It is desirable to minimize the amount of introduction of the catalyst element and perform crystallization with the minimum amount, but the amount of the catalyst element required for crystallization has an extremely small surface density (10 ¹³ atoms / c).
m ² ), and it is practically impossible to control the introduction of such a trace amount of a catalytic element, and therefore, in practice, there is no choice but to introduce a considerably larger amount than the minimum amount. At present, the above problems cannot be solved.

In addition, it is difficult to secure the uniformity of the amount of the catalyst element added in the substrate and the stability (reproducibility) between the substrates in the catalytic element addition treatment method in view of the characteristics of the trace amount control.
When the nonuniformity of the amount of catalyst element added is large, a region where crystal growth does not occur locally due to insufficient amount of the catalyst element, a region where the catalyst element is contained in such a large amount as to significantly adversely affect the semiconductor element, and the like appear. Therefore, like an active matrix substrate of a liquid crystal display device-hundreds of thousands of Ts are formed on one substrate.
It can be said that it is very difficult to produce FT with good uniformity by the above method.

Even if a small amount of control can be performed with good reproducibility in the method of adding a catalytic element, a certain amount of the catalytic element or more (the concentration causing crystallization or more)
Since it always exists in the element region, it is impossible to completely prevent adverse effects on the semiconductor element.

Therefore, an object of the present invention is to provide a semiconductor device having extremely high performance and high reliability. Also,
An object of the present invention is to provide a manufacturing method capable of manufacturing a semiconductor device having extremely high performance and high reliability by a simple process.

[0024]

According to the present invention, there is provided a semiconductor device comprising:
A film to be an active region is laminated on a substrate having an insulating surface, and the film to be an active region is crystallized based on an amorphous silicon film, and each column in the crystal grain is It is composed of a crystalline silicon film in a substantially single crystal state in which crystals are bonded to each other.

In the above crystalline silicon film, the crystal growth direction is preferably set substantially parallel to the moving direction of carriers, and the grain size of the crystal grains of the crystalline silicon film is It is preferably set to 5 to 40 μm.

The first semiconductor device manufacturing method of the present invention is
Forming an amorphous silicon film on a substrate having an insulating surface; introducing a catalytic element that promotes crystallization into the amorphous silicon film; and heating the amorphous silicon film at a relatively low temperature And thereby crystallizing the crystalline silicon film to obtain a crystalline silicon film, and heating the crystalline silicon film at a temperature higher than the temperature at the time of heating to promote the crystallinity.

According to a second method of manufacturing a semiconductor device of the present invention,
A step of forming an amorphous silicon film on a substrate having an insulating surface, a step of introducing a catalytic element that promotes crystallization of the amorphous silicon film locally, and the amorphous silicon film at a relatively low temperature. Heating to crystallize the region into which the catalytic element has been introduced, and crystallize the region from the crystallized region to the peripheral region in a direction substantially parallel to the substrate surface; and the crystalline silicon film. Is heated at a temperature higher than the temperature at the time of heating to promote its crystallinity.

The above-mentioned heating at a relatively high temperature is
It is preferably performed in an oxidizing atmosphere of O ₂ , H ₂ O, HCl or the like. In addition, the heating at the relatively low temperature described above is performed at a temperature of 520 to 520.
It is preferably carried out within the range of 600 ° C. Furthermore, the above-mentioned heating at a relatively high temperature is preferably performed within a temperature range of 800 to 1100 ° C. In addition, the heating at the relatively high temperature described above reduces the concentration of the catalytic element in the crystalline silicon film to 1 × 10 5.
^It is preferable to carry out control so as to be controlled within the range of ¹⁴ atoms / cm ³ to 1 × 10 ¹⁷ atoms / cm ³ . Further, the above-mentioned catalyst elements are Ni, Co, Pd, Pt, Cu and A.
It is preferable to use one or more kinds of elements among g, Au, In, Sn, Al and Sb.

In summary, according to the present invention, the amorphous silicon film is subjected to a heat treatment at a relatively low temperature using a catalytic element and a heat treatment at a relatively high temperature to obtain a crystal of high quality comparable to a single crystal. The present invention provides a manufacturing method for converting a crystalline silicon film, and a semiconductor device obtained by the manufacturing method.

By the way, a method for obtaining a high-quality crystalline silicon film by further heat-treating a crystalline silicon film by a usual solid-phase crystallization process without using a catalytic element has been put into practical use, but according to the present invention. Crystalline silicon films exhibit even higher levels of crystallinity. In other words, a crystalline silicon film formed by normal solid-phase crystallization has a twin crystal structure with many crystal defects in its crystal grains, and the high temperature heat treatment performed later eliminates some intra-grain defects and improves the quality. However, the crystal grain size does not change and the crystal structure is maintained as a twin crystal structure. On the other hand, in the production method of the present invention, the introduction of the catalytic element,
By heat treatment at a relatively low temperature, a crystalline silicon film having a network structure of columnar crystals in the crystal grains can be obtained, and when this crystalline silicon film is subjected to a heat treatment at a relatively high temperature, it exists. Not only the crystal defects disappear, but also the columnar crystals in the grains are combined, and the inside of one crystal grain becomes almost a single crystal state. Further, the crystal grain size of the silicon film obtained by the usual solid phase crystallization is 5 μm or less, whereas the crystal grain size of the crystalline silicon film obtained by the heat treatment at a relatively low temperature according to the present invention is 5-40 μm. Grows very large. Therefore, when heat treatment at a relatively high temperature is applied,
In the case of the present invention, a crystalline silicon film having a very good crystallinity and a level comparable to that of a single crystal is obtained.

According to the second manufacturing method of the present invention, the crystallinity of the crystalline silicon film obtained is more significantly improved.
That is, when individual columnar crystals are grown in one direction using the region into which the catalytic element is introduced as a seed, the crystal grains do not exist there. Therefore, by subjecting this region to heat treatment at a relatively high temperature, a region in a substantially single crystal state can be obtained over a wide range. TFT using crystalline silicon film
By making the crystal growth direction substantially parallel to the carrier movement direction, a TFT with higher mobility can be realized.

When the atmosphere during the heat treatment at a relatively high temperature is an oxidizing atmosphere of O ₂ , H ₂ O, HCl or the like, the oxidizing effect of the crystalline silicon film is generated in addition to the annealing effect, and the crystal is formed. The crystalline silicon film can be made thinner, and the catalytic element in the crystalline silicon film can be attracted to the surface oxide film side. This mechanism is such that when the energy of the ternary system of crystalline silicon / catalytic element / silicon oxide is considered, the difference in chemical potential and free energy at each interface causes the catalytic element to move to the surface oxide film side. I think it depends on working. Therefore, if the surface oxide film is selectively removed later, a high-quality crystalline silicon film having a much lower concentration of the catalytic element in the film than in the initial state can be obtained. In addition, when the thin crystalline silicon film is used as the active region of the TFT, the threshold voltage (V _TH ) can be reduced as the TFT characteristic.
The rise coefficient (S coefficient) can be reduced.

Assuming that the concentration of the catalytic element in the crystalline silicon film is 1 × 10 ¹⁴ atoms / cm ³ to 1 × 10 ¹⁷ a.
When controlled to toms / cm ³ , the concentration of the catalytic element can be reduced by about one digit or more as compared with the crystalline silicon film obtained by the conventional publication technique. By the way, as a result of the investigation by the present inventors, at such a concentration of the catalytic element, there is almost no effect on the semiconductor element, and the level is not a problem.

In addition, heating at a relatively low temperature is performed at a temperature of 520 to 520.
If the temperature is within the range of 600 ° C., the crystal growth without disturbing the crystal structure can be favorably performed. Further, if the heating at a relatively high temperature is performed within the temperature range of 800 to 1100 ° C., the defects in the crystal grains can be further eliminated, and the columnar crystals can be bonded well.

Further, the most remarkable effect can be obtained when Ni is used as the catalyst element, but Co, Pd,
The same crystallization-promoting effect can be obtained by using one or more elements selected from Pt, cu, Ag, Au, In, Sn, Al, and Sb.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the embodiments shown in FIGS. 1 and 2
1 is a longitudinal sectional view showing a semiconductor device, and FIG. 2 is a process drawing showing a method for manufacturing the same semiconductor device. Here, a MOS structure TFT (thin film transistor) is taken as an example of the semiconductor device.

In the figure, 1 is an insulating substrate, 2 is an active region (source region 21, drain region 22, channel region 2).
3) is an island-shaped crystalline silicon film, 3 is a gate insulating film, 4 is a gate electrode, 5 is an oxide layer, 6 is an interlayer insulating film, 7 is a source electrode, and 8 is a drain electrode. The arrangement and structure of these are well known.

The present embodiment is characterized by the crystalline silicon film 2. That is, the crystalline silicon film 2 is crystallized based on the amorphous silicon film and is in a substantially single crystal state in which the columnar crystals in the crystal grains are bonded to each other. The crystal grain size is also very large, 5 to 40 μm, and the concentration of the catalytic element contained in the crystalline silicon film 2 is 1 × 10 ¹⁴ atoms / cm ³ to 1 × 10 ¹⁷ a.
It is managed at a fairly low level of toms / cm ³ .

The TFT as described above can be used not only as a driver circuit or pixel portion of an active matrix type liquid crystal display device but also as an element constituting a CPU on the same substrate. It goes without saying that TFTs can be applied not only to liquid crystal display devices but also to thin film integrated circuits that are generally called.

Next, a method of manufacturing the TFT having the structure shown in FIG. 1 will be described with reference to FIG. Briefly, an amorphous silicon film is formed on an insulating substrate, a catalytic element for promoting crystallization is introduced into this amorphous silicon film, and the amorphous silicon film is heat-treated at a relatively low temperature. Then, the crystallized silicon film is further heat treated at a relatively high temperature to deepen the degree of crystallization. The process proceeds from (A) to (F) in FIG.

(A) The surface of the insulative substrate 1 made of quartz glass is washed with a low concentration hydrofluoric acid of about 1%, and then the surface of the substrate 1 is reduced to a thickness of 30 to 100 nm by a low pressure CVD method. For example, an intrinsic (I-type) amorphous silicon film (α-Si film) 2a having a thickness of 50 nm is formed. Only the amorphous silicon film 2a of the substrate 1 is brought into contact with an aqueous solution containing nickel. Nickel acetate was used as the solute of the above-mentioned aqueous solution, and the nickel concentration in the aqueous solution was set to 50 ppm. A small amount of nickel 9 is added to the surface of the amorphous silicon film 2a by uniformly spreading the aqueous solution on the amorphous silicon film 2a of the substrate 1 with a spinner and drying it.

(B) The substrate 1 is annealed in a hydrogen reducing atmosphere or an inert atmosphere at a heating temperature of 520 to 600 ° C. for several hours to several tens of hours, for example at 550 ° C. for 4 hours.
As a result, nickel of nickel 9 becomes nuclei and diffuses throughout the amorphous silicon film 2a thereunder, so that the crystallization of the amorphous silicon film 2a occurs in the thickness direction (direction perpendicular to the substrate).
Happens in. As a result, the amorphous silicon film 2a changes to the crystalline silicon film 2b. Crystalline silicon film 2 at this time
The nickel concentration in b is 2 × 10 ¹⁸ atoms / cm ³
It was about. The individual crystal grains of the crystalline silicon film 2b had a columnar crystal network structure with a width of 100 to 200 nm and a grain size of about 30 to 40 μm.

(C) Anneal in an oxygen gas atmosphere at a heating temperature of 800 to 1100 ° C., for example, 1050 ° C. for about 30 minutes. As a result, the surface of the crystalline silicon film 2b is oxidized, so that the surface oxide film 10 is formed and the crystalline silicon film 2b is thinned to a film thickness of about 30 nm. The crystalline silicon film 2c is changed to a high quality. In other words, by annealing,
In the crystal grains of the crystalline silicon film 2b, the defects disappear and the respective columnar crystals combine to change into a substantially single crystal state. Further, the crystal grain boundary portion is well processed, and the trap level and trap density for carriers are reduced.
Moreover, since nickel existing in the crystalline silicon film 2b (especially the crystal grain boundary portion) before the annealing is attracted to the side of the surface oxide film 10 formed by the annealing, the surface after the annealing is Nickel is localized at the oxide film 10 and the interface between the surface oxide film 10 and the high-quality crystalline silicon film 2c.

(D) The surface oxide film 10 is removed by selective etching. As a result, the nickel concentration in the exposed high-quality crystalline silicon film 2c is 3 × 10 ¹⁶ ato.
It was reduced to about ms / cm ³ . By patterning the crystalline silicon film 2c in an island shape, an island-shaped crystalline silicon film 2 for forming an active region is obtained.

(E) A gate insulating film 3 made of a silicon oxide film having a thickness of 20 to 150 nm, for example 100 nm, is formed so as to cover the island-shaped crystalline silicon film 2. This silicon oxide film is, for example, TEOS (Tetra Ethoxy Ortho
Silicate) as the raw material, and the substrate temperature of 150-
It can be obtained by decomposing and depositing at 600 ° C., preferably 300 to 400 ° C., by an RF plasma CVD method. In addition to this, TEOS is used as a raw material together with ozone gas for decompression CV.
The substrate temperature is set to 350 by the D method or the atmospheric pressure CVD method.
~ 600 ° C, preferably 400 to 550 ° C. In order to improve the bulk characteristics of the gate insulating film 3 and the characteristics at the interface between the crystalline silicon film 2 and the gate insulating film 3, the value of 800 to 800 is set in an inert gas atmosphere.
Anneal at 1000 ° C. for 30 to 60 minutes. The thickness is 400 to 800 nm, for example, 6 by the sputtering method.
A gate electrode 4 is formed by forming a 00 nm aluminum film and patterning this aluminum film. The oxide layer 5 is formed on the surface by anodizing the surface of the gate electrode 4 made of this aluminum film. In addition, tartaric acid is 1
It is carried out in an ethylene glycol solution containing -5%, and the voltage is first raised to 220 V at a constant current, and the state is maintained for 1 hour to finish. The thickness of the obtained oxide layer 5 is 20.
0 nm. Further, since the oxide layer 5 has a thickness that forms the offset gate region in the subsequent ion doping process, the length of the offset gate region can be determined by the above-described anodic oxidation process. By the ion doping method, N-type impurities such as phosphorus are implanted using the gate electrode 4 and the oxide layer 5 around it as a mask. At this time, phosphine (PH ₃ ) is used as the doping gas, the acceleration voltage is 60 to 90 kV, for example 80 kV, and the dose amount is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 2 × 10.
¹⁵ cm ^-2 . By this step, the regions 21 and 22 into which impurities are implanted in the crystalline silicon film 2 will later become the source region and the drain region, and the regions 23 into which the impurities are not implanted are masked by the gate electrode 4 and the oxide layer 5 around it. Later, it will be a channel region. By performing annealing by irradiation with laser light, the ion-implanted impurities are activated, and at the same time, the crystallinity of the portion where the crystallinity is deteriorated in the impurity introduction step is improved. At this time, a XeCl excimer laser (wavelength 308 nm, pulse width 40 nsec) is used as a laser, and has an energy density of 150 to 400 mJ / cm ² , preferably 200 to 250 mJ / cm ² , and 4 per spot.
Shot irradiation. Source region 2 thus formed
1. The sheet resistance of the drain region 22 is 200 to 800.
Ω / □.

(F) A silicon oxide film or a silicon nitride film having a thickness of about 600 nm is formed as the interlayer insulating film 6. When the interlayer insulating film 6 is a silicon oxide film, T
Plasma CVD of EOS as raw material with oxygen
Method, reduced pressure CVD method with ozone, or normal pressure CV
It can be formed by the D method. In this case, a good interlayer insulating film having excellent step coverage can be obtained. on the other hand,
When the interlayer insulating film 6 is a silicon nitride film, SiH ₄ and N
It can be formed by plasma CVD using H ₃ as a source gas. In this case, by supplying hydrogen atoms to the interface between the active region 23 and the gate insulating film 3, it is possible to reduce dangling bonds that deteriorate the TFT characteristics.
After forming the contact holes 61 and 62 in the interlayer insulating film 6, the electrodes 7 and 8 are formed of a metal material, for example, a two-layer film of a titanium nitride film and an aluminum film. The titanium nitride film is provided as a barrier film for the purpose of preventing aluminum from diffusing into the source region 21 and the drain region 22. And finally, by annealing at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm,
Complete.

By the way, when the TFT having the above structure is used as a switching element for a pixel electrode, the electrodes 7 and 8 are used.
Connected to a pixel electrode made of a transparent conductive film such as ITO,
Input a signal from the other electrode. When the TFT having the above structure is used in a thin film integrated circuit, the gate electrode 4
A contact hole may be formed thereover and a required wiring may be provided.

N produced by the production method described above
The channel type TFT has a field effect mobility of 200 to 300.
cm ² / Vs, high threshold voltage of 0 to 1V, and very good leak current in the TFT off region of several p.
It is suppressed to a value as low as A. In addition, there is almost no change with time due to repeated measurement, and it is stable and highly reliable.

3 to 5 relate to another embodiment of the present invention. FIG. 3 is a longitudinal sectional view of a semiconductor device, FIG. 4 is a process diagram showing a method of manufacturing the same semiconductor device, and FIG. 4 (E)
It is a top view in a process.

In this embodiment, a CMOS structure circuit in which an N-channel TFT and a P-channel TFT which form a peripheral drive circuit of an active matrix type liquid crystal display device and a general thin film integrated circuit are formed in a complementary type is shown. There is. In the figure, 20 is an N-channel type TFT, 30 is a P-channel type T
FT, 1 is an insulating substrate, 2n is an N-channel TFT 2
0 active region (source region 21n, drain region 22
n, the channel region 23n) is formed on the island-shaped crystalline silicon film, 2p is an active region (source region 21p, drain region 22p, channel region 2) of the P-channel TFT 30.
3p) formed island-shaped crystalline silicon film, 3 is a gate insulating film, 4n is a gate electrode of the N-channel TFT 20,
4p is a gate electrode of the P-channel TFT 30, 6 is an interlayer insulating film, 7n is a source electrode of the N-channel TFT 20,
7p is the source electrode of the P-channel TFT 30, and 8n is N
The drain electrode of the channel TFT 20 and the drain electrode 8p of the P channel TFT 30.

Also in this embodiment, the crystalline silicon films 2n, 2
The fact that p is crystallized with the amorphous silicon film as a base and is in a substantially single crystal state in which the respective columnar crystals in the crystal grains are bonded to each other is the same as in the above-mentioned embodiment. However, the crystalline silicon film 2 of this example is
The n and 2p are different from those of the above-mentioned embodiment in that the crystal growth direction is set substantially parallel to the carrier movement direction.

Next, a method of manufacturing a circuit having a CMOS structure having the structure shown in FIG. 3 will be described with reference to FIGS. 4 and 5. The process proceeds from (A) to (F) in FIG.

(A) The surface of the insulating substrate 1 made of quartz glass is washed with low-concentration hydrofluoric acid of about 1%, and then the surface of the substrate 1 is thickened by a low pressure CVD method or a plasma CVD method. 25-100 nm, for example 80 nm, intrinsic (I-type) amorphous silicon film (α-Si
Film) 2a is formed. A mask 11 is formed by applying a photosensitive resin (photoresist) on the amorphous silicon film 2a and exposing and developing the photosensitive resin. As shown in FIG. 4, the surface of the amorphous silicon film 2a is exposed through the slit-shaped through holes 111 of the mask 11. Substrate 1
A nickel film 9a is deposited on the surface of the. In this vapor deposition, the distance between the vapor deposition source and the substrate is made larger than usual and the vapor deposition rate is lowered, so that the thickness of the nickel film 9a is controlled to be about 1 to 2 nm. When the areal density of the nickel 9a on the substrate 1 at this time was actually measured, it was about 4 × 10 ¹³ atoms / cm ² .

(B) By removing the mask 11 which is the lower layer of the nickel film 9a, the nickel film 9a on the mask 11 is lifted off. As a result, the through hole 11
For the amorphous silicon film 2a in the region corresponding to 1,
This means that a small amount of nickel was selectively added. This is annealed in an inert atmosphere at a heating temperature of 550 ° C. for 16 hours, for example. Thereby, the amorphous silicon film 2
Crystallization of the amorphous silicon film 2a progresses in the film thickness direction (direction perpendicular to the substrate 1) from the region to which nickel is added in a in the direction of the horizontal direction as indicated by arrow X. Crystallization proceeds in the direction (parallel to the substrate 1) to form the crystalline silicon film 2b. The distance that travels in the lateral direction is, for example, about 80 μm, and the amorphous silicon film 2 is formed in regions farther than that (both ends in the figure).
It remains as a. The nickel concentration in the crystalline silicon film 2b was about 1 × 10 ¹⁷ atoms / cm ³ .

(C) Annealing is performed in an oxygen gas atmosphere at a heating temperature of 800 to 1100 ° C., for example, 1050 ° C. for about 1 hour. As a result, the surface of the crystalline silicon film 2b is oxidized, so that the surface oxide film 10a is formed and the crystalline silicon film 2b is thinned to a film thickness of about 30 nm. The crystalline silicon film 2c is changed to a high quality. That is, by annealing, defects are eliminated and the respective columnar crystals are combined with each other in the crystal grains of the crystalline silicon film 2b, and the state is changed to a substantially single crystal state. Further, the crystal grain boundary portion is well processed, and the trap level and trap density for carriers are reduced. It should be noted that the amorphous silicon film 2a in the region which was not crystallized by nickel in the above (B) is crystallized for the time being, even if the above-mentioned high quality cannot be expected. Moreover, since nickel existing in the crystalline silicon film 2b (especially the crystal grain boundary portion) before the annealing is attracted to the side of the surface oxide film 10a formed by the annealing, the surface after the annealing is Nickel is localized at the oxide film 10a and the interface between the surface oxide film 10a and the high-quality crystalline silicon film 2c.

(D) The surface oxide film 10a is removed by selective etching. As a result, the nickel concentration in the high-quality crystalline silicon film 2c of the exposed crystalline silicon films 2b and 2c was reduced to about 5 × 10 ¹⁵ atoms / cm ³ . By patterning the high-quality crystalline silicon film 2c, island-shaped crystalline silicon films 2n and 2p for forming active regions are obtained.

(E) Island-like crystalline silicon film 2n, 2
A gate insulating film 3 made of a silicon oxide film having a thickness of 100 nm is formed so as to cover p. The silicon oxide film is made of, for example, SiH ₄ gas and N ₂ O gas as raw materials, and the substrate temperature is 800 ° C.
Then, it can be obtained by decomposing and depositing by the low pressure CVD method.
Thickness 400-800n by sputtering method
m, eg 500 nm aluminum film (0.1-2%
Of the gate electrode 4 is formed by patterning the aluminum film.
n, 4p are formed.

(F) By the ion doping method,
Using the gate electrodes 4n and 4p as a mask, N-type impurities such as phosphorus and P-type impurities such as boron are sequentially and selectively implanted into the island-shaped crystalline silicon films 2n and 2p. In addition, at the time of doping, each element is selectively doped by covering a region where doping is unnecessary with a photoresist. At this time, phosphine (PH ₃ ) or diborane (B ₂ H ₆ ) is used as a doping gas. In the former case, the acceleration voltage is 60 to 90 kV, for example 80 kV,
In the latter case, 40 to 80 kV, for example 65 kV,
The dose amount is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, phosphorus is 2 × 10 ¹⁵ cm ⁻² and boron is 5 × 10 ¹⁵ cm ⁻² . As a result, the regions 21n, 21p, 22n, 22p in which the impurities are implanted in the crystalline silicon films 2n, 2p.
Will later become the source region and the drain region, and the gate electrode 4
Region 23 masked with n and 4p and not implanted with impurities
The n and 23p will be the channel regions later. When this state is viewed from above, as shown in FIG. 4, the active regions 23n,
In 23p, the crystallization progressing direction X is arranged so as to be substantially parallel to the carrier moving direction (source → drain direction), and therefore the TFT having mobility is arranged.
Is obtained. By performing annealing by irradiation with laser light, the ion-implanted impurities are activated, and at the same time, the crystallinity of the portion where the crystallinity is deteriorated in the impurity introduction step is improved. At this time, the laser used is a XeCl excimer laser (wavelength 308 nm,
Pulse width 40 nsec) and energy density 150
~ 400 mJ / cm ² , for example 250 mJ / cm ² , 1
Irradiate 4 shots at each location. A 600-nm-thick silicon oxide film is formed as the interlayer insulating film 6. The interlayer insulating film 6 made of this silicon oxide film can be formed by a plasma CVD method using TEOS as a raw material. Contact holes 61n, 62n, 61 are formed in the interlayer insulating film 6.
After forming p and 62p, the electrodes 7n and 8 are made of a metal material, for example, a two-layer film of a titanium nitride film and an aluminum film.
n, 7p, 8p are formed. Finally, annealing is performed at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm to complete the process.

By the way, when the TFT having the above structure is used as a switching element of a pixel electrode, the electrodes 7n,
8n, 7p, and 8p are connected to a pixel electrode made of a transparent conductive film such as ITO, and a signal is input from the other electrode.
When the TFT having the above structure is used in a thin film integrated circuit, contact holes may be formed also on the gate electrodes 4n and 4p and necessary wirings may be provided.

C manufactured by the manufacturing method described above
In a TFT having a MOS structure circuit, the field effect mobility is
230-350 cm ² / V in case of N-channel type TFT
s, 120-200 cm ^{2 for} P-channel TFT
/ Vs, the threshold voltage is 0 to 1V in the case of the N-channel type TFT, and -2 to -3V in the case of the P-channel type TFT.
And shows very good characteristics. Further, the leak current value in the TFT off region is also N-channel TFT, P-channel TF.
Both T are about several DA, which are suppressed to values lower than those of the conventional method. In addition, there is almost no deterioration in characteristics due to repeated measurement, and it is stable and highly reliable.

The present invention is not limited to the above embodiments, and various applications and modifications are conceivable based on the technical idea of the present invention.

(1) In the manufacturing methods of the above-described two embodiments, in the first crystallization, an aqueous solution in which a nickel salt is dissolved is applied to the surface of the amorphous silicon film, or the nickel film is formed by vapor deposition. After the formation, a small amount of nickel is added to the amorphous silicon film to allow crystal growth. However, before forming the amorphous silicon film on the insulating substrate, a film for introducing nickel is provided on the surface of the substrate so that nickel is diffused from the lower side of the amorphous silicon film to perform crystal growth. You can also in short,
Crystallization may be performed from the upper surface side or the lower surface side of the amorphous silicon film. Also, as the method of introducing nickel, various other methods can be used. For example, as a solvent for dissolving nickel salt, SOG
A method of using a (spin-on-glass) material to diffuse from a SiO ₂ film is also effective, and a method of forming a thin film by a sputtering method or a plating method, a method of directly introducing it by an ion doping method, or the like can be used.

(2) As catalyst elements for promoting crystallization, in addition to nickel (Ni), cobalt (Co), palladium (Pd), platinum (Pt), copper (Cu), silver (A)
g), gold (Au), indium (In), tin (S
n), aluminum (Al), and antimony (Sb) can be used.

(3) In the second crystallization, as the atmosphere during annealing, in addition to the oxygen atmosphere shown in the manufacturing method of the above-mentioned two embodiments, steam (H ₂ O) or hydrogen chloride (HCl) gas is used. The atmosphere may be good. In particular, when a steam atmosphere is used, a very high oxidation rate can be obtained as compared with the case of oxygen, which is more advantageous for improving the throughput. Further, when the hydrogen chloride gas atmosphere is used, the gettering effect of catalytic elements such as nickel is large, and it is effective in reducing the concentration as compared with the oxygen atmosphere,
It is more advantageous in improving TFT characteristics.

(4) The present invention is not limited to the MOS type transistors described in the above embodiments, but can be applied to a wide variety of semiconductor processes including bipolar transistors and static induction transistors using crystalline semiconductors as element materials. You can

(5) As an application of the present invention, in addition to the active matrix type substrate for liquid crystal display, for example, a contact type image sensor, a thermal head with a built-in driver, an organic EL (electroluminescence), etc. are used as light emitting elements. The optical writing element, the display element, the three-dimensional IC and the like having a built-in driver can be considered. If the present invention is applied to these elements, high performance such as high speed and high resolution of these elements can be realized.

[0067]

According to the present invention, since a semiconductor device can be formed by forming an active region made of a crystalline silicon film that is almost equivalent to a single crystal on an insulating substrate, a semiconductor device with extremely high performance and high reliability can be obtained. Can be realized.

In particular, when the semiconductor device is used as a liquid crystal display device, the switching characteristics of the pixel switching TFT required for the active matrix substrate are improved, and the high performance required for the TFT constituting the peripheral drive circuit section is improved.
It is possible to realize a full-driver monolithic type active matrix substrate that simultaneously satisfies high integration and that forms an active matrix portion and a peripheral drive circuit portion on the same substrate.
The module can be made compact, high performance, and low cost.

Further, in the manufacturing method of the present invention, since the heat treatment is divided into two steps by using the catalytic element, it is easy to manufacture the above-mentioned high performance and highly reliable semiconductor device. It will be possible.

[Brief description of the drawings]

FIG. 1 is a vertical sectional view showing the structure of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process drawing of the method for manufacturing the same semiconductor device.

FIG. 3 is a vertical cross-sectional view showing the structure of a semiconductor device according to another embodiment of the present invention.

FIG. 4 is a process diagram of the method for manufacturing the same semiconductor device.

FIG. 5 is a plan view in the step (E) of FIG.

[Explanation of symbols]

 1 substrate 2 crystalline silicon film 21 source region 22 drain region 23 active region 3 gate insulating film 4 gate electrode 5 oxide layer 6 interlayer insulating film 7 source electrode 8 drain electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 21/336

Claims (10)

[Claims] 1. A semiconductor device comprising a substrate having an insulating surface and a film serving as an active region laminated on the substrate, wherein the film serving as the active region is crystallized based on an amorphous silicon film. A semiconductor device comprising a crystalline silicon film in a substantially single crystal state in which columnar crystals in crystal grains are bonded to each other. 2. The semiconductor device according to claim 1, wherein the crystal growth direction of the crystalline silicon film is set substantially parallel to the carrier movement direction. 3. The grain size of crystal grains of the crystalline silicon film is:
The semiconductor device according to claim 1, having a thickness of 5 to 40 μm. 4. A comparison between the step of forming an amorphous silicon film on a substrate having an insulating surface, the step of introducing a catalytic element that promotes crystallization of the amorphous silicon film, and the step of introducing the amorphous silicon film. A step of crystallizing by heating at an extremely low temperature to obtain a crystalline silicon film, and a step of promoting the crystallinity by heating the crystalline silicon film at a temperature higher than the heating temperature. A method of manufacturing a semiconductor device, comprising: 5. A step of forming an amorphous silicon film on a substrate having an insulating surface, a step of locally introducing a catalytic element for promoting crystallization thereof into the amorphous silicon film, and the amorphous silicon film. By heating at a relatively low temperature,
Crystallizing the region into which the catalytic element has been introduced, and growing the crystal from the crystallized region to the peripheral region in a direction substantially parallel to the surface of the substrate; And a step of promoting the crystallinity thereof by heating at a temperature higher than the temperature of 1. 6. The heating at the relatively high temperature is performed by using O ₂ , H
_The method for manufacturing a semiconductor device according to claim 4, wherein the method is performed in an oxidizing atmosphere of ₂ O, HCl or the like. 7. The heating at the relatively low temperature is performed at a temperature of 520.
The method for manufacturing a semiconductor device according to claim 4 or 5, wherein the method is performed within a range of to 600 ° C. 8. The heating at the relatively high temperature is performed at a temperature of 800.
The method for manufacturing a semiconductor device according to claim 4 or 5, wherein the method is performed within a temperature range of 1100C. 9. The heating at a relatively high temperature reduces the concentration of the catalytic element in the crystalline silicon film to 1 × 10 ¹⁴ atoms / c.
The method for manufacturing a semiconductor device according to claim 4, wherein the method is performed so as to be controlled within a range of m ³ to 1 × 10 ¹⁷ atoms / cm ³ . 10. The catalyst element is Ni, Co, Pd,
The method for manufacturing a semiconductor device according to claim 4, wherein the element is one or a plurality of elements selected from Pt, Cu, Ag, Au, In, Sn, Al, and Sb.