JP3227392B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a crystalline silicon film obtained by crystallizing an amorphous silicon film as an active region and a method of manufacturing the same. In particular, the present invention provides a thin film transistor (T) provided on a substrate having an insulating surface.
It is effective for a semiconductor device using FT), and is an active matrix type liquid crystal display device, a contact type image sensor,
It can be used for three-dimensional ICs.

[0002]

2. Description of the Related Art In recent years, large and high resolution liquid crystal display devices have been developed.
High-speed, high-resolution contact image sensor, 3D IC
In order to realize such a technique, attempts have been made to form a high-performance semiconductor element on an insulating substrate such as glass or an insulating film. In general, a thin film silicon semiconductor is used for a semiconductor element used in these devices. As the thin film silicon semiconductor, an amorphous silicon semiconductor (a-Si)
And those composed of crystalline silicon semiconductors.

[0003] Amorphous silicon semiconductors are most commonly used because they have a low production temperature, can be produced relatively easily by a gas phase method, and have high mass productivity. Since it is inferior to a crystalline silicon semiconductor, a method for manufacturing a semiconductor device made of a crystalline silicon semiconductor has been strongly demanded in order to obtain higher-speed characteristics in the future. In addition, as a silicon semiconductor having crystallinity,
Polycrystalline silicon, microcrystalline silicon, amorphous silicon containing a crystalline component, semi-amorphous silicon having an intermediate state between crystalline and amorphous, and the like are known.

As a method of obtaining a silicon semiconductor in the form of a thin film having crystallinity, (1) a film having crystallinity is directly formed at the time of film formation.

(2) An amorphous semiconductor film is formed in advance,
Crystallinity is imparted by the energy of laser light.

(3) An amorphous semiconductor film is formed in advance,
Crystallinity is imparted by applying heat energy.

[0007] Such a method is known. However, in the method (1), crystallization proceeds simultaneously with the film formation step. Therefore, it is indispensable to increase the thickness of the silicon film in order to obtain crystalline silicon having a large grain size, and to obtain a film having good semiconductor properties. It is technically difficult to form a film uniformly over the entire surface of the substrate. Further, since the film formation temperature is as high as 600 ° C. or higher, there is a problem of cost that an inexpensive glass substrate cannot be used.

In the method (2), the crystallization phenomenon in the melting and solidification process is used, so that the grain boundaries are satisfactorily treated with a small grain size, and a high-quality crystalline silicon film can be obtained. Taking a commonly used excimer laser as an example, there is a problem that the irradiation area of the laser beam is small and the throughput is low, and the laser stability is not enough to uniformly treat the entire surface of a large-area substrate. There is a strong sense of next-generation technology.

The method (3) has an advantage that it can cope with a large area as compared with the methods (1) and (2). However, the crystallization requires a heat treatment at a high temperature of 600 ° C. or more for several tens of hours. is necessary. In other words, considering the use of inexpensive glass substrates and improving the throughput, the heating temperature was lowered,
It is necessary to simultaneously solve the conflicting problem of crystallization in a shorter time. In the method (3), since the solid-phase crystallization phenomenon is used, the crystal grains spread in parallel to the substrate surface, and even those having a grain size of several μm appear, but the grown crystal grains collide with each other and become grainy. As a boundary is formed, the grain boundary acts as a trap level for carriers, and T
This is a major cause of lowering the mobility of the FT.

A method for solving the above-mentioned problem by using the above method (3) has been proposed in JP-A-6-244103 and JP-A-6-244104. In these methods, the use of a catalyst element that promotes the crystallization of the amorphous silicon film aims at lowering the heating temperature and shortening the processing time. Specifically, a minute amount of a metal element such as nickel or palladium is introduced on the surface of the amorphous silicon film, and then heated at 550 ° C., 4 ° C.
The crystallization is performed in a processing time of about an hour.

The mechanism of the low-temperature crystallization is understood to be that crystal nuclei are generated at an early stage with a metal element as a nucleus, and then the metal element acts as a catalyst to promote crystal growth, and crystallization proceeds rapidly. You. In this sense, these metal elements are hereinafter referred to as catalyst elements. Crystallized silicon film grown by the promotion of crystallization by these catalyst elements,
While one grain of a crystalline silicon film crystallized by a normal solid-phase growth method has a twin structure, the grain is composed of a number of columnar crystal networks. The inside is in an almost ideal single crystal state.

Further, in Japanese Patent Application Laid-Open No. 6-244104, a catalyst element is selectively introduced into a part of an amorphous silicon film and heated to leave another part in an amorphous silicon film state. By selectively crystallizing only the region into which the catalyst element is selectively introduced, and further extending the heating time, the crystal is grown in a lateral direction (parallel to the substrate) from the introduction region. Inside this lateral crystal growth region, columnar crystals whose growth directions are almost aligned in one direction are tied together, and the crystallinity is better than the region where the catalyst element is directly introduced and crystal nuclei are generated randomly. Area. Therefore, by using the crystalline silicon film in the lateral crystal growth region for the active region of the semiconductor device, the performance of the semiconductor device can be improved.

In the crystalline silicon film in the lateral crystal growth region, the concentration of the catalytic element is reduced by about one digit (in terms of volume density) as compared with the region where the catalytic element is directly introduced and crystallized. That is, after the crystallization of the amorphous silicon film, the catalytic element is mainly localized near the crystal grain boundaries, while the position of the crystal grain boundaries can be consciously controlled in the lateral crystal growth region. This is because the portion can be excluded from the element region. One such method is described in Japanese Patent Application Laid-Open No. 7-58339. In this publication, crystal is grown from both ends (ends of a source region and a drain region) of a TFT element region, and a crystal grain boundary is intentionally formed in a central portion of a channel region.

[0014]

SUMMARY OF THE INVENTION The above-mentioned Japanese Patent Application Laid-Open No. 6-24 / 1994
The methods proposed in JP-A-4103 and JP-A-6-244104 are extremely effective in lowering the crystallization temperature, shortening the crystallization time, and improving the crystallinity. However, TFTs made using it
However, there is a large problem in element characteristics.

That is, although the crystallinity of the crystalline silicon film is very good, the catalytic element remaining in the film may adversely affect the device characteristics. The above-mentioned catalytic element greatly contributes to the crystallization of the amorphous silicon film, but as described above, thereafter, it is mainly localized at the crystal grain boundaries and remains in the crystalline silicon film. The presence of a large amount of these catalytic elements in the crystalline silicon film impairs the reliability and electrical stability of devices using these semiconductors, and is, of course, not preferred.

In particular, elements such as nickel and palladium which efficiently act as catalysts for promoting the crystallization of the amorphous silicon film form impurity levels near the center of the band gap in silicon. Therefore, when a TFT is manufactured using a silicon film crystallized with these catalytic elements, a phenomenon of an increase in a leak current mainly when the TFT is turned off appears as an effect thereof. That is, the catalyst element is
In the TFT element, in order to improve the crystallinity of the channel region, current driving capability such as field effect mobility, on-current, and on-current rise coefficient (S coefficient) is greatly improved. It makes it worse.

Further, the above-mentioned phenomenon of increase in the leakage current at the time of the OFF operation in the TFT was confirmed by an experiment conducted by the present inventors.
The concentration of the catalyst element in the crystalline silicon film is 10 ¹⁶
It was confirmed when the value was atoms / cm ³ or more. The above-mentioned JP-A-6-244104 and JP-A-7-5833.
Selectively introducing a catalyst element as 9 JP, even at the concentration of the catalytic element in the lateral crystal growth regions obtained by a method of crystal growth in the lateral direction that region as a seed region, how the even 10 ¹⁶ The limit is about 10 ¹⁷ atoms / cm ³ , and it cannot be suppressed below that. Therefore, the above technique does not fundamentally solve the problem of an increase in leakage current in a TFT.

The present invention relates to a method for producing T using a catalytic element.
It is an object of the present invention to provide a high-performance TFT that eliminates the above-mentioned trade-off relationship between the ON characteristic and the OFF characteristic, has excellent current driving capability, and has a small leakage current during an OFF operation.

[0019]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems and provides a means that satisfies the above-mentioned objects. The present invention provides a high-performance, high-performance substrate on a substrate having an insulating surface such as glass. A semiconductor device having reliability is provided.
Another object of the present invention is to provide a method for manufacturing the semiconductor device by simple steps. More specifically, the present invention has the following features.

The semiconductor device according to the first aspect of the present invention comprises:
A thin film transistor in which an active region including a source region, a drain region, and a channel region is formed on a crystalline silicon film formed over a substrate having an insulating surface, wherein the active region is formed of an amorphous silicon film. A catalyst element that promotes crystallization is included, and in the active region, the concentration of the catalyst element near the junction between the source region or the drain region and the channel region is set to be lower than at least the center of the channel region.

A semiconductor device according to a second aspect of the present invention comprises:
A thin film transistor in which an active region including a source region, a drain region, and a channel region is formed on a crystalline silicon film formed over a substrate having an insulating surface. ,
The amorphous silicon film is crystallized and contains a catalytic element that promotes crystallization of the amorphous silicon film, and is constituted by a columnar crystal network structure.The vicinity of a junction between the source region or the drain region and the channel region contains the catalytic element. It is characterized by being a crystalline silicon film crystallized without containing.

According to a third aspect of the present invention, there is provided a semiconductor device comprising:
A thin film transistor in which an active region including a source region, a drain region, and a channel region is formed on a crystalline silicon film formed over a substrate having an insulating surface. ,
From the region into which the catalytic element that promotes crystallization of the amorphous silicon film is selectively introduced to the peripheral region, the silicon film grows in the lateral direction, and the direction of each columnar crystal is almost one direction. It has a uniform crystal structure, and is characterized in that the vicinity of the junction between the source region or the drain region and the channel region is a crystalline silicon film crystallized without containing the catalyst element.

A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the third aspect, wherein the crystalline silicon film is formed by laterally growing a crystal constituting a central portion of a channel region of the thin film transistor, The crystal growth direction and the carrier moving direction in the thin film transistor are configured to be substantially parallel to each other.

Here, in the semiconductor device of the present invention, the vicinity of the junction between the source region or the drain region containing no catalytic element and the channel region is irradiated with a laser beam having a wavelength of 500 nm or less in a melting and solidifying process in a short time. It is preferably crystallized.

A semiconductor device according to a fifth aspect of the present invention comprises:
The semiconductor device according to claim 2 or 3, wherein the width of each columnar crystal forming the channel region is 150 nm to 400 nm.

As the catalyst element, Ni, Co, Pd,
It is preferable to use one or more elements selected from Pt, Cu, Ag, Au, In, Sn, Al, and Sb.

According to a sixth aspect of the present invention, there is provided a semiconductor device comprising:
4. The semiconductor device according to claim 1, wherein the concentration of the catalytic element in the central portion of the channel region is 10 ¹⁶ to 10 ¹⁹ atoms / cm ³ , and the source region or the drain region is The concentration of the catalyst element near the junction with the region is 10 ¹⁶ at
oms / cm ³ .

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming an amorphous silicon film on a substrate;
Before or after the step, a step of selectively introducing a catalyst element that promotes crystallization of the amorphous silicon film, and selectively heating the amorphous silicon film in a region where the catalyst element is introduced by heat treatment. Crystallizing the amorphous silicon film in the other region by intense light irradiation, and using the region where the catalyst element is introduced and crystallized by heat treatment to form a channel region of the thin film transistor. A step of forming a junction region between a source region or a drain region of the thin film transistor and a channel region using another region crystallized by intense light irradiation.

A method of manufacturing a semiconductor device according to claim 8, wherein a step of forming a first amorphous silicon film on a substrate, and the step of forming the amorphous silicon film before or after the step. A step of introducing a catalytic element that promotes crystallization of, and a step of crystallizing the first amorphous silicon film into which the catalytic element has been introduced by heat treatment to form a first crystalline silicon film, Patterning the first crystalline silicon film to form an island-shaped region that is to be a part of a channel region of a thin film transistor to be formed later; and forming a second amorphous silicon film so as to cover the island-shaped region. Crystallized by intense light irradiation,
A step of forming a second crystalline silicon film, and a step of forming a junction region between a source region or a drain region of the thin film transistor and a channel region using the region of only the second crystalline silicon film. And

A method of manufacturing a semiconductor device according to claim 9 of the present invention, comprising the steps of: forming a first amorphous silicon film on a substrate; and forming the first amorphous silicon film before or after the step. A step of selectively introducing a catalytic element that promotes crystallization of a part, and a step of selectively crystallizing the amorphous silicon film in a region where the catalytic element is selectively introduced by heat treatment. By further continuing the heat treatment, the amorphous silicon film grows in a direction substantially parallel to the substrate surface from the region where the amorphous silicon film is selectively crystallized to a peripheral portion thereof. And forming a first crystalline silicon film, and patterning the first crystalline silicon film,
A step of forming an island-shaped region that becomes a part of a channel region of a subsequent thin film transistor by using a region where crystal growth is performed in a direction substantially parallel to a substrate surface in the crystalline silicon film; and Forming a second amorphous silicon film so as to cover it, crystallizing it by intense light irradiation to form a second crystalline silicon film, and using a region of only the second crystalline silicon film, Forming a junction region between a source region or a drain region of the thin film transistor and the channel region.

Here, the method of manufacturing a semiconductor device according to the present invention is characterized in that the amorphous silicon film is roughly applied to the substrate surface from the region where the amorphous silicon film is selectively crystallized to the periphery thereof. In the step of growing crystals in a parallel direction to form a first crystalline silicon film, it is preferable to design in advance such that the crystal growth direction is substantially parallel to the carrier movement direction in a thin film transistor to be manufactured. .

Preferably, the crystallization of the amorphous silicon film by irradiation with strong light is performed by irradiation with a laser beam having a wavelength of 500 nm or less. Among the laser beams having a wavelength of 500 nm or less, it is particularly preferable to use a XeCl excimer laser beam having a wavelength of 308 nm.

According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the seventh, eighth or ninth aspect, the introduction of the catalytic element is performed by a vacuum evaporation method. By depositing a catalyst element in a thin film on the surface of the amorphous silicon film.

[0034] In the method of manufacturing a semiconductor device according to claim 11 of the present invention, in the method of manufacturing a semiconductor device according to claim 7, 8, or 9, the introduction of the catalyst element may be performed by using the catalyst element. By spin-coating a solution containing

According to a twelfth aspect of the present invention, in the method for manufacturing a semiconductor device according to the eleventh aspect, the solute of the solution containing the catalyst element is a nitrate or an acetate of the catalyst element. Is used.

According to a thirteenth aspect of the present invention, in the method for manufacturing a semiconductor device according to the eleventh aspect, an alcohol such as ethanol is used as a solvent of the solution containing the catalyst element. It is characterized by the following.

In the method of manufacturing a semiconductor device according to claim 14 of the present invention, in the semiconductor device according to claim 10 or 11, the step of introducing a catalytic element comprises the step of: The introduction concentration of the catalyst element is controlled as the areal density on the surface of the amorphous silicon film by total reflection X-ray fluorescence spectrometry.

In the present invention, it is preferable that the area density of the catalyst element on the surface of the amorphous silicon film managed in the step is 10 ¹² to 10 ¹⁴ atoms / cm ² .

According to a fifteenth aspect of the present invention, in the method for manufacturing a semiconductor device according to the seventh, eighth, or ninth aspect, the catalyst element is introduced and crystallized. The thickness of the amorphous silicon film,
It is characterized by being in the range of 25 to 50 nm.

According to a method of manufacturing a semiconductor device according to a sixteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the eighth or ninth aspect, the contact region in contact with the source electrode or the drain electrode is formed of the first region. It is formed by a laminated structure of a crystalline silicon film and a second crystalline silicon film.

Here, as the catalyst element, Ni, Co,
Pd, Pt, Cu, Ag, Au, In, Sn, Al, S
It is preferable to use one or more elements selected from b. Among the above types of catalyst elements, it is particularly preferable to use at least Ni element.

As described above, a crystalline silicon film using a catalytic element has very high quality crystallinity, and a TFT using it as a channel has a high current driving capability. In order to solve the problem of leakage current at the time of off operation, and to realize an excellent TFT, research was conducted day and night.
As a result, the cause of the leakage current during the off operation was investigated. FIG. 8 shows the mechanism.

FIG. 8 is a band diagram from the channel region to the drain region in the N-type TFT. Here, it is assumed that a positive bias is applied from the channel region to the drain region, and a current flows from the channel region to the drain region when the TFT is turned on. FIG. 8 (a)
FIG. 8B is a band diagram when the TFT is turned on when the gate voltage Vg> 0, and FIG. 8B is a band diagram when Vg = 0. FIG. 8C is a band diagram when Vg <0, that is, at the time of the off operation. In both figures, the right side is the drain region, the left side is the channel region, the line 801 indicates the conduction band, the line 802 indicates the valence band, and the line 803 indicates the Fermi level. When Vg = 0, as shown by the line 803, the Fermi level is the same in the channel region and the drain region.

What should be noted here is the band diagram when Vg <0 shown in FIG. When the TFT is turned off, the conduction band 801c and the valence band 802c undulate at the junction between the channel region and the drain region. At this time, if there is any trap level such as 804 at the junction, the carrier at the position 805 is conducted through the trap level 804, that is, through the path shown by the arrow 807. Obi 80
Move to position 806 on 1c. That is, the mechanism of the leakage current during the off operation is understood as a kind of tunnel current phenomenon via the trap level 804. Although the junction between the channel region and the drain region has been described with reference to FIG. 8, the same can be said for the junction between the channel region and the source region since the actual TFT element is AC-driven.

The current driving capability, that is, the ON characteristic of a TFT is mainly determined by the crystallinity of its channel region.
On the other hand, the leak current at the time of the OFF operation of the TFT is caused by the trap level density near the junction between the channel region and the source region or the drain region as described above. Here, the present inventors made most of the TFT channel region with a crystalline silicon film made of a catalytic element, and formed a conventional crystalline region without a catalytic element near the junction between the channel region and the source or drain region. By making with a silicon film,
We thought that the intended high-performance TFT with small leakage current could be realized. In other words, an attempt was made to actually reduce the trap level due to the catalytic element in the vicinity of the junction, which causes the generation of a leak current, and to actually produce an N-type TFT. FIG. 7 shows the result.

In FIG. 7, (A) shows the conventional characteristics including the catalytic element in the entire element region, and (B) shows the characteristics according to the present invention. In both cases, when a voltage of 14 V is applied between the source and the drain, the drain current Id and the gate voltage Vg
, That is, the Vg-Id characteristic curve of the TFT.
The horizontal axis represents the gate voltage Vg, and the vertical axis represents the drain current Id on a logarithmic scale. FIG. 7 shows that in the conventional example (A), the leak current increases as the gate voltage Vg is applied in the negative direction. On the other hand, the TFT characteristics according to the present invention shown in FIG.
Although the Id, that is, the on-state characteristics when adding Vg in the plus direction is as good as that of the conventional example (A), the leakage current when Vg is added in the minus direction is smaller than that of the conventional example (A). And greatly reduced. That is, it has been found that the present invention is very effective in reducing the leak current in a high-performance TFT using a catalytic element, and that the present invention can realize a high-performance TFT with a small leak current.

Therefore, the gist of the present invention is to provide a TFT in which an active region including a channel region, a source region, and a drain region is formed on a crystalline silicon film formed on a substrate having an insulating surface. The active region contains a catalyst element that promotes crystallization of the amorphous silicon film, and within the active region, the concentration of the catalyst element near the junction between the source region or the drain region and the channel region,
At least the structure is made smaller than the central part of the channel region. The TFT having such a configuration is shown in FIG.
It has the electrical characteristics shown in FIG. 1B, and can solve all of the above problems.

In the present invention, the central portion of the channel region contains a catalytic element, is crystallized by heating, and has a columnar crystal network structure. The vicinity of the junction between the source region or the drain region and the channel region is near. Since the crystalline silicon film is crystallized without containing a catalytic element, the crystallinity of the source or drain region junction is good to some extent, so that trap levels due to crystal defects and the like can be reduced, and the leakage current can be further reduced. Can be reduced.

Further, in the present invention, the amorphous silicon film is grown laterally in the center of the channel region from the region into which the catalytic element is selectively introduced to the peripheral region, and the direction of each columnar crystal is increased. However, by using a crystalline silicon film having a crystal structure aligned substantially in one direction, it is possible to further improve the crystallinity of a channel region that mainly determines the ON characteristics of a TFT. As a result, a TFT having a small leak current and a large current driving capability can be obtained. In particular, at this time, the growth direction of the crystalline silicon film grown in the lateral direction and the carrier movement direction in the TFT are
When the carriers are substantially parallel, carriers can move without crossing a crystal grain boundary serving as a scattering center, so that ON characteristics such as field-effect mobility can be further improved.

In the present invention, the vicinity of the junction between the source or drain region and the channel region has a wavelength of 500 nm.
If it is crystallized in a short time melting and solidifying process by laser light irradiation of nm or less, the crystallinity near the junction between the source region or the drain region and the channel region is further improved, and the leakage current is reduced. It can be further reduced. Conventionally, in the crystallization step of melting and solidifying within a short time using such laser light irradiation, it is necessary to heat the silicon film to its melting point of 1414 ° C. or more in a short time, and thus a high-power laser oscillator is required. However, the one that meets the needs has not been developed yet. At present, the output per unit area is increased by focusing on a small beam size, and the beam is sequentially scanned on the substrate surface. This causes non-uniformity of crystallinity, and makes it difficult to commercialize the laser crystallization technique. In the present invention, a crystalline silicon film formed by laser irradiation is used only in the vicinity of a junction between a source region or a drain region and a channel region, and most of the channel regions are solid-phase crystallization by a catalyst element having good uniformity. Since it is formed by the method, it is hardly affected by the non-uniformity due to the laser scanning.

The width of each columnar crystal constituting the channel region is 80 nm in a stress-free state. The crystallinity of the channel region depends on the width of the columnar crystal, and it is difficult to obtain a high-performance TFT aimed at by the present invention if the thickness is 80 nm. The present invention relates to a TFT using a crystalline silicon film by laser irradiation as a channel.
It aims at a TFT having a higher current driving capability than that of the TFT having a field effect mobility of 150 cm ² / V.
s is the target value. This is because, in a driver monolithic liquid crystal display device, the field effect mobility of the target value is required in a driver circuit unit (particularly, a shift register unit). The width of the columnar crystal is
It can be changed by applying stress, and its width can be expanded to some extent. In order to achieve the above-mentioned field effect mobility value, it is necessary to form the channel region with a columnar crystal having a width of 150 nm or more.

When the concentration of the catalytic element in the central portion of the channel region is 10 ¹⁶ atoms / cm ³ or more, the catalytic element contributes to crystallization of the amorphous silicon film, and a good crystalline silicon film can be obtained. . However, 10 ¹⁹ atoms /
If it exceeds cm ³ , precipitation of a catalytic element is observed, and damage during etching becomes remarkable. Therefore, the range of the concentration of the catalytic element in the central part of the channel region is 10 ¹⁶ to 1
It may be 0 ¹⁹ atoms / cm ³ .

On the other hand, the concentration of the catalytic element near the junction between the source region or the drain region and the channel region is less than 10 ¹⁶ atoms / cm ^{3 in} order to eliminate the influence of the catalytic element on the leak current. It is necessary. As a result of investigations by the present inventors, if the concentration is not more than the above, there is no increase in leakage current apparently due to the influence of the catalytic element, and the contamination level is generally referred to.

The following three methods are particularly effective as manufacturing methods for actually manufacturing the TFT according to the present invention.

As a first method, first, a catalytic element is selectively introduced into an amorphous silicon film, and the amorphous silicon film in a region where the catalytic element is introduced is selectively crystallized by heat treatment. After that, the remaining amorphous silicon region is crystallized by intense light irradiation. Then, the center of the channel region of the TFT is formed by using the region where the catalyst element is selectively introduced and crystallized by the heat treatment, and the source region or the drain region is formed by using the other region crystallized by intense light irradiation. Are formed respectively. According to this manufacturing method, the high-performance TFT according to the present invention can be manufactured with a small number of steps and a simple process.

As a second method, a first amorphous silicon film is formed, a catalytic element is introduced into the entire surface thereof, and the first amorphous silicon film is crystallized by heat treatment. , First
Is patterned to form an island-shaped region which is to be a central portion of a channel region of a later TFT. Thereafter, a second amorphous silicon film is formed so as to cover the above-mentioned island region, crystallized by irradiating strong light, and a region including only the second silicon film is used to form a source region or a drain region of the TFT and a channel region. Is formed. In this manufacturing method, the central portion of the channel region is constituted by a laminated structure of the first and second silicon films, and the junction region between the source region or the drain region and the channel region is constituted by the single layer of the second silicon film. Will be. This manufacturing method, a silicon film crystallized by a catalytic element, and a silicon film constituting a junction region of a source region or a drain region and a channel region,
By separating as described above, it is possible to completely prevent the diffusion of the catalytic element into the bonding region generated at the time of heating for crystallization of the catalytic element, and it is more stable as compared with the first manufacturing method. A manufacturing method can be realized.

As a third method, a catalytic element is selectively introduced into a part of the first amorphous silicon film, and a region where the catalytic element is selectively introduced is crystallized by heat treatment. From the region to the periphery, the amorphous silicon film is crystal-grown in a direction substantially parallel to the substrate surface. Thereafter, an island-shaped region serving as a channel region of the TFT is formed using the region of the crystalline silicon film where lateral crystal growth is performed with good crystallinity, and a second island-shaped region is formed so as to cover the island-shaped region. An amorphous silicon film is formed and crystallized by intense light irradiation. Then, a junction region between the source region or the drain region of the TFT and the channel region is formed using only the region of the second silicon film. This manufacturing method has the same advantages as the above-described second manufacturing method, and the channel region can be formed of a laterally grown crystalline silicon film having better crystallinity. As compared with the second method, a TFT having higher current driving capability can be obtained.

In the above three manufacturing methods, if the crystallization of the amorphous silicon film by irradiation with intense light is performed by irradiating a laser beam having a wavelength of 500 nm or less, there are merits in manufacturing.
Since the absorption coefficient with respect to the silicon film is high, only the silicon film can be instantaneously heated without thermally damaging the glass substrate. Among them, especially the wavelength of 308 nm
XeCl excimer laser light has a large output,
The beam size at the time of irradiating the substrate can be increased, it is easy to cope with a large-area substrate, and the output stability is relatively stable.

The introduction of the catalytic element is carried out by vapor-depositing the catalytic element in a thin film on the surface of the amorphous silicon film by a vacuum deposition method, or by applying a solution containing the catalytic element to the surface of the amorphous silicon film. It is preferably performed by spin coating. From experiments by the present inventors, it has been found that the catalyst element works most efficiently when it is present on the outermost surface of the amorphous silicon film. Actually, not only in the ion doping method but also in the thin film formation by sputtering, a small amount of the catalyst element is implanted into the amorphous silicon film, and such a catalyst element does not contribute to crystallization, and It remains in that position after the conversion. Therefore, in order for all of the introduced catalyst elements to efficiently act on crystallization, the above two methods are most suitable as the method for introducing the catalyst element.

In the method of spin-coating a solution containing a catalyst element on the surface of an amorphous silicon film, it is desirable to use a nitrate or acetate of a catalyst element as a solute of the solution containing the catalyst element. In experiments by the present inventors, crystallization was particularly efficiently performed when these solutes were used when the same amount of catalyst element was used. In addition, these solutes do not contain any element that has a significant effect on the semiconductor other than the catalytic element. Further, it is desirable to use alcohols such as ethanol as a solvent of the solution containing the catalyst element. The spin coating method is essentially different from conventional spin coating such as photoresist coating, and is like an image in which a catalytic element is uniformly placed on an amorphous silicon surface. When the present inventors used water as a solvent, the drying unevenness was directly reflected in crystallization, and a uniform crystalline silicon film could not be obtained. Then, it was found that a uniform crystalline silicon film could be obtained by using an alcohol such as ethanol as a more volatile solvent. Further, the use of an organic solvent such as acetone having high volatility is conceivable, but such an organic solvent is generally insoluble in the above-mentioned nitrates and acetates, has low safety, and is used in the present invention. Is not preferred.

It is necessary to control the amount of the catalyst element introduced into the amorphous silicon film to an optimum value for crystallization in the step of introducing the catalyst element. However, the amount is very small and is very difficult to control. Difficult. As this control method, a method of introducing a catalytic element to the outermost surface of the amorphous silicon film and then measuring the surface density on the surface of the amorphous silicon film by total reflection X-ray fluorescence spectrometry is particularly effective. In the total reflection X-ray fluorescence spectrometry, the measurement limit as the areal density is 10 ¹¹ atoms / cm ² or more for all the catalytic element species used in the present invention, and the accurate and sufficient introduction amount in the present invention is obtained. Can be managed.

The areal density of the surface of the amorphous silicon film of the catalytic element, which is controlled in the above steps, is 10 ¹² to 10 ¹⁴ atoms / s
cm ² is desirable. That is, 10 ¹² ato
If the amount is less than ms / cm ² , sufficient crystallization is not performed due to the shortage of the absolute amount of the catalyst element, and conversely, 10 ¹⁴ atoms / cm ²
If it is more than ² cm ² , the above-mentioned precipitation of the catalytic element upon crystallization and etching damage in the process become remarkable.

In the present invention, the thickness of the amorphous silicon film to be crystallized by introducing a catalyst element is 25 to 50 nm.
Is preferably within the range. As described above, the width of the columnar crystal of the crystalline silicon film forming the channel region is
It is determined by stress, and attempts to spread in the horizontal direction by reducing the film thickness from 80 nm. As a result of experiments conducted by the present inventors, when the film thickness is 50 nm or less, the width of the columnar crystal becomes 150 nm or more. However, when the amorphous silicon film was further reduced in thickness to a thickness of 25 nm or less, sufficient crystallization did not occur even if the introduction amount of the catalytic element was increased.

In the second and third manufacturing methods of the present invention, in addition to the central portion of the channel region, the contact region in contact with a part of the source or drain electrode of the source or drain region is formed by the first crystal. More preferably, it is formed by a laminated structure of a crystalline silicon film and a second crystalline silicon film. The contact area is
When a contact hole is opened in the upper layer film, it is simultaneously exposed to etching. That is, the contact region is likely to be thinned due to over-etching in the etching step, and in the worst case, the silicon film may disappear. Therefore, configuring the film thickness in this region to be as thick as possible leads to the stabilization of the whole process, and an improvement in the yield rate can be expected.

The types of catalyst elements that can be used in the present invention include Ni, Co, Pd, Pt, Cu, Ag, and A.
u, In, Sn, Al, and Sb can be used.
One or a plurality of elements selected from these elements have a slight effect on crystallization.

Among them, the most remarkable effect can be obtained particularly when Ni is used. The reason for this has not been fully understood, but the following model is conceivable. The catalyst element does not act alone, but acts on crystal growth by bonding to the silicon film to form silicide.
The model is such that the crystal structure at that time acts like a kind of template when the amorphous silicon film is crystallized, and promotes the crystallization of the amorphous silicon film. Ni is two Si and NiSi
Form a silicide of ₂ . NiSi ₂ exhibits a fluorite-type crystal structure, which is very similar to the diamond structure of single crystal silicon. Moreover, NiSi
₂ has a lattice constant of 5.406 °, which is very close to the lattice constant of 5.430 ° in the diamond structure of crystalline silicon. Therefore, NiSi ₂ is the best template for crystallizing an amorphous silicon film,
As the catalyst element in the present invention, it is particularly desirable to use Ni in particular.

The areal density of the surface of the amorphous silicon film of the catalytic element controlled in the above process is 10 ¹² to 10 ¹⁴ atoms / cm 2.
cm ² is desirable. That is, 10 ¹² ato
If the amount is less than ms / cm ² , sufficient crystallization is not performed due to the shortage of the absolute amount of the catalyst element, and conversely, 10 ¹⁴ atoms / cm ²
If it is more than ² cm ² , the above-mentioned precipitation of the catalytic element upon crystallization and etching damage in the process become remarkable.

In the present invention, the thickness of the amorphous silicon film to be crystallized by introducing a catalytic element is 25 to 50 nm.
Is preferably within the range. As described above, the width of the columnar crystal of the crystalline silicon film forming the channel region is
It is determined by stress, and attempts to spread in the horizontal direction by reducing the film thickness from 80 nm. As a result of experiments conducted by the present inventors, when the film thickness is 50 nm or less, the width of the columnar crystal becomes 150 nm or more. However, when the amorphous silicon film was further reduced in thickness to a thickness of 25 nm or less, sufficient crystallization did not occur even if the introduction amount of the catalytic element was increased.

In the second and third manufacturing methods according to the present invention, in addition to the central portion of the channel region, the contact region in contact with a part of the source or drain electrode of the source or drain region is formed by the first crystal. More preferably, it is formed by a laminated structure of a crystalline silicon film and a second crystalline silicon film. The contact area is
When a contact hole is opened in the upper layer film, it is simultaneously exposed to etching. That is, the contact region is likely to be thinned due to over-etching in the etching step, and in the worst case, the silicon film may disappear. Therefore, configuring the film thickness in this region to be as thick as possible leads to the stabilization of the whole process, and an improvement in the yield rate can be expected.

The types of catalyst elements that can be used in the present invention include Ni, Co, Pd, Pt, Cu, Ag, and A.
u, In, Sn, Al, and Sb can be used.
One or a plurality of elements selected from these elements have a slight effect on crystallization.

Among them, the most remarkable effect can be obtained particularly when Ni is used. The reason for this has not been fully understood, but the following model is conceivable. The catalyst element does not act alone, but acts on crystal growth by bonding to the silicon film to form silicide.
The model is such that the crystal structure at that time acts like a kind of template when the amorphous silicon film is crystallized, and promotes the crystallization of the amorphous silicon film. Ni is two Si and NiSi
Form a silicide of ₂ . NiSi ₂ exhibits a fluorite-type crystal structure, which is very similar to the diamond structure of single crystal silicon. Moreover, NiSi
₂ has a lattice constant of 5.406 °, which is very close to the lattice constant of 5.430 ° in the diamond structure of crystalline silicon. Therefore, NiSi ₂ is the best template for crystallizing an amorphous silicon film,
As the catalyst element in the present invention, it is particularly desirable to use Ni in particular.

[0072]

BEST MODE FOR CARRYING OUT THE INVENTION

[Embodiment 1] A first embodiment of the present invention will be described. In this embodiment, a case where the present invention is used in a process of manufacturing an N-type TFT on a glass substrate will be described. The TFT of this embodiment can be used not only as a pixel portion of an active matrix type liquid crystal display device but also as a driver circuit or an element constituting a CPU on the same substrate. It goes without saying that TFTs can be applied not only to liquid crystal display devices but also to thin film integrated circuits that are generally called.

FIG. 1 is a plan view showing an outline of a TFT manufacturing process described in this embodiment. FIG.
1 shows a cross-sectional view taken along the line AA ′ of FIG. 1, and (A) → (F)
, The manufacturing process proceeds sequentially.

First, as shown in FIG. 2A, a thickness of 30 mm is formed on a glass substrate 101 by, for example, a sputtering method.
A base film 102 of about 0 nm made of silicon oxide is formed. This silicon oxide film is provided to prevent diffusion of impurities from the glass substrate. Next, an intrinsic (I-type) amorphous silicon film (a-Si) having a thickness of 25 to 50 nm, for example, 50 nm is formed by a low pressure CVD method or a plasma CVD method.
A film 103 is formed.

Next, an insulating thin film such as a silicon oxide film or a silicon nitride film is deposited on the a-Si film 103 and patterned to provide a mask film 104. Here, FIG.
As shown in (A), the a-Si film 103 is exposed in a slit shape in the region 100 through the through hole of the mask film 104. That is, when the state of FIG. 2A is viewed from above, the a-Si film 103 is exposed in a slit shape in the region 100 as shown in FIG. 1, and the other portions are in a masked state. . In FIG. 1, reference numeral 115 denotes a source region, 116 denotes a drain region, and 114 denotes a channel region.

After providing the mask film 104, a-Si
In the region 100 where the surface of the film 103 is exposed, the catalyst element film 1
The substrate is held in contact with an aqueous solution in which nickel is dissolved to form 05. In this example, nickel nitrate was used as the solute and ethyl alcohol was used as the solvent, and the nickel concentration in the aqueous solution was adjusted to 10 ppm. Thereafter, the aqueous solution is uniformly spread on the substrate by a spinner and dried. By this step, nickel is selectively introduced into the portion of the a-Si film 103 exposed in the region 100. The surface density of nickel on the substrate surface at this time was determined by total reflection X-ray fluorescence impurity analysis.
The average was about 10 ¹³ atoms / cm ² . Then, this is annealed in an inert atmosphere, for example, at a heating temperature of 550 ° C. for 2 hours to be crystallized.

By the annealing step, only the a-Si film 103 in the region exposed in the region 100 is crystallized to become a crystalline silicon region 103a, and the other regions covered with the mask film 104 are a-Si films. Si region 103d
Remains as. In the present embodiment, when the above annealing step is further continued, nickel becomes crystalline silicon region 10.
Since it diffuses in the lateral direction from 3a, control of the annealing time is very important. The nickel concentration in the crystalline silicon region 103a obtained as described above was confirmed by secondary ion mass spectrometry (SIMS), and as a result, 2 × 10
It was about ¹⁸ atoms / cm ³ . The crystalline silicon region 103a is formed of a columnar crystal network structure, and the width of each columnar crystal at this time is 150 nm.
２００200 nm. Then, the mask film 104 is removed to obtain FIG.

Next, as shown in FIG. 2C, by irradiating a laser beam 108, the a-Si region 103d is crystallized and the crystallinity of the crystalline silicon region 103a introduced with nickel is promoted. I do. Laser light 1 at this time
08 is a XeCl excimer laser (wavelength 308).
nm, and a pulse width of 40 nsec). The irradiation condition of the laser beam is such that the substrate is heated to 200 to 450 ° C., for example, 400 ° C. at the time of irradiation, and the energy density is 200 to 350 mJ.
/ Cm ² , for example, at 250 mJ / cm ² . By this step, the a-Si region 103d becomes the crystalline silicon film 10d.
3c, nickel-introduced crystalline silicon region 103a
Becomes a crystalline silicon film 103a 'having better crystallinity. The nickel concentration in the crystalline silicon film 103c is equal to or lower than the measurement limit, and there is almost no diffusion of nickel from the crystalline silicon region 103a by this laser irradiation step.

Then, as shown in FIG. 2D, unnecessary portions of the a-Si film 103 are removed to perform element isolation.
Thereafter, an island-shaped crystalline silicon film to be an active region (source / drain region, channel region) 109 of the TFT is formed. Therefore, the active region 109 of the TFT is composed of two types of crystalline silicon films, that is, the crystalline silicon film 103a ′ formed by a catalytic element and the crystalline silicon film 103c formed by laser irradiation. When this state is viewed from above the substrate, it is as shown in FIG. That is, the active region 1 of the TFT
In 09, the central part of the channel region 114, that is, most of the channel region is composed of the crystalline silicon film 103a 'made of a catalytic element, and the junction between the channel region 114 and the source region 115 or the drain region 116 is formed only by laser irradiation. It is composed of a crystalline silicon film 103c.

Next, a thickness of 20 to 150 nm, in this case 1 to cover the crystalline silicon film to be the active region 109.
A 00 nm silicon oxide film is formed as the gate insulating film 110. Here, TEOS is used for forming the silicon oxide film.
(Tetra Ethoxy Ortho Silica
te) as a raw material and a substrate temperature of 150 to 60 together with oxygen.
RF plasma C at 0 ° C., preferably 300-450 ° C.
Decomposed and deposited by VD method. Alternatively, low pressure CVD or normal pressure CVD using TEOS as a raw material together with ozone gas
Depending on the method, the substrate may be formed at a substrate temperature of 350 to 600C, preferably 400 to 550C.

Subsequently, by a sputtering method,
An aluminum film having a thickness of 300 to 600 nm, for example, 400 nm is formed. Then, the gate electrode 111 is formed by patterning the aluminum film. Further, the surface of the aluminum electrode is anodized to form an oxide layer 112 on the surface. This state is shown in FIG. The anodization is performed in an ethylene glycol solution containing tartaric acid at 1 to 5%, and the voltage is first increased to 220 V at a constant current, and the state is maintained for 1 hour to complete the process. The thickness of the obtained oxide layer 112 is 200 nm. Note that this oxide layer 112 is used in a later ion doping step.
Since the thickness is such that the offset gate region is formed, the length of the offset gate region can be determined in the anodic oxidation step.

Next, an impurity (phosphorus) is implanted into the active region by ion doping using the gate electrode 111 and the oxide layer 112 around the gate electrode 111 as a mask. Phosphine (PH ₃ ) is used as the doping gas, the acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose is 1 × 10 4
¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 2 × 10 ¹⁵ cm ⁻² . By this step, the region into which the impurities are implanted becomes
FT source region 115 and drain region 116,
A region which is masked by the gate electrode 111 and the surrounding oxide layer 112 and into which impurities are not implanted will later become a channel region 114 of the TFT.

Thereafter, as shown in FIG. 1 (E), annealing is performed by irradiation with a laser beam 113 to activate the ion-implanted impurities, and at the same time, to the portions where the crystallinity has deteriorated in the above-described impurity introducing step. Improves crystallinity. In this case, the laser used with an XeCl excimer laser (wavelength 308 nm, pulse width 40 nsec), the energy density of 150~400mJ / cm ^2, preferably irradiation was performed at 200~250mJ / cm ^2. The sheet resistance of the source region 115 and the drain region 116 into which the N-type impurity (phosphorus) thus formed is implanted is 2
It was 00 to 800 Ω / □.

Subsequently, a silicon oxide film or a silicon nitride film having a thickness of about 600 nm is formed as the interlayer insulating film 117. When a silicon oxide film is used, if TEOS is used as a raw material and formed by plasma CVD with oxygen, reduced pressure CVD with ozone, or normal pressure CVD, good interlayer insulation with excellent step coverage can be obtained. A film is obtained. In addition, when a silicon nitride film formed by a plasma CVD method using SiH ₄ and NH ₃ as a source gas is used, hydrogen atoms are supplied to the interface between the active region and the gate insulating film, and the dangling bond that deteriorates TFT characteristics is supplied. Has the effect of reducing

Next, a contact hole is formed in the interlayer insulating film 117, and a metal material, for example, a two-layer film of titanium nitride and aluminum is used to form a TFT electrode / wiring 118, 1
19 is formed. The titanium nitride film is provided as a barrier film for preventing aluminum from diffusing into the semiconductor layer. Finally, in a hydrogen atmosphere of 1 atm.
C. for about one hour, and the T
Complete FT.

When the TFT manufactured as described above is used as an element for switching the pixel electrode, the electrode / wiring 118 or 119 is connected to the pixel electrode made of a transparent conductive film such as ITO, and the other electrode is connected. Input the signal. When the TFT according to the present invention is used for a thin film integrated circuit, a contact hole is also formed on the gate electrode 111 and a necessary wiring is provided.

The N-type TFT manufactured as described above has a field effect mobility μ _FE of 100 to 150 cm ² / Vs, a threshold voltage V _{TH of 2} to 3 V, and a rise coefficient (S coefficient) in a sub-threshold region. Very good ON characteristics of about 0.3 V / digit. In addition, T is particularly problematic for catalytic elements.
In the leakage current in the FT off region, Vds = 14
At V and Vg = 5 V, the voltage was greatly reduced to several pA as compared with the conventional 10 to 15 pA.

[Embodiment 2] A second embodiment of the present invention will be described. Also in this embodiment, as in the first embodiment,
A description will be given of a case where the present invention is used in a process of manufacturing an N-type TFT on a glass substrate.

FIG. 3 is a plan view showing an outline of a TFT manufacturing process described in this embodiment. FIG.
Shows a cross-sectional view taken along the line BB 'in FIG. 3, and (A) → (F)
, The manufacturing process proceeds sequentially.

First, as shown in FIG. 4A, a glass substrate 201 having a thickness of 30
A base film 202 of about 0 nm made of silicon oxide is formed. This silicon oxide film is provided to prevent diffusion of impurities from the glass substrate. Next, an intrinsic (I-type) amorphous silicon film (a-Si) having a thickness of 25 to 50 nm, for example, 30 nm is formed by a low pressure CVD method or a plasma CVD method.
A film 203 is formed.

Further, in order to form the catalyst element film 205 on the surface of the a-Si film 203, the gakaras substrate 201 is held so as to be in contact with an aqueous solution in which nickel is dissolved. In this example, nickel nitrate was used as the solute and ethyl alcohol was used as the solvent, and the nickel concentration in the aqueous solution was adjusted to 3 ppm. Thereafter, the aqueous solution is uniformly spread on the substrate by a spinner and dried. At this time, the surface density of nickel on the substrate surface was determined to be 5 × 10 ¹² atoms / cm ^{2 on} average as a result of total reflection X-ray fluorescence impurity analysis.
It was about. Then, this is annealed in an inert atmosphere, for example, at a heating temperature of 550 ° C. for about 4 hours to be crystallized.

By the above annealing step, the a-Si film 20 is formed.
3 is crystallized to form a crystalline silicon region 203a. In the present embodiment, the strict control of the annealing time is not necessary as in the first embodiment, and there is no problem even if the annealing time is extended beyond the time for sufficiently performing crystallization. The nickel concentration in the crystalline silicon region 203a obtained in this way was confirmed by secondary ion mass spectrometry (SIMS), and was about 2 × 10 ¹⁸ atoms / cm ³ . The crystalline silicon region 203a was constituted by a columnar crystal network, and the width of each columnar crystal at this time was 200 to 300 nm. Then, as shown in FIG. 4B, the crystalline silicon region 203a is patterned in an active region island shape except for the vicinity of the junction region between the source region or the drain region and the channel region.

Next, as shown in FIG. 4C, a second silicon film (a-Si film) 207 is formed so as to cover the crystalline silicon region 203a patterned in an island shape. The second a-Si film 207 was formed with a thickness of 30 nm by a plasma CVD method using SiH ₄ as a source gas. Then, as shown in FIG. 4C, the second a-Si film 207 is irradiated with a laser beam 208.
Is crystallized. At this time, the laser beam 208 includes
A XeCl excimer laser (wavelength 308 nm, pulse width 40 nsec) was used. The irradiation condition of the laser beam was such that the substrate was heated to 200 to 450 ° C., for example, 400 ° C. at the time of irradiation, and was irradiated at an energy density of 200 to 350 mJ / cm ² , for example, 250 mJ / cm ² . By this step, the second a-Si film 207 becomes the crystalline silicon film 207c. In particular, in the second a-Si film 207 on the island-shaped crystalline silicon region 203a, crystallization proceeds, reflecting good crystallinity of the lower-layer crystalline silicon region 203a, and is fused to form an interface boundary. Almost disappears. As a result, the crystalline silicon region 203a in the form of an island becomes a crystalline silicon film 203a ′ having better crystallinity as a whole. Further, the nickel concentration in the crystalline silicon film 207c is equal to or less than the measurement limit value, and there is almost no diffusion of nickel from the crystalline silicon region 203a due to the laser irradiation step.

Then, as shown in FIG. 4D, an unnecessary portion of the crystalline silicon film 207c is removed to perform element isolation, and thereafter, an active region (source / drain region,
An island-shaped crystalline silicon film to be a channel region 209 is formed. Therefore, the active region 209 of the TFT is mainly composed of two types of crystalline silicon films, that is, the crystalline silicon film 203a ′ formed by the catalytic element and the crystalline silicon film 207c formed only by the laser irradiation. When this state is viewed from above the substrate, it is as shown in FIG. That is, TFT
In the active region 209, the central portion of the channel region 214, that is, the majority of the channel region, and the majority of the source region 215 and the drain region 216, which will be contact regions with the electrodes later, are formed by the crystalline silicon film 203 formed by the catalytic element.
a ′, the channel region 214 and the source region 21
5 or only the junction of the drain region 216 is formed of the crystalline silicon film 207c by laser irradiation alone.

Next, a silicon oxide film having a thickness of 20 to 150 nm, here 100 nm, is formed as the gate insulating film 210 so as to cover the crystalline silicon film to be the active region 209. Here, TEOS is used for forming the silicon oxide film.
(Tetra Ethoxy Ortho Silica
te) as a raw material and a substrate temperature of 150 to 60 together with oxygen.
RF plasma C at 0 ° C., preferably 300-450 ° C.
Decomposed and deposited by VD method.

Subsequently, by a sputtering method,
An aluminum film having a thickness of 300 to 600 nm, for example, 400 nm is formed. Then, the gate electrode 211 is formed by patterning the aluminum film. Further, the surface of the aluminum electrode is anodized to form an oxide layer 212 on the surface. This state is shown in FIG. The anodization is performed in an ethylene glycol solution containing tartaric acid at 1 to 5%, and the voltage is first increased to 220 V at a constant current, and the state is maintained for 1 hour to complete the process. The thickness of the obtained oxide layer 212 is 200 nm. Note that this oxide layer 212 is formed in a later ion doping step.
Since the thickness is such that the offset gate region is formed, the length of the offset gate region can be determined in the anodic oxidation step.

Next, impurities (phosphorus) are implanted into the active region by ion doping using the gate electrode 211 and the oxide layer 212 around the gate electrode 211 as a mask. Phosphine (PH ₃ ) is used as the doping gas, the acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose is 1 × 10 4
¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 2 × 10 ¹⁵ cm ⁻² . By this step, the region into which the impurities are implanted becomes
FT source region 215 and drain region 216,
A region which is masked by the gate electrode 211 and its surrounding oxide layer 212 and into which impurities are not implanted will later become a channel region 214 of the TFT.

Thereafter, as shown in FIG. 4 (E), annealing is performed by irradiation with laser light 213 to activate the ion-implanted impurities, and at the same time, to remove the portions whose crystallinity has deteriorated in the above-described impurity introduction step. Improves crystallinity. In this case, the laser used with an XeCl excimer laser (wavelength 308 nm, pulse width 40 nsec), the energy density of 150~400mJ / cm ^2, preferably irradiation was performed at 200~250mJ / cm ^2. The sheet resistance of the source region 215 and the drain region 216 into which the N-type impurity (phosphorus) thus formed is implanted is 2
It was 00 to 800 Ω / □.

Subsequently, a silicon oxide film or a silicon nitride film having a thickness of about 600 nm is formed as the interlayer insulating film 217. When a silicon oxide film is used, if TEOS is used as a raw material and formed by plasma CVD with oxygen, reduced pressure CVD with ozone, or normal pressure CVD, good interlayer insulation with excellent step coverage can be obtained. A film is obtained.

Next, a contact hole is formed in the interlayer insulating film 217, and the electrode / wiring 218, 2
19 is formed. The titanium nitride film is provided as a barrier film for preventing aluminum from diffusing into the semiconductor layer. Finally, in a hydrogen atmosphere of 1 atm.
C., annealing for about 1 hour is performed, and T shown in FIG.
Complete FT.

When the TFT manufactured as described above is used as an element for switching the pixel electrode, the electrode / wiring 218 or 219 is connected to the pixel electrode made of a transparent conductive film such as ITO, and the other electrode is Input the signal. When the TFT according to the present invention is used for a thin film integrated circuit, a contact hole is also formed on the gate electrode 211 and a necessary wiring is provided.

The N-type TFT manufactured as described above has a field effect mobility μ _FE of 100 to 150 cm ² / Vs, a threshold voltage V _{TH of 2} to 3 V, and a rise coefficient (S coefficient) in a subthreshold region. Very good ON characteristics of about 0.3 V / digit. In addition, T is particularly problematic for catalytic elements.
In the leakage current in the FT off region, Vds = 14
At V and Vg = 5 V, the voltage was greatly reduced to several pA as compared with the conventional 10 to 15 pA.

[Embodiment 3] A third embodiment of the present invention will be described. In this embodiment, a peripheral drive circuit of an active matrix type liquid crystal display device and a circuit of a CMOS structure in which an N-type TFT and a P-type TFT forming a general thin film integrated circuit are formed in a complementary manner on a glass substrate. The steps will be described.

FIG. 5 is a plan view showing an outline of a manufacturing process of the TFT described in this embodiment. FIG. 6 is a cross-sectional view of FIG.
A cross-sectional view taken along the line C ′ is shown, and the process sequentially proceeds in the order of (A) → (F). Hereinafter, the manufacturing process of this embodiment will be described.

First, as shown in FIG. 6A, a glass substrate 301 having a thickness of 30
A base film 302 of about 0 nm made of silicon oxide is formed. Next, by plasma CVD or low pressure CVD, the intrinsic (I
) Amorphous silicon film (a-Si film) 303 is formed.

Next, a photosensitive resin (photoresist) is applied on the a-Si film 303, and is exposed and developed to form a mask film 304. Due to the through holes in the photoresist mask film 304, a-
The Si film 303 is exposed. That is, when the state of FIG. 6A is viewed from above, the a-Si film 303 is exposed in the region 300 as shown in FIG. 5, and the other portions are masked by the photoresist mask film 304. It has become.

After providing the mask film 304, FIG.
As shown in FIG. 3A, a thin film of nickel is deposited to form a catalyst element film 305. In this example, the distance between the deposition source and the substrate was made larger than usual, and the deposition rate was reduced, so that the thickness of the nickel film was controlled to be about 1 nm. When the areal density of nickel on the substrate at this time was actually measured, it was 4 × 10 ¹³ atoms /
cm ² . Then, as shown in FIG. 6B, by removing the photoresist mask film 304, the catalyst element film 305 on the mask film 304 is lifted off, and only the a-Si film 303 indicated by the region 300 is selected. This means that the catalytic element film 305, that is, a very small amount of nickel was introduced. Then, this is annealed in an inert atmosphere, for example, at a heating temperature of 550 ° C. for 8 hours to be crystallized.

At this time, in the region 300, a-Si
The substrate 3 is formed by using nickel added to the surface of the film 303 as a nucleus.
Crystallization of the silicon film occurs in a direction perpendicular to 01, and a crystalline silicon film 303a is formed. And the area 30
In the peripheral region of 0, crystal growth is performed in a lateral direction (a direction parallel to the substrate) from the region 300 as shown by an arrow 306 in FIG. 5 and FIG. The formed crystalline silicon film 303b is formed.
The other region of the a-Si film 303 remains as the amorphous silicon film region 303d. The nickel concentration in the laterally grown crystalline silicon film 303b is 10 ¹⁷
atoms / cm was about ^3, the nickel concentration in the seed region and the crystalline silicon film was introduced grown directly nickel also say 303a is 10 ¹⁹ atoms / cm ³
It was about. In the above crystal growth, arrows 306
The distance of crystal growth in the direction parallel to the substrate indicated by
It was about μm. Further, the crystalline silicon film 303b
Shows a crystal structure in which columnar crystals are one-dimensionally arranged along the crystal growth direction indicated by arrow 306, and the width of each columnar crystal was 200 to 300 nm. Then, as shown in FIG. 6C, patterning is performed so that the crystalline silicon film 303b having the best crystallinity among the a-Si films 303 is used as an element.

Next, as shown in FIG. 6C, a second silicon film (a-Si film) 307 is formed so as to cover the crystalline silicon film 303b patterned in an island shape.
The second a-Si film 307 is formed by a plasma CVD method.
It was formed with a thickness of 30 nm. And FIG.
As shown in (C), the second a-Si film 307 is crystallized by irradiation with a laser beam 308. As the laser light 308 at this time, a XeCl excimer laser (wavelength 308 nm, pulse width 40 nsec) was used.
The irradiation conditions of the laser beam are as follows.
0 ° C., for example, 400 ° C., and an energy density of 200
Irradiation was performed at 350 mJ / cm ² , for example, 250 mJ / cm ² . Through this step, the second a-Si film 307 becomes a crystalline silicon film 307c. In particular, in the second a-Si film 307 on the island-shaped crystalline silicon film 303b, crystallization proceeds, reflecting good crystallinity of the lower crystalline silicon film 303b, and the interface boundary almost disappears. I do. As a result, the island-shaped crystalline silicon film 303b region as a whole
Further, a crystalline silicon film 303b 'having good crystallinity is obtained. Further, the nickel concentration in the crystalline silicon film 307c is equal to or less than the measurement limit value, and there is almost no diffusion of nickel from the crystalline silicon film 303b by this laser irradiation step.

Thereafter, as shown in FIG.
Leaving crystalline silicon films to be FT active regions (source / drain regions, channel regions) 309n and 309p;
The crystalline silicon film 307 in the other area is removed by etching to perform element isolation. Therefore, the active region 309n of the N-type TFT and the active region 309p of the P-type TFT
Is a crystalline silicon film 30 laterally grown mainly by a catalytic element.
3b 'and crystalline silicon film 307 by laser irradiation only
It is composed of two types of crystalline silicon films of c. When this state is viewed from above the substrate, it is as shown in FIG. That is, in both the N-type and P-type TFTs, in the active region 309, the central part of the channel region 314, that is, most of the channel region, and most of the source region 315 and the drain which will later become the contact region with the electrode. The region 316 includes the crystalline silicon film 3 formed by the catalytic element.
Only the junction between the channel region 314 and the source region 315 or the drain region 316 is formed of the crystalline silicon film 307c formed by laser irradiation alone. Here, the direction in which carriers move in the TFT is the direction from the source region 315 to the drain region 316, and the direction in which the crystal growth direction of the crystalline silicon film 303b is 3
It is designed in advance so as to be in a direction substantially parallel to 06.

Next, the active regions 309n and 39
100 nm thick so as to cover the crystalline silicon film which becomes 0p
A silicon oxide film is formed as the gate insulating film 310. In this embodiment, as a method for forming the gate insulating film 310, TEOS is used as a raw material, and a substrate temperature of 350 ° C. is used together with oxygen.
Then, it was decomposed and deposited by the RF plasma CVD method.

Subsequently, as shown in FIG. 6E, aluminum (including 0.1 to 2% silicon) having a thickness of 300 to 600 nm, for example, 400 nm is formed by sputtering, and the aluminum film is patterned. Thus, gate electrodes 311n and 311p are formed.

Next, the gate electrodes 311n, 311n are formed in the active regions 309n, 309p by ion doping.
Impurities (phosphorus and boron) are implanted using p as a mask. Phosphine (PH ₃ ) as doping gas
And using diborane (B ₂ H _6), in the former case, the acceleration voltage 60～90KV, for example 80 kV, in the latter case, 40KV～80kV, for example, a 65 kV, the dose is 1 × 10 ¹⁵ ~8 × 10 ¹⁵ cm ^-2 , for example 2x phosphorus
It is 10 ¹⁵ cm ^-2 and boron is 5 × 10 ¹⁵ cm ^-2 . By this step, regions which are masked by the gate electrodes 311n and 311p and into which impurities are not implanted later become channel regions 314n and 314p of the TFT. For doping,
Each element is selectively doped by covering a region where doping is unnecessary with a photoresist.
As a result, the source region 3 into which the N-type impurity region has been implanted.
15n, a drain region 316n, and a source region 315p and a drain region 316p into which P-type impurities are implanted are formed. As shown in FIGS. 5 and 6E, an N-channel TFT (NTFT) and a P-channel TFT ( PTFT)
And can be formed.

Then, as shown in FIG. 6E, annealing is performed by irradiation with a laser beam 313 to activate the ion-implanted impurities. As the laser light, Xe
Cl excimer laser (wavelength 308 nm, pulse width 40
nsec), and the laser beam was irradiated at an energy density of 250 mJ / cm ² for 5 shots per location.

Subsequently, as shown in FIG.
A 00 nm silicon oxide film is formed as an interlayer insulating film 317 by a plasma CVD method, a contact hole is formed in the interlayer insulating film 317, and a metal material, for example, a two-layer film of titanium nitride and aluminum is used to form a TFT electrode / wiring 318, 31.
9, 320 are formed. Finally, annealing is performed at 350 ° C. for about 1 hour in a hydrogen atmosphere at 1 atm.
A CMOS circuit using NTFT and PTFT shown in FIG.

The CMO manufactured according to the above embodiment
In the S structure circuit, the field-effect mobility of each TFT is 150 to ²⁰⁰ cm ² / Vs for an N-type TFT, and
The FT is as high as 80 to 100 cm ² / Vs, and the threshold voltage is N
Very good characteristics of 1.5 to 2 V for a TFT and -2 to -3 V for a P-type TFT. Furthermore, the leakage current in the TFT off region was suppressed to about several pA for both the N-type TFT and the P-type TFT, which was lower than the conventional method.

Although the three embodiments according to the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications based on the technical idea of the present invention are possible. It is.

For example, in the above three embodiments,
As a method for introducing nickel, a method of applying an aqueous solution in which a nickel salt is dissolved on the surface of an amorphous silicon film, or a method of forming a nickel thin film by a vapor deposition method is employed.
However, a method in which nickel is introduced into the surface of the base film before the amorphous silicon film is formed, and nickel is diffused from the lower layer of the amorphous silicon film to perform crystal growth. That is, crystal growth may be performed from the upper surface side or the lower surface side of the amorphous silicon film. Also, as a method for introducing nickel,
In addition, various methods can be used. For example, as a solvent for dissolving a nickel salt, there is a method of diffusing an SOG (spin-on-glass) material from a SiO ₂ film as a solvent, a method of forming a thin film by a sputtering method or a plating method, or a method of directly introducing a thin film by an ion doping method. Also available. Further, as impurity metal elements that promote crystallization, besides nickel (Ni), cobalt (Co), palladium (Pd), platinum (Pt), copper (C
u), silver (Ag), gold (Au), indium (In),
Tin (Sn), aluminum (Al), antimony (S
A similar effect can be obtained by using b).

In the above embodiment, a heating method using XeCl excimer laser irradiation as a pulse laser was used as a means for forming a crystalline silicon film for forming a junction between a channel region and a source region or a drain region. The same processing can be performed with other lasers (for example, a KrF excimer laser having a wavelength of 248 nm, a continuous oscillation Ar laser having a wavelength of 488 nm, or the like). In addition, a so-called R which heats the sample by raising the temperature to 1000 to 1200 ° C. (temperature of the silicon monitor) in a short time by using an infrared light or a flash lamp instead of the laser light is used.
Intense light equivalent to so-called laser light such as TA (rapid thermal annealing) (RTP, also referred to as rapid thermal process) may be used.

Further, as an application of the present invention, in addition to an active matrix type substrate for liquid crystal display, for example, a contact type image sensor, a thermal head with a built-in driver, and a driver built-in type using an organic EL as a light emitting element. An optical writing element, a display element, a three-dimensional IC, and the like can be considered. By using the present invention, high performance such as high speed and high resolution of these elements is realized.

[0121]

By using the present invention, it is possible to realize a high-performance semiconductor device having a high current driving capability, a small leakage current at the time of an off operation, and a stable characteristic. In particular, in a liquid crystal display device, the switching characteristics of the pixel switching TFT required for the active matrix substrate are improved, and the high performance and high integration required for the TFTs constituting the peripheral driving circuit are simultaneously satisfied. In addition, a driver monolithic active matrix substrate constituting an active matrix section and a peripheral drive circuit section can be realized, and the module can be made compact, high performance, and low cost.

[Brief description of the drawings]

FIG. 1 shows an outline of a first embodiment.

FIG. 2 shows a manufacturing process of the first embodiment.

FIG. 3 shows an outline of a second embodiment.

FIG. 4 shows a manufacturing process of the second embodiment.

FIG. 5 shows an outline of a third embodiment.

FIG. 6 shows a manufacturing process of the third embodiment.

FIG. 7 shows the effect of the present invention over the conventional method.

FIG. 8 shows a mechanism of generating a leak current.

[Explanation of symbols]

101, 201, 301 Glass substrate 102, 202, 302 Base film 103, 203, 303 Amorphous silicon film (a
-Si film) 104, 304 Mask film 105, 205, 305 Catalyst element film 306 Arrows 207, 307 Second silicon film (a-Si)
Film) 108, 208, 308 Laser light 109, 209, 309 Active region 110, 210, 310 Gate insulating film 111, 211, 311 Gate electrode 112, 212 Oxide layer 113, 213, 313 Laser light 114, 214, 314 Channel Region 115, 215, 315 Source region 116, 216, 316 Drain region 117, 217, 317 Interlayer insulating film 118, 218, 318 Electrode / wiring 119, 219, 319, 320 Electrode / wiring

Claims (16)

(57) [Claims] 1. A thin film transistor in which an active region including a source region, a drain region, and a channel region is formed in a crystalline silicon film formed over a substrate having an insulating surface, wherein the active region is a non-conductive type. A catalyst element for promoting crystallization of the amorphous silicon film, wherein the concentration of the catalyst element near the junction between the source region or the drain region and the channel region in the active region is made smaller than at least the central portion of the channel region. Semiconductor device. 2. A thin film transistor in which an active region including a source region, a drain region and a channel region is formed on a crystalline silicon film formed on a substrate having an insulating surface, wherein: The central portion of the channel region is crystallized and contains a catalyst element that promotes crystallization of the amorphous silicon film, and is constituted by a columnar crystal network structure, near the junction between the source region or the drain region and the channel region. Is a crystalline silicon film crystallized without containing the catalyst element. 3. A thin film transistor in which an active region including a source region, a drain region and a channel region is formed on a crystalline silicon film formed on a substrate having an insulating surface, wherein: The central portion of the channel region is formed by laterally growing the amorphous silicon film from the region into which the catalytic element for promoting crystallization of the amorphous silicon film is selectively introduced to the peripheral region. The columnar crystal has a crystal structure in which directions are almost aligned in one direction, and the vicinity of a junction between the source region or the drain region and the channel region is a crystalline silicon film crystallized without containing the catalyst element. A semiconductor device, comprising: 4. The semiconductor device according to claim 3, wherein the crystalline silicon film is a crystal silicon film grown laterally and constituting a central portion of a channel region of the thin film transistor. A semiconductor device characterized in that the moving direction is substantially parallel. 5. The semiconductor device according to claim 2, wherein each of the columnar crystals constituting the channel region has a width of 1
A semiconductor device having a thickness of 50 nm to 400 nm. 6. The semiconductor device according to claim 1, wherein the concentration of the catalytic element in the central part of the channel region is 10 ¹⁶ to 10 ¹⁶ .
A 10 ¹⁹ atoms / cm ^3, the concentration of the catalyst element near the junction between the source region or the drain region and the channel region, and wherein a is less than 10 ¹⁶ atoms / cm ^3. 7. A step of forming an amorphous silicon film on a substrate; a step of, before or after the step, selectively introducing a catalyst element that promotes crystallization of the amorphous silicon film; A step of selectively crystallizing the amorphous silicon film in the region into which the element is introduced by heat treatment; a step of crystallizing the amorphous silicon film in the other region by irradiating with strong light; A part of the channel region of the thin film transistor is formed using the region crystallized by the introduced heat treatment,
Producing a junction region between a source region or a drain region of a thin film transistor and a channel region by using another region crystallized by intense light irradiation, respectively. 8. A step of forming a first amorphous silicon film on a substrate, before or after the step, a step of introducing a catalytic element that promotes crystallization of the amorphous silicon film, A step of crystallizing the first amorphous silicon film into which the catalyst element has been introduced by heat treatment to form a first crystalline silicon film; and patterning the first crystalline silicon film. Forming an island-shaped region that is to be a part of a channel region of the thin film transistor; forming a second amorphous silicon film so as to cover the island-shaped region; A semiconductor film comprising: a step of forming a crystalline silicon film; and a step of forming a junction region between a source region or a drain region and a channel region of a thin film transistor by using a region of the second crystalline silicon film alone. Equipment manufacturing method . 9. A step of forming a first amorphous silicon film on a substrate, and before or after the step, a catalytic element for promoting crystallization of the amorphous silicon film is partially selected. A step of selectively crystallizing the amorphous silicon film in a region where the catalytic element is selectively introduced by heat treatment, and further continuing the heat treatment to form the amorphous silicon film. From the region where the silicon film was selectively crystallized to its periphery,
Crystal-growing the amorphous silicon film in a direction substantially parallel to the substrate surface to form a first crystalline silicon film; and patterning the first crystalline silicon film. A step of forming an island-shaped region that becomes a part of a channel region of a subsequent thin film transistor by using a region where crystal growth is performed in a direction substantially parallel to a substrate surface in the silicon film; Forming a second amorphous silicon film, crystallizing the film by intense light irradiation to form a second crystalline silicon film, and using a region of the second crystalline silicon film alone to form a source of the thin film transistor. Forming a junction region between a region or a drain region and a channel region. 10. The method for manufacturing a semiconductor device according to claim 7, wherein the introduction of the catalyst element is performed by depositing a thin film of the catalyst element on the surface of the amorphous silicon film by a vacuum evaporation method. A method of manufacturing a semiconductor device. 11. The method of manufacturing a semiconductor device according to claim 7, wherein the introduction of the catalytic element is performed by spin-coating a solution containing the catalytic element on the surface of the amorphous silicon film. A method of manufacturing a semiconductor device. 12. The method for manufacturing a semiconductor device according to claim 11, wherein a nitrate or an acetate of a catalyst element is used as a solute of the solution containing the catalyst element. 13. The method for manufacturing a semiconductor device according to claim 11, wherein an alcohol such as ethanol is used as a solvent of the solution containing the catalyst element. 14. The method of manufacturing a semiconductor device according to claim 10, wherein the step of introducing the catalyst element comprises measuring the concentration of the catalyst element introduced into the amorphous silicon film by total reflection X-ray fluorescence spectrometry. A method of manufacturing a semiconductor device, wherein the surface concentration is controlled as a surface concentration on a surface of an amorphous silicon film. 15. The method of manufacturing a semiconductor device according to claim 7, wherein the amorphous silicon film for introducing and catalyzing the catalyst element has a thickness of 25 to 50 nm. A method for manufacturing a semiconductor device, wherein the range is within the range. 16. The method for manufacturing a semiconductor device according to claim 7, wherein the contact region that is in contact with the source electrode or the drain electrode includes the first crystalline silicon film and the second crystalline silicon. A method for manufacturing a semiconductor device, wherein the method is formed by a laminated structure of films.