JP3981517B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using a crystalline silicon film obtained by crystallizing an amorphous silicon film as an active region. In particular, the present invention is effective for manufacturing a semiconductor device using a thin film transistor (TFT) provided over a substrate having an insulating surface, such as an active matrix liquid crystal display device, a contact image sensor, and a three-dimensional IC. Available for manufacturing.
[0002]
[Prior art]
  In recent years, high-performance liquid crystal display devices, high-speed, high-resolution contact-type image sensors, three-dimensional ICs, etc. have been developed with high-performance semiconductor elements on insulating substrates such as glass and insulating films. Attempts have been made to form. As a semiconductor element used in these devices, a thin film silicon semiconductor is generally used. Thin film silicon semiconductors can be broadly classified into two types: those composed of amorphous silicon semiconductors (a-Si) and those composed of crystalline silicon semiconductors.
[0003]
  Amorphous silicon semiconductors are most commonly used because they have a low production temperature, can be produced relatively easily by a vapor phase method, and are excellent in mass productivity. It is inferior to a silicon semiconductor having crystallinity. For this reason, in order to obtain higher speed characteristics in the future, establishment of a method for manufacturing a semiconductor device made of a crystalline silicon semiconductor has been strongly demanded. Note that polycrystalline silicon, microcrystalline silicon, and the like are known as crystalline silicon semiconductors.
[0004]
  As a method of obtaining a thin film silicon semiconductor having these crystallinity,
    (1) A film having crystallinity is directly formed at the time of film formation.
[0005]
    (2) An amorphous semiconductor film is formed and given crystallinity by the energy of laser light.
[0006]
    (3) An amorphous semiconductor film is formed, and crystallinity is imparted by applying thermal energy.
[0007]
  Such a method is known.
[0008]
  However, in the method (1), since crystallization proceeds simultaneously with the film forming step, it is indispensable to increase the thickness of the silicon film in order to obtain large-grained crystalline silicon, and it has good semiconductor properties. It is technically difficult to form a film uniformly on the entire surface of the substrate.
[0009]
  In the method (2), since the crystallization phenomenon of the melt-solidification process is used, the grain boundary is well processed despite the small particle size, and a high-quality crystalline silicon film can be obtained. Taking the excimer laser used in the above as an example, a sufficiently stable one has not yet been obtained. Therefore, it is difficult to uniformly treat the entire surface of the large area substrate, and further technical improvement in hardware is desired.
[0010]
  On the other hand, the method (3) is advantageous in terms of uniformity and stability in the substrate as compared with the methods (1) and (2), but heating at 600 ° C. for about 30 hours. There is a problem that processing is necessary, processing time is long, and throughput is low. Further, in this method, since the crystal structure is a twin structure, one crystal grain is relatively large as a few μm. However, the crystal grain includes a large number of twin defects and is larger than the method (2). Crystallinity is inferior. As a means for improving the crystallinity, a method of performing a heat treatment in an oxygen atmosphere at about 1000 ° C. is also used, but in this case, it is not a process in which an inexpensive glass substrate can be used. As a characteristic, field effect mobility 100 cm in TFT²Only characteristics as low as / Vs are obtained.
[0011]
  In contrast to these methods, Japanese Patent Laid-Open Nos. 10-223534 and 10-229048 propose methods for improving the method (3) and obtaining a high-quality crystalline silicon film. In these methods, a catalytic element that promotes crystallization of the amorphous silicon film is used to lower the heating temperature, shorten the treatment time, and improve the crystallinity. Specifically, a trace amount of a metal element such as nickel or palladium is introduced into the surface of the amorphous silicon film, and then heating is performed.
[0012]
  The mechanism of this low-temperature crystallization is understood by the fact that crystal nucleation occurs first with a metal element as a nucleus, and then the metal element acts as a catalyst to promote crystal growth and the crystallization proceeds rapidly. . In this sense, these metal elements are hereinafter called catalyst elements. Crystalline silicon films crystallized and promoted by these catalytic elements are formed by twinning within one grain of the crystalline silicon film crystallized by the usual solid phase growth method (method (3) above). Although it has a structure and many crystal defects, the inside of the grain is composed of a number of columnar crystal networks, and each columnar crystal has an almost ideal single crystal state. Yes.
[0013]
  Further, in the above publication, the catalytic element is selectively introduced into a part of the amorphous silicon film and heated to selectively leave the other part in the amorphous silicon film state while selectively leaving the catalytic element. Only the region where is introduced is crystallized. Further, a method is shown in which the crystal growth is performed in the lateral direction (direction parallel to the substrate) from the introduction region by extending the heating time. Inside this lateral crystal growth region, columnar crystals with almost uniform growth directions are packed together, and the crystallinity is higher than that of the region where the catalyst element is directly introduced and random generation of crystal nuclei occurs. It is a better region. Therefore, by using the crystalline silicon film in the lateral crystal growth region in the active region of the semiconductor device, higher performance of the semiconductor device can be achieved.
[0014]
  Here, in the said Unexamined-Japanese-Patent No. 10-223534 and Unexamined-Japanese-Patent No. 10-229048, the group 5 B elements, such as phosphorus, are selectively introduce | transduced into one part with respect to the silicon crystallized by the catalytic element, By performing the heat treatment, the catalytic element is moved (gettered) to the region where the Group 5 B element is introduced. Furthermore, in these publications, the heat treatment in the gettering step is performed by intense light irradiation. And in order to raise the heating efficiency of the light in the case of this intense light irradiation, the film | membrane with high absorption efficiency with respect to the strong light to be used is further laminated | stacked. In this case, in JP-A-10-223534, a film having a high absorption efficiency for strong light at this time is selectively provided also as an introduction mask for introducing a group 5 B element. On the other hand, in Japanese Patent Application Laid-Open No. 10-229048, the above-described film having a high strong light absorption efficiency is newly provided on the entire surface of the substrate after introducing the Group 5 B element.
[0015]
[Problems to be solved by the invention]
  The method of crystallizing an amorphous silicon film by introducing a catalytic element can lower the heating temperature and shorten the heating time, and the crystallinity of the silicon film obtained after crystallization is different from that of other crystallization. It is clearly superior to the method.
[0016]
  However, the presence of a large amount of catalytic elements mainly composed of these metals in the semiconductor hinders the reliability and electrical stability of the apparatus using these semiconductors, and is not preferable. .
[0017]
  That is, the catalyst element for promoting crystallization, such as nickel, is necessary for crystallizing amorphous silicon, but it is desirable that the crystallized silicon is not contained as much as possible. In order to achieve this object, first, it is necessary to minimize the amount of catalyst element necessary for crystallization and perform crystallization with a minimum amount. However, if the amount of catalyst element introduced is reduced, the growth state becomes very unstable. A crystalline silicon film prepared in such a state has a very large variation in crystallinity within the substrate, and cannot be used as a film constituting an active region of a semiconductor device.
[0018]
  Therefore, as described in the above publication, the second method is a method of removing or reducing the catalytic element in the element region by moving (gettering) the catalytic element after crystal growth using the catalytic element. Is considered. However, when the inventors actually conducted experiments using methods such as Japanese Patent Laid-Open Nos. 10-223534 and 10-229048 and prototyped a thin film transistor (TFT) device, sufficient effects were obtained. I knew it was n’t there. Specifically, even after a process called gettering, a large amount of the catalytic element still exists, which has an obvious adverse effect on the TFT element. In particular, after the gettering step, when the introduction region is removed and heat treatment is performed at a higher temperature, the catalyst elements remaining in the element region reaggregate and appear in a silicide state. This is proof that these gettering methods are still insufficient. If these catalytic elements are present at the junction of the TFT, they become a leakage source, and the leakage current during the off operation is greatly increased. When a TFT was actually prototyped, a defective TFT with a very large leakage current at the off time appeared with a probability of about 3% in the methods disclosed in Japanese Patent Laid-Open Nos. 10-223534 and 10-229048. When the cause of the defective TFT was analyzed, it was confirmed that silicide due to the catalytic element was present at the junction between the channel portion and the drain portion.
[0019]
  As described above, the methods of the above two publications cannot sufficiently reduce the amount of catalytic element in the element region. As a result, even if a high-performance semiconductor device can be partially manufactured, the defect rate is high, the reliability is very poor, and it is not a technology that can be mass-produced.
[0020]
  Accordingly, an object of the present invention is to solve these problems. In other words, an object of the present invention is to use a silicon film crystallized using a catalytic element as an active region of a semiconductor device, and to sufficiently reduce the catalytic element in the element region after crystallization, thereby achieving high performance and high reliability. An object of the present invention is to provide a manufacturing method capable of mass-producing the semiconductor device.
[0021]
[Means for Solving the Problems]
  The present inventors paid attention to high-quality crystalline silicon films crystallized using catalytic elements, and thought that they could be evolved from a current laboratory level to a process that can withstand mass production. Piled up. And finally, a method for solving the above problems was found.
[0022]
  The present invention solves all the above-mentioned problems and provides means for satisfying the above-mentioned object, and has a high performance and high performance having stable characteristics with good uniformity on a substrate having an insulating surface such as glass. The present invention provides a reliable semiconductor device with a good product rate. More specifically, the present invention has the following features.
[0023]
  That is, in the method for manufacturing a semiconductor device of the present invention, a catalytic element introduction step of forming an amorphous silicon film on a substrate having an insulating surface and introducing a catalytic element for promoting crystallization into the amorphous silicon film. When,
  A crystal growth step for performing a heat treatment to perform crystal growth of the amorphous silicon film into which the catalyst element is introduced;
  A group 5 element introduction step of selectively introducing an element selected from group 5 B into a portion of the silicon film grown as a crystal;
  A catalytic element transfer step of performing a rapid thermal annealing process to move the catalyst element to a region into which an element selected from Group 5 B is introduced;
  An active region forming step of forming an active (channel) region of a semiconductor device using a silicon film in a region other than a region into which an element selected from Group 5 B is introduced,
  In the group 5 element introduction step, the silicon film in the region where the element selected from group 5 B is introduced is amorphized,
  In the catalyst element transfer step, during a temperature rising period from a preheating temperature at which an element selected from Group 5 B is introduced and amorphized to at least crystallize, to a temperature at which rapid thermal annealing is performed , Rapid thermal annealing is performed at a rate of temperature rise that does not completely crystallize the amorphous region,
  In the rapid thermal annealing, the substrate is inserted one by one in a resistive heating furnace having a thermal gradient in the furnace, and the temperature raising / lowering speed is controlled by controlling the speed of this insertion,
  The catalyst element transfer step includes
  The temperature is increased from a preheating temperature of 600 ° C. or less to a rapid thermal annealing temperature at a temperature rising rate exceeding 30 ° C./min.
[0024]
  In the present invention, a catalytic element for promoting crystallization is introduced into an amorphous silicon film formed on an insulating substrate, and crystal growth is performed by heat treatment. An element selected from Group B is introduced, and rapid thermal annealing is performed to move the catalyst element to a region where the element selected from Group 5 B is introduced. Then, the active (channel) region of the semiconductor device is formed by using the silicon film in a region other than the region into which the element selected from Group 5 B is introduced. By doing so, it becomes possible to greatly reduce the amount of residual catalytic elements in the active region of the semiconductor device as compared with the conventional method.
[0025]
  In one embodiment of the method for manufacturing a semiconductor device, an amorphous silicon film is formed on a substrate having an insulating surface, and a catalytic element that promotes crystallization is selectively formed on a part of the amorphous silicon film. A catalyst element introduction step to be introduced into
  A crystal growth step of performing a heat treatment and causing the amorphous silicon film to grow in the lateral direction (parallel to the substrate) from the region where the catalytic element is selectively introduced to the peripheral region thereof;
  A group 5 element introduction step of selectively introducing an element selected from group 5 B into a portion of the silicon film grown as a crystal;
  A catalytic element transfer step of performing a rapid thermal annealing process to move the catalyst element to a region into which an element selected from Group 5 B is introduced;
  An active region forming step of forming an active (channel) region of a semiconductor device using a silicon film crystallized in the lateral direction outside the region in which an element selected from Group 5 B is introduced;
  In the group 5 element introduction step, the silicon film in the region where the element selected from group 5 B is introduced is amorphized,
  In the catalyst element transfer step, during a temperature rising period from a preheating temperature at which an element selected from Group 5 B is introduced and amorphized to at least crystallize, to a temperature at which rapid thermal annealing is performed , Rapid thermal annealing is performed at a rate of temperature rise that does not completely crystallize the amorphous region,
  In the rapid thermal annealing, the substrate is inserted one by one in a resistive heating furnace having a thermal gradient in the furnace, and the temperature raising / lowering speed is controlled by controlling the speed of this insertion,
  The catalyst element transfer step includes
  The temperature is increased from a preheating temperature of 600 ° C. or less to a rapid thermal annealing temperature at a temperature rising rate exceeding 30 ° C./min.
[0026]
  In this embodiment, the catalytic element is selectively introduced into a part of the amorphous silicon film formed on the insulating substrate and heated, so that the area around the area from the selective introduction of the catalytic element is increased. Crystal growth of the amorphous silicon film is performed in the lateral direction (parallel to the substrate) to the region. Furthermore, a region in which the element selected from Group 5 B is introduced by selectively introducing an element selected from Group 5 B into a part of the silicon film that has been crystal-grown, and performing rapid thermal annealing treatment. Then, the catalyst element is moved. In this case, when an active (channel) region of a semiconductor device is formed using a silicon film that is laterally grown outside the region in which an element selected from Group 5 B is introduced, a higher current driving capability can be obtained. A high-performance semiconductor device can be obtained. Of course, the amount of residual catalytic elements in the active region of the semiconductor device can also be greatly reduced as compared with the conventional method, and there is no abnormal leakage current during off-operation, which is a problem, and high reliability can be secured at the same time. did it.
[0027]
  Now, this embodiment is different from the above-mentioned Japanese Patent Laid-Open Nos. 10-223534 and 10-229048 in that the strong heat is irradiated to selectively heat the silicon film. In contrast to using a mask film for absorbing light, in this embodiment, the entire substrate is uniformly annealed by rapid thermal annealing. Therefore, an extra mask film as in the above publication is not necessary. The point is to uniformly heat the entire substrate. For example, in the above-mentioned JP-A-10-223534, a region covered with a strong light absorption mask is intensively annealed, but a group 5 B element is introduced. The area does not rise sufficiently in temperature. In such a case, it has been found that sufficient gettering cannot be obtained. Therefore, the inventors of the above publication continue to make an invention such as the following Japanese Patent Application Laid-Open No. 10-229048. In this publication, a film for absorbing strong light is formed on the entire surface of the substrate, and the entire substrate including the region into which the group 5 B element is introduced is to be annealed uniformly. Although this method has a higher gettering effect, the formation of a mask film for heat absorption of intense light is an extra step. In addition, this method alone still does not have a sufficient gettering effect, and further requires a plus α. The reason for this will be described next.
[0028]
  Further, the major points of the present invention and the above embodiment lie in the state of the introduction region after the introduction of the group 5 B element and the temperature increase rate in the subsequent rapid thermal annealing treatment. That is, in this embodiment, in the step of selectively introducing an element selected from Group 5 B into the crystal-grown silicon film, the silicon film in the region where the element selected from Group 5 B is introduced is amorphous. It is important to be qualitative.
[0029]
  Further, in the subsequent rapid thermal annealing process, the temperature is increased from a preheating temperature at which the Group 5 B element is introduced and the amorphous region is not crystallized to a temperature at which the rapid thermal annealing process is performed. During the period, it is very important that the heating is performed at such a temperature rising rate that the amorphous region is not completely crystallized. Accordingly, the effect of moving (gettering) the obtained catalyst element to the introduction region of the group 5 B element is greatly different. Generally, the gettering effect is improved by increasing the temperature of the heat treatment after the introduction of the Group 5 B element. This is because the diffusion rate of the catalytic element in the silicon film is improved and the solid solubility limit is increased. However, it is known that the gettering effect at this time reaches a peak at about 650 ° C., and the effect cannot be obtained even if the temperature is increased further. The experimental results are shown in FIG. The vertical axis represents the residual ratio of the catalyst element in the silicon film before and after the heat treatment is performed by introducing the group 5 B element. The horizontal axis indicates the temperature of the heat treatment. In FIG. 8, a broken line is data in the conventional method. As described above, the reduction effect has reached its peak at about 650 ° C., and the residual ratio at that time is about 0.2, that is, about 20% of the catalyst elements existing after crystallization of the silicon film. Elements still remained and could not be removed even if the temperature was raised further.
[0030]
  When the present inventors examined this reason in detail, whether or not the introduction region of the group 5 B element is crystallized in this heat treatment is a big point in terms of the gettering efficiency. all right. Then, the region into which the Group 5 B element has been introduced is made amorphous in the introduction step, and while maintaining the amorphous state, the temperature is raised to a higher temperature and heat treatment is performed. It has been found that a higher gettering effect than ever seen can be obtained at 650 ° C. or higher. Data when using this embodiment at this time is shown by a solid line in FIG. In particular, at a temperature of 650 ° C. or higher, there is a clear difference from the conventional method, and the catalyst element residual ratio is greatly reduced. Therefore, the reason for limiting the conventional gettering effect is considered to be that the region into which the group 5 B element has been introduced is recrystallized during the heat treatment of gettering. However, at this time, unless the region into which the group 5 B element is introduced is also kept at a high temperature, the gettering effect cannot be obtained, and crystal growth inevitably occurs during the temperature rising process.
[0031]
  That is, in the conventional method, when the region into which the group 5 B element is introduced is crystallized in the temperature raising process, the gettering effect cannot be obtained at that temperature. It is thought that there is a limit to the effect.
[0032]
  On the other hand, in this embodiment, high-speed thermal annealing is used as the heat treatment at this time, and a high-speed heat treatment is performed from a preheating temperature at which the region made amorphous by introduction of the Group 5 B element is not crystallized. It is a very important point to perform the heating at such a temperature rising rate that the amorphous region is not completely crystallized during the temperature rising period up to the temperature at which the thermal annealing treatment is performed. By doing so, annealing can be performed for the first time at the intended annealing temperature with the region into which the Group 5 B element has been introduced being in an amorphous state, and the heat treatment temperature at this time is inherently high. A gettering effect can be obtained.
[0033]
  According to the present embodiment, the crystalline silicon film thus obtained is subjected to a light etching process using a hydrofluoric acid-based etchant, which has been conventionally used as a method for simply confirming the remaining of the catalytic element, and remains. Even when an evaluation for revealing the catalyst element is performed, no etch pits that have been seen in the past can be seen. Further, as a more severe evaluation, when further heat treatment is performed, the catalytic element remaining in the element region re-aggregates and appears in a silicide state, but even if such an evaluation is performed, No reaggregation of the catalytic element was observed as found in the techniques of JP-A-10-223534 and JP-A-10-229048. Then, when a thin film transistor (TFT) was actually created using this embodiment, when the TFT was similarly created in the above publication and the prior art, an abnormal leakage current at the time of TFT off, which was found with a probability of 3% or more, was found. The increase phenomenon was not seen at all in the method of this embodiment, and was exactly 0%. Furthermore, the liquid crystal display device made using this TFT has no display irregularities (due to sampling TFTs in the driver section) and pixel defects caused by leakage current at the time of off, which are frequently caused by conventional methods, and display quality is greatly improved. In addition to the improvement, the yield rate was dramatically increased.
[0034]
  Further, according to the present invention and the above embodiment, in the method for manufacturing a semiconductor device described above, the catalyst element transfer step is performed at a rate of temperature increase exceeding 30 ° C./min from a preheating temperature of 600 ° C. or less to a rapid thermal annealing temperature. Raise the temperature at.
[0035]
  In another embodiment, in the semiconductor device manufacturing method described above, the catalytic element transfer step is performed at a temperature rising rate exceeding 100 ° C./min from a preheating temperature of 600 ° C. or less to a rapid thermal annealing temperature. Let warm.
[0036]
  As in the present invention and the above embodiment, the rapid thermal annealing treatment for moving the catalytic element to the introduction region of the group 5 B element is at least 30 ° C./min from the preheating temperature of 600 ° C. or less to the rapid thermal annealing temperature. It is desirable to raise the temperature at a rate of temperature rise exceeding minutes. More preferably, it is more desirable to raise the temperature at a rate of temperature exceeding 100 ° C./min. If the preheating temperature is 600 ° C. or lower, no crystal growth occurs in the region where the Group 5 B element is introduced and made amorphous. If the rate of temperature increase at this time is 30 ° C./min or more, crystallization in the region into which the Group 5 B element has been introduced is not completely completed in the temperature increasing process, and the amorphous component is removed. It is possible to enter a rapid thermal annealing process with the remaining state. Furthermore, if the temperature rising rate at this time is 100 ° C./min or more, in the temperature increasing process, almost no crystallization occurs in the region where the Group 5 B element is introduced, and it remains high in an almost amorphous state. Thermal annealing can be entered. FIG. 7 shows experimental data regarding the temperature increase rate at this time, which was conducted by the present inventors. FIG. 7 shows the results of experiments conducted at a rapid thermal annealing temperature of 720 ° C. FIG. 7A shows the remaining ratio of the catalyst element in the silicon film before and after the rapid thermal annealing treatment. The measurement was performed by micro area SIMS (secondary ion mass spectrometry). From FIG. 7 (A), it can be seen that when the rate of temperature increase exceeds this value at about 30 ° C./min, a further decrease in the residual ratio of the catalytic element occurs. That is, below this value, even if the temperature of the rapid thermal annealing treatment is increased, the effect is not seen, and the temperature increase rate of 30 ° C./min is the minimum increase necessary to obtain the effect of this embodiment. It turns out that it is a temperature rate. The residual rate of the catalyst element further decreases as the temperature rising rate increases from 30 ° C./min, and saturates at about 100 ° C./min or more. Therefore, the gettering effect of the catalytic element at the temperature of the rapid thermal annealing treatment can be maximized by setting the temperature rising rate to 100 ° C./min or more. FIG. 7B shows the result of an experiment conducted to elucidate this mechanism. FIG. 7B shows the ratio of the amorphous region in the temperature rising process in the group 5 B element introduction region. The experiment was performed by using a quartz substrate, rapidly cooling when the annealing temperature reached 720 ° C., and examining the Raman peak ratio of crystalline silicon to amorphous silicon by Raman spectroscopy of a spot of 1 μmφ. As can be seen from FIG. 7 (B), the same result was obtained with respect to the reduction rate of the catalytic element, and an amorphous peak began to appear at a rate of temperature increase of 30 ° C./min. The ratio increases and is saturated at about 100 ° C./min. Therefore, it can be clearly seen that the cause is the crystal state of the Group 5 B element introduction region.
[0037]
  In one embodiment, in the method for manufacturing a semiconductor device described above, the catalytic element transfer step is performed by a rapid thermal annealing process having an average temperature in the range of 650 to 800 ° C. and a duration of 1 second to 15 minutes. Is called.
[0038]
  In this embodiment, in the step of moving the catalyst element to the region into which the Group 5 B element has been introduced, the average temperature during the rapid thermal annealing treatment is in the range of 650 to 800 ° C., and 1 second to 15 minutes. Of time. That is, as can be seen in FIG. 7, for the first time at a temperature of 650 ° C. or higher, the effect of greatly reducing the catalyst element concentration according to the present embodiment appears. In the data of FIG. 8, the experiment was conducted at a temperature rising rate of 120 ° C./min. In the conventional method shown by the broken line in FIG. 8, the reduction effect has reached its peak at about 650 ° C. as described above. However, in this embodiment, as shown by the solid line, it has been observed up to this temperature so far. A higher gettering effect can be obtained. However, the higher the annealing temperature at this time, the better, and there is an upper limit. That is, when the temperature becomes higher, random diffusion of the catalytic element occurs, and the catalytic element moves from the introduction region of the group 5 element to the outside. As a result, the concentration of the catalytic element starts to increase. In particular, when the temperature exceeds 800 ° C., the residual rate of the catalytic element increases rapidly. At this time, if oxygen is present even a little, the silicide of the catalytic element is selectively oxidized and a hole is formed in the silicon film. . Therefore, the upper limit is limited by these two points and is 800 ° C. The annealing time has a sufficient effect within the above range.
[0039]
  In another embodiment, in the semiconductor device manufacturing method described above, the catalytic element transfer step is performed by a rapid thermal annealing process having an average temperature in a range of 700 to 750 ° C. and a duration of 1 minute to 10 minutes. Done.
[0040]
  In this embodiment, more preferably, the average treatment temperature of the rapid thermal annealing treatment is in the range of 700 to 750 ° C., and the treatment is performed for a duration of 1 minute to 10 minutes. As can be seen from FIG. 8, the catalytic element reduction effect is almost saturated at about 700 ° C., and then gradually decreases to about 750 ° C., but takes an extreme value at 750 ° C., and increases at higher temperatures. This is for the reason described above. Therefore, 700 to 750 ° C. is the optimum temperature range in the present embodiment. Furthermore, if the treatment time at this time is in the range of 1 minute to 10 minutes, a sufficient catalytic element reduction effect in the present embodiment can be obtained, and thermal damage when glass is used as the substrate ( Warpage and shrinkage) can also be minimized.
[0041]
  Further, in one embodiment, in the method for manufacturing a semiconductor device described above, when the glass substrate is used as the substrate, the catalytic element transfer step includes a shrinkage (heat shrinkage rate or The rate of temperature decrease from the rapid thermal annealing temperature is controlled so that the (thermal expansion coefficient) is 25 ppm or less.
[0042]
  In this embodiment, rapid thermal annealing is performed in the step of moving the catalyst element to the region where the Group 5 B element is introduced. The rapid thermal annealing process obtains the effect of this embodiment by heating the entire substrate uniformly at a relatively high temperature as in the above temperature range. One problem arises here. Although it does not matter when a heat-resistant substrate such as a quartz substrate is used as the substrate, in a normal glass substrate, the warpage of the substrate itself and the shrinkage (thermal shrinkage coefficient or thermal expansion coefficient) are caused in this rapid thermal annealing process. It becomes a problem. In this embodiment, this problem is solved by controlling the temperature lowering rate from the rapid thermal annealing temperature at this time. In this embodiment, when a glass substrate is used as the substrate, the temperature drop from the rapid thermal annealing temperature so that the shrinkage (thermal shrinkage coefficient or thermal expansion coefficient) of the glass substrate before and after this step is 25 ppm or less. Control the speed. If it is below such a shrinkage value, the substrate is not actually warped, and mask alignment in the photolithography process can also be handled.
[0043]
  In one embodiment, in the semiconductor device manufacturing method described above, the group 5 element introduction step is performed by an ion doping method.
[0044]
  In this embodiment, the step of selectively introducing an element selected from Group 5 B into the silicon film is performed by an ion doping method. Although other methods can achieve a certain effect, the effect when using the ion doping method is particularly remarkable. The reason for this is considered to be that the crystal of the silicon film is strongly broken and becomes amorphous in the region where the group 5 B element is introduced by ion doping. In this embodiment, it is one point to make the introduction region of the group 5 B element amorphous, and the stronger the amorphousization, the more effective. The catalytic element tends to move from the crystalline silicon film to the amorphous silicon film even when considered from the crystal growth process. That is, it is considered that the catalytic element is more energetically present in amorphous silicon. That is, it is considered that the component made amorphous by ion doping has a synergistic effect and further enhances the gettering effect of the Group 5 B element.
[0045]
  Also,UpIn the semiconductor device manufacturing method described above, in the catalyst element transfer step,AntA rapid thermal annealing process is performed using a resistance heating furnace.
[0046]
  thisManufacturing method of semiconductor deviceThen, as a specific technique of rapid thermal annealing treatment to move the catalyst element to the region where the group 5 B element is introducedAntUsing a resistance heating furnaceThe ResistanceIn the case of using a resistance heating furnace, the substrates are inserted into the furnace one by one in order to provide a thermal gradient in the furnace and reduce the heat capacity of the substrate. The temperature increase rate may be controlled by controlling the insertion speed at that time. In this case, the entire substrate can be heated more uniformly and instantaneously, and the temperature increase rate and temperature decrease rate can be controlled with high accuracy, which is suitable for this embodiment.
[0047]
  In one embodiment, in the semiconductor device manufacturing method described above, in the group 5 element introduction step, the active (channel) region of the semiconductor device finally formed is masked at least in the active (channel) region. An element selected from Group 5 B is introduced into the periphery of the active region so as to surround the (channel) region.
[0048]
  This embodiment relates to an introduction pattern in the step of selectively introducing a group 5 B element into a silicon film, and uses a patterned introduction mask to mask at least an active (channel) region of a finally formed semiconductor device. In the state, a Group 5 B element is introduced into the periphery of the active (channel) region so as to surround it. At this time, if a group 5 B element is introduced into the periphery of the semiconductor device so as to surround the active region in a state where the entire active (element) region of the semiconductor device is masked, not only the channel region but also the active region (channel + A state in which the catalyst element is hardly contained in the entire source / drain region is obtained. By doing in this way, the later process contamination by a catalyst element can be prevented. In this way, when the Group 5 B element is introduced so as to surround the channel region and further the active region, the catalyst element in the channel and the active region may move outward in all directions in all directions. it can. For this reason, the catalytic element in the active region can be moved to the outside very efficiently, and an excellent gettering effect can be obtained.
[0049]
  In another embodiment, in the semiconductor device manufacturing method described above, in the group 5 element introduction step, the impurity (source / drain) region in the element region (channel and source / drain region) of the semiconductor device is used. The element is introduced and used as it is as an impurity (source / drain) region.
[0050]
  In this embodiment, as a method for introducing a Group 5 B element into a silicon film, impurities (sources) in an element region (channel and source / drain regions) of a semiconductor device are used without using a special introduction mask. Introduce Group 5 B element into the drain region. Then, it is used as an impurity (source / drain) region as it is. In this case, without using a dedicated introduction mask, both the group 5 B element introduction step for gettering and the impurity introduction step of the impurity (source / drain) region are performed, and in the rapid thermal annealing step, impurities are introduced. Also serves as the activation of the (source / drain) region. Thereby, a process can be simplified greatly and as a result, productivity can be improved most.
[0051]
  In one embodiment, in the semiconductor device manufacturing method described above, the catalyst element introduction step and the group 5 element introduction step are performed using the same introduction mask.
[0052]
  In this embodiment, when a catalytic element is selectively introduced into a part of an amorphous silicon film and a crystal is grown in a lateral direction, the selective introduction step of the catalytic element at that time is performed using a patterned introduction mask. The subsequent selective introduction process of the group 5 B element is also performed using the same introduction mask. By doing in this way, it is not necessary to create an introduction mask separately for each introduction process, and the process can be simplified. At the same time, the silicon film region constituting the channel region of the subsequent semiconductor device can always be kept covered and exposed by the mask film throughout the process of introducing the catalyst element and the group 5 B element. Disappear. As a result, process-induced contamination of the channel region can be minimized. And the improvement of a non-defective product and cost reduction can be achieved by the action of these two points.
[0053]
  In another embodiment, in the semiconductor device manufacturing method described above, Ni, Co, Fe, Pd, Pt, Cu, or Au is selected as a catalytic element that promotes crystallization of the amorphous silicon film. At least one element is used.
[0054]
  In this embodiment, Ni, Co, Fe, Pd, Pt, Cu, and Au can be used as the type of catalytic element. One or more kinds of elements selected from these have an effect of promoting crystallization in a very small amount. Among them, the most remarkable effect can be obtained particularly when Ni is used. The following model can be considered for this reason. The catalytic element does not act alone, but acts on crystal growth by combining with the silicon film and silicidation. The crystal structure at that time acts as a kind of template when the amorphous silicon film is crystallized, and promotes crystallization of the amorphous silicon film. Ni is two Si and NiSi₂The silicide is formed. NiSi₂Shows a meteorite-type crystal structure, which is very similar to the diamond structure of single crystal silicon. Moreover, NiSi₂Has a lattice constant of 5.406 Å, which is very close to the lattice constant of 5.430 で in the diamond structure of crystalline silicon. Therefore, NiSi₂Is the best template for crystallizing the amorphous silicon film, and it is most desirable to use Ni as the catalyst element in this embodiment.
[0055]
  In one embodiment, in the semiconductor device manufacturing method described above, at least one element selected from P, N, As, Sb, and Bi is used as the element selected from Group 5 B.
[0056]
  In this embodiment, at least one element selected from P, N, As, Sb, and Bi is used as an element selected from Group 5 B. If one or more kinds of elements selected from these are used, the catalyst element can be efficiently moved, and a sufficient gettering effect can be obtained. Although no detailed knowledge has been obtained yet regarding the mechanism of this gettering, it is known that P is the most effective of these elements.
[0057]
  In another embodiment, in the semiconductor device manufacturing method described above, the concentration of the catalytic element in the active (element) region of the semiconductor device finally obtained is 1 × 10¹⁶~ 2x10¹⁷cm^-3Is within the range.
[0058]
  This embodiment aims to reduce the amount of catalytic elements remaining in the active region of the semiconductor device as much as possible, and to realize a semiconductor device with high performance, high reliability, and high stability. For this purpose, the concentration of the catalytic element in the active (channel) region of the finally obtained semiconductor device is 1 × 10 5.¹⁶~ 2x10¹⁷cm^-3If it is in the range. The catalyst element concentration in the channel region is 2 × 10¹⁷cm^-3By making the following, no adverse electrical influence of the catalytic element on the semiconductor element characteristics is observed. And as a result of using this invention, such a low density | concentration is realizable. In addition, as long as crystallization is performed using a catalytic element, a minimum of 1 × 10¹⁶cm^-3However, it is impossible to reduce the concentration of the catalytic element to a level below this level by any method currently conceivable. Therefore, as a result of crystallization with the catalytic element, at least 1 × 10¹⁶cm^-3The catalytic element having the above concentration remains in the channel region.
[0059]
  In the present invention, as a method for further improving the crystallinity of the silicon film crystallized by the catalytic element and further improving the performance of the semiconductor device, particularly the current driving capability, the silicon film crystallized by the catalytic element is applied. On the other hand, it is also effective to add a step of performing a heat treatment in a higher temperature oxidizing atmosphere and a step of irradiating laser light.
[0060]
  In the former method of performing heat treatment in an oxidizing atmosphere at a high temperature to further improve the crystallinity, the silicon film crystallized by the catalytic element is oxidized at a higher temperature (800 ° C. to 1100 ° C.). . Then, supersaturated Si atoms generated by the oxidation action are supplied into the silicon film, and these enter crystal defects (particularly dangling bonds) in the silicon film, and the defects can be eliminated. Thereby, the defect density in the silicon film crystallized by the catalytic element is greatly reduced, and the mobility is greatly improved. As a result, the performance of the semiconductor device is dramatically improved.
[0061]
  In the latter laser light irradiation process, when the crystalline silicon film is irradiated with strong light such as a laser, the crystal grain boundary portion and the crystalline silicon film are different from the melting point difference between the crystalline silicon film and the amorphous silicon film. Minute residual amorphous regions (non-crystallized regions) are intensively processed. Here, in the crystalline silicon film formed by the normal solid phase growth method, the crystal structure is in a twin crystal state, and therefore the inside of the crystal grain remains as a twin defect even after intense light irradiation.
[0062]
  On the other hand, a crystalline silicon film crystallized by introducing a catalytic element is formed of columnar crystals and the inside thereof is in a single crystal state, so that the grain boundary portion is treated by irradiation with strong light. Then, a high-quality crystalline silicon film close to a single crystal state can be obtained over the entire surface of the substrate. This is very effective from the viewpoint of crystallinity. In addition, since laser irradiation is originally performed on a silicon film having crystallinity, unlike the method of crystallizing by directly irradiating an amorphous silicon film with laser, the variation in laser irradiation is greatly reduced, and uniformity is improved. No problem arises.
[0063]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, the present invention will be described in detail based on the illustrated embodiments.
[0064]
      [First Embodiment]
  With reference to FIG. 1, a first embodiment of a method of manufacturing a semiconductor device according to the present invention will be described. The first embodiment is a method in which the present invention is adopted in a process for producing an N-type TFT on a glass substrate.
[0065]
  The TFT manufactured in the first embodiment can be used not only as a driver circuit and a pixel portion of an active matrix type liquid crystal display device but also as an element constituting a thin film integrated circuit. In this embodiment, as representatives thereof, a description will be given by taking, as an example, a pixel driving TFT of an active matrix substrate for a liquid crystal display device in which hundreds of thousands to millions of N-type TFTs need to be uniformly formed on a substrate I do.
[0066]
  The plan view of FIG. 1 shows an outline of a manufacturing process of a pixel TFT on an active matrix substrate described as this embodiment. As described above, the active matrix substrate is actually composed of several hundreds of thousands or more TFTs, but in this embodiment, the description will be simplified with nine TFTs of 3 rows × 3 columns.
[0067]
  FIG. 2 shows a cross section of any one TFT in FIG. 1 cut along the line AA ′. FIG. 2 (A) → FIG. 2 (B) → FIG. 2 (C) → FIG. ) → FIG. 2 (E) → FIG. 2 (F) → FIG. 2 (G) in this order.
[0068]
  First, as shown in FIG. 2A, a base film 102 made of silicon oxide having a thickness of about 300 to 500 nm is formed on a glass substrate 101 by, for example, a sputtering method. This silicon oxide film 102 is provided to prevent diffusion of impurities from the glass substrate 101. Next, an intrinsic (I-type) amorphous silicon film (a-Si film) 103 having a thickness of 20 to 80 nm, for example, 40 nm is formed by plasma CVD or low pressure CVD. In this embodiment, a parallel plate type plasma CVD apparatus is used, the heating temperature is 300 ° C., and SiH₄Gas and H₂Gas was used as the material gas. And the power density of RF power is 10 to 200 mW / cm.²For example, 80 mW / cm²It was.
[0069]
  Next, a slight amount of nickel 104 is added on the surface of the a-Si film 103. The addition of a small amount of nickel 104 was performed by holding a solution in which nickel was dissolved on the a-Si film 103, and uniformly extending the solution onto the substrate 101 with a spinner and drying it. In the first embodiment, nickel acetate is used as the solute, ethanol is used as the solvent, and the nickel concentration in the solution is 2 ppm. This state. As shown in FIG. When the nickel concentration on the surface of the a-Si film 103 added in the state shown in FIG. 2A is measured by the total reflection X-ray fluorescence analysis (TRXRF) method, 8 × 10 8 is obtained.¹²atoms / cm²It was about.
[0070]
  And this is heat-processed in inert atmosphere, for example, nitrogen atmosphere. In this heat treatment, during the temperature increase, first, a hydrogen desorption process in the a-Si film 103 was performed, and then the a-Si film 103 was crystallized at a higher temperature. Specifically, as the heat treatment in the first step, annealing is performed at 450 to 520 ° C. for 1 to 2 hours, and as the second heat treatment, annealing is performed at 520 to 570 ° C. for 2 to 8 hours. Do. In this embodiment, as an example, after annealing at 500 ° C. for 1 hour, heat treatment was performed at 550 ° C. for 4 hours. In this heat treatment, nickel 104 added to the surface of the a-Si film 103 is diffused into the a-Si film 103 and silicidation occurs, and the crystallization of the a-Si film 103 proceeds using this as a nucleus. To do. As a result, as shown in FIG. 2B, the a-Si film 103 is crystallized to become a crystalline silicon film 103a.
[0071]
  Next, as shown in FIG. 2C, an insulating thin film such as a silicon oxide film or a silicon nitride film is deposited on the crystalline silicon film 103a and patterned to form a mask. In this embodiment, the mask 106 is formed by using a silicon oxide film, using TEOS (Tetra Ethoxy Ortho Silicate) as a raw material, and decomposing and depositing it together with oxygen by an RF plasma CVD method. The thickness of the mask is desirably 100 nm to 400 nm. In this embodiment, the thickness of the silicon oxide film is 150 nm. When the state at this time is viewed from above the substrate, a part 103a of the crystalline silicon film is masked in an island shape by a mask 106 as shown in FIG.
[0072]
  Next, in this state, as shown in FIG. 2C, phosphorus 108 is ion-doped from above the glass substrate 101 over the entire surface. In this case, the phosphorus 108 is doped with an acceleration voltage of 5 to 10 kV and a dose of 5 × 10 5.¹⁵~ 1x10¹⁶cm^-2It was. Through this step, phosphorus is implanted into the exposed crystalline silicon film 103a, thereby forming a phosphorus-doped crystalline silicon region 103d. The crystalline silicon film 103a in the region covered with the mask 106 is not doped with phosphorus. When this state is viewed from above the glass substrate 101, the state is as shown in FIG. The TFT active (element) region to be formed later is completely covered with the mask 106 at this stage.
[0073]
  In this state, this is subjected to rapid thermal annealing in an inert atmosphere, for example, in a nitrogen atmosphere. As the rate of temperature increase up to the rapid thermal annealing treatment temperature at this time, it is desirable to raise the temperature from a preheating temperature of 600 ° C. or less to at least 30 ° C./min, preferably 100 ° C./min or more.
[0074]
  Further, the annealing temperature and processing time at this time are preferably 1 second to 15 minutes at a temperature of 650 to 800 ° C., more preferably 1 minute to 10 minutes at a temperature of 700 to 750 ° C. In the first embodiment, since the glass substrate 101 is used, it is desirable that the rate of temperature decrease from the rapid thermal annealing temperature to at least 600 ° C. is 20 ° C./min or less.
[0075]
  In the first embodiment, in the heat treatment, the temperature is raised from room temperature to a rapid thermal annealing treatment temperature of 700 ° C. at a rate of temperature rise of 100 ° C./min. The temperature was lowered in minutes, and the temperature was further lowered from 580 ° C. to 100 ° C. at 80 ° C./min. The temperature profile at this time is shown in FIG. In the first embodiment, using a resistance heating furnace, a temperature gradient is provided in the furnace, and the speed at which the substrate 101 is inserted into the furnace is controlled, so that the rapid thermal annealing process of the above temperature profile is performed. It was realized.
[0076]
  At this time, it is important to process the substrates 101 one by one and reduce the heat capacity when inserting them into the furnace as much as possible. One merit of using a resistive heating furnace with such a temperature gradient is that it is possible to control the temperature drop rate with good control, especially for other lamp irradiation methods when using a glass substrate. More suitable than
[0077]
  By this rapid thermal annealing treatment, phosphorus doped in the region 103d first traps nickel present in the region 103d. Then, as shown in FIGS. 1B and 2D, the nickel 104 existing in the crystalline silicon film 103a under the mask 106 is further moved outwardly as indicated by an arrow 109, that is, surroundings. The region 103d is pulled out in all directions. As a result, the nickel concentration in the crystalline silicon film 103a region under the mask 106 is greatly reduced. The actual nickel concentration in the crystalline silicon film 103a at this time was measured by secondary ion mass spectrometry (SIMS).¹⁶atoms / cm³It was reduced to the extent. Incidentally, in the case of the conventional method not using the rapid thermal annealing treatment as in the present invention, the nickel concentration is 2 × 10.¹⁷atoms / cm³Degree.
[0078]
  The nickel concentration in the crystalline silicon film 103a before this step is 1 × 10¹⁸atoms / cm³The residual nickel concentration could be reduced to about 1/20 by the rapid thermal annealing process in the first embodiment. Further, in the first embodiment, the shrinkage of the glass substrate 101 after the rapid thermal annealing treatment is about 20 ppm, there is no problem in warping, and mask alignment in the photolithography process in the subsequent process can be performed without any problem.
[0079]
  Next, the silicon oxide film 106 used as a mask is removed by etching. As the etchant, 1:10 buffered hydrofluoric acid (BHF) having sufficient selectivity with respect to the underlying silicon film 103a was used, and wet etching was performed.
[0080]
  Thereafter, the silicon film 103a in the region covered with the mask 106 is used, and other unnecessary portions of the silicon film are removed to perform element isolation. That is, by this process, an island-shaped crystal that later becomes an active region (source / drain region, channel region) of the TFT using the silicon film 103a in at least the above region in the arrangement shown in FIG. The conductive silicon film 110 is formed, and the state of FIG.
[0081]
  Next, as shown in FIG. 2E, the crystallinity of the crystalline silicon film 110 in the active region is promoted by irradiation with a laser beam 105. As the laser light at this time, an XeCl excimer laser (wavelength 308 nm, pulse width 40 n (nanosecond)) was used. In addition, the irradiation condition of the laser beam is that the substrate 101 is heated to 200 to 450 ° C., for example, 400 ° C. during irradiation, and the energy density is 250 to 450 mJ / cm.²For example, 350 mJ / cm²Irradiated with. Further, the beam size was formed to be a long shape of 150 mm × 1 mm on the surface of the substrate 101, and scanning was sequentially performed with a step width of 0.05 mm in a direction perpendicular to the long direction. That is, a total of 20 laser irradiations are performed at an arbitrary point of the crystalline silicon film 110.
[0082]
  Next, a silicon oxide film having a thickness of 20 to 150 nm, here 100 nm, is formed as the gate insulating film 111 so as to cover the crystalline silicon film 110 serving as the active region. In the formation of the silicon oxide film, here, TEOS (Tetra Ethoxy Ortho Silicate) was used as a raw material, and it was decomposed and deposited by RF plasma CVD at a substrate temperature of 150 to 600 ° C., preferably 300 to 450 ° C. together with oxygen. Alternatively, the substrate temperature may be 350 to 600 ° C., preferably 400 to 550 ° C. using TEOS as a raw material by ozone or atmospheric pressure CVD together with ozone gas.
[0083]
  After film formation, annealing was performed at 500 to 600 ° C. for 1 to 4 hours in an inert gas atmosphere in order to improve the bulk characteristics of the gate insulating film 111 itself and the interface characteristics of the crystalline silicon film / gate insulating film. .
[0084]
  Subsequently, an aluminum film having a thickness of 400 to 800 nm, for example, 600 nm is formed by sputtering. Then, the aluminum film is patterned to form the gate electrode 113. Further, the surface of the aluminum electrode is anodized to form an oxide layer 114 on the surface. This state corresponds to FIG. The gate electrode 113 simultaneously forms a gate bus line in a plan view, and this state is as shown in FIG. 1D when seen in a plan view. The anodic oxidation is carried out in an ethylene glycol solution containing 1 to 5% tartaric acid. First, the voltage is increased to 220 V at a constant current, and this state is maintained for 1 hour to complete the process. The thickness of the obtained oxide layer 114 is 200 nm. Note that since the oxide layer 114 has a thickness for forming an offset gate region in a subsequent ion doping step, the length of the offset gate region can be determined in the anodic oxidation step.
[0085]
  Next, an impurity (phosphorus) is implanted into the active region (crystalline silicon film) 110 by ion doping using the gate electrode 113 and the surrounding oxide layer 114 as a mask. As a doping gas, phosphine (PH₃), The acceleration voltage is 60 to 90 kV (for example, 80 kV), and the dose is 1 × 10¹⁵~ 8x10¹⁵cm^-2(For example, 2 × 10¹⁵cm^-2).
[0086]
  By this process, the regions 116 and 117 into which the impurity is implanted later become the source / drain regions of the TFT, and the region 115 where the impurity is not implanted after being masked by the gate electrode 113 and the surrounding oxide layer 114 becomes the channel region of the TFT. It becomes.
[0087]
  Thereafter, as shown in FIG. 2 (F), annealing is performed by irradiating laser light 120 to activate the implanted impurity, and at the same time, the crystallinity of the portion where the crystallinity has deteriorated in the impurity introduction step is Improve. At this time, a XeCl excimer laser (wavelength: 308 nm, pulse width: 40 nanoseconds) is used as the laser to be used, and the energy density is 150 to 400 mJ / cm.²(Preferably 200 to 250 mJ / cm²). The sheet resistance of the N-type impurity (phosphorus) regions 116 and 117 thus formed was 200 to 800 Ω / □.
[0088]
  Subsequently, as shown in FIG. 2G, a silicon oxide film or a silicon nitride film having a thickness of about 600 nm is formed as the interlayer insulating film 121. When a silicon oxide film is used, it is possible to form TEOS as a raw material by using a plasma CVD method with oxygen, a low pressure CVD method with ozone, or an atmospheric pressure CVD method, and a good interlayer insulation with excellent step coverage. A film 121 is obtained. SiH₄And NH₃If a silicon nitride film formed by a plasma CVD method is used as a source gas, hydrogen atoms are supplied to the interface between the active region and the gate insulating film, thereby reducing the number of dangling bonds that degrade TFT characteristics.
[0089]
  Next, a contact hole is formed in the interlayer insulating film 121, and a TFT source electrode wiring (source bus line) 122 is formed of a metal material, for example, a two-layer film of titanium nitride and aluminum. The titanium nitride film is provided as a barrier film for the purpose of preventing aluminum from diffusing into the semiconductor layer. Since the TFT 125 shown in FIGS. 1E and 2G is an element for switching a pixel electrode, a pixel electrode 123 made of a transparent conductive film such as ITO is provided on the other drain electrode. That is, in FIG. 1E, a video signal is supplied through the source bus line 122, and necessary charges are written into the pixel electrode 123 based on the gate signal of the gate bus line (gate electrode) 113. Finally, annealing is performed at 350 ° C. for 1 hour in a hydrogen atmosphere of 1 atm to complete the pixel TFT 125 shown in FIGS. 1E and 2G. Furthermore, a protective film made of a silicon nitride film or the like may be provided on the pixel TFT 125 for the purpose of protecting the pixel TFT 125 as necessary.
[0090]
  The TFT 125 fabricated according to the first embodiment has a field effect mobility of 150 cm.²In spite of the very high performance of about / Vs and the threshold voltage of about 2 V, there is no abnormal increase in leakage current frequently observed in the TFT off operation, which is frequently seen in the conventional example, and it is 1 pA or less per unit W. Very low value was shown stably. This value is completely different from that of a conventional TFT prepared without using a catalyst element, and the production yield can be greatly improved. Moreover, even when a durability test by repeated measurement or bias or temperature stress is performed, the characteristics are hardly deteriorated and the reliability is very high as compared with the conventional one. When the active matrix substrate for liquid crystal display manufactured based on the first embodiment was actually evaluated for lighting, display unevenness was clearly smaller than that produced by the conventional method, and pixel defects due to TFT leakage were extremely small. A high-quality LCD panel with a small contrast and a high contrast ratio was obtained. Although the TFT manufacturing process according to the first embodiment has been described for the pixel electrode of the active matrix substrate, the TFT manufactured in this manufacturing process can be easily applied to a thin film integrated circuit or the like. In that case, a contact hole may be formed over the gate electrode 113 and necessary wiring may be provided.
[0091]
      [Second Embodiment]
  Next, a second embodiment of the semiconductor device manufacturing method of the present invention will be described. In the second embodiment, a peripheral drive circuit of an active matrix type liquid crystal display device, or a circuit having a CMOS structure in which an N-type TFT and a P-type TFT forming a general thin film integrated circuit are configured in a complementary manner is formed on a glass substrate. The manufacturing process will be described.
[0092]
  3A to 3G sequentially show the TFT manufacturing steps described in the second embodiment. 3A to 3G sequentially show cross sections of the manufacturing steps.
[0093]
  First, as shown in FIG. 3A, a base film 202 made of silicon oxide having a thickness of about 300 to 500 nm is formed on a glass substrate 201 by, eg, sputtering. This silicon oxide film 202 is provided to prevent diffusion of impurities from the glass substrate 201. Next, an intrinsic (I-type) amorphous silicon film (a-Si film) 203 having a thickness of 20 to 80 nm, for example, 40 nm is formed by plasma CVD. In this second embodiment, a parallel plate type plasma CVD apparatus is used, the heating temperature is 300 ° C., and SiH₄Gas and H₂Gas was used as the material gas. And the power density of RF power is 10 to 200 mW / cm.²For example, 80 mW / cm²It was.
[0094]
  Next, a small amount of nickel 204 is added onto the surface of the a-Si film 203. This small amount of nickel 204 was added by holding a solution in which nickel was dissolved on the a-Si film 203, uniformly extending the solution onto the glass substrate 201 with a spinner, and drying the solution. In this second embodiment, nickel acetate was used as the solute, ethanol was used as the solvent, and the nickel concentration in the solution was 1 ppm. When the nickel concentration on the surface of the a-Si film 203 added in this way is measured by a total reflection X-ray fluorescence (TRXRF) method, 5 × 10 5 is obtained.¹²atoms / cm²It was about. Then, heat treatment is performed on the a-Si film 203 in an inert atmosphere, for example, in a nitrogen atmosphere. As the heat treatment at this time, it is desirable to perform an annealing treatment at 520 to 570 ° C. for 2 to 8 hours. In the second embodiment, as an example, the heat treatment was carried out at 550 ° C. for 4 hours. In this heat treatment, silicidation of nickel 204 added to the surface of the a-Si film 203 occurs, and the crystallization of the a-Si film 203 proceeds using this as a nucleus. However, with the amount of nickel added, the amount of the catalytic element is insufficient to crystallize the entire a-Si film 203, and a partly minute (about several μm) amorphous region remains. Crystal growth stops. Further, in the annealing process, at a temperature of 570 ° C. or lower, the silicon film itself does not grow, so that the uncrystallized region where the crystal growth does not reach remains a-Si. As a result, the silicon film 203 obtained after the heat treatment at 550 ° C. for 4 hours according to the second embodiment is in a state where minute amorphous regions are mixed in the crystallized region.
[0095]
  Next, as shown in FIG. 3B, the silicon film 203 is further crystallized by irradiating the laser beam 205 to obtain a crystalline silicon film 203a. As the laser light at this time, a XeCl excimer laser (wavelength: 308 nm, pulse width: 40 nanoseconds) was used. The laser light irradiation conditions are as follows. At the time of irradiation, the substrate 201 is heated to 200 to 450 ° C., for example, 400 ° C., and the energy density is 200 to 450 mJ / cm.²For example, 350 mJ / cm²Irradiated with. The beam size was formed to be a long shape of 150 mm × 1 mm on the surface of the substrate 201, and scanning was performed sequentially with a step width of 0.05 mm in a direction perpendicular to the long direction. That is, a total of 20 laser irradiations are performed at any one point of the silicon film 203. By this laser irradiation, the amorphous region remaining in the silicon film 203 is preferentially melted, and the entire film is crystallized reflecting only the good crystal component in the crystallization region.
[0096]
  Thereafter, as shown in FIG. 3C, the crystalline silicon film 203a crystallized over the entire surface is used to leave the regions that later become the active regions (element regions) 210n and 210p of the TFT, and other regions. Are removed by etching.
[0097]
  Next, a silicon oxide film having a thickness of 20 to 150 nm, here 100 nm, is formed as the gate insulating film 211 so as to cover the crystalline silicon films 210n and 210p serving as the active regions. Here, TEOS (Tetra Ethoxy Ortho Silicate) was used as a raw material, and was decomposed and deposited by RF plasma CVD at a substrate temperature of 150 to 600 ° C., preferably 300 to 450 ° C. together with oxygen, to form a silicon oxide film.
[0098]
  Subsequently, as shown in FIG. 3D, a refractory metal is deposited by sputtering and patterned to form gate electrodes 213n and 213p. As the refractory metal at this time, tantalum (Ta) or tungsten (W) is desirable. In the second embodiment, Ta to which a small amount of nitrogen is added is used, and the thickness is set to 300 to 600 nm, for example, 450 nm.
[0099]
  Next, in this state, as shown in FIG. 3D, phosphorus 208 is implanted into the active regions 210n and 210p using the gate electrodes 213n and 213p as a mask by ion doping. Doping at this time is so-called through doping performed through the gate insulating film 211. Phosphine (PH) as doping gas₃As the doping conditions, the acceleration voltage is 60 to 90 kV, for example 80 kV, and the dose is 2 × 10 15 to 8 × 10¹⁵cm^-2For example 5 × 10¹⁵cm^-2It was. By this ion doping process, the regions that are masked by the gate electrodes 213n and 213p and are not implanted with phosphorus later become channel regions 215n and 215p of the TFT. Further, N-type impurity regions 216n and 217n in the N-channel TFT are formed by this ion doping process. However, in the P-channel TFT, the source / drain regions 216p ′ and 217p ′ are N-type impurity regions as a result of doping with phosphorus at this stage.
[0100]
  Next, as shown in FIG. 3E, a mask 218 for selective doping is formed by photoresist on the N-type TFT by a photolithography process. In this state, boron 219 is implanted selectively into the active region 210p using the gate electrode 213p as a mask by ion doping only in the P-type TFT. At this time, diborane (B2H6) is used as a doping gas, and an acceleration voltage of 40 kV to 80 kV, for example, 65 kV, is 1 × 10¹⁶~ 5x10¹⁶cm^-2For example 2 × 10¹⁶cm^-2Doping was performed at a high dose of. In this step, the channel region 215p of the later P-type TFT is masked by the gate electrode 213p, and boron is not implanted.
[0101]
  As a result, the source / drain regions 216p ′ and 217p ′ doped with boron 219 through the gate insulating film 211 cancel phosphorus previously doped N-type impurities, and are inverted by excess boron, so that P Type impurity regions 216p and 217p are formed. This is so-called counter doping. In this way, an N-channel TFT and a P-channel TFT can be formed, respectively.
[0102]
  Then, after removing the photoresist mask 218 used as a mask for selective doping, this is subjected to rapid thermal annealing treatment in an inert atmosphere, for example, in a nitrogen atmosphere. The temperature increase rate up to the rapid thermal annealing treatment temperature at this time is preferably a temperature increase rate of at least 30 ° C./min, preferably 100 ° C./min or more, from a preheating temperature of 600 ° C. or less.
[0103]
  Further, the annealing temperature and processing time at this time are preferably 1 second to 15 minutes at a temperature of 650 to 800 ° C., more preferably 1 minute to 10 minutes at a temperature of 700 to 750 ° C. In the second embodiment, since a glass substrate is used, it is desirable that the rate of temperature decrease from the rapid thermal annealing temperature to at least 600 ° C. is 20 ° C./min or less. In the second embodiment, as in the first embodiment, the rapid thermal annealing process was performed with a temperature profile as shown in FIG. Specifically, the temperature is increased from room temperature to a rapid thermal annealing treatment temperature of 700 ° C. at a rate of temperature increase of 100 ° C./min, heat treatment is performed for 8 minutes, and then the temperature is decreased to 580 ° C. at 15 ° C./min. The temperature was decreased from 80 ° C. to 100 ° C. at 80 ° C./min. In the second embodiment, a high-speed thermal annealing process with the above temperature profile was realized by using a resistive heating furnace to provide a temperature gradient in the furnace and controlling the speed at which the substrate was inserted into the furnace. . At this time, it is important to process the substrates one by one and reduce the heat capacity when inserting into the furnace as much as possible. One advantage of using a resistive heating furnace with such a temperature gradient is that it is possible to control the temperature-decreasing rate in a controlled manner and is more suitable for the use of glass substrates than other lamp irradiation methods. ing.
[0104]
  By this rapid thermal annealing treatment, phosphorus doped in the source / drain regions 216n, 217n, 216p, and 217p in the TFT active region first traps nickel present in the region. Then, as shown in FIG. 3F, the nickel existing in the channel regions 215n and 215p is moved in the direction indicated by the arrow 209, that is, to the adjacent source / drain regions 216n, 217n, 216p, and 217p. Move. As a result, the nickel concentration in the channel regions 215n and 215p is greatly reduced. The nickel concentration in the channel regions 215n and 215p at this time was measured by secondary ion mass spectrometry (SIMS).¹⁶atoms / cm³It was reduced to the extent. Further, in this second embodiment, the shrinkage of the glass substrate 201 after the rapid thermal annealing treatment is about 20 ppm, there is no problem in warping, and mask alignment in the photolithography process in the subsequent process can be performed without any problem. The rapid thermal annealing process also activates the source / drain regions 216n, 217n, 216p, and 217p at the same time. The sheet resistance values of the N-type impurity regions 216n and 217n obtained by this process are 0.5 to 1 kΩ / □, and the sheet resistance values of the P-type impurity regions 216p and 217p are 2 to 3 kΩ / □. . Furthermore, the baking process of the gate insulating film 211 is also performed at the same time, so that the bulk characteristics of the gate insulating film itself and the interface characteristics of the crystalline silicon film / gate insulating film can be improved.
[0105]
  Subsequently, as shown in FIG. 3G, a silicon oxide film having a thickness of 900 nm is formed as an interlayer insulating film 221 by a plasma CVD method, a contact hole is formed in the silicon oxide film, and a metal material such as titanium nitride is formed. An electrode wiring 224 of the TFT is formed by a two-layer film of aluminum. Finally, annealing is performed at 350 ° C. for 1 hour in a hydrogen atmosphere of 1 atm to complete the N-channel TFT 226 and the P-channel TFT 227. Furthermore, if necessary, a contact hole may be provided on the gate electrode 213 of the TFTs 226 and 227 and the wiring 224 may be provided. Further, for the purpose of protecting these TFTs, a protective film made of a silicon nitride film or the like may be provided on the TFTs.
[0106]
  In the CMOS structure circuit fabricated according to the second embodiment, the field effect mobility of each TFT is 200 to 250 cm for an N-type TFT.²/ Vs, 100-130cm with P-type TFT²/ Vs is high, and the threshold voltage is about 1.5 V for an N-type TFT and about −2 V for a P-type TFT, and exhibits very good characteristics. In addition, there was no abnormal increase in the leakage current frequently observed in the conventional example, and the leakage current value itself stably showed a very low value of 1 pA or less per unit W. This value is completely different from that of a conventional TFT manufactured without using a catalyst element, and the manufacturing yield can be greatly improved. In addition, even when repeated measurements and durability tests with bias and temperature stress were performed, there was almost no deterioration in characteristics, and the reliability was very high and stable circuit characteristics compared to the conventional one.
[0107]
      [Third Embodiment]
  Next explained is a third embodiment of the method for manufacturing a semiconductor device according to the invention. In the third embodiment, a peripheral drive circuit of an active matrix type liquid crystal display device and a circuit having a CMOS structure in which an N-type TFT and a P-type TFT forming a general thin film integrated circuit are complementary are formed on a quartz substrate. It is a manufacturing process.
[0108]
  FIG. 4 is a plan view showing an outline of a manufacturing process of the TFT manufactured in the third embodiment. 5 and 6 are cross-sectional views taken along the line BB 'in FIG. 4. FIG. 5 (A) → FIG. 5 (B) → FIG. 5 (C) → FIG. The process proceeds in the order of 6 (E) → FIG. 6 (F) → FIG. 6 (G) → FIG. 6 (H).
[0109]
  First, after the surface of the quartz glass substrate 301 is washed with a low concentration hydrofluoric acid, an intrinsic (I type) film having a thickness of 40 to 100 nm (for example, 55 nm) is formed on the quartz glass substrate 301 by a low pressure CVD method. An amorphous silicon film (a-Si film) 303 is formed.
[0110]
  Next, an insulating thin film such as a silicon oxide film or a silicon nitride film is deposited on the a-Si film 303 and patterned to form a mask 306. In the third embodiment, the mask 306 is made of a silicon oxide film, TEOS (Tetra Ethoxy Ortho Silicate) is used as a raw material, and is decomposed and deposited together with oxygen by an RF plasma CVD method. The thickness of the mask 306 is desirably 100 nm to 400 nm. In the third embodiment, the thickness of the silicon oxide film is 150 nm. The a-Si film 303 is exposed in a slit shape in the region 300 by the through hole of the mask 306. That is, when the state of FIG. 5A is viewed from above, the a-Si film 303 is exposed in the region 300 as shown in FIG. 4, and the other part is masked by the silicon oxide film 306. It has become. The line width of the line-shaped region 300 at this time is preferably 2 to 15 μm, and in this third embodiment, it is 10 μm.
[0111]
  After providing the mask 306, a small amount of nickel 304 is added from above. This small amount of nickel 304 was added by DC sputtering using a target of pure nickel (99.9% or more). Specifically, the sputtering process was performed by increasing the substrate conveyance speed to 2000 mm / min with an extremely low power of about 50 W of DC power. As the sputtering gas, by using argon and raising the gas pressure at the time of sputtering to 10 Pa or higher with respect to a pure nickel target, it becomes possible to perform ultra-low density sputtering of nickel. The nickel 304 thus sputtered is displayed as a thin film in FIG. 5A, but is actually in a state of about a monoatomic layer or less and is not a state that can be called a film. . Specifically, when sputtering was performed under the conditions of a DC power of 60 W and an argon gas pressure of 18 Pa, the nickel concentration on the substrate surface (the a-Si film 303 exposed in the mask 306 and the region 300) was 6 × 10.¹³atoms / cm²Degree (TRXRF measured value).
[0112]
  In this state, this is annealed and crystallized in an inert atmosphere (for example, in a nitrogen atmosphere) at a heating temperature of 530 to 600 ° C. (for example, 580 ° C.) for 11 hours. At this time, in the region 300, the a-Si film 303 is crystallized using a small amount of nickel 304 existing on the surface of the a-Si film 303 as a nucleus, and a crystalline silicon film 303a is first formed. Subsequently, in the peripheral region of the region 300, as shown by an arrow 307 in FIGS. 4 and 5B, crystal growth is performed from the region 300 in the lateral direction (direction parallel to the substrate), and the mask 306 is obtained. Underneath, a crystalline silicon film 303b having lateral crystal growth is formed. The rest of the region remains as an amorphous silicon film region as it is, but actually, the line-shaped introduction region is adjacent, and another lateral crystal growth from that region proceeds, The crystal growth is completed when the lateral crystal growth regions of each other collide with each other. The growth boundary of the lateral crystal growth is 303c. At this time, the nickel 304 existing on the mask 306 is blocked by the mask film 306 and does not reach the underlying a-Si film 303, and the crystal of the a-Si film 303 is formed only by the nickel 304 introduced in the region 300. Is done. The nickel concentration in the crystalline silicon film 303b grown laterally is 5 × 10¹⁷~ 1x10¹⁸atoms / cm³The nickel concentration in the crystalline silicon film 303a grown directly by adding nickel is 1 × 10¹⁹atoms / cm³It was about.
[0113]
  In the above crystal growth, the distance of the crystal growth in the direction parallel to the substrate indicated by the arrow 307 is about 130 μm when the entire periphery is an amorphous region and the collision of the lateral crystal growth does not occur. Become.
[0114]
  Next, in this state, as shown in FIG. 5C, using the mask 306 used for selective introduction of nickel as it is, phosphorus 308 is ion-doped from above the substrate 301 over the entire surface. As the doping conditions of phosphorus 308 at this time, the acceleration voltage is 5 to 10 kV, and the dose is 5 × 10 5.¹⁵~ 1x10¹⁶cm²It was. By this step, phosphorus is implanted into the exposed crystalline silicon film 303a, and a phosphorus-doped crystalline silicon region 303d is formed. The crystalline silicon film 303 b in the region covered with the mask 306 is not doped with phosphorus 308.
[0115]
  The crystalline silicon film 303b is subjected to a rapid thermal annealing process under an inert atmosphere (for example, a nitrogen atmosphere). The rate of temperature increase up to the rapid thermal annealing treatment temperature at this time is desirably at least 30 ° C./min or more (preferably 100 ° C./min or more) from the preheating temperature of 600 ° C. or less. The annealing temperature and processing time at this time are preferably 1 second to 15 minutes at a temperature of 650 to 800 ° C. (more preferably 1 minute to 10 minutes at a temperature of 700 to 750 ° C.).
[0116]
  In the third embodiment, since the quartz substrate 301 having excellent heat resistance is used, it is not necessary to be particularly concerned about the cooling rate as in the first and second embodiments described above. An example of the temperature profile of the rapid thermal annealing process in the third embodiment is shown in FIG. Specifically, the temperature was increased from room temperature to a rapid thermal annealing temperature of 730 ° C. at a temperature increase rate of 150 ° C./min, heat treatment was performed for 5 minutes, and then the temperature was decreased to 100 ° C. at 150 ° C./min. In this third embodiment, a high-temperature thermal annealing process is realized by the above temperature profile by using a resistive heating furnace to give a temperature gradient in the furnace and by controlling the speed at which the substrate 301 is inserted into the furnace. did.
[0117]
  By this rapid thermal annealing treatment, in the silicon film 303, phosphorus doped in the region 303d first traps nickel present in the region. As shown in FIGS. 4 and 5D, the nickel existing in the laterally grown region 303b is oriented in the direction indicated by the arrow 309, that is, completely opposite to the direction of crystal growth. To the region 303d. As a result, the nickel concentration in the lateral crystal growth region 303b is greatly reduced. The nickel concentration in the lateral crystal growth region 303b at this time was measured by secondary ion mass spectrometry (SIMS).¹⁶atoms / cm³It was reduced to the extent.
[0118]
  Next, the silicon oxide film 306 used as a mask is removed by etching. As the etchant, 1:10 buffered hydrofluoric acid (BHF) having sufficient selectivity with respect to the underlying silicon film 303 was used, and etching removal was performed by wet etching.
[0119]
  Thereafter, as shown in FIG. 6 (E), the silicon film 303b is grown in the lateral direction, which later becomes the active regions (element regions) 310n and 310p of the TFT, and the other regions are removed by etching. Perform separation. At this time, the positional relationship between the nickel and phosphorus introduction region 300 and the active regions 310n and 310p is as shown in FIG.
[0120]
  Next, as shown in FIG. 6F, a silicon oxide film having a thickness of 60 nm is formed as a gate insulating film 311 so as to cover the crystalline silicon films 310n and 310p serving as the active regions. In the third embodiment, SiH is used as a method for forming the gate insulating film 311.₄Gas and N₂A low pressure CVD method was employed at a temperature of 850 ° C. using O gas as a raw material. This gate insulating film 311 is a so-called HTO film (High Temperature Oxide).
[0121]
  Next, in such a state, heat treatment in an oxidizing atmosphere is performed on the active regions 310n and 310p made of the silicon film. This oxidizing atmosphere is an oxidizing atmosphere such as oxygen, water vapor, and HCl. In the third embodiment, heat treatment was performed in an oxygen atmosphere of 1 atm. The temperature of this heat treatment is preferably 850 to 1100 ° C. In this third embodiment, the heat treatment was performed at 950 ° C. Under such conditions, annealing is performed for 2 hours and 30 minutes, whereby oxygen diffuses and moves in the gate insulating film 311, and the surfaces of the lower active regions 310n and 310p are oxidized. By performing the oxidation treatment under the above conditions, oxide films 312n and 312p of about 50 nm are formed on the surfaces of the active regions 310n and 310p made of island-like silicon films. As a result, the film thicknesses of the active regions 310n and 310p made of the silicon film are reduced from the initial 55 nm to 30 nm. The gate insulating film of the TFT is composed of two layers of an oxide film 311 formed by CVD and an oxide film 312 formed by thermal oxidation of the active regions 310n and 310p made of silicon film, and the total film thickness is 110 nm. become. The channel interface is composed of active regions 310n and 310p made of a silicon film and oxide films 312n and 312p formed by oxidation of the silicon film, and good interface characteristics can be obtained. Furthermore, this oxidation step significantly reduces unbonded bonds (dangling bonds) in the active regions 310n and 310p made of island-like silicon films, and greatly improves their crystallinity. As a result, active regions 310n ′ and 310p ′ made of high-quality crystalline silicon films thinned to 30 nm are generated.
[0122]
  Subsequently, as shown in FIG. 6G, a 400 to 800 nm thickness (for example, 500 nm of aluminum (including 0.1 to 2% of silicon)) is formed by sputtering, and the aluminum film is patterned. Thus, gate electrodes 313n and 313p are formed.
[0123]
  Next, impurities (phosphorus and boron) are implanted into the active regions 310n ′ and 310p ′ using the gate electrodes 313n and 313p as a mask by ion doping. As a doping gas, phosphine (PH₃) And diborane (B₂H₆In the case of the former, the acceleration voltage is 60 to 90 kV (for example, 80 kV), in the case of the latter, 40 kV to 80 kV (for example, 65 kV), and the dose is 1 × 10¹⁵~ 8x10¹⁵cm^-2(For example, phosphorus 2 × 10¹⁵cm^-2, Boron 5 × 10¹⁵cm^-2). In this ion doping process, regions which are masked by the gate electrodes 313n and 313p and are not implanted with impurities become channel regions 315n and 315p of the TFT later.
[0124]
  In the ion doping, each element is selectively doped by covering a region where doping is unnecessary with a photoresist. As a result, N-type impurity regions 316n and 317n and P-type impurity regions 316p and 317p are formed, and an N-channel TFT 326 and a P-channel TFT 327 can be formed as shown in FIG.
[0125]
  After that, as shown in FIG. 6G, annealing is performed by irradiation with a laser 320 to activate the implanted impurities. As the laser light, a XeCl excimer laser (wavelength: 308 nm, pulse width: 40 nanoseconds) is used, and the laser light irradiation condition is an energy density of 250 mJ / cm²Then, 20 shots were irradiated at one place.
[0126]
  Subsequently, as shown in FIG. 6H, a silicon oxide film having a thickness of 900 nm is formed as an interlayer insulating film 321 by a plasma CVD method, a contact hole is formed therein, and a metal material (for example, titanium nitride and the like) is formed. An electrode wiring 324 of the TFT is formed by an aluminum two-layer film. Finally, annealing is performed at 350 ° C. for 1 hour in a hydrogen atmosphere of 1 atm to complete the N-channel TFT 326 and the P-channel TFT 327.
[0127]
  Further, if necessary, a contact hole is also provided on the gate electrode 313n (p), and necessary electrodes are connected by a wiring 324. For the purpose of protecting the TFTs 326 and 327, a protective film made of a silicon nitride film or the like may be provided on the TFT.
[0128]
  In the CMOS structure circuit fabricated according to the third embodiment, the field effect mobility of each TFT is 250 to 300 cm for an N-type TFT.²/ Vs, 120-150cm with P-type TFT²/ Vs is high, and the threshold voltage is about 1V for the N-type TFT and about -1.5V for the P-type TFT, and exhibits very good characteristics. In addition, there was no abnormal increase in the leakage current frequently observed in the conventional example, and the leakage current value itself stably showed a very low value of 1 pA or less per unit W. This value is completely different from that of a conventional TFT prepared without using a catalyst element, and the production yield can be greatly improved. In addition, even when repeated measurements and durability tests with bias and temperature stress were performed, there was almost no deterioration in characteristics, and the reliability was very high and stable circuit characteristics compared to the conventional one.
[0129]
  The first to third embodiments according to the present invention have been specifically described above. However, the present invention is not limited to the above-described embodiments, and various types based on the technical idea of the present invention. Can be modified.
[0130]
  Further, in the above embodiment, as a method for introducing nickel, a small amount of nickel is added by a method in which an amorphous silicon film surface is coated with an ethanol solution in which a nickel salt is dissolved or a method in which a nickel thin film is formed by a sputtering method. And adopting a method of crystal growth. On the other hand, before the amorphous silicon film is formed, a method may be adopted in which nickel is introduced into the surface of the base film and the nickel is diffused from the lower layer of the amorphous silicon film to grow crystals. That is, crystal growth may be performed from the upper surface side or the lower surface side of the amorphous silicon film. In addition, various other methods can be used for introducing nickel. For example, water may be used simply as a solvent for dissolving a nickel salt, or SiO as a solvent using an SOG (spin-on-glass) material.₂There is also a method of diffusing from the film. In addition, a method of forming a thin film by an evaporation method or a plating method, a method of directly introducing nickel by an ion doping method, or the like can be used. Further, the same effect can be obtained by using cobalt, iron, palladium, platinum, copper, or gold in addition to nickel as the impurity metal element for promoting crystallization.
[0131]
  Moreover, in the said embodiment, although phosphorus was used as a group 5 B element for gettering nickel, you may utilize nitrogen, arsenic, antimony, and bismuth other than phosphorus. As a pattern for introducing a Group 5 B element, patterns other than those in the above three embodiments can be employed without any problem as long as a region doped with phosphorus is not included in the TFT channel region.
[0132]
  In the first and second embodiments, as a means for further promoting the crystallinity of the crystalline silicon film crystallized with nickel, a heating method using excimer laser irradiation as a pulse laser is used. A similar process is possible even with a continuous wave Ar laser (for example).
[0133]
  Further, as an application of the present invention, in addition to an active matrix substrate for liquid crystal display, for example, a contact built-in type optical writing element using a contact type image sensor, a driver built-in thermal head, an organic EL or the like as a light emitting element. A display element, a three-dimensional IC, and the like are conceivable. By using the present invention, high performance such as high speed and high resolution of these elements is realized. Furthermore, the present invention is not limited to the MOS transistors described in the above-described embodiments, but can be applied to a wide variety of semiconductor processes including bipolar transistors and electrostatic induction transistors using a crystalline semiconductor as an element material.
[0134]
【The invention's effect】
  As apparent from the above, the semiconductor device manufacturing method according to the present invention introduces a catalytic element that promotes crystallization into an amorphous silicon film formed on an insulating substrate, and after crystal growth is performed by heat treatment. Then, an element selected from Group 5 B is selectively introduced into the-part of the silicon film, rapid thermal annealing is performed, and the catalyst element is introduced into a region where the element selected from Group 5 B is introduced. Is to move. Then, the active (channel) region of the semiconductor device is formed by using the silicon film in a region other than the region into which the element selected from Group 5 B is introduced. By doing so, it becomes possible to greatly reduce the amount of residual catalytic elements in the active region of the semiconductor device as compared with the conventional method.
[0135]
  In one embodiment, the method for manufacturing a semiconductor device further selectively introduces a catalytic element into a part of an amorphous silicon film formed on an insulating substrate and heats the catalytic element to selectively select the catalytic element. Crystal growth of the amorphous silicon film is performed in the lateral direction (parallel to the substrate) from the region introduced into the region to the peripheral region. Furthermore, a region in which the element selected from Group 5 B is introduced by selectively introducing an element selected from Group 5 B into a part of the silicon film that has been crystal-grown, and performing rapid thermal annealing treatment. Then, the catalyst element is moved. In this case, when an active (channel) region of a semiconductor device is formed using a silicon film that is laterally grown outside the region in which an element selected from Group 5 B is introduced, a higher current driving capability can be obtained. A high-performance semiconductor device can be obtained. Of course, the amount of residual catalytic element in the active region of the semiconductor device can be greatly reduced as compared with the conventional method, and there is no abnormality in leakage current during off operation, which is a problem, and high reliability can be secured at the same time.
[0136]
  Further, in the present invention and the above-described embodiment, there is a point in the state of the introduction region after the introduction of the group 5 B element and the temperature increase rate in the subsequent rapid thermal annealing treatment. That is, according to the present invention, in the step of selectively introducing an element selected from Group 5 B into the crystal-grown silicon film, the silicon film in the region where the element selected from Group 5 B is introduced is amorphous. It is important that
[0137]
  Further, in the subsequent rapid thermal annealing process, the temperature is increased from a preheating temperature at which the Group 5 B element is introduced and the amorphous region is not crystallized to a temperature at which the rapid thermal annealing process is performed. During the period, it is very important that the heating is performed at such a temperature rising rate that the amorphous region is not completely crystallized. Accordingly, the effect of moving (gettering) the obtained catalyst element to the introduction region of the group 5 B element is greatly different. Generally, the gettering effect is improved by increasing the temperature of the heat treatment after the introduction of the Group 5 B element. This is because the diffusion rate of the catalytic element in the silicon film is improved and the solid solubility limit is increased. However, it is known that the gettering effect at this time reaches a peak at about 650 ° C., and the effect cannot be obtained even if the temperature is increased further.
[0138]
  In the present invention and the above-described embodiment, rapid thermal annealing is used as the heat treatment at this time, and rapid thermal annealing is performed from a preheating temperature at which the region that has been made amorphous by introduction of the Group 5 B element is not crystallized. It is a very important point to carry out the heating at such a temperature raising rate that the amorphous region is not completely crystallized during the temperature raising period up to the treatment temperature. By doing so, annealing can be performed for the first time at the intended annealing temperature with the region into which the Group 5 B element has been introduced being in an amorphous state, and the heat treatment temperature at this time is inherently high. A gettering effect can be obtained.
[0139]
  When a thin film transistor (TFT) is produced according to the present invention and the embodiment, when the TFT is similarly produced in the above publication and the prior art, an abnormal increase phenomenon of the leakage current when the TFT is turned off, which is seen with a probability of 3% or more, is observed. In the method of the present invention, it was not seen at all and was exactly 0%. Furthermore, the liquid crystal display device made using this TFT has no display irregularities (due to sampling TFTs in the driver section) and pixel defects caused by leakage current at the time of off, which are frequently caused by conventional methods, and display quality is greatly improved. In addition to the improvement, the yield rate was dramatically increased.
[0140]
  Further, as in the present invention and embodiment, the rapid thermal annealing treatment for moving the catalytic element to the introduction region of the group 5 B element is at least 30 ° C. from the preheating temperature of 600 ° C. or less to the rapid thermal annealing temperature. It is desirable to increase the temperature at a temperature increase rate exceeding 1 minute. More preferably, it is more desirable to raise the temperature at a rate of temperature exceeding 100 ° C./min. If the preheating temperature is 600 ° C. or lower, no crystal growth occurs in the region where the Group 5 B element is introduced and made amorphous. If the rate of temperature increase at this time is 30 ° C./min or more, crystallization in the region into which the Group 5 B element has been introduced is not completely completed in the temperature increasing process, and the amorphous component is removed. It is possible to enter a rapid thermal annealing process with the remaining state. Furthermore, if the temperature rising rate at this time is 100 ° C./min or more, in the temperature increasing process, almost no crystallization occurs in the region where the Group 5 B element is introduced, and it remains high in an almost amorphous state. Thermal annealing can be entered.
[0141]
  In one embodiment, in the step of moving the catalyst element to the region into which the Group 5 B element has been introduced, the average temperature during the rapid thermal annealing treatment is in the range of 650 to 800 ° C., and 1 second to It takes only 15 minutes. That is, as can be seen in FIG. 8, the effect of greatly reducing the concentration of the catalytic element according to the present embodiment appears only at 650 ° C. or higher. In the data of FIG. 8, the experiment was conducted at a temperature rising rate of 120 ° C./min. In the conventional method shown by the broken line in FIG. 8, the reduction effect has reached its peak at about 650 ° C. as described above. However, in this embodiment, as shown by the solid line, it has been observed up to this temperature so far. A higher gettering effect can be obtained. However, the higher the annealing temperature at this time, the better, and there is an upper limit. That is, when the temperature becomes higher, random diffusion of the catalytic element occurs, and the catalytic element moves from the introduction region of the group 5 element to the outside. As a result, the concentration of the catalytic element starts to increase. In particular, when the temperature exceeds 800 ° C., the residual rate of the catalytic element increases rapidly. At this time, if oxygen is present even a little, the silicide of the catalytic element is selectively oxidized and a hole is formed in the silicon film. . Therefore, the upper limit is limited by these two points and is 800 ° C. The annealing time has a sufficient effect within the above range.
[0142]
  In another embodiment, the average processing temperature of the rapid thermal annealing process is more preferably in the range of 700 to 750 ° C., and the processing is performed for a duration of 1 minute to 10 minutes. As can be seen from FIG. 8, the catalytic element reduction effect is almost saturated at about 700 ° C., and then gradually decreases to about 750 ° C., but takes an extreme value at 750 ° C., and increases at higher temperatures. Therefore, 700 to 750 ° C. is the optimum temperature range in the present embodiment. Furthermore, if the treatment time at this time is in the range of 1 minute to 10 minutes, a sufficient catalytic element reduction effect in the present embodiment can be obtained, and thermal damage when glass is used as the substrate ( Warpage and shrinkage) can also be minimized.
[0143]
  Further, in one embodiment, in the method for manufacturing a semiconductor device described above, when the glass substrate is used as the substrate, the catalytic element transfer step includes a shrinkage (heat shrinkage rate or The rate of temperature decrease from the rapid thermal annealing temperature is controlled so that the (thermal expansion coefficient) is 25 ppm or less. In this embodiment, the effect of this embodiment is obtained by heating the entire substrate uniformly at a relatively high temperature such as the above temperature range. In the present embodiment, the temperature lowering rate from the rapid thermal annealing temperature is controlled so that the shrinkage (thermal shrinkage rate or thermal expansion rate) of the glass substrate is 25 ppm or less. If it is below such a shrinkage value, the substrate is not actually warped, and mask alignment in the photolithography process can also be handled.
[0144]
  In one embodiment, in the semiconductor device manufacturing method described above, the group 5 element introduction step is performed by an ion doping method. In the region where the Group 5 B element is introduced by ion doping, the crystal of the silicon film is strongly broken and becomes amorphous. In this embodiment, it is one point to make the introduction region of the group 5 B element amorphous, and the stronger the amorphousization, the more effective. The catalytic element tends to move from the crystalline silicon film to the amorphous silicon film even when considered from the crystal growth process. That is, it is considered that the catalytic element is more energetically present in amorphous silicon. That is, the component made amorphous by ion doping has a synergistic effect and further enhances the gettering effect of the Group 5 B element.
[0145]
  Also,UpIn the semiconductor device manufacturing method described above, in the catalyst element transfer step,AntRapid thermal annealing is performed using a resistance heating furnace. ResistanceIn the case of using a resistance heating furnace, the substrates are inserted into the furnace one by one in order to provide a thermal gradient in the furnace and reduce the heat capacity of the substrate. The temperature increase rate may be controlled by controlling the insertion speed at that time. In this case, the entire substrate can be heated more uniformly and instantaneously, and the temperature increase rate and temperature decrease rate can be controlled with high accuracy, which is suitable for this embodiment.
[0146]
  In addition, one embodiment relates to an introduction pattern in the group 5 B element selective introduction step into the silicon film, using a patterned introduction mask, and at least on an active (channel) region of a semiconductor device to be finally formed In the masked state, a Group 5 B element is introduced into the peripheral portion so as to surround the active (channel) region. At this time, if a group 5 B element is introduced into the periphery of the semiconductor device so as to surround the active region in a state where the entire active (element) region of the semiconductor device is masked, not only the channel region but also the active region (channel + A state in which the catalyst element is hardly contained in the entire source / drain region is obtained. By doing in this way, the later process contamination by a catalyst element can be prevented. In this way, when the Group 5 B element is introduced so as to surround the channel region and further the active region, the catalyst element in the channel and the active region may move outward in all directions in all directions. it can. For this reason, the catalytic element in the active region can be moved to the outside very efficiently, and an excellent gettering effect can be obtained.
[0147]
  In another embodiment, as a method for introducing a Group 5 B element into a silicon film, a special introduction mask is not used, and a device region (channel and source / drain regions) of a semiconductor device is used. A group 5 B element is introduced into the impurity (source / drain) region. Then, it is used as an impurity (source / drain) region as it is. In this case, without using a dedicated introduction mask, both the group 5 B element introduction step for gettering and the impurity introduction step of the impurity (source / drain) region are performed, and in the rapid thermal annealing step, impurities are introduced. Also serves as the activation of the (source / drain) region. Thereby, a process can be simplified greatly and as a result, productivity can be improved most.
[0148]
  In one embodiment, in the case where a catalytic element is selectively introduced into a part of an amorphous silicon film and crystal growth is performed in the lateral direction, the selective introduction step of the catalytic element at that time is performed as a patterned introduction mask. Then, the selective introduction process of the group 5 B element is also performed using the same introduction mask. By doing in this way, it is not necessary to create an introduction mask separately for each introduction process, and the process can be simplified. At the same time, the silicon film region constituting the channel region of the subsequent semiconductor device can always be kept covered and exposed by the mask film throughout the process of introducing the catalyst element and the group 5 B element. Disappear. As a result, process-induced contamination of the channel region can be minimized. And the improvement of a non-defective product and cost reduction can be achieved by the action of these two points.
[0149]
  In another embodiment, Ni, Co, Fe, Pd, Pt, Cu, or Au can be used as the type of catalyst element. One or more kinds of elements selected from these have an effect of promoting crystallization in a very small amount. Among them, the most remarkable effect can be obtained particularly when Ni is used. Ni is two Si and NiSi₂The silicide is formed. NiSi₂Shows a meteorite-type crystal structure, which is very similar to the diamond structure of single crystal silicon. Moreover, NiSi₂Has a lattice constant of 5.406 Å, which is very close to the lattice constant of 5.430 で in the diamond structure of crystalline silicon. Therefore, NiSi₂Is the best template for crystallizing the amorphous silicon film, and it is most desirable to use Ni as the catalyst element in this embodiment.
[0150]
  In one embodiment, as an element selected from Group 5 B, at least one element selected from P, N, As, Sb, and Bi is used. If one or more kinds of elements selected from these are used, the catalyst element can be efficiently moved, and a sufficient gettering effect can be obtained.
[0151]
  In another embodiment, in the semiconductor device manufacturing method described above, the concentration of the catalytic element in the active (element) region of the semiconductor device finally obtained is 1 × 10¹⁶~ 2x10¹⁷cm^-3Is within the range.
[0152]
  In this embodiment, the concentration of the catalytic element in the channel region is 2 × 10.¹⁷cm^-3By making the following, no adverse electrical influence of the catalytic element on the semiconductor element characteristics is observed. As a result of using this embodiment, such a low concentration can be realized.
[0153]
  In the present invention, as a method for further improving the crystallinity of the silicon film crystallized by the catalytic element and further improving the performance of the semiconductor device, particularly the current driving capability, the silicon film crystallized by the catalytic element is applied. On the other hand, it is also effective to add a step of performing a heat treatment in a higher temperature oxidizing atmosphere and a step of irradiating laser light.
[0154]
  In the former method of performing heat treatment in an oxidizing atmosphere at a high temperature to further improve the crystallinity, the silicon film crystallized by the catalytic element is oxidized at a higher temperature (800 ° C. to 1100 ° C.). . Then, supersaturated Si atoms generated by the oxidation action are supplied into the silicon film, and these enter crystal defects (particularly dangling bonds) in the silicon film, and the defects can be eliminated. Thereby, the defect density in the silicon film crystallized by the catalytic element is greatly reduced, and the mobility is greatly improved. As a result, the performance of the semiconductor device is dramatically improved.
[0155]
  In the latter laser light irradiation process, when the crystalline silicon film is irradiated with strong light such as a laser, the crystal grain boundary portion and the crystalline silicon film are different from the melting point difference between the crystalline silicon film and the amorphous silicon film. Minute residual amorphous regions (non-crystallized regions) are intensively processed. Here, in the crystalline silicon film formed by the normal solid phase growth method, the crystal structure is in a twin crystal state, and therefore the inside of the crystal grain remains as a twin defect even after intense light irradiation.
[0156]
  On the other hand, a crystalline silicon film crystallized by introducing a catalytic element is formed of columnar crystals and the inside thereof is in a single crystal state, so that the grain boundary portion is treated by irradiation with strong light. Then, a high-quality crystalline silicon film close to a single crystal state can be obtained over the entire surface of the substrate. This is very effective from the viewpoint of crystallinity. In addition, since laser irradiation is originally performed on a silicon film having crystallinity, unlike the method of crystallizing by directly irradiating an amorphous silicon film with laser, the variation in laser irradiation is greatly reduced, and uniformity is improved. No problem arises.
[0157]
  Therefore, by using the present invention, it is possible to realize a high-performance semiconductor element having stable characteristics with little characteristic variation such as an abnormal increase in leakage current, and a high-performance semiconductor device having a high degree of integration with a simple manufacturing process. can get. In addition, the yield rate can be greatly improved in the manufacturing process, and the cost of the product can be reduced. In particular, in the liquid crystal display device, the switching characteristics of the pixel switching TFT required for the active matrix substrate and the high performance and high integration required for the TFT constituting the peripheral drive circuit unit are satisfied at the same time. A driver monolithic active matrix substrate that constitutes the active matrix portion and the peripheral drive circuit portion on the top can be realized, and the module can be made compact, high performance, and low in cost.
[Brief description of the drawings]
FIG. 1A to FIG. 1E are plan views sequentially showing a manufacturing process of a first embodiment of a method for manufacturing a semiconductor device of the present invention.
FIGS. 2A to 2G are cross-sectional views sequentially showing manufacturing steps of the first embodiment.
FIGS. 3A to 3G are cross-sectional views sequentially showing manufacturing steps of a second embodiment of the method for manufacturing a semiconductor device of the present invention. FIGS.
FIG. 4 is a plan view for explaining a manufacturing process of the second embodiment.
FIGS. 5A to 5D are cross-sectional views sequentially showing the first half of a process according to a third embodiment of the present invention.
FIGS. 6E to 6H are cross-sectional views sequentially showing the latter half of the process of the third embodiment.
FIGS. 7A and 7B are experiments showing the relationship between the temperature rising rate and the remaining rate of the catalyst element, the temperature rising rate and the Raman peak intensity ratio in the rapid thermal annealing process in the embodiment of the present invention. It is a characteristic view by data.
FIG. 8 is a characteristic diagram based on experimental data showing the catalyst element residual ratio with respect to the processing temperature in the rapid thermal annealing process in the embodiment of the present invention.
FIGS. 9A and 9B are graphs showing examples of temperature profiles in the rapid thermal annealing process in the second and third embodiments of the present invention.
[Explanation of symbols]
  101, 201 ... glass substrate, 301 ... quartz substrate,
  102, 202 ... Undercoat film,
  103, 203, 303 ... amorphous silicon film,
  103a, 203a, 303a ... crystalline silicon film,
  104, 204, 304 ... nickel, 105, 205 ... laser light,
  106,306 ... mask, 307 ... arrow indicating crystal growth direction,
  108,208,308 ... Phosphorus,
  109, 209, 309 ... arrows indicating the gettering direction of nickel,
  110, 210, 310 ... island-like crystalline silicon film to be a TFT active region,
  111, 211, 311 ... gate insulating film,
  312 ... Si oxide film (gate insulating film),
  113, 213, 313 ... gate electrodes (gate electrode bus lines),
  114 ... oxide layer,
  115, 215, 315 ... regions to be channels,
  116, 216, 316 ... source region,
  117, 217, 317 ... regions to be drains,
  218 ... Photoresist mask,
  219 ... Boron, 120, 320 ... Laser light,
  121,221,321 ... interlayer insulating film,
  122 ... Source electrode wiring (source bus line),
  123: Pixel electrode, 224, 324 ... Electrode wiring,
  125 ... pixel TFT,
  226, 326 ... N-channel TFT,
  227, 327 ... P-channel TFTs.

Claims (13)

A catalyst element introduction step of forming an amorphous silicon film on a substrate having an insulating surface and introducing a catalyst element for promoting crystallization of the amorphous silicon film;
A crystal growth step for performing a heat treatment to perform crystal growth of the amorphous silicon film into which the catalyst element is introduced;
A group 5 element introduction step of selectively introducing an element selected from group 5 B into a portion of the silicon film grown as a crystal;
A catalytic element transfer step of performing a rapid thermal annealing process to move the catalyst element to a region into which an element selected from Group 5 B is introduced;
An active region forming step of forming an active region of a semiconductor device using a silicon film in a region other than a region into which an element selected from Group 5 B is introduced,
In the group 5 element introduction step, the silicon film in the region where the element selected from group 5 B is introduced is amorphized,
In the catalyst element transfer step, during a temperature rising period from a preheating temperature at which an element selected from Group 5 B is introduced and amorphized to at least crystallize, to a temperature at which rapid thermal annealing is performed , Rapid thermal annealing is performed at a rate of temperature rise that does not completely crystallize the amorphous region,
In the rapid thermal annealing, the substrate is inserted one by one in a resistive heating furnace having a thermal gradient in the furnace, and the temperature raising / lowering speed is controlled by controlling the speed of this insertion,
The catalyst element transfer step includes
A method of manufacturing a semiconductor device, wherein the temperature is increased from a preheating temperature of 600 ° C. or less to a rapid thermal annealing temperature at a temperature rising rate exceeding 30 ° C./min. A catalyst element introduction step of forming an amorphous silicon film on a substrate having an insulating surface and selectively introducing a catalyst element that promotes crystallization into a part of the amorphous silicon film;
A crystal growth step in which the amorphous silicon film is grown in parallel with the substrate from the region where the catalytic element is selectively introduced to the peripheral region by performing heat treatment;
A group 5 element introduction step of selectively introducing an element selected from group 5 B into a portion of the silicon film grown as a crystal;
A catalytic element transfer step of performing a rapid thermal annealing process to move the catalyst element to a region into which an element selected from Group 5 B is introduced;
An active region forming step of forming an active region of a semiconductor device using a silicon film crystallized laterally outside the region into which an element selected from Group 5 B is introduced;
In the group 5 element introduction step, the silicon film in the region where the element selected from group 5 B is introduced is amorphized,
In the catalyst element transfer step, during a temperature rising period from a preheating temperature at which an element selected from Group 5 B is introduced and amorphized to at least crystallize, to a temperature at which rapid thermal annealing is performed , Rapid thermal annealing is performed at a rate of temperature rise that does not completely crystallize the amorphous region,
In the rapid thermal annealing, the substrate is inserted one by one in a resistive heating furnace having a thermal gradient in the furnace, and the temperature raising / lowering speed is controlled by controlling the speed of this insertion,
The catalyst element transfer step includes
A method of manufacturing a semiconductor device, wherein the temperature is increased from a preheating temperature of 600 ° C. or less to a rapid thermal annealing temperature at a temperature rising rate exceeding 30 ° C./min. In the manufacturing method of the semiconductor device according to claim 1 or 2,
The catalyst element transfer step includes
A method of manufacturing a semiconductor device, wherein the temperature is increased from a preheating temperature of 600 ° C. or less to a rapid thermal annealing temperature at a rate of temperature exceeding 100 ° C./min. In the manufacturing method of the semiconductor device according to any one of claims 1 to 3,
The catalyst element transfer step includes
A method of manufacturing a semiconductor device, which is performed by a rapid thermal annealing process having an average temperature in a range of 650 to 800 ° C. and a duration of 1 second to 15 minutes. In the manufacturing method of the semiconductor device according to claim 4,
The catalyst element transfer step includes
A method of manufacturing a semiconductor device, which is performed by a rapid thermal annealing process having an average temperature in a range of 700 to 750 ° C. and a duration of 1 minute to 10 minutes. In the manufacturing method of the semiconductor device according to any one of claims 1 to 5,
The catalyst element transfer step includes
When a glass substrate is used as the substrate, the method for manufacturing a semiconductor device is characterized in that the rate of temperature decrease from the rapid thermal annealing temperature is controlled so that the shrinkage of the glass substrate before and after this step is 25 ppm or less. . In the manufacturing method of the semiconductor device according to any one of claims 1 to 6 ,
The group 5 element introduction step is performed by an ion doping method. In the manufacturing method of the semiconductor device according to any one of claims 1 to 7 ,
In the group 5 element introduction step,
An element selected from Group 5 B is introduced into the periphery of the active region so as to surround the active region in a state where at least the active region of the semiconductor device to be finally formed is masked. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to any one of claims 1 to 7 ,
In the group 5 element introduction step,
A method of manufacturing a semiconductor device, wherein an element is introduced into an impurity region in an element region of the semiconductor device and used as an impurity region as it is. In the manufacturing method of the semiconductor device according to any one of claims 2 to 7 ,
The method for manufacturing a semiconductor device, wherein the catalyst element introduction step and the group 5 element introduction step are performed using the same introduction mask. The method of manufacturing a semiconductor device according to any one of claims 1 to 1 0,
A method of manufacturing a semiconductor device, wherein at least one element selected from Ni, Co, Fe, Pd, Pt, Cu, and Au is used as a catalyst element for promoting crystallization of the amorphous silicon film. . The method of manufacturing a semiconductor device according to any one of claims 1 to 1 0,
A method of manufacturing a semiconductor device, wherein at least one element selected from P, N, As, Sb, and Bi is used as an element selected from Group 5 B. The method of manufacturing a semiconductor device according to any one of claims 1 to 1 2,
The method of manufacturing a semiconductor device, wherein the concentration of the catalytic element in the active region of the finally obtained semiconductor device is in the range of 1 × 10 ¹⁶ to 2 × 10 ¹⁷ cm ⁻³ .

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