JP2001135574A - Method of fabrication for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control a trace of catalytic element. SOLUTION: An a-Si film 3 is formed on a glass substrate 1, a thin oxide film 4 is formed thereon and nickel 5 is introduced, as a catalytic element, through the thin oxide film 4. After removing the thin oxide film 4 where a large quantity of nickel 5 exists, the a-Si film 3 is crystallized by heat treatment. After phosphorus 8 is doped except an active region, nickel 5 diffused into a crystalline silicon film 3a' is attracted into a phosphorus doped crystalline silicon film 3b. A channel region is formed using the crystalline silicon film 3a' thus obtained. A trace of nickel 5 introduced into the a-Si film 3 is controlled by growing the a-Si film 3 epitaxially after the thin oxide film 4 is removed and leaving only a trace of nickel 5 introduced through the thin oxide film 4 in the a-Si film 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using a crystalline silicon film obtained by crystallizing an amorphous silicon film as an active region. In particular, the present invention is effective for a semiconductor device using a thin film transistor (TFT) provided on a substrate having an insulating surface, and includes an active matrix liquid crystal display device, a contact image sensor, and a three-dimensional IC (integrated circuit). Etc. can be used.

[0002]

2. Description of the Related Art In recent years, large-scale, high-resolution liquid crystal display devices, high-speed, high-resolution contact-type image sensors, and three-dimensional ICs have been developed to achieve high performance on insulating substrates or insulating films such as glass. Attempts have been made to form various semiconductor devices. In general, a thin-film silicon semiconductor is used for a semiconductor element used in each of the above apparatuses. Thin-film silicon semiconductors are broadly classified into two types: amorphous silicon (a-Si (amorphous silicon)) semiconductors and crystalline silicon semiconductors.

The above-mentioned amorphous silicon semiconductor is most commonly used because it has a low production temperature, can be relatively easily produced by a gas phase method, and has high mass productivity. However, since physical properties such as conductivity are inferior to crystalline silicon semiconductors, in order to obtain higher speed characteristics in the future, it is strongly required to establish a method for manufacturing a semiconductor device made of crystalline silicon semiconductor. I have. Note that polycrystalline silicon, microcrystalline silicon, and the like are known as crystalline silicon.

As a method of obtaining a silicon semiconductor in the form of a thin film having crystallinity, (1) a film having crystallinity is directly formed at the time of film formation. (2) An amorphous semiconductor film is formed, and crystallinity is imparted by the energy of laser light. (3) An amorphous semiconductor film is formed and crystallinity is imparted by applying thermal energy. And other methods are known.

However, in the method (1), crystallization proceeds simultaneously with the film forming step. Therefore, in order to obtain crystalline silicon having a large grain size, it is necessary to increase the thickness of the silicon film, and it is technically difficult to uniformly form a film having good semiconductor properties over the entire surface of the substrate. is there.

In the method (2), since the crystallization phenomenon in the melt-solidification process is used, the grain boundaries are favorably treated, and a high-quality crystalline silicon film having a small grain size can be obtained. However, an excimer laser, which is currently most commonly used, has not yet been obtained with sufficient stability. Therefore, it is difficult to uniformly treat the entire surface of a large-area substrate, and further technical improvement in hardware is desired.

In the method (3), (1), (2)
This method is advantageous in terms of uniformity and stability in the substrate as compared with the above method. However, heat treatment at 600 ° C. for a long time of about 30 hours is necessary, and the treatment time is long,
There is a problem that the throughput is low. Further, in this method, since the crystal structure becomes a twin structure, one crystal grain is relatively large as several μm. The crystallinity is inferior to the method. As a method for improving crystallinity, 10
A technique of performing heat treatment in an oxygen atmosphere at about 00 ° C. has also been used. However, in that case, an inexpensive glass substrate cannot be used, and the device characteristics thus obtained also show a field effect mobility of 100 cm ² / V in the TFT.
s low.

A method for obtaining a high-quality crystalline silicon film by improving the above method (3) with respect to the above method is disclosed in
It is proposed in JP-A-135174 and JP-A-10-256155. In these methods, the use of a catalyst element that promotes crystallization of the amorphous silicon film reduces the heating temperature and shortens the processing time, thereby improving the crystallinity. Specifically, a minute amount of a metal element such as nickel or palladium is introduced into the surface of the amorphous silicon film, and then heating is performed.

The mechanism of this low-temperature crystallization is that crystal nucleus generation with a metal element as a nucleus occurs at an early stage, and then the metal element acts as a catalyst to promote crystal growth, and crystallization proceeds rapidly. Understood. In that sense, these metal elements are hereinafter referred to as catalyst elements. Crystalline silicon films grown by the promotion of crystallization by these catalyst elements are formed by twinning in one grain of the crystalline silicon film crystallized by the ordinary solid phase growth method (method (3) above). While the structure has many crystal defects, the inside of the grains is composed of a number of columnar crystal networks, and the interior of each columnar crystal becomes an almost ideal single crystal state. I have.

Further, in each of the above publications, a catalyst element is selectively introduced into a part of the amorphous silicon film and heated to leave the other part in the state of the amorphous silicon film. By selectively crystallizing only the region into which the catalytic element has been introduced, and further extending the heating time, crystal growth is performed in a lateral direction (a direction parallel to the substrate) from the introduced region. Inside the lateral crystal growth region, columnar crystals whose growth directions are substantially aligned in one direction are tied together, and the crystallinity is further improved as compared with the region where the catalyst element is directly introduced and crystal nuclei are generated randomly. It's getting better. Therefore, the performance of the semiconductor device can be improved by using the crystalline silicon film in the lateral crystal growth region for the active region of the semiconductor device.

The above-mentioned JP-A-7-135174 and JP-A-10-256155 both relate to a method for introducing a catalytic element into an amorphous silicon film when a catalytic element is selectively introduced, The catalyst element is introduced by spin-coating a solution of the catalyst element on the surface of the amorphous silicon film. In this method, the amount of the catalyst element introduced into the amorphous silicon film can be easily controlled by arbitrarily controlling the concentration of the solution. There is also an advantage that a very small amount of a catalyst element can be relatively accurately controlled and introduced into the amorphous silicon film. However, in this case, since the surface of the amorphous silicon film is hydrophobic, when water or alcohol is used as a solvent, the solution is repelled, and stable coating cannot be performed. Therefore, in these publications, after the surface of the amorphous silicon film is oxidized in a thin film to make the surface hydrophilic, spin coating of a catalyst element solution is performed.

[0012]

However, Japanese Patent Application Laid-Open Nos. Hei 7-135174 and Hei 10-256 describe above.
The method for obtaining a high-quality crystalline silicon film as disclosed in JP-A-155-155 has the following problems.

That is, as described above, since the amorphous silicon film is crystallized by introducing the catalytic element,
The heating temperature can be lowered and the heating time can be reduced, and the crystallinity of the silicon film obtained after crystallization is clearly superior to other conventional crystallization methods. However, the presence of a large amount of the above-mentioned metal-based catalyst elements in a semiconductor impairs the reliability and electrical stability of a device using such a semiconductor, and is by no means preferable.

Therefore, the above-mentioned catalytic element for promoting crystallization, such as nickel, is necessary when crystallizing amorphous silicon, but should be contained as little as possible in the crystallized silicon. Is desirable. To do so, it is necessary to select a catalyst element that has a strong tendency to be inactive in crystalline silicon as well as minimize the amount of the catalyst element required for crystallization and perform crystallization with the minimum amount. . In order to do so, it is necessary to control the amount of addition of the above-mentioned catalyst element precisely and introduce it. ) Is essential.

In addition, in this method, the crystallization of the amorphous silicon film is performed depending on the catalytic element. Conversely, if the amount of the introduced catalytic element varies, the crystal state also changes. Thus, the characteristics will vary, and the characteristics of the semiconductor element using the active region as the active region will also vary. At present, these are the biggest problems in the crystallization method using this catalytic element.

As a method for efficiently introducing a trace amount of nickel only to the vicinity of the surface of an amorphous silicon film, the above-mentioned JP-A-7-135174 and JP-A-10-25 have been disclosed.
As in the case of JP-A-6155, there is a method in which a solution in which a catalytic element is dissolved is applied to the surface of an amorphous silicon film by a spinner. According to this method, the amount of nickel introduced into the amorphous silicon film can be easily controlled by controlling the concentration of nickel in the solution, and a minimum amount of catalyst element necessary for crystallization can be added. become.

However, one of the biggest problems in the method for obtaining a crystalline silicon film disclosed in the above publication is that the uniformity in the substrate is not good. In this method, when the catalyst element is, for example, nickel, a nickel salt such as nickel nitrate or nickel acetate is used as a solute, and water, ethanol, or the like is used as a solvent for dissolving it. This solution is spin-coated on the surface of the amorphous silicon film, but actually, the catalyst element is deposited on the surface of the amorphous silicon film by a spin-drying process instead of spin coating. Therefore, in this method, the image of depositing and depositing the ionic catalyst element on the surface of the amorphous silicon film rather than the image of coating is more correct.

Therefore, in the above-mentioned method, the uneven drying of the solution appears as it is in the amount of the introduced catalyst element and further, the non-uniformity of the crystallinity of the crystalline silicon film obtained by heating. The nonuniformity referred to here includes both macroscopic nonuniformity due to the influence of the spinner and microscopic nonuniformity due to minute (μm order) remaining water droplets during the drying process. In particular, the latter microscopic non-uniformity appears more remarkably on a substrate having a pattern step, such as when a catalyst element is selectively introduced. Actually, when this method is used, the macroscopic variation in the actual amount of the catalyst element added is 12
There is about ± 20% on 7 mm square substrate, and the long side 4
For a large substrate of 00 mm or more, it is expanded to about ± 40%.
This value is simply a macro-variation in the surface addition concentration, and the variability in the crystal state is further enlarged by other factors. That is, in addition to the above-mentioned micro-variation, the macro-variation in the surface addition concentration is very sensitive to particles such as dust, and the coating unevenness is so large that it is almost always necessary that fine dust exists on the substrate surface. This leads to uneven crystal growth.

Also, in the above-mentioned method, the most important point is how much the solution containing the catalyst element dropped on the surface of the amorphous silicon film is dried while being in contact with the surface by the spinner. The wettability of the solution to the surface of the crystalline silicon film becomes important. Therefore, a process such as thin film oxidation of the amorphous silicon film surface is required to improve wettability, and not only an extra process is increased,
Since the parameters governing the amount of catalyst element introduced further increase, the stability of the treatment method itself also decreases.

Further, as a mechanism of the crystallization method using the catalyst element, first, a silicide reaction occurs between the catalyst element and the amorphous silicon film by heat treatment, and crystal growth occurs using the silicide reaction as a crystal nucleus. . However,
In the method of spin-coating the solution, the catalytic element is not in the form of metal atoms but exists in an incomplete ionic crystal (salt) state, and this silicide reaction becomes unstable, so that generation of crystal nuclei and crystal growth are also not possible. Become stable. Furthermore, between the catalytic element and the amorphous silicon film to be reacted, there is a thin oxide film formed for improving wettability during spin coating,
This further destabilizes the silicide reaction, destabilizing generation of crystal nuclei and crystal growth.

Therefore, the above-mentioned Japanese Patent Application Laid-Open No. Hei 7-135174
In the method for obtaining a crystalline silicon film as described in JP-A-10-256155 and JP-A-10-256155,
The addition amount of the catalyst element in the substrate is largely non-uniform, and the crystal growth unevenness due to minute particles and the like is locally generated, and the generation of crystal nuclei is also unstable. Crystal growth with high uniformity and high reproducibility cannot be achieved.

That is, hundreds of thousands of TFTs are formed on one substrate such as an active matrix substrate of a liquid crystal display device.
It is very difficult to fabricate with good uniformity by the above-mentioned method. In particular, in the manufacturing process of an active matrix substrate for a liquid crystal display, the mainstream has shifted to a large substrate of 400 mm square or more in accordance with a demand for lower cost and larger area of the device. For such large substrates,
The methods described in the above publications cannot cope at all, and there is a demand for a method of manufacturing a semiconductor device having excellent uniformity and stability, which can replace the methods described in the above publications.

Therefore, an object of the present invention is to provide a thin-film silicon semiconductor in which an amorphous silicon film is crystallized by a heat treatment using a catalytic element. Minimize that amount. (2) A catalyst element is introduced into the substrate surface with good uniformity so that a large-area substrate can be handled. (3) Use a method with high productivity. (4) Higher crystallinity than that obtained by heat treatment is obtained. Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device capable of obtaining a highly integrated high-performance semiconductor device having stable characteristics with small characteristic variations by a simple manufacturing process.

[0024]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming an amorphous silicon film on a substrate having an insulating surface; Forming a thin oxide film by thinly oxidizing the surface of the silicon film, introducing a catalytic element that promotes crystallization to the amorphous silicon film through the thin oxide film, and removing the thin oxide film A step of performing a heat treatment to crystallize the amorphous silicon film, and a step of forming a channel region of a semiconductor device using the crystalline silicon film obtained by the crystallization. And

According to the above configuration, after the catalytic element is introduced into the amorphous silicon film through the thin oxide film formed on the surface of the amorphous silicon film, a large amount of the catalytic element exists on the surface or inside. The thin oxide film is removed. Therefore, only a trace amount of the catalyst element introduced through the thin oxide film remains in the amorphous silicon film, and the introduction amount of the catalyst element promotes crystallization of the amorphous silicon film. It is controlled to the required minimum amount and with high precision.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming an amorphous silicon film on a substrate having an insulating surface; A step of forming a film, a step of selectively introducing a catalyst element that promotes crystallization to a part of the amorphous silicon film through the thin oxide film, a step of removing the thin oxide film, and a heat treatment Crystallizing the amorphous silicon film in parallel with the substrate from the region in which the catalytic element is introduced to the peripheral region thereof by using the crystalline silicon film obtained by the crystallization. A step of forming a channel region of the semiconductor device is provided.

According to the above configuration, as in the case of the first invention, the thin oxide film having a large number of catalytic elements on its surface or inside is removed, and the above-mentioned amorphous silicon film is removed. The introduction amount of the catalyst element is controlled to a very small amount necessary for promoting the crystallization of the amorphous silicon film and accurately.

Further, the crystallization of the amorphous silicon film into which the catalyst element has been introduced is performed in parallel with the substrate from the introduction region to the peripheral region. As a result, within the lateral crystal growth region, columnar crystals whose growth directions are substantially aligned in one direction are crowded. As in the case of the first aspect, the catalyst element is directly introduced and the The crystallinity becomes better than when nucleation occurs. Therefore, by using the crystalline silicon film in the lateral crystal growth region for the channel region of the semiconductor device, the performance of the semiconductor device can be improved.

In the method of manufacturing a semiconductor device according to the first and second aspects of the present invention, the catalyst element is introduced into the amorphous silicon film through the thin oxide film using a target containing the catalyst element. It is desirable that the sputtering be performed by sputtering from the above thin oxide film.

According to the above configuration, since the introduction of the catalytic element is performed by sputtering from above the thin film oxide film, the deposition atoms enter even deeper than in the CVD or vapor deposition method. As a result, a part of the catalyst element is uniformly introduced through the thin oxide film to the amorphous silicon film.

In the method of manufacturing a semiconductor device according to the first and second aspects of the present invention, the amount of a catalytic element introduced into the amorphous silicon film is controlled by controlling the sputtering power during the sputtering. It is desirable.

According to the above-mentioned sputtering method, in a low power region, the depth of a deposition atom implanted in a film by power changes. Therefore, according to the above configuration, the amount of the catalyst element entering the amorphous silicon film is easily and accurately controlled by utilizing this phenomenon.

In the method of manufacturing a semiconductor device according to the first and second aspects of the present invention, the thin film oxidation of the surface of the amorphous silicon film may be performed at a temperature lower than a temperature at which crystallization of the amorphous silicon film starts. It is desirable that the thin film oxidation be performed in such a manner that the oxide film thickness is saturated with respect to the processing time.

According to the above configuration, the thin film oxidation is performed in such a manner that the oxide film thickness is saturated with respect to the processing time.
Therefore, by performing the thin-film oxidation for a predetermined time to reach the above-mentioned saturation state, the thickness of the thin-film oxide film within the substrate and between the substrates is always kept constant. As a result, the control of the introduction amount of the catalyst element is performed stably, the accuracy is improved, and the uniformity is further improved.

In the method of manufacturing a semiconductor device according to the first and second aspects of the present invention, the thin-film oxidation of the surface of the amorphous silicon film comprises at least one of sulfuric acid, hydrogen peroxide and ozone water. It is desirable to carry out by immersing the surface of the amorphous silicon film in a liquid.

According to the above configuration, since the reaction is performed only on the active surface of the amorphous silicon film, oxidation proceeds to form an oxide film, and at the same time, the oxidation reaction decreases. As a result, the thickness of the thin oxide film becomes saturated with respect to the processing time. Further, particles and the like adhering to the surface of the amorphous silicon film are washed.

In the method of manufacturing a semiconductor device according to the first and second inventions, the thin film oxidation of the surface of the amorphous silicon film may be performed by applying UV light to the surface of the amorphous silicon film in an oxygen atmosphere. It is desirable to perform the irradiation.

According to the above configuration, since the active surface reaction of the amorphous silicon film is used, the thickness of the oxide film becomes saturated as the oxidation proceeds. Further, a denser thin oxide film is formed as compared with the method of immersing the surface of the amorphous silicon film in the liquid. Therefore, the barrier effect is high, and the amount of the catalytic element introduced into the amorphous silicon film can be controlled to be lower.

In the method of manufacturing a semiconductor device according to the first and second aspects of the present invention, the thin film oxide film is removed, the catalyst element and the amorphous silicon film are not etched,
It is preferable to perform the etching by using an etchant in which only the silicon oxide film is selectively etched.

According to the above configuration, when the thin oxide film is removed, the catalyst element introduced into the amorphous silicon film is removed, or the amorphous silicon film is etched to remove the catalyst element. Elements are not etched back.
Thus, the target crystallization is performed on the amorphous silicon film.

In the method of manufacturing a semiconductor device according to the first and second aspects of the present invention, it is preferable that at least hydrofluoric acid is used as the etchant.

According to the above configuration, only the thin oxide film is selectively etched by hydrofluoric acid.
At this time, the hydrofluoric acid causes very little contamination of the silicon film, and the catalyst element in the thin oxide film does not adhere to the amorphous silicon film again.

In the method of manufacturing a semiconductor device according to the first and second inventions, it is desirable to use at least a nickel element as the catalyst element.

According to the above structure, the silicide NiSi ₂ formed by the nickel element has a fluorite type crystal structure, and the crystal structure is very similar to the diamond structure of single crystal silicon. Moreover, the lattice constant of silicide NiSi ₂ is very close to the lattice constant of crystalline silicon (diamond structure). Therefore, silicide NiSi ₂ functions as the best template for crystallizing the amorphous silicon film, and crystallization of the amorphous silicon film is promoted.

In the method of manufacturing a semiconductor device according to the first aspect of the present invention, the nickel concentration on the surface of the amorphous silicon film after the removal of the thin oxide film is set to 1 × 10 ¹² atoms / cm ^2.
It is desirable that the density be equal to or more than 1 × 10 ¹³ atoms / cm ² .

According to the above configuration, the nickel concentration is 1 × 1
Since it is 0 ¹² atoms / cm ² or more, sufficient crystal growth is performed on the amorphous silicon film. 1 × 10 ¹³ at
Since it is not more than oms / cm ² , the region which is unevenly distributed in the crystalline silicon film as silicide after crystallization does not increase and does not adversely affect the characteristics of the semiconductor element.

In the method of manufacturing a semiconductor device according to the second aspect of the present invention, the nickel concentration in the nickel-introduced region on the surface of the amorphous silicon film after the removal of the thin oxide film is reduced to 1%.
It is desirable that the density be at least × 10 ¹³ atoms / cm ² and at most 1 × 10 ¹⁴ atoms / cm ² .

According to the above configuration, the nickel concentration is 1 × 1
Since it is 0 ¹³ atoms / cm ² or more, sufficient crystal growth is performed on the amorphous silicon film. Furthermore, 1 × 10 ¹⁴ at
Since it is not more than oms / cm ² , the region which is unevenly distributed in the crystalline silicon film as silicide after crystallization does not increase and does not adversely affect the characteristics of the semiconductor element.

[0049]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. <First Embodiment> In this embodiment, a case where the present invention is applied to a process for manufacturing an N-type TFT on a glass substrate will be described. TF in the present embodiment
T can be used not only as a driver circuit and a pixel portion of an active matrix type liquid crystal display device but also as an element constituting a thin film integrated circuit. In the present embodiment, a typical example is a TFT for driving a pixel of an active matrix substrate for a liquid crystal display device in which hundreds of thousands to several millions of N-type TFTs need to be particularly uniformly formed on a substrate. To explain.

FIG. 1 is a plan view showing an outline of a manufacturing process of a pixel TFT on an active matrix substrate in the present embodiment. Actually, as described above, it is composed of hundreds of thousands or more TFTs, but in the present embodiment, the description will be simplified to 12 TFTs of 3 rows × 4 columns. 2 and 3 are cross-sectional views showing a manufacturing process corresponding to a cross section taken along the line AA ′ in FIG. 1 (e). The manufacturing process of the pixel TFT is performed in the order of FIG. 2 (a) to FIG. proceed.

First, as shown in FIG. 2 (a), a 300 nm-thick
A base film made of silicon oxide 2 having a thickness of about 500 nm is formed. This silicon oxide film 2 is provided to prevent diffusion of impurities from the glass substrate 1. Next, plasma CVD
According to the (chemical vapor deposition) method, the thickness is 20 nm to 80 nm (for example, 3 nm).
An intrinsic (I-type) amorphous silicon film (a-Si film) 3 having a thickness of 0 nm is formed. In this embodiment, a parallel plate type plasma CVD apparatus is used, SiH ₄ gas and H ₂ gas are used as material gases, the substrate heating temperature is set to 200 ° C. to 400 ° C., and the power of RF (high frequency) power is set. Density of 10mW / cm ² ~
The operation was performed at 100 mW / cm ² .

Next, as shown in FIG.
-The surface of the Si film 3 is thin-film oxidized to form a thin-film oxide film 4. The thin oxide film 4 is formed by heating a liquid obtained by mixing concentrated sulfuric acid and hydrogen peroxide solution at a ratio of 1: 1 from 100 ° C. to 150 ° C., and immersing the semiconductor laminated substrate therein. The processing time is about 5 minutes, and even if the processing is continued for a longer time, the substantially oxide film thickness becomes saturated. The thickness of the thin oxide film 4 thus formed is about 20 ° to 30 °.

Then, a small amount of nickel 5 is added from above. This small amount of nickel 5 is pure nickel
(99.9% or more) by DC sputtering using a target. Specifically, a very low DC power of about 100 W increases the substrate transfer speed to 2000
Sputtering process is performed up to mm / min. Argon was used as a sputtering gas, and the gas pressure during sputtering on a pure nickel target was 10 Pa.
With the above, extremely low concentration sputtering of nickel becomes possible.

The nickel 5 sputtered in this manner is represented as a thin film in FIG. 2A, but is actually in a state of about a monoatomic layer or less, and is very thin. Not in a callable state. Specifically, DC
When sputtering was performed under the conditions of a power of 40 W and an argon gas pressure of 18 Pa, the nickel concentration on the surface of a-Si3 (thin oxide film 4) was about 4 × 10 ¹³ atoms / cm ² . The nickel concentration in this case was determined by total reflection X-ray fluorescence analysis (T
Although the measurement is performed by the RXRF method, since the resolution in the depth direction is about 100 °, not only the upper thin film oxide film 4 but also a part of the lower a-Si film 3 are included in the measurement. At this time, most of the sputtered nickel 5 exists on the surface of the thin oxide film 4 or in the thin oxide film 4, but a part of the lower a-S
Some of them enter the surface of the i-film 3. That is, at this stage, the state is schematically as shown in FIG.

Next, as shown in FIG. 2B, the thin oxide film 4 is removed. Regarding the removal of the thin oxide film 4, a
-Use hydrofluoric acid having a sufficient etching selectivity with Si and nickel, specifically, buffered hydrofluoric acid (BHF) containing ammonium fluoride. By this step, a large amount of nickel 5 existing on the surface of or in the thin film oxide film 4 is lifted off together with the thin film oxide film 4 and removed. Then, FIG. 2 (b)
As shown in the figure, only a part of the nickel 5 reached by sputtering remains on the surface of the a-Si film 3. At this stage, a-S
When the nickel concentration on the i3 surface is measured, 5 × 10 ¹² ato
It is about ms / cm ² , and it can be seen that the concentration can be reduced by about one digit compared to nickel addition by direct sputtering. Further, when the uniformity of the nickel concentration in the substrate at this stage is examined in a substrate of 320 mm × 400 mm square, it is about ± 10%, which is very good.

Further, this is subjected to a heat treatment in an inert atmosphere such as a nitrogen atmosphere. In this heat treatment, a heat treatment of a first step for desorbing hydrogen in the a-Si film 3 is performed during the temperature rise, and then a second heat treatment at a higher temperature is performed.
The a-Si film 3 is crystallized by the heat treatment in the step. Specifically, as the heat treatment of the first step, 450
C. to 530.degree. C. for 1 hour to 2 hours,
As the heat treatment in the second step, annealing is performed at 530 ° C. to 650 ° C. for 2 hours to 8 hours. In this embodiment, as an example, the first step heat treatment is performed at 480 ° C. for 1 hour, and then the second step heat treatment is performed at 550 ° C. for 4 hours. By this heat treatment, a-Si
The silicidation of the nickel 5 added to the surface of the film 3 occurs, and the a-Si film 3 is crystallized using the silicidation as a nucleus to form a crystalline silicon film 3a. It diffuses into the silicon film 3a. The average crystal grain size of the crystalline silicon film 3a formed here is 3 μm to 5 μm.
It is about.

Next, as shown in FIG.
Irradiation promotes the crystallinity of the crystalline silicon film 3a. At this time, a XeCl excimer laser (wavelength 308 nm, pulse width 40 nsec) was used as the laser beam 6. The irradiation conditions of the laser beam are as follows.
00 was heated to ° C. to 450 ° C. (e.g., 400 ° C.), and irradiated with an energy density of 250~450mJ / cm ² (e.g., 350mJ / cm ^2). The beam size is 15 on the surface of the glass substrate 1.
It was molded so as to have a long shape of 0 mm × 1 mm, and was sequentially scanned in a direction perpendicular to the long direction at a step width of 0.05 mm. That is, laser irradiation is performed 20 times in total at an arbitrary point on the crystalline silicon film 3a. By this step, even if minute residual amorphous regions remain in the crystalline silicon film 3a, they are completely crystallized by reflecting the good crystallinity (columnar crystal component) of the crystallized region. . In addition, crystal defects such as dislocations contained in the crystal are further reduced. As a result, a higher quality crystalline silicon film 3a 'can be obtained.

Next, an insulating thin film such as a silicon oxide film or a silicon nitride film is deposited on the crystalline silicon film 3a ',
By performing patterning, a mask 7 as shown in FIG. 2D is formed. In the present embodiment, a silicon oxide film is used as an insulating thin film, TEOS (tetraethoxyorthosilicate) is used as a raw material, and RF plasma
Decomposed and deposited by VD method. The thickness of the mask 7 is 1
The thickness is desirably from 00 nm to 400 nm, and in the present embodiment, the thickness of the silicon oxide film is set to 150 nm. When this state is viewed from above, as shown in FIG. 1A, a part of the crystalline silicon film 3a 'is covered with the mask 7 in an island shape.

Next, in this state, as shown in FIG. 2D, phosphorus 8 is ion-doped over the entire surface of the semiconductor laminate from above. In this case, the doping condition of the phosphorus 8 is as follows: the accelerating voltage is 5 kV to 10 kV, and the dose is 5 ×
10 ¹⁵ cm ^-2 to 1 × 10 ¹⁶ cm ^-2 . By this step, phosphorus 8 is implanted into the exposed crystalline silicon film 3a 'to form a phosphorus-doped crystalline silicon region 3b. On the other hand, the crystalline silicon film 3a 'in the region covered by the mask 7 is not doped with phosphorus 8. In addition, FIG. 1 (b) of the next step following FIG. 1 (a) viewed from above.
In order to clarify the relationship between the crystalline silicon film 3a 'and the phosphorus-doped crystalline silicon region 3b in the region to be a TFT element later and the region covered with the mask 7,
The region 9 to be the active region is shown. Note that the TFT active region 9 to be formed later is completely covered with the mask 7 at this stage.

In this state, a heat treatment is performed at a temperature of 580 ° C. to 700 ° C. for several hours to tens of hours in an inert atmosphere such as a nitrogen atmosphere. In this embodiment, as an example, heat treatment is performed at 600 ° C. for 12 hours. By this heat treatment, the arrow in FIG.
In the direction shown by (A), the phosphorus in the phosphorus-doped crystalline silicon region 3b attracts the nickel 5 diffused into the crystalline silicon film 3a '. As a result, the nickel concentration in the crystalline silicon film 3a 'further decreases. When the actual nickel concentration in the crystalline silicon film 3a 'in that case was measured by secondary ion mass spectrometry (SIMS), it was reduced to a measurement limit level of about 5 × 10 ¹⁶ atoms / cm ³ . Incidentally, the nickel concentration in the crystalline silicon film 3a 'before this step was about 5 × 10 ¹⁷ atoms / cm ³ .
However, in that case, the crystalline silicon film 3a '
If the nickel concentration is 1 × 10 ¹⁸ atoms / cm ³ or more, the concentration cannot be reduced sufficiently even by performing this step.

Next, the silicon oxide film used as the mask 7 is removed by etching. The etching is performed by wet etching using 1:10 buffered hydrofluoric acid (BHF), which is sufficiently selective with the underlying silicon film 3.

Thereafter, unnecessary portions of the silicon film 3 are removed to perform element isolation. That is, by this step, in an arrangement as shown in FIG. 1B, at least the crystalline silicon film 3a 'is formed into an island-shaped crystalline silicon film which will later become an active region (source / drain region and channel region) of the TFT. 9 are formed, and the state shown in FIGS. 1C and 3E is obtained.

Next, a thickness of 20 nm to 150 nm (here, 10 nm) is covered so as to cover the crystalline silicon film 9 serving as the active region.
A silicon oxide film (0 nm) is formed as the gate insulating film 10. In order to form the silicon oxide film, here, the TEO is used.
S as raw material, substrate temperature 150 ℃ -600 ℃ with oxygen
(Preferably 300 ° C. to 450 ° C.) and RF plasma CV
Decomposition and deposition were performed by Method D. Alternatively, the above TEOS
Substrate temperature is reduced to 350 ° C. to 600 ° C. by a low pressure CVD method or a normal pressure CVD method together with ozone gas.
(Preferably 400 ° C. to 550 ° C.). After the formation of the gate insulating film 10, in order to improve the bulk characteristics of the gate insulating film 10 itself and the interface characteristics between the crystalline silicon film and the gate insulating film, the gate insulating film 10 is subjected to an inert gas atmosphere.
Anneal at 0 ° C. to 600 ° C. for 1 hour to 4 hours.

Subsequently, by the sputtering method,
An aluminum film having a thickness of 400 nm to 800 nm (for example, 600 nm) is formed. Then, the gate electrode 11 is formed by patterning the aluminum film. Further, the surface of the aluminum electrode is anodized to form an oxide layer 12 on the surface. This state corresponds to FIG. The gate electrode 11 also constitutes a gate bus line 22 at the same time in plan view. When this state is viewed in plan view, FIG.
It is in the state as shown in. The anodization is performed in an ethylene glycol solution containing tartaric acid at 1% to 5%, and the voltage is first increased to 220 V at a constant current, and the state is maintained for one hour to complete the process. The thickness of the obtained oxide layer 12 is 200 nm. Since the oxide layer 12 has a thickness to form an offset gate region in a later ion doping process, the length of the offset gate region can be determined in the anodic oxidation process.

Next, an impurity (phosphorus) is implanted into the active region by ion doping using the gate electrode 11 and the oxide layer 12 around the gate electrode 11 as a mask. Phosphine (PH ₃ ) is used as the doping gas, the acceleration voltage is 60 kV to 90 kV (for example, 80 kV), and the dose is 1 × 1.
0 ¹⁵ cm ⁻² to 8 × 10 ¹⁵ cm ⁻² (for example, 2 × 10 ¹⁵ cm ⁻² ). By this step, the region 13 and the region 14 into which impurities are implanted later become source / drain regions of the TFT, and the region 15 which is masked by the gate electrode 11 and the oxide layer 12 therearound and into which the impurity is not implanted is later formed by TF
It becomes a T channel region.

Then, as shown in FIG. 3 (f), annealing is performed by irradiating a laser beam 16 to activate the ion-implanted impurities, and at the same time, the portions where the crystallinity is deteriorated in the above-described impurity introducing step. To improve the crystallinity of At that time, a XeCl excimer laser (wavelength 30) was used as a laser.
8 nm, pulse width 40 nsec) and energy density 15
0 to 400 mJ / cm ² (preferably 200 to 250 mJ / cm ² )
Irradiation. The sheet resistance of the N-type impurity (phosphorus) regions 13 and 14 thus formed is 200 Ω / □ to 600 Ω /
□.

Subsequently, as shown in FIG.
An interlayer insulating film 17 such as a silicon oxide film or a silicon nitride film having a thickness of about 0 nm is formed. When using the silicon oxide film, TEOS is used as a raw material, and the above-mentioned plasma CVD method of TEOS and oxygen, or a decompression CV of ozone is used.
When formed by the method D or the normal pressure CVD method, a good interlayer insulating film having excellent step coverage can be obtained. Also, SiH ₄ and N
If a silicon nitride film formed by plasma CVD using H ₃ as a source gas is used, hydrogen atoms are supplied to the interface between the active region and the gate insulating film to reduce dangling bonds that degrade TFT characteristics. There is.

Next, a contact hole is formed in the interlayer insulating film 17 and the source electrode / wiring 1 of the TFT is made of a metal material (for example, a two-layer film of titanium nitride and aluminum).
8 is formed. The titanium nitride film is provided as a barrier film for preventing aluminum from diffusing into the semiconductor layer. Since the TFT 20 is an element for switching a pixel electrode, the other drain electrode is provided with a pixel electrode 19 made of a transparent conductive film such as ITO (indium tin oxide). That is, in FIG.
A video signal is supplied via the source bus line 21 and the source electrode / wiring 18, and necessary charges are written to the pixel electrodes 19 based on the gate signals from the gate bus line 24 and the gate electrode 11. Finally, annealing is performed at 350 ° C. for 1 hour in a hydrogen atmosphere of 1 atm, and the TFT shown in FIG. 1 (e) and FIG.
Complete 20. Further, if necessary, the TFT 20
For the purpose of protecting the TFT, a protective film made of a silicon nitride film or the like may be provided on the TFT 20.

The TFT manufactured according to the present embodiment is
Despite the extremely high performance of the field effect mobility of about 150 cm ² / Vs and the dark value voltage of about 2 V, the characteristic variation in the substrate is about 10% in the field effect mobility and about 10% in the threshold voltage. The result was very good, about ± 0.2 V (result of measuring 30 points in the substrate using a size of 400 mm × 320 mm as the substrate). On the other hand, when prepared by the conventional method, the variation in nickel concentration in the substrate is large, as a result, the crystallinity varies, and the variation in the field effect mobility is as large as about 50% of the soil. Also 2 ± 0.5V ~
It greatly varies in the range of 2 ± 1.0V.

Therefore, according to the present embodiment, it can be seen that there is a great effect particularly on the improvement in the characteristic variation of the TFT. Further, even if a durability test is performed by repeated measurement or bias or temperature stress, almost no deterioration in TFT characteristics is observed, and the reliability is extremely high as compared with the conventional TFT. Also,
The increase and variation of the leakage current in the TFT off region where the catalytic element is particularly problematic can be reduced to about several pA, which is the same as when no catalytic element is used, without any abnormal point, and the production yield can be greatly improved. it can.

Furthermore, when an active matrix substrate for a liquid crystal display manufactured according to the present embodiment was actually evaluated for lighting, display unevenness was smaller than that manufactured by a conventional method, and pixel defects due to TFT leak were extremely small. It was possible to obtain a high-quality liquid crystal panel with a low contrast and a high contrast ratio.

As described above, in the present embodiment,
A silicon oxide 2 and an a-Si film 3 are formed on a glass substrate 1. Then, a thin oxide film 4 is formed on the surface of the a-Si film 3, and nickel 5 as a catalytic element is added to the a-Si film 3 through the thin oxide film 4 by 4 × 10 ¹³ atoms / cm. Introduce at a concentration of about cm ² .
Then, the thin oxide film 4 in which a large amount of nickel 5 exists
Is removed, and a heat treatment is performed to form silicide of nickel 5 in the a-Si film 3 and a-Si
The crystallization of the film 3 is performed. Further, the crystallization is promoted by irradiating a laser beam 6 to obtain a high-quality crystalline silicon film 3a '. Then, a mask 7 is formed in a region including a region to be the active region 9, and a heat treatment is performed after ion doping with phosphorus 8, and nickel 5 diffused in the crystalline silicon film 3 a ′ is diffused in the phosphorus-doped crystalline silicon region 3 b. Attraction. Thus, the nickel concentration of the crystalline silicon film 3a 'is further reduced. Thereafter, the active (channel) region of the semiconductor device is formed using the obtained crystalline silicon film 3a 'having a low nickel concentration.

As described above, in this embodiment, nickel 5 is introduced into the a-Si film 3 through the thin oxide film 4 and
After removing the thin oxide film 4 in which a large amount of nickel 5 is present, the crystal growth of the a-Si film 3 is performed. Therefore, a large amount is not introduced into the a-Si film 3 by the diffusion of the nickel 5 on the thin oxide film 4 and in the thin oxide film 4. As a result, only a small amount of nickel 5 introduced through the thin oxide film 4 remains in the a-Si film 3, and the introduction of nickel 5 is reduced to an extremely low power DC.
Combined with sputtering, a-Si
It is possible to control a very small amount of the nickel 5 introduced into the film 3.

That is, by applying this embodiment, the variation in the concentration of nickel 5 on the surface of the a-Si film 3 before the heat treatment for crystallization is reduced by 320 mm ×
On the large glass substrate 1 of 400 mm, it can be set to about ± 10%, and a very good result can be obtained as compared with the conventional spin coating method of about ± 40%. Further, the concentration of nickel 5 at that time can be controlled at an extremely low concentration which is almost the same as that in the case of the spin coating method.

Further, when a semiconductor device having a plurality of thin film transistors on a substrate was manufactured based on the present embodiment, a semiconductor device having very high performance, small characteristic variation between elements, and high reliability was obtained. Can be obtained. In addition, the manufacturing yield in each manufacturing process at that time can be significantly improved.

The TFT manufacturing process according to the present embodiment is directed to a pixel electrode on an active matrix substrate. However, the method of manufacturing the semiconductor device can be easily applied to a thin film integrated circuit or the like.
A contact hole may be formed also on the gate electrode 11 and a necessary wiring may be provided.

<Second Embodiment> In this embodiment, an N-type TFT and a P-type TFT which form a peripheral driving circuit of an active matrix type liquid crystal display device and a general thin film integrated circuit are used.
A case in which the present invention is applied to a step of manufacturing a TFT circuit having a complementary metal oxide semiconductor (CMOS) structure on a quartz glass substrate, in which a type TFT and a complementary TFT are configured, will be described.

FIG. 4 is a plan view for explaining the TFT manufacturing method according to the present embodiment. 5 and 6 are cross-sectional views showing a manufacturing process corresponding to the cross section taken along the line BB 'in FIG. 4, and the TFs are shown in order from FIG. 5 (a) to FIG. 6 (h).
The manufacturing process of T proceeds.

First, the surface of the quartz glass substrate 31 is washed with low-concentration hydrofluoric acid, and then, on the quartz glass substrate 31 by a low pressure CVD method or a plasma CVD method.
Intrinsic (I-type) a having a thickness of 40 nm to 100 nm (for example, 55 nm)
-Forming the Si film 32;

Next, an insulating thin film such as a silicon oxide film or a silicon nitride film is deposited on the a-Si film 32 and patterned to form a mask 33. The mask 33 in the present embodiment is formed using a silicon oxide film,
Is decomposed by RF plasma CVD together with oxygen.
This was done by depositing. The thickness of the mask 33 is 1
The thickness is desirably from 00 nm to 400 nm, and in the present embodiment, the thickness of the silicon oxide film is set to 150 nm. The a-Si film 32 is exposed in a slit shape in the through-hole region 34 of the mask 33. That is, FIG.
When viewed from above, as shown in FIG. 4, the a-Si film 32 is exposed in the region 34, and the other portions are covered by the mask 33.

After forming the mask 33, the region 3
In 4, the surface of the a-Si film 32 exposed in a slit shape is thinly oxidized to form a thin oxide film 35. This thin oxide film 35 is formed by UV (ultraviolet) in an oxygen atmosphere.
This is performed by light irradiation. Specifically, the semiconductor laminated substrate is 1
The surface of the semiconductor laminated substrate was heated to 00 ° C. to 200 ° C. and irradiated with UV light using a UV lamp in the atmosphere (oxygen partial pressure: 20%). The irradiation time is about 5 minutes, and even if the treatment is continued for a longer time, the oxide film thickness is substantially saturated. The thickness of the thin oxide film 35 thus obtained is about 20 ° to 30 °.

Then, a very small amount of nickel 36 is added from above. The addition of a small amount of nickel 36 is performed by DC sputtering using a target of pure nickel (99.9% or more). Specifically, if the DC power is 100
At an extremely low power of about W,
The sputtering process is performed by increasing the pressure to 00 mm / min. Argon was used as a sputtering gas, and the gas pressure during sputtering on a pure nickel target was 10
By raising it to Pa or more, it becomes possible to perform ultra-low concentration sputtering of nickel.

Although the nickel 36 thus sputtered is represented as a thin film in FIG. 5 (a), it is actually in a state of a monoatomic layer or less, and is very small. It is not a state that can be called a membrane. Specifically, when sputtering was performed under the conditions of a DC power of 100 W and an argon gas pressure of 18 Pa, the nickel concentration on the surface of the semiconductor laminate (the mask 33 and the thin oxide film 35 / a-Si32) was 2 × 10 ¹⁴ It was about atoms / cm ² (TRXRF measurement value). In this case, in the region 34 where the a-Si 32 is exposed, the sputtered nickel 3
6 is mostly present on the surface of the thin film oxide film 35 or in the thin film oxide film 35, but there is also a portion 6 which has entered the surface of the lower a-Si film 32 by sputtering. That is, at this stage, the state is schematically as shown in FIG.

Next, as shown in FIG. 5B, the thin oxide film 35 is removed. For removing the thin oxide film 35, hydrofluoric acid having a sufficient etching selectivity with a-Si and nickel was used. However, unlike the first embodiment, since the mask 33 made of a silicon oxide film exists, the mask 33 disappears at the same time if excessive etching is performed. Therefore, it is desirable to perform etching so that only the thin oxide film 35 in the region 34 is completely removed and the mask 33 is reduced to a thickness that does not cause a problem. Specifically, the treatment was performed using hydrofluoric acid having a low concentration of about 1% for about 30 seconds. The film thickness of the mask 33 is originally 1500 °, and the film reduction by this process is 50 °, which is a level that does not cause any problem.

In this step, a large amount of nickel 36 existing on the surface of the thin oxide film 35 or in the thin oxide film 35 is lifted off together with the thin oxide film 35 and removed. At the same time, since the mask 33 is also a silicon oxide film, its surface is etched off,
6 is also lifted off and removed. Then, as shown in FIG. 5B, only the region 34 on the semiconductor laminate is
Only a portion of the nickel 36 reached by sputtering on the surface of the a-Si film 32 exists,
There is no nickel at all (on the mask 33). At this stage, when the nickel concentration on the surface of the a-Si 32 exposed to the region 34 was further measured by the TRXRF method, it was about 2 × 10 ¹³ atoms / cm ^2, which was about The density can be reduced by one digit. Further, when the uniformity of the nickel concentration in the substrate at this stage is examined in a substrate of 320 mm × 400 mm square, it is about ± 10%, which is very good.

Further, under an inert atmosphere in the state shown in FIG.
(For example, under a nitrogen atmosphere) at a heating temperature of 530 ° C. to 600 ° C.
(For example, at 580 ° C.) for 11 hours for crystallization. At this time, in the region 34, a small amount of nickel 36 existing on the surface of the a-Si
Crystallization of the film 32 occurs, and a crystalline silicon film 32a is formed as shown in FIG. And then,
In the peripheral region of the region 34, as shown by an arrow (B), crystal growth is performed in a lateral direction (a direction parallel to the substrate) from the region 34, and a crystalline silicon film 32b formed by lateral crystal growth is formed. . Other regions remain as amorphous silicon film regions 32c. When another TFT is formed beside the TFT on the layout, the amorphous silicon film region 32c becomes a lateral growth region from an adjacent pattern,
The boundary is formed outside the element region.

Here, in the case where nickel is introduced by spin coating as in the conventional method of forming a crystalline silicon film, nickel is also present on the mask. Nickel diffused downward and reached the a-Si film in the region to be laterally grown, destabilizing the crystal growth and becoming one of the factors that caused the crystallinity of the laterally grown region to vary. .

On the other hand, in the present embodiment,
Since the nickel 36 on the mask 33 has been removed in the previous step, crystal growth is performed only by the nickel 36 introduced into the region 34, and the growth state is stabilized. Nickel concentration in the lateral crystal grown crystalline silicon film 32b is about ^{2 × 10 17 atoms / cm 3} , the crystalline silicon film 32a was grown by adding directly nickel
The nickel concentration therein was about 1 × 10 ¹⁸ atoms / cm ³ . In the above crystal growth, the distance of crystal growth in the direction parallel to the substrate indicated by the arrow (B) is about 130 μm. FIG. 4 shows this state as viewed from above. In FIG. 4, in order to clarify the relationship between the crystalline silicon film 32 a into which nickel is directly introduced and the crystalline silicon film 32 b grown laterally in the region 34, the TFT will be described later. The region 38 serving as an active region is also shown. At this stage, a region 38 which will be a TFT active region is completely covered by the mask 33 at this stage.

Next, in this state, as shown in FIG. 5D, phosphorus 37 is ion-doped over the entire surface of the semiconductor laminate from above. That is, the mask 33 used for selective introduction of nickel is used as it is as a mask for ion doping. In this case, the doping condition of the phosphorus 37 is such that the acceleration voltage is 5 kV to 10 kV, and the dose is 5 × 10 ¹⁵ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² . By this step, the crystalline silicon film 3 exposed in the region 34
Phosphorus 37 is implanted into 2a to form phosphorus-doped crystalline silicon region 32d. Note that the crystalline silicon film 32b in the lateral crystal growth region covered with the mask 33 is not doped with phosphorus.

In this state, a heat treatment is performed at a temperature of 580 ° C. to 650 ° C. for several hours to tens of hours in an inert atmosphere such as a nitrogen atmosphere. In the present embodiment, as an example, processing was performed at 600 ° C. for 12 hours. In this heat treatment, the phosphorus in the phosphorus-doped crystalline silicon region 32d draws the nickel 36 diffused in the crystalline silicon film 32b in the direction shown by the arrow (C). That is, it is returned to the original introduction area 34. As a result, the nickel concentration in the crystalline silicon film 32b is significantly reduced. Crystalline silicon film 32 in that case
When the nickel concentration in b was measured by SIMS, it was reduced to about 5 × 10 ¹⁶ atoms / cm ³ .

Next, the silicon oxide film used as the mask 33 is removed by etching. As an etchant,
The etching is performed by wet etching using 1:10 buffered hydrofluoric acid (BHF) having sufficient selectivity with the lower silicon film 32.

Thereafter, as shown in FIG.
The crystalline silicon film 32b in the regions 38n and 38p to be the active regions (element regions) of the FT is left, and the other silicon films are removed by etching to perform element isolation. The etching in that case is performed by RIE (reactive ion etching) using RF plasma using a mixed gas of BCl ₃ and Cl ₂ . As the etching conditions, the flow rate of BCl ₃ was set to 15
sccm, the flow rate of Cl ₂ and 70 sccm, the pressure under a reduced pressure of about 8 mTorr, performed by multiplying the RF power of 1300 W. By this etching process, the phosphorus-doped crystalline silicon region 32d in the region 34 where a large amount of nickel 36 exists is formed.
Also, since the nickel 36 is etched together with the silicon film, a clean substrate surface having no etching residue can be obtained, and further fine processing can be performed as compared with the case where wet etching is used.

Thus, the active region (source / source) of the TFT is later formed.
The island-shaped crystalline silicon films 38n and 38p to be the drain regions and the channel regions are formed, and the state shown in FIG. 6E is obtained. That is, in this step, at least the region of the laterally grown crystalline silicon film 32b is used in the arrangement shown in FIG. 4 to form an island-like crystal which will later become the active region (source / drain region and channel region) of the TFT. The silicon films 38n and 38p are formed.

Next, as shown in FIG. 6F, the crystalline silicon films 38n and 38p serving as the active regions are covered with
A silicon oxide film 39 having a thickness of 60 nm is formed as a gate insulating film. In the present embodiment, a silicon oxide film 39 is formed at a temperature of 850 ° C. by a low pressure CVD method using SiH ₄ gas and N ₂ O gas as raw materials. This is a so-called HTO film.

Next, in such a state, the crystalline silicon films 38n and 38p are subjected to a heat treatment in an oxidizing atmosphere. The atmosphere is an oxidizing atmosphere of oxygen, water vapor, HCl, or the like. In this embodiment, the atmosphere is an oxygen atmosphere of 1 atm. The temperature is preferably 850 ° C. to 1100 ° C., and in this embodiment, the temperature was 950 ° C. By performing annealing for 2 hours and 30 minutes under the above-described conditions, oxygen diffuses and moves in the silicon oxide film 39, and the surfaces of the underlying island-like silicon films 38n and 38p are oxidized to about 50n.
m silicon oxide films 40n and 40p are formed.

As a result, the thickness of the silicon films 38n and 38p is reduced from 55 nm at the initial stage to 30 nm. Also, TFT
The gate insulating film is composed of a silicon oxide film 39 formed by CVD and a silicon oxide film 40 formed by thermal oxidation of the silicon film 38, and has a total film thickness of 110 nm. Further, the channel interface is composed of the silicon film 38 in the active region and the silicon oxide film 40 obtained by oxidizing the silicon film 38, so that good interface characteristics can be obtained. Further, the island-like silicon film 38 is formed by the oxidation process.
The dangling bonds in the n, 38p film are greatly reduced, and the crystallinity is greatly improved. As a result, the active regions 38n 'and 38p' of the high-quality crystalline silicon film thinned to 30 nm can be obtained.

Subsequently, as shown in FIG. 6G, aluminum (including 0.1% to 2% silicon) having a thickness of 400 nm to 800 nm (for example, 500 nm) is formed by a sputtering method. Patterning,
Gate electrodes 41n and 41p are formed.

Next, by the ion doping method, using the gate electrodes 41n and 41p as a mask, the active regions 38n ',
Impurities (phosphorus and boron) are implanted into 38p '. In that case, phosphine (PH ₃ ) and diborane (B ₂ H ₆ ) are used as doping gases. The acceleration voltage is 60 kV to 90 kV (for example, 80 kV) in the former case, and 40 kV to 80 kV (for example, 65 kV) in the latter case, and the dose is 1 × 10 ¹⁵ cm ⁻² to 8 × 10 ¹⁵ cm ^−2. (For example, phosphorus is 2 × 10 ¹⁵ cm ⁻² and boron is 5 × 10 ¹⁵ cm ⁻² ). By this step, the regions which are masked by the gate electrodes 41n and 41p and into which impurities are not implanted will later become the channel regions 42n and 42p of the TFT. At the time of the above doping, each element is selectively doped by covering a region where doping is unnecessary with a photoresist. As a result, N-type impurity regions 43n and 44n and P-type impurity regions 43p and 44p are formed, and an N-channel TFT and a P-channel TFT can be formed as shown in FIG.

Thereafter, as shown in FIG. 6G, annealing is performed by irradiating a laser beam 45 to activate the ion-implanted impurities. As a laser beam 45, a XeCl excimer laser (wavelength: 308 nm, pulse width: 40 nsec) was used, and 20 shots were irradiated at one place at an energy density of 250 mJ / cm ² .

Subsequently, as shown in FIG.
A 0 nm silicon oxide film is formed by a plasma CVD method to form an interlayer insulating film 46. Then, the interlayer insulating film 46
A contact hole is formed in the TFT electrode using a metal material (for example, a two-layer film of titanium nitride and aluminum).
Wirings 47, 48 and 49 are formed. Finally, annealing is performed at 350 ° C. for 1 hour in a hydrogen atmosphere at 1 atm, so that an N-channel TFT 50 and a P-channel TFT
51 is completed. Further, if necessary, a TFT5
For the purpose of protecting 0,51, a protective film made of a silicon nitride film or the like may be provided on the TFTs 50,51.

[0102] In the CMOS structure TFT manufactured in accordance with this embodiment, the field effect mobility of each TFT, in N-type ^{TFT50 210cm 2 / Vs~250cm 2 / Vs} ,
In P-type TFT51 high as 120cm ² / Vs~150cm ² / Vs, the threshold voltage is about 1V at N-type TFT 50, P-type TFT
51 showed very good characteristics of about -1.5 V. Further, the characteristic variation, which has been a problem when a conventional catalytic element is used, is reduced to about ± 10% in field effect mobility and about ± 0.2 V in threshold voltage (at 30 points in a 400 mm × 320 mm size substrate). (Measurement result), and stable circuit characteristics were shown.

As described above, in the present embodiment,
A-Si film 32 is formed on a quartz glass substrate 31;
A mask 33 is formed on the Si film 32. The a-Si exposed from the through-hole region 34 of the mask 33
A thin oxide film 35 is formed on the surface of the film 32. Nickel 36 as a catalyst element is applied to the a-Si film 32 through the thin oxide film 35 by 2 × by DC sputtering with extremely low power.
It is introduced at a concentration of about 10 ¹⁴ atoms / cm ² . Then, the thin oxide film 35 on which a large amount of nickel 36 is present is removed by etching, and at the same time, the nickel 36 on the mask 33 is lifted off. After that, a heat treatment is applied to the a-Si film 32 with the nickel 36 as a nucleus.
The Si film 32 is crystallized. As a result, a crystalline silicon film 32a is formed in the through-hole region 34, and subsequently, a crystal is grown in the lateral direction from the region 34 to form a crystalline silicon film 32b which has grown in the lateral direction. Then, heat treatment is performed after the ion doping of the phosphorus 37, and the nickel 36 diffused in the crystalline silicon film 32b is drawn into the phosphorus-doped crystalline silicon region 32d. Thus, the nickel concentration of the crystalline silicon film 32b is significantly reduced. Thereafter, the CMOS is formed using the crystalline silicon films 32b having a low nickel concentration obtained on both sides of the region 34.
It forms the active (channel) region of the structure.

As described above, according to the present embodiment, a very small amount of nickel 36 introduced into the a-Si film 32 can be controlled as in the first embodiment.

Further, the nickel a introduced with a 36
The crystallization of the Si film 32 is performed laterally from the introduction region 34 to its peripheral region. Therefore, inside the lateral crystal growth region, columnar crystals whose growth directions are substantially aligned in one direction are tied together, and as in the first embodiment,
A crystalline silicon film 3 having higher crystallinity than when nickel 5 is directly introduced and crystal nuclei are randomly generated.
2b can be obtained. Also, the lateral growth is constant and stable. Therefore, by using the crystalline silicon film 32b in the lateral crystal growth region for the channel region of the semiconductor device, the performance of the semiconductor device can be improved.

Furthermore, it is possible to solve all of the uneven growth at the mask step portion for selective introduction and the poor growth due to dust, which have been problems in the conventional spin coating, and the manufacturing yield can be greatly improved.

As a method for introducing the catalyst element (nickel 5, 36) in each of the above-described embodiments, as described above, the sputtering method using the target containing the catalyst element is used to form a film on the thin oxide films 4, 35. Is most suitable. That is, a catalyst element is deposited on the thin oxide films 4 and 35 by sputtering. In this case, some catalyst elements pass through the thin oxide films 4 and 35 and reach the a-Si films 3 and 32. . In the sputtering method, as compared with the CVD method and the vapor deposition method, deposition atoms penetrate to a certain depth, as can be seen from the principle thereof. Therefore, it can be said that the sputtering method is a very convenient method for introducing the catalyst element used in each embodiment.

The sputtering method is originally a deposition method with excellent uniformity, and the distribution of the catalytic element in the semiconductor laminate is satisfactory. Incidentally, when the spin coating method is used as a method for introducing the catalyst element in each of the above embodiments, all the catalyst elements are completely removed by the subsequent thin film oxide film 4, 35 removal step, and the a-Si film 3 is removed. , 3
Nothing remains in 2. Therefore, no crystal growth occurs.
That is, the spin coating method is an unstable addition method such that all the added catalyst elements are removed even by pure water washing after coating.

In each of the above embodiments, when the amount of the catalytic element to be sputtered is large and the deposited film of the catalytic element is completely formed, it is necessary to remove the catalytic element film before removing the thin oxide films 4, 35. Become. However, experiments show that the amount of deposition can be controlled to the level of a single atom by sputtering conditions (still too much if direct catalytic element introduction is performed). In the case of the level, the catalyst element on or in the thin oxide films 4, 35 can be lifted off only by removing the thin oxide films 4, 35.

In each of the above embodiments, the amount of the catalytic element introduced into the a-Si films 3 and 32 is controlled by controlling the sputtering power during the sputtering. As a control factor in that case, DC power is used in the case of DC sputtering. In the sputtering method, in a low power region, the depth of deposition atoms implanted into a film changes depending on power. Therefore, utilizing this phenomenon, a
The amount of the catalyst element entering the Si films 3, 32 can be easily controlled.

In each of the above embodiments, the thin oxide films 4, 3 formed on the surfaces of the a-Si films 3, 32 are described.
A thickness of 5 is very important. The amount of the catalytic element introduced into the a-Si films 3 and 32 can be controlled by either the catalyst element implantation depth by the sputtering power or the thickness of the thin oxide films 4 and 35 as parameters. However, it is difficult to control the thickness of the thin oxide films 4 and 35 in view of the uniformity and stability in the plane, and the thickness of the thin oxide films 4 and 35 is always kept constant. It is better to control the amount introduced.

Therefore, it is necessary that the thin oxide films 4 and 35 have a constant thickness and have excellent uniformity. For this purpose, it is most preferable that the surface oxidation step of the a-Si films 3 and 32 be performed in such a manner that the oxide film thickness is saturated with respect to the processing time. In other words, the formation process of the thin oxide films 4 and 35 is not a method that can be oxidized without limitation by extending the deposition time or processing time such as CVD.
By using a method in which the oxide film thickness is saturated with respect to the processing time and performing the oxidation treatment until the saturation state, the oxide film thickness can be always kept constant within the substrate and between the substrates. As a result, the control of the introduction amount of the catalyst element becomes stable,
The precision is improved, and the uniformity of the amount of the catalyst element introduced can be further improved. However, in this case, the oxidation temperature must be lower than the temperature at which crystallization of the a-Si films 3 and 32 starts.

As a specific method for thin-film oxidation of the surfaces of the a-Si films 3, 32, in the first embodiment, a liquid comprising at least one of sulfuric acid, hydrogen peroxide, ozone water and the like is used. Is performed by immersing the surface of the a-Si film 3 in the first step. According to this method, since the reaction is performed only on the active surface of the a-Si film 3, the oxidation proceeds to form an oxide film, and the oxidation reaction also decreases. As a result, the oxide film thickness is saturated with respect to the processing time,
By performing the treatment for a certain period of time or more, a thin oxide film 4 of about 20 ° to 40 ° can be stably obtained. Further, the uniformity of the oxide film thickness in the substrate is also satisfactory. Further, since a liquid is used, a cleaning effect can be expected at the same time, and particles such as dust adhering to the surface of the a-Si film 3 can be greatly reduced.

Further, in the second embodiment,
As a method of forming the thin oxide film 35, the surface of the a-Si film 32 is irradiated with UV light in an oxygen atmosphere.
Also in this method, the active surface reaction of the a-Si film 32 is used, so that the oxide film thickness is saturated as oxidation proceeds. Therefore, similar to the above-described method of immersion in a liquid, a treatment for a certain period
An oxide film thickness of about {40} is stably obtained, and the uniformity of the oxide film thickness within the substrate is also good. This method has a higher barrier effect because the oxide film to be formed is denser than the above-described method of immersion in a liquid, and further limits the implantation of a catalytic element into the a-Si film 32 in sputtering. Can be. That is, the amount of the catalyst element introduced into the a-Si film 32 can be controlled to be lower.

In each of the above embodiments, as described above, the surfaces of the a-Si films 3 and 32 are thin-film oxidized, and the catalyst element is added, and then the heat treatment is performed. Another important point is that the thin oxide films 4, 35 on the surfaces of the a-Si films 3, 32 are removed. Here, in the step of removing the thin oxide films 4, 35, an etchant is used in which the catalytic element and the a-Si films 3, 32 are not etched, and only the thin oxide films 4, 35 are selectively etched. It must be done using That is, if the catalytic element introduced into the a-Si films 3 and 32 together with the thin oxide films 4 and 35 is removed, the desired crystallization does not occur in the a-Si films 3 and 32. is there. Also,
Even when the a-Si films 3 and 32 are etched, the introduced catalytic element is removed at the same time. Further, in each of the above-described embodiments, the thickness of the thin oxide films 4 and 35 on the surfaces of the a-Si films 3 and 32 and the depth of implantation of the catalyst elements by sputtering determine the conductivity of the catalyst elements to the a-Si films 3 and 32. Since a large amount is controlled, if the surfaces of the a-Si films 3 and 32 are etched in the step of removing the thin oxide films 4 and 35, the amount of introduction cannot be sufficiently controlled. Therefore, in particular, a sufficient etching selectivity is required between the thin oxide films 4, 35 and the catalyst element and the a-Si films 3, 32. Specifically, it is most preferable to use hydrofluoric acid as such an etchant. Hydrofluoric acid satisfies all of the above conditions, has a good track record in semiconductor processes, and has very little contamination of the silicon film. Further, the catalyst element a contained in the thin oxide films 4, 35
-There is no fear of re-adhesion to the surface of the Si film 3, 32.

The types of catalyst elements that can be used in each of the above embodiments include nickel (Ni) 5,
36, cobalt (Co), palladium (Pd), platinum (P
t), copper (Cu), silver (Ag), gold (Au), indium (In), tin (S
n), aluminum (Al), and antimony (Sb) can be used. One or a plurality of elements selected from these elements have an effect of promoting crystallization in a trace amount. Among them, the most remarkable effect can be obtained particularly when nickel 5,36 is used. . For the reason, the following model can be considered.

That is, the catalyst element does not act alone, but acts on the crystal growth by bonding to the silicon atoms in the a-Si films 3 and 32 to form silicide. In other words, the crystal structure in that case acts as a kind of template when the a-Si films 3, 32 are crystallized, and the a-Si films 3, 32
This is a model that promotes crystallization. Ni is two Si
And a silicide of NiSi ₂ are formed. NiSi ₂ has a fluorite-type crystal structure, which is very similar to the diamond structure of single crystal silicon. And N
iSi ₂ has a lattice constant of 5.406 °, which is very close to the lattice constant of 5.430 ° in the diamond structure of crystalline silicon. Therefore, NiSi ₂ is a-
This is the best template for crystallizing the Si films 3 and 32, and it is most preferable to use Ni as the catalyst element in each of the above embodiments.

The amount of the catalytic element introduced into the a-Si films 3 and 32 in each of the above embodiments is not the total amount added by sputtering, but the amount after the removal of the thin oxide films 4 and 35 (before the crystallization treatment). The amount of the catalyst element on the surfaces of the a-Si films 3 and 32 is important. When Ni is used as a catalyst element, the a-Si films 3, 32 after removing the thin oxide films 4, 35 are used.
The nickel concentration on the surface is 1 × 10 ¹² atoms / cm ² to
It is desirable that the concentration be 1 × 10 ¹³ atoms / cm ² . If the amount of Ni added is less than 1 × 10 ¹² atoms / cm ^2, sufficient crystal growth does not occur. 1 × 10 ¹³ at
If oms / cm ² higher than the order region unevenly distributed silicon film as a nickel silicide after crystallization increases,
The characteristics of the semiconductor device are adversely affected. Incidentally, the measurement of the nickel concentration on the surfaces of the a-Si films 3 and 32 requires T
The RXRF method is effective, and the surface concentration defined in each of the above embodiments is also a measured value in the TRXRF method.

However, the above-mentioned concentration value is a case in which nickel is entirely added to the a-Si film 3 as in the first embodiment to grow crystals, and as in the second embodiment, a-
This is different when nickel is selectively added to a part of the Si film 32 and crystal growth is performed in the lateral direction from there. In such a case, the nickel concentration on the surface of the a-Si film 32 after removing the thin oxide film 35 is 1
It is preferably from × 10 ¹³ atoms / cm ² to 1 × 10 ¹⁴ atoms / cm ² . This is because, in the case of the lateral crystal growth, the growth distance is long because the region into which nickel is selectively introduced is grown as a seed region, and more nickel is required for crystal growth. That is, the nickel concentration in the lateral crystal growth region is lower by about one digit in volume concentration than in the introduction region to which nickel is directly added. Therefore, in the case of the lateral growth method by selective introduction of nickel, 1
If the amount of the catalyst element is less than × 10 ¹³ atoms / cm ^2, sufficient crystal growth does not occur. 1 × 10 ¹⁴ at
If it is more than oms / cm ² , the area which is unevenly distributed in the silicon film as nickel silicide after crystallization increases, which adversely affects the characteristics of the semiconductor element.

In each of the above embodiments, the aS
The purpose is to add a small amount of a catalytic element to the i-films 3, 32,
It has been described that a great effect can be obtained by setting the amount of introduction into the a-Si films 3 and 32 within the above range. However, when it is necessary to further reduce the amount of the remaining catalytic element in the active region, it is impossible to reduce the amount of the introduced catalytic element below the above range from the viewpoint of crystal growth, so that another approach is required. In each of the above embodiments, after the catalytic element is used for the crystallization treatment of the a-Si films 3, 32, the crystalline silicon film 3
Most of the catalyst element remaining in a ′, 32b is moved to a region other than the semiconductor element formation region. As a specific method, after the a-Si films 3 and 32 are crystallized, phosphorus 8,37 is ion-doped in at least a region other than a region where a semiconductor element is to be formed, and a heat treatment at about 600 ° C. is performed. By doing so, at least nickel or the like existing in a silicide state becomes phosphorus 8,
37 migrates to the doped region. Therefore, the semiconductor element region may be formed by removing the region where the phosphorus 8, 37 is drawn. In this method, all the nickel diffused in the crystalline silicon films 3a 'and 32b cannot be removed, and a large effect cannot be obtained when the amount of introduced nickel is larger than the above upper limit.
However, if the amount of nickel introduced into the a-Si films 3, 32 is within the above range, the crystalline silicon film 3
The nickel concentration in a ′, 32b can be reduced to the level of its solid solubility limit.

Furthermore, in the first embodiment,
The crystalline silicon film 3a crystallized by the catalyst element
In order to further improve the crystallinity of the semiconductor device and further improve the performance of the semiconductor device, particularly the current driving capability, the a-Si film 3 is crystallized by a heat treatment, and then the crystalline silicon film 3a is irradiated with laser light 6. Process is added. In the second embodiment, a step of performing a heat treatment in an oxidizing atmosphere at a temperature higher than the crystallization temperature is added.

As in the first embodiment, when the crystalline silicon film 3a is irradiated with intense light such as a laser beam 6, the difference in melting point between the crystalline silicon film 3a and the a-Si film 3 is obtained. , Crystal grain boundaries and minute residual amorphous regions (uncrystallized regions)
Will be intensively processed. Since the crystalline silicon film formed by the ordinary solid-phase growth method has a twinned crystal structure, the inside of the crystal grain remains as a twin defect even after intense light irradiation. On the other hand, the crystalline silicon film 3a crystallized by introducing the catalytic element as in the first embodiment is formed of columnar crystals, and the inside thereof is in a single crystal state. Therefore, when the crystal grain boundary portion is treated by intense light irradiation, a high-quality crystalline silicon film 3a 'close to a single-crystal state is obtained over the entire surface of the substrate, and its effectiveness is extremely low from the viewpoint of crystallinity. high. In addition, since laser irradiation is performed on the silicon film that originally has crystallinity, the variation in laser irradiation is greatly reduced, unlike the method of directly performing laser irradiation on the a-Si film 3 for crystallization. And there is no uniformity problem.

Further, as in the second embodiment, when the a-Si film 32 is crystallized by heat treatment and then heat-treated in an oxidizing atmosphere at a temperature higher than the heat treatment temperature, The crystalline silicon films 38n and 38p crystallized by the catalytic element are oxidized at a higher temperature (800 ° C. to 1100 ° C.) than the crystallization temperature. Then, supersaturated Si atoms generated by the oxidizing action are supplied into the crystalline silicon film. Then, the supersaturated Si atoms enter crystal defects (particularly, dangling bonds) in the crystalline silicon films 38n and 38p, thereby eliminating the defects. Thus, the defect density in the crystalline silicon films 38n and 38p crystallized by the catalytic element is greatly reduced, and the mobility is greatly improved.
As a result, the performance of the semiconductor device is dramatically improved.

As described above, according to each of the above-described embodiments, a high-performance semiconductor element having stable characteristics with little characteristic variation can be realized, and a high-performance semiconductor device with a high degree of integration can be obtained by a simple manufacturing process. Can be. In addition, the non-defective product rate can be greatly improved in the manufacturing process, and the cost of the product can be reduced. In particular, in the liquid crystal display device, it is possible to simultaneously improve the switching characteristics of the pixel switching TFT required for the active matrix substrate and the high performance and high integration required for the TFT constituting the peripheral drive circuit unit. . Therefore, it is possible to realize a driver monolithic active matrix substrate in which an active matrix portion and a peripheral drive circuit portion are configured on the same substrate, and it is possible to reduce the size, performance, and cost of the module. is there.

Although the present invention has been specifically described with reference to the two embodiments, the present invention is not limited to the above-described embodiments, and various modifications based on the technical concept of the present invention are possible. It is.

For example, in the above-described two embodiments, the DC sputtering method is used as a method for introducing nickel, but an RF sputtering method using an RF power supply may be used. In that case, RF power is used as a control factor of the amount of catalyst element introduced. Alternatively, the thin oxide films 4, 35 before the nickel addition treatment may be made thicker, and nickel may be introduced into the a-Si film by an ion doping method.
Further, as described above, as the impurity metal element that promotes crystallization, in addition to nickel, cobalt, palladium,
Similar effects can be obtained by using one or more elements selected from platinum, copper, silver, gold, indium, tin, aluminum, and antimony. However, as described above, the most remarkable effect is obtained when nickel is used.

In the second embodiment, as a method of further reducing nickel, a step of introducing phosphorus and performing a heat treatment is added. However, depending on the required characteristics and size of the semiconductor element, the method may be modified. Even if this step is omitted, a considerable reduction in concentration can be achieved, and it is sufficiently applicable.

As means for further promoting the crystallinity of the crystalline silicon film crystallized by nickel,
A heating method using excimer laser irradiation as a pulse laser was used. However, similar processing can be performed with other lasers (for example, a continuous wave Ar laser or the like). Also,
So-called RTA (Rapid Thermal Annealing) (RTP: Rapid) in which a sample is heated to 1000 ° C. to 1200 ° C. (temperature of a silicon monitor) in a short time by using infrared light or a flash lamp instead of laser light to heat the sample. (Also referred to as a thermal process) may be used.

Further, as an application of the present invention, in addition to an active matrix type substrate for a liquid crystal display, for example,
Contact-type image sensor, driver built-in thermal head, driver built-in optical writing element and display element using organic EL (electroluminescence), etc.
A three-dimensional IC or the like is conceivable. In any case, by applying the present invention, high performance such as high speed and high resolution of these elements can be realized. Further, the present invention provides a MOS (metal oxide semiconductor) described in the above embodiment.
The invention can be applied not only to the type transistor but also to a wide range of semiconductor processes including a bipolar transistor and an electrostatic induction transistor using a crystalline semiconductor as an element material.

[0129]

As is apparent from the above description, the method of manufacturing a semiconductor device according to the first aspect of the present invention is to form a thin oxide film by oxidizing the surface of an amorphous silicon film with a thin film, and to pass the non-oxide film through the thin oxide film. After introducing a catalytic element into the crystalline silicon film, removing the thin film oxide film and then performing a heat treatment to crystallize the amorphous silicon film, a channel region of a semiconductor device is obtained using the obtained crystalline silicon film. When the catalyst element is introduced through the thin film oxide film, the thin film oxide film having many catalyst elements introduced on the surface and inside is removed, and the thin film oxide film is contained in the amorphous silicon film. Only a trace amount of the catalyst element introduced through the membrane can be left. Therefore, the amount of the catalyst element to be introduced can be controlled to an extremely small amount necessary for promoting the crystallization of the amorphous silicon film and accurately.

That is, according to the present invention, the amount of the catalyst element remaining in the crystalline silicon film can be minimized, and the reliability and electrical stability of the obtained semiconductor device can be improved.

Further, in the method of manufacturing a semiconductor device according to the second invention, the surface of the amorphous silicon film is thinly oxidized to form a thin oxide film, and a part of the amorphous silicon film is passed through the thin oxide film. The catalyst element is selectively introduced into the amorphous silicon film in parallel with the substrate from a region where the catalyst element is introduced to a peripheral region from a region where the catalyst element is introduced, after removing the thin oxide film. Since the channel region of the semiconductor device is formed using the crystalline silicon film obtained by crystallization, the thin film in which many catalytic elements exist on the surface and inside as in the case of the first invention. By removing the oxide film, the amount of the catalyst element introduced into the amorphous silicon film can be controlled to a very small amount and precisely required to promote crystallization.

Further, since the crystallization of the amorphous silicon film into which the catalyst element has been introduced is performed in parallel with the substrate from the introduction region to the peripheral region, the crystallinity of the lateral crystal growth region is reduced. This is better than the case where the catalyst element is directly introduced and crystal nuclei are randomly generated as in the case of the first invention. Therefore, by using the crystalline silicon film in the lateral crystal growth region for the channel region of the semiconductor device, the performance of the semiconductor device can be improved.

In the method of manufacturing a semiconductor device according to the first and second aspects of the present invention, the catalyst element is introduced through the thin film oxide film by a sputtering method using a target containing the catalyst element. From the top, deposition atoms can be uniformly introduced to a deep position as compared with the above-described CVD method and vapor deposition method. Therefore, a part of the catalyst element can be uniformly introduced to the amorphous silicon film through the thin oxide film.

In the method of manufacturing a semiconductor device according to the first and second aspects of the present invention, if the amount of the catalytic element introduced into the amorphous silicon film is controlled by the sputtering power during the sputtering, The amount of the catalytic element in the crystalline silicon film can be easily and accurately controlled.

Therefore, the variation in the concentration of the catalyst element on the surface of the amorphous silicon film before the crystallization is reduced by 32%.
± 10% on a large glass substrate of 0mm x 400mm
And a very good result can be obtained as compared with a conventional spin coating method of about ± 40%.

In the method of manufacturing a semiconductor device according to the first and second aspects of the present invention, the thin film oxidation of the surface of the amorphous silicon film may be performed at a temperature lower than a temperature at which crystallization of the amorphous silicon film starts. If the thin film oxidation is performed in such a manner that the oxide film thickness is saturated with respect to the processing time, the thin film oxidation is performed until a predetermined time until the saturated state is reached, thereby forming a thin film oxide film in the substrate and between the substrates. The thickness can always be kept constant. Therefore, the introduction amount of the catalyst element can be more stably controlled, and the accuracy can be improved to improve the uniformity.
Can be enhanced.

In the method of manufacturing a semiconductor device according to the first and second aspects of the present invention, the thin film oxidation of the surface of the amorphous silicon film is performed by using at least one of sulfuric acid, hydrogen peroxide and ozone water. By immersing the surface of the amorphous silicon film in a liquid, the thickness of the thin oxide film can be saturated with respect to the processing time by the reaction of only the active surface of the amorphous silicon film. Further, particles and the like adhering to the surface of the amorphous silicon film can be cleaned.

In the method of manufacturing a semiconductor device according to the first and second inventions, the thin film oxidation of the surface of the amorphous silicon film may be performed by applying UV light to the surface of the amorphous silicon film in an oxygen atmosphere. When the irradiation is performed, the thickness of the thin oxide film can be saturated with respect to the processing time by utilizing the active surface reaction of the amorphous silicon film. Further, a denser thin oxide film can be formed as compared with the method of immersing the surface of the amorphous silicon film in the liquid. Therefore, the barrier effect can be enhanced and the amount of the catalytic element introduced into the amorphous silicon film can be controlled to be lower.

In the method of manufacturing a semiconductor device according to the first and second aspects of the present invention, the thin film oxide film is removed by removing the catalyst element and the amorphous silicon film.
If the etching is performed using an etchant that selectively etches only the silicon oxide film, the catalyst element introduced into the amorphous silicon film is removed, or the amorphous silicon film is etched to form the catalyst. Elements can also be prevented from being etched back. Therefore, the desired crystallization can be performed on the amorphous silicon film.

In the method for manufacturing a semiconductor device according to the first and second aspects of the present invention, if at least hydrofluoric acid is used as the etchant, only the thin oxide film can be selectively etched. At this time, the hydrofluoric acid causes very little contamination of the silicon film, and the catalyst element in the thin oxide film does not adhere to the amorphous silicon film again.

Further, in the method of manufacturing a semiconductor device according to the first and second aspects of the present invention, if at least nickel element is used as the catalyst element, the silicide NiSi ₂ formed by nickel element By functioning as the best template, crystallization of the amorphous silicon film can be promoted.

In the method of manufacturing a semiconductor device according to the first aspect of the present invention, the nickel concentration on the surface of the amorphous silicon film after the removal of the thin oxide film is 1 × 10 ¹² atoms / cm ² or more and 1 × 10 ¹² atoms / cm ² or more. When the density is 10 ¹³ atoms / cm ² or less, sufficient crystal growth can be performed on the amorphous silicon film, and a region unevenly distributed as silicide in the crystalline silicon film after crystallization is reduced. Therefore, it is possible to prevent the characteristics of the semiconductor element from being adversely affected.

Further, in the method of manufacturing a semiconductor device according to the second aspect of the present invention, the nickel concentration in the nickel-introduced region on the surface of the amorphous silicon film after the removal of the thin oxide film is reduced to 1%.
When the concentration is at least × 10 ¹³ atoms / cm ^{2 and not} more than 1 × 10 ¹⁴ atoms / cm ² , sufficient crystal growth can be performed on the amorphous silicon film, and the crystal as a silicide after crystallization can be obtained. The region unevenly distributed in the conductive silicon film can be reduced to prevent the characteristics of the semiconductor element from being adversely affected.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing a manufacturing process of a TFT to which a method of manufacturing a semiconductor device according to the present invention is applied.

FIG. 2 is a manufacturing process sectional view corresponding to a section taken along line AA ′ in FIG. 1 (e).

FIG. 3 is a sectional view of the manufacturing process following FIG. 2;

FIG. 4 is a plan view for explaining a method of manufacturing a CMOS-structured TFT to which the method of manufacturing a semiconductor device according to the present invention is applied.

FIG. 5 is a cross-sectional view of a manufacturing step corresponding to a cross section taken along line BB ′ in FIG. 4;

FIG. 6 is a cross-sectional view of the manufacturing process continued from FIG. 5;

[Explanation of symbols]

1: glass substrate, 2: silicon oxide film (underlying film), 3, 3
2 ... a-Si film, 3a, 3a ', 32a ... crystalline silicon film, 3b, 32d ... phosphorus-doped crystalline silicon region, 4,35 ... thin oxide film, 5,36 ...
Nickel, 7,33 ... mask, 8,
37 ... phosphorous, 9,38n, 38p ... TFT active area, 10
... Gate insulating film, 11, 41n, 41p ... Gate electrode, 1
3,14 ... impurity region (source / drain region), 15,4
2n, 42p: channel region, 17, 46: interlayer insulating film, 18: source electrode / wiring, 19: pixel electrode, 20: TFT, 31: quartz glass substrate, 34: through-hole region,
32b: laterally grown crystalline silicon film, 32c: amorphous silicon film region, 39, 40n, 40p: silicon oxide film (gate insulating film), 43n, 44n: N-type impurity region, 43p,
44p: P-type impurity region; 47, 48, 49: electrodes and wiring;
50: N-channel TFT; 51: P-channel TFT.

Continued on front page F-term (reference) 2H092 JA25 JA29 JA33 JA35 JA38 JA39 JA42 JA43 JA44 JA46 JB13 JB23 JB27 JB32 JB33 JB36 JB38 JB51 JB58 JB63 JB69 KA04 KA07 MA05 MA07 MA08 MA14 MA15 MA16 MA18 MA19 MA29 MA27 NA22 NA25 NA27 PA06 RA05 5F052 AA02 AA17 BB07 DA02 FA24 JA01 5F110 BB01 BB10 BB11 CC02 DD02 DD13 EE03 EE34 EE44 FF02 FF30 FF36 GG02 GG13 GG25 GG35 GG45 HJ18 HJ23 HL03 Q04 PPQ35 PP11

Claims (12)

[Claims] A step of forming an amorphous silicon film on a substrate having an insulating surface; a step of forming a thin oxide film by oxidizing the surface of the amorphous silicon film in a thin film; Introducing a catalytic element for promoting crystallization to the amorphous silicon film, removing the thin oxide film, and subjecting the amorphous silicon film to a heat treatment to crystallize the amorphous silicon film. Forming a channel region of a semiconductor device using the crystalline silicon film obtained by the crystallization. 2. A step of forming an amorphous silicon film on a substrate having an insulating surface; a step of forming a thin oxide film by oxidizing the surface of the amorphous silicon film as a thin film; Through a step of selectively introducing a catalyst element that promotes crystallization into a part of the amorphous silicon film; a step of removing the thin film oxide film; and performing a heat treatment to introduce the catalyst element. Crystallizing the amorphous silicon film in parallel with the substrate from the region to the peripheral region, and forming a channel region of a semiconductor device using the crystalline silicon film obtained by the crystallization. A method for manufacturing a semiconductor device, comprising: 3. The method for manufacturing a semiconductor device according to claim 1, wherein the catalyst element is introduced into the amorphous silicon film through the thin oxide film by sputtering using a target containing the catalyst element. A method for manufacturing a semiconductor device, wherein the method is performed by sputtering from a thin oxide film on the thin film. 4. The method for manufacturing a semiconductor device according to claim 3, wherein the amount of a catalyst element introduced into the amorphous silicon film is controlled by controlling a sputtering power during the sputtering. A method for manufacturing a semiconductor device. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the thin film oxidation on the surface of the amorphous silicon film starts crystallization of the amorphous silicon film. A method for manufacturing a semiconductor device, wherein the method is performed at a temperature equal to or lower than a temperature so that an oxide film thickness is saturated with respect to a processing time. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the thin film oxidation on the surface of the amorphous silicon film is performed by converting the thin film of the amorphous silicon film into a liquid comprising at least one of sulfuric acid, hydrogen peroxide and ozone water. A method for manufacturing a semiconductor device, wherein the method is performed by immersing a surface of a crystalline silicon film. 7. The method for manufacturing a semiconductor device according to claim 5, wherein the thin film oxidation of the surface of the amorphous silicon film is performed by irradiating the surface of the amorphous silicon film with ultraviolet light in an oxygen atmosphere. A method for manufacturing a semiconductor device, comprising: 8. The method for manufacturing a semiconductor device according to claim 1, wherein the removing of the thin film oxide film is performed without etching the catalyst element and the amorphous silicon film. A method for manufacturing a semiconductor device, wherein the method is performed by etching using an etchant in which only a silicon film is selectively etched. 9. The method of manufacturing a semiconductor device according to claim 8, wherein at least hydrofluoric acid is used as said etchant. 10. The method for manufacturing a semiconductor device according to claim 1, wherein at least a nickel element is used as the catalyst element. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the thin film oxide film is removed when a catalytic element is introduced through the thin film oxide film to the entire surface of the amorphous silicon film. The nickel concentration on the surface of the amorphous silicon film after and before the above crystallization is 1 × 10
^A method for manufacturing a semiconductor device, wherein the concentration is ¹² atoms / cm ² or more and 1 × 10 ¹³ atoms / cm ² or less. 12. The method for manufacturing a semiconductor device according to claim 10, wherein a catalyst element is selectively introduced into a part of the amorphous silicon film through the thin film oxide film. Is removed and the nickel concentration in the nickel-introduced region on the surface of the amorphous silicon film before the crystallization is 1 × 10 ¹³ atoms / cm ² or more and 1 × 1
A method for manufacturing a semiconductor device, wherein the concentration is equal to or less than 0 ¹⁴ atoms / cm ² .