JP3582766B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using a crystalline silicon film obtained by crystallizing an amorphous silicon film as an active region.
[0002]
[Prior art]
In recent years, high-performance semiconductor elements have been formed on insulating substrates such as glass and insulating films for the realization of large, high-resolution liquid crystal display devices, high-speed, high-resolution contact image sensors, and three-dimensional ICs. Attempts have been made to do so. In general, a thin film silicon semiconductor is used for a semiconductor element used in these apparatuses. Thin-film silicon semiconductors are broadly classified into two types: amorphous silicon semiconductors (a-Si) and crystalline silicon semiconductors.
[0003]
Amorphous silicon semiconductors are most commonly used because they have a low production temperature and can be relatively easily produced by a gas phase method and have high mass productivity. However, since physical properties such as conductivity are inferior to crystalline silicon semiconductors, in order to obtain even higher speed characteristics in the future, it is strongly required to establish a method for manufacturing a semiconductor device made of crystalline silicon semiconductor. Had been. In addition, as a silicon semiconductor having crystallinity, polycrystalline silicon, microcrystalline silicon, amorphous silicon containing a crystalline component, semi-amorphous silicon having an intermediate state between crystalline and amorphous, and the like are known. .
[0004]
The following methods are known as conventional methods for obtaining a thin film silicon semiconductor having such crystallinity.
[0005]
(1) A film having crystallinity is directly formed at the time of film formation.
[0006]
(2) An amorphous semiconductor film is formed and crystallinity is imparted by the energy of laser light.
[0007]
(3) An amorphous semiconductor film is formed and crystallinity is imparted by applying thermal energy.
[0008]
However, in the method (1), crystallization proceeds at the same time as the film formation step. Therefore, it is indispensable to increase the thickness of the silicon film in order to obtain crystalline silicon having a large grain size, and to obtain a film having good semiconductor properties. It is technically difficult to form a film uniformly over the entire surface of the substrate.
[0009]
In the method (2), the crystallization phenomenon in the melt-solidification process is used, so that the grain boundaries are satisfactorily processed in spite of the small grain size, and a high-quality crystalline silicon film is obtained. Taking the excimer laser used as an example, one with sufficient stability has not yet been obtained. Therefore, it is difficult to uniformly process the entire surface of a large-area substrate, and further technical improvement in hardware is desired.
[0010]
In addition, the method (3) is advantageous in terms of uniformity and stability in the substrate as compared with the methods (1) and (2), and is used for an ultra-small high-definition liquid crystal panel using a quartz substrate. ing. However, in this case, after the crystal is grown by heat treatment at 600 ° C. for a long time of about 30 hours, heat treatment for improving the crystallinity at a higher temperature, for example, about 1000 ° C. for several tens minutes to several hours is performed. Is going. That is, there is a problem that the processing time is long and the throughput is low, and the TFT (thin film transistor) has a field effect mobility of 100 cm ² / Vs only.
[0011]
In contrast to these methods, a method of improving the above method (3) to obtain a high-quality crystalline silicon film has been proposed in JP-A-7-94757 and JP-A-9-148245. In these methods, the use of a catalytic element that promotes crystallization of the amorphous silicon film aims at lowering the heating temperature, shortening the treatment time, and improving the crystallinity.
[0012]
Specifically, a small amount of a metal element such as nickel or palladium is introduced into the surface of the amorphous silicon film, and then heating is performed. The mechanism of this low-temperature crystallization is understood from the fact that crystal nucleus generation with a metal element as a nucleus occurs at an early stage, and then the metal element serves as a catalyst to promote crystal growth, and crystallization proceeds rapidly. . In that sense, these metal elements are hereinafter referred to as catalyst elements. Crystalline silicon films grown by the promotion of crystallization by these catalytic elements have a twin structure in one grain of the crystalline silicon film crystallized by the ordinary solid phase growth method. The inside of the grain is composed of a number of columnar crystal networks, and the inside of each columnar crystal is in an almost ideal single crystal state.
[0013]
Further, in the above publication, the catalyst element is selectively introduced into a part of the amorphous silicon film and heated, so that the catalyst element is selectively introduced while leaving the other part in the state of the amorphous silicon film. By crystallizing only the formed region and further extending the heating time, crystal growth is performed in a lateral direction (a direction parallel to the substrate) from the introduction region. Inside this lateral crystal growth region, columnar crystals whose growth directions are almost aligned in one direction are tied together, and the crystallinity is lower than that of the region where the catalytic element is directly introduced and crystal nuclei occur randomly. This is a better area. Therefore, by using the crystalline silicon film in the lateral crystal growth region for the active region of the semiconductor device, the performance of the semiconductor device can be improved.
[0014]
Japanese Patent Application Laid-Open No. 7-94757 discloses that such a high-quality crystalline silicon film is further irradiated with strong light such as laser light in an atmosphere containing a chloride gas or a fluoride gas, and the crystal is further irradiated with the crystal light. High performance semiconductor devices have been manufactured with improved performance. In Japanese Patent Application Laid-Open No. Hei 9-148245, a high-temperature crystalline silicon film is subjected to a second heat treatment at a temperature higher than a crystallization annealing temperature to further improve its crystallinity. Used as
[0015]
[Problems to be solved by the invention]
However, the conventional method of crystallizing a silicon film using a catalytic element has problems with respect to the film quality and impurities of the crystalline silicon film.
[0016]
Regarding the film quality, experiments performed by the present inventors have revealed that each columnar crystal has good crystallinity, but contains crystal defects (dislocations) having a considerably high density as a whole. Therefore, since the active region of the semiconductor device is formed with approximately one crystal orientation, a relatively high mobility can be obtained. On the other hand, since the defect density is high, the threshold voltage and the leak current are hardly reduced.
[0017]
Actually, when a crystalline silicon film crystallized using a catalytic element is used to fabricate an N-channel TFT, the field-effect mobility is 60 cm. ² / Vs ~ 80cm ² / Vs. However, this value is about twice as large as that of a conventional silicon film formed by solid phase growth without using a catalytic element, but is still not a sufficient value in consideration of application to a thin film integrated circuit and the like.
[0018]
Regarding impurities, the catalytic element itself becomes a problem. That is, the catalyst element as described above greatly contributes to the crystallization of the amorphous silicon film, but thereafter is mainly localized at the crystal grain boundaries and remains in the crystalline silicon film. The presence of a large amount of these catalytic elements in the crystalline silicon film constituting the active region (semiconductor element region) of a semiconductor device impairs the reliability and electrical stability of the device using these semiconductors. And, of course, not preferred.
[0019]
In particular, an element such as nickel or palladium that efficiently acts as a catalyst for promoting crystallization of an amorphous silicon film forms an impurity level near the center of a band gap in silicon. Therefore, when a TFT is manufactured using a silicon film crystallized with these catalyst elements, phenomena such as an increase in leak current and a decrease in reliability mainly during a TFT-off operation appear as the effects. That is, in order to improve the crystallinity of the channel region in the TFT element, the catalytic element improves the current drive capability such as the field effect mobility, the on-current, and the on-current rise coefficient (S coefficient). As a price, the off characteristic and the reliability are deteriorated.
[0020]
A method for solving these problems has been proposed in the above-mentioned JP-A-7-94757 and JP-A-9-148245.
[0021]
JP-A-7-94757 discloses that a crystalline silicon film crystallized using a catalytic element is irradiated with strong light such as a laser beam to further improve its crystallinity and to improve the film quality. It is trying to solve the problem that is not.
[0022]
However, in such a case, the problems of uniformity and stability conventionally associated with the laser annealing technique are added. That is, good film quality uniformity, which is a merit of solid-phase crystallization, is impaired, and the intended high-performance semiconductor device cannot be realized.
[0023]
Regarding the problem of the catalytic element, it is stated that laser light irradiation is performed in an atmosphere containing a chloride gas or a fluoride gas to chlorinate or fluoridate the catalyst element to remove gettering. However, as a result of actual experiments by the present inventors using the same method, almost no gettering effect is obtained in such instantaneous laser annealing, and the concentration of the catalytic element in the silicon film cannot be significantly reduced. It was confirmed that.
[0024]
On the other hand, Japanese Patent Application Laid-Open No. 9-148245 discloses a method of improving the crystallinity by performing a heat treatment at a higher temperature after crystallization annealing using a catalytic element. From the experiments of the present inventors, it has been confirmed that a very high quality crystalline silicon film can be obtained by this method. ² Ultra-high performance TFT elements exceeding / Vs are manufactured. In addition, by performing the second heat treatment in an oxidizing atmosphere such as HCl, the gettering and removal of the catalyst element in the silicon film can be efficiently performed in addition to the improvement in crystallinity. Therefore, this method is very effective as a method for manufacturing a high performance thin film semiconductor device.
[0025]
However, in this method, a new problem has arisen in mass-producing TFTs. A new problem is the generation of microscopic holes in the silicon film. Actually, as shown in the photograph of FIG. 7, a hole 509 is generated in a portion where the silicon film has been lost. Initially, the present inventors previously predicted that a hole 509 would be formed in the silicon film due to the removal of the catalyst element as long as the catalyst element in the silicon film was gettered, and tried to control the position of the hole 509. However, the occurrence of holes 509 was observed also in an unexpected region, that is, an element formation region.
[0026]
Here, the above problem will be described in detail with reference to FIG. FIG. 5A is a schematic plan view after solid phase crystal growth by selective addition of a catalyst element, and FIG. 5B is a schematic plan view after a problematic second heat treatment.
[0027]
In FIG. 5A, regions 501 and 502 are regions where a catalytic element is introduced. The catalytic element selectively introduced into this region first crystallizes the regions 501 and 502, and causes crystal growth in the peripheral portion. As a result, crystal growth of the regions 503 and 504 is performed. At this time, in regions 501 and 502, crystal growth is caused by random nucleation by the introduced catalytic element, whereas in regions 503 and 504, crystal growth is performed in the direction of H3, and the growth direction is pseudo one-dimensional. It is aligned. The region 505 which has not reached the crystal growth remains in the amorphous silicon state.
[0028]
Due to the crystal growth mechanism, the catalytic element moves at the tip of the crystal growth, that is, at the boundary between the crystallized region and the amorphous region, and successively crystallizes the amorphous silicon film beyond that. Therefore, the position where the catalyst element is unevenly distributed is the crystal grain boundary where the crystal growth has collided and the tip of the crystal growth. That is, in FIG. 5A, the nucleation occurs randomly, and the inside of the catalyst element introduction regions 501 and 502 where the crystal grains collide with the lateral crystal growth regions (lateral growth regions) 503 and 504. The catalyst element is unevenly distributed in the boundary 507 and in three regions 508 between the lateral growth regions 503 and 504 and the amorphous region 505. Therefore, the semiconductor element region is formed using the lateral growth regions 503 and 504, for example, in an arrangement like the region 510.
[0029]
However, after the second heat treatment, as shown in FIG. 5B, fine holes 509 with a substantially uniform density were found over the entire surface of the film. That is, such a hole 509 is also generated in the lateral growth regions 503 and 504 to be used as the semiconductor element region 510, and a hole 509 is also generated in the region 505 where the crystal growth by the catalytic element has not reached. did. When a semiconductor device is manufactured in such a state, a very high-performance semiconductor element can be locally realized. However, when the hole 509 covers an element region, a defect occurs in the element. In addition, such a hole 509 causes damage to a lower layer in a later etching process or the like, and causes a reduction in reliability as a whole. Therefore, when this method is used, the yield in the semiconductor device manufacturing process is extremely low, and application to a semiconductor device in which hundreds of thousands of TFTs are arranged on a substrate, such as an active matrix substrate for a liquid crystal display, is almost impossible. Impossible.
[0030]
The present invention solves such problems of the prior art, and can prevent re-diffusion of a catalyst element in the second heat treatment for improving crystallinity, and generate fine holes in the crystalline silicon film. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of solving a problem such as the problem of manufacturing a semiconductor device having very high performance and high reliability with high yield.
[0031]
[Means for Solving the Problems]
Of the present invention The method for manufacturing a semiconductor device includes a first step of forming an amorphous silicon thin film on an insulating substrate, and selectively introducing a catalyst element that promotes crystallization to the amorphous silicon film; A first heat treatment at a temperature of 540 to 620 ° C., and a crystal growth of the amorphous silicon film in a lateral direction from a region where the catalytic element is introduced to a peripheral region thereof. A specific silicon film region where the catalyst element is localized, at least a region where the catalyst element is introduced in the first step, and a crystal growth formed by the crystal growth in the second step. Border By etching using a mixed solution of hydrofluoric acid and nitric acid together with the catalyst element and a silicide compound of the catalyst element contained in those portions. A third step of removing, and a second heat treatment is performed in an oxidizing atmosphere containing a halide at a temperature of 800 to 1100 ° C. higher than the temperature of the first heat treatment. A fourth step of improving the crystallinity of the remaining crystalline silicon film region and removing the catalytic element, thereby achieving the above object.
[0033]
Said The silicon film region left in the third step is a semiconductor device region Is .
[0035]
Said The step of selectively introducing the catalyst element in the first step includes forming a mask at a position corresponding to a region where the catalyst element is not introduced in the amorphous silicon film. Do .
[0036]
Said The step of selectively introducing the catalyst element in the first step includes, after depositing the catalyst element in a thin film on the surface of the amorphous silicon film by a sputtering method or a vacuum evaporation method using a photoresist as a mask. By stripping off the photoresist and lifting off the catalytic element on the mask Do .
[0037]
Said In the step of selectively introducing the catalyst element in the first step, using a silicon oxide film or a silicon nitride film as a mask, a solution in which the catalyst element is dissolved is applied to the surface of the amorphous silicon film and dried. After that, by performing a pre-annealing process, by removing the mask of the silicon oxide film or the silicon nitride film Do .
[0040]
Said In the second step, the direction in which the amorphous silicon film is crystal-grown from the region where the catalytic element is introduced to the peripheral region is substantially parallel to the direction of carrier movement in the semiconductor device. Do .
[0041]
Said As a catalyst element, one or more elements among Ni, Co, Pd, Pt, Cu, Ag, Au, In, Sn, Al and Sb Use .
[0042]
Hereinafter, the gist and operation of the present invention will be described.
[0043]
With respect to the above-mentioned problem, the present inventors have experimentally confirmed that the cause of the above-mentioned minute holes is caused by the uneven distribution of the catalytic element, and the catalytic element is selectively oxidized and etched. did. The problem is that in the lateral growth regions 503 and 504 and the amorphous region 505 in FIG. It was confirmed that the main cause was re-diffusion of the catalytic element during the second heat treatment.
[0044]
That is, after the crystallization annealing (first heat treatment) in FIG. 5A, the catalyst elements are unevenly distributed in the catalyst element introduction regions 501 and 502 and the crystal growth boundaries 507 and 508, but the crystallinity is further improved. At the time of the second heat treatment for improvement, the catalyst element is re-diffused, so that the catalyst element is present at the same level in the lateral growth regions 503 and 504 and the region 505 which has not been grown by the catalyst element. As a result, micro holes are also generated in the lateral growth regions 503 and 504 where the element is to be formed.
[0045]
Therefore, the gist of the present invention is to selectively introduce a catalyst element into an amorphous silicon film formed on an insulating substrate and to crystallize in a lateral direction from a catalyst element introduction region to a peripheral region by a first heat treatment. After the growth, and before the second heat treatment step for improving the crystallinity of the silicon film, a step of removing a specific silicon film region where the catalytic element is localized is performed. That is, before the catalyst element is re-diffused by the second heat treatment, in other words, while the catalyst element is unevenly distributed, the unevenly distributed region of the catalyst element is removed. As a result, the main source of the re-diffusion of the catalyst element generated in the second heat treatment is cut off, so that the above-described problem can be solved, and the intended high-performance semiconductor device can be obtained at a high yield. .
[0046]
That is, in the method of manufacturing a semiconductor device of the present invention, at least the first step forms an amorphous silicon thin film on an insulating substrate and promotes the crystallization of the amorphous silicon film. A catalyst element is selectively introduced, a first heat treatment is performed in a second step, and an amorphous silicon film is grown laterally from a region where the catalyst element is introduced to a peripheral region thereof. Removing the silicon film in a specific region where the catalytic element is localized in the third step, performing the second heat treatment in the fourth step, and removing the crystalline silicon film region left in the third step. The crystallinity is improved.
[0047]
The silicon film in the region where the catalyst element is localized here means a catalyst element introduction region where the catalyst element is unevenly distributed after crystallization annealing, and a crystal growth boundary portion, that is, a crystallization region due to its growth mechanism. The main region is a boundary between the crystallized region and the uncrystallized region and a boundary where crystal growth has collided, and it is desirable that at least these regions be removed. That is, when the crystal growth is performed with the introduction pattern as shown in FIG. 5, the catalyst element introduction regions 501 and 502, the boundary 507 where the lateral crystal growths collide, the region crystallized by the lateral crystal growth. It suffices that at least three points of the boundary 508 between the first region and the amorphous region have been removed. Then, the second heat treatment is performed thereafter.
[0048]
In particular, it is desirable to perform patterning so that the silicon film region left in the third step becomes a semiconductor element region (active region of a semiconductor device). By removing the localized region of the catalyst element in this manner, not only can the process be shortened, but also all unnecessary regions are removed. For this reason, the diffusion amount of the catalyst element into the semiconductor element region can be further reduced. Of course, the semiconductor element region is formed at a position indicated by, for example, a region 510 using only the lateral growth regions 503 and 504 in FIG.
[0049]
Here, in the step of removing the silicon film in the region where the catalytic element is localized, including the step of forming the semiconductor element region, the etching property between the target silicon film and the catalytic element is important. That is, if the catalyst element remains without being etched even after the silicon film is removed, the substrate surface is re-diffused from there, and the effect of the present invention is impaired. In addition, it may cause damage to a lower layer, disconnection of a bus line or the like formed thereon, and decrease in reliability of a semiconductor element. Further, the present inventors have found that many catalytic elements are present in the silicon film as silicide compounds. Therefore, in the third step of removing the specific silicon film region where the catalyst element is localized in the present invention, at the same time as the silicon film, the catalyst element and the silicide compound of the catalyst element are removed. Most preferably, it is performed by etching.
[0050]
As a specific method of removing the silicon film in the region where the catalyst element is localized, it is desirable to perform etching removal using a mixed solution of hydrofluoric acid and nitric acid. In this removal step, as described above, in addition to the silicon film, the catalytic element or its silicide compound must be etched at the same time. For that purpose, etching using a mixed solution of hydrofluoric acid and nitric acid is optimal, and the catalyst element is etched simultaneously with the silicon film, so that a clean state with no residue in the removal region is obtained.
[0051]
When fine processing is desired, dry etching by plasma is effective. However, CF which has been conventionally used for etching a silicon film is used. ₄ In dry etching using a Freon-based gas such as a gas and an oxygen-based gas, the silicon film is etched but the silicide compound is not etched, and the silicide compound due to the catalytic element remains on the substrate surface as a residue. If these silicide compounds remaining on the substrate cause re-diffusion during the second heat treatment, the effectiveness of the present invention is impaired.
[0052]
Therefore, in dry etching, it is necessary to simultaneously etch the catalyst element or its silicide compound in addition to the silicon film. ₃ RIE (reactive ion etching) using a chlorine-based gas such as HCl or HCl is very effective. By using such an RIE method, a clean state with no residue in the removal region can be obtained, and fine processing can be performed.
[0053]
By the way, the main cause of the fine holes observed after the second heat treatment is the re-diffusion of the catalyst element during the second heat treatment as described above. However, as a result of repeating the experimental research by the present inventors, in addition to the above-mentioned causes, the lateral growth regions (503, 504 in FIG. 5) of the silicon film in which the semiconductor element region is provided can also be obtained by the introduction treatment of the catalytic element. ) And an amorphous region (505 in FIG. 5) which has not been grown by the catalyst element.
[0054]
That is, as a conventional method for introducing a catalytic element, as shown in FIG. 6A, a catalytic element 604 is mainly introduced using the silicon oxide film 603 as a mask film over the entire surface of the substrate, and then the crystallization is performed. For the first heat treatment. Here, reference numeral 601 denotes a substrate, and 602 denotes an amorphous silicon film. However, in such a conventional method, at the time of the first heat treatment, as shown in FIG. 6B, the introduction region 605 in contact with the catalyst element is crystallized, and the crystal growth further proceeds in the lateral direction H4. The catalytic element 604 existing on the silicon oxide film 603 serving as a mask diffuses through the silicon oxide film 603 as indicated by an arrow H5, and reaches the lower silicon film 602.
[0055]
Since the diffusion coefficient of the catalyst element in the silicon oxide film is much smaller than that in the silicon film, the catalyst element 604 reaches the surface of the lateral growth region 602b after crystal growth in the lateral direction. The catalyst element will be present in a region where the catalyst element must not be present. The catalyst element is also present in the amorphous region 602c where the crystal growth has not been reached for the same reason. In this case, after the first heat treatment for crystallization, the catalytic element is present in the laterally grown region 602b and the amorphous region 602c which has not been grown. Will be greatly impaired.
[0056]
Therefore, in order to maximize the effects of the present invention, the first step of selectively introducing a catalytic element into the amorphous silicon film is performed by using a mask film such as a silicon oxide film, a silicon nitride film, or a photoresist. The first heat treatment is performed after covering the portion of the amorphous silicon film where the catalytic element is not introduced, removing the mask film after introducing the catalytic element, and subjecting the amorphous silicon film to the above-described process. It is desirable to cause crystal growth in the lateral direction from the region where the catalytic element is introduced to the peripheral region. By this step, the catalytic element present on the mask is removed before the first heat treatment for crystallization, and the phenomenon that the catalytic element diffuses from the mask is completely eliminated. Further, as a secondary effect, at the time of the first heat treatment, the overall amount of the catalyst element on the substrate to be put into the heat treatment furnace is significantly reduced, so that contamination of the heat treatment furnace due to the catalyst element can be reduced. .
[0057]
As a specific step of selectively introducing a catalytic element into the amorphous silicon film, using a photoresist as a mask, a sputtering method or a vacuum deposition method is used to deposit the catalytic element in a thin film on the surface of the amorphous silicon film. It is preferable to remove the photoresist mask, lift off the catalyst element on the mask, and then perform the first heat treatment. Since the catalyst element formed in a thin film on the amorphous silicon film by the sputtering method or the vacuum evaporation method is not removed in the photoresist stripping step, the selective introduction of the catalyst element by this method should be completed. Becomes possible. In addition, there is no need to form a mask film such as a silicon oxide film, and the number of steps can be reduced.
[0058]
Further, as another method, using a silicon oxide film or a silicon nitride film as a mask, a solution in which a catalytic element was dissolved was applied to the substrate surface and dried, and thereafter, a pre-annealing treatment was performed before the first heat treatment. After that, a method of performing the first heat treatment after removing the mask of the silicon oxide film or the silicon nitride film is also effective. In this method, since a solution in which a catalytic element is dissolved is used, by controlling the concentration of the catalytic element in the solution, it becomes possible to control a very small amount of the catalytic element introduced on the substrate. However, the catalytic element applied on the silicon film has such a weak bond with the silicon film that it can be removed only by washing with water, and the catalyst element is necessarily removed simultaneously by removing the mask film. Therefore, in this method, the catalyst element is diffused into the silicon film in the introduction region by applying a solution to the substrate surface and drying it, and then performing a pre-annealing process. Are not removed.
[0059]
However, since this pre-annealing requires a certain high temperature, a simple photoresist mask cannot be used, and a mask made of a silicon oxide film or a silicon nitride film is required. In addition, in the pre-annealing treatment, it is meaningless that the catalyst element diffuses in the silicon oxide film or the silicon nitride film and reaches the lower silicon film. It is necessary to set conditions so as not to reach the lower silicon film. According to this method, the problem of generation of micro holes during the above-described second heat treatment can be solved, and a trace amount of the catalyst element can be controlled.
[0060]
Here, in the solution in which the catalyst element is dissolved in the above method, it is desirable to use an acetate or nitrate of the catalyst element as a solute and use an alcohol system such as ethanol or isopropyl alcohol (IPA) as a solvent. By using such a solution, stable crystal growth can be obtained over the entire surface of the substrate. In particular, excellent in-plane uniformity can be obtained for a large substrate such as a liquid crystal substrate. When the acetate of the catalyst element used is insoluble in alcohol, the acetate may be first dissolved with a very small amount of water and then mixed with the alcohol as the main solvent.
[0061]
Further, the step of applying a solution in which the above-mentioned catalyst element is dissolved on the substrate surface and drying the solution is preferably performed by spin coating and spin drying using a spin coater. According to this method, the catalyst element can be uniformly added to the substrate surface. In fact, in the experiments of the present inventors, as a result of applying and drying a solution on a glass substrate having a size of 320 mm × 400 mm by this method, the surface concentration of the catalytic element is in a distribution within approximately ± 10%. It was confirmed that.
[0062]
Further, as the pre-annealing performed before the first heat treatment, it is necessary that the catalyst element in the introduction region is not removed in a subsequent mask film removing step. Hydrofluoric acid is generally used to remove a silicon oxide film or a silicon nitride film used as a mask film, but most of the catalytic elements are removed by this etchant.
[0063]
That is, in the pre-annealing treatment performed before the first heat treatment in the present invention, it is necessary to sufficiently diffuse the catalyst element into the silicon film in the catalyst element introduction region. Specifically, the amorphous silicon film In this case, it is necessary to grow at least a part of the selective introduction region of the catalyst element. Therefore, it is preferable that the pre-annealing performed before the first heat treatment be performed at a heating temperature and a heating time that satisfy the above conditions. Then, the catalyst element is not simultaneously removed by removing the mask, and sufficient crystal growth is performed by the first heat treatment.
[0064]
Now, the present invention is characterized in that the second heat treatment is performed after the first heat treatment. However, the treatment temperature of these heat treatments is higher than the first heat treatment temperature by the second heat treatment temperature. The processing temperature must be at least higher. That is, the first heat treatment aims at crystallization of the amorphous silicon film, and the second heat treatment aims at further improving the crystallinity of the silicon film crystallized by the first heat treatment. The so-called crystallinity improving process is performed.
[0065]
For this purpose, the first heat treatment needs to be performed at a relatively low temperature. This is because, when the first heat treatment is performed at a high temperature, the crystallization speed is too high, so that crystal nuclei are randomly generated over the entire surface of the substrate, and the crystal growth direction branches in various ways, so that stable crystal growth can be expected. Absent. As the second heat treatment, it is necessary to apply at least the energy of the first heat treatment or more in order to further improve the quality of the crystalline silicon film formed in the first heat treatment. Crystal defects generated in the crystallization step of the first heat treatment can be significantly reduced.
[0066]
Specifically, the first heat treatment is preferably performed at a temperature in the range of 540 ° C to 620 ° C, and the second heat treatment is preferably performed in a range of 800 ° C to 1100 ° C. If the first heat treatment is performed in such a temperature range, spontaneous crystal growth that does not depend on the catalyst element generated outside the region where the catalyst element is introduced can be suppressed, and stable crystal growth can be obtained. In addition, when the second heat treatment is performed in the above temperature range, crystal defects can be efficiently reduced, and each of the columnar crystals in the lateral crystal growth region forming the semiconductor element region is recombined. A highly crystalline silicon film comparable to high quality single crystal silicon is obtained.
[0067]
In addition, the pre-annealing performed before the first heat treatment in the method of adding a catalyst element by applying the above catalyst element solution to the substrate surface is performed at a temperature in the range of 500 ° C. to 550 ° C. for 10 minutes. It is desirable to carry out for 30 minutes. By this pre-annealing treatment, at least a part of the selective introduction region of the catalyst element in the amorphous silicon film can be crystal-grown.
[0068]
Here, it is preferable that the second heat treatment be performed in an oxidizing atmosphere containing a halide. By performing the second heat treatment in such an atmosphere, the concentration of the catalyst element used for crystal growth in the film can be significantly reduced by the impurity gettering action of the halide. Further, by supplying supersaturated Si atoms generated by the oxidizing action into the silicon film, crystal defects, in particular, dangling bonds (unpaired bonds) can be eliminated more efficiently.
[0069]
Further, as the oxidizing atmosphere containing a halide in the second heat treatment, it is particularly preferable to use HCl gas. By using HCl gas, the catalytic element can be converted into chloride and vaporized, and the catalytic element can be efficiently removed from the silicon film.
[0070]
In the present invention, in order to realize a semiconductor device with higher mobility and higher performance, it is desirable that the crystal growth direction of the silicon film by the catalytic element and the carrier movement direction in the semiconductor device be substantially parallel. As a result, a crystal grain boundary that becomes a trap when carriers move is theoretically not present in the moving direction, and a semiconductor device having higher mobility can be obtained. Actually, in the lateral crystal growth region, a certain amount of bending or branching of the columnar crystal occurs, but by adopting such a configuration, the trap amount such as a crystal grain boundary in the carrier moving direction is reduced. Will definitely drop.
[0071]
Ni, Co, Pd, Pt, Cu, Ag, Au, In, Sn, Al, and Sb can be used as the types of catalyst elements that can be used in the present invention. One or a plurality of elements selected from these elements have an effect of promoting crystallization in a small amount.
[0072]
Among them, the most remarkable effect can be obtained particularly when Ni is used. The following model can be considered for this reason. The catalyst element does not act alone, but acts on crystal growth by bonding to the silicon film to form silicide. The model is such that the crystal structure at that time acts like a kind of template when the amorphous silicon film is crystallized, and promotes the crystallization of the amorphous silicon film. Ni is two Si and NiSi ₂ Is formed. NiSi ₂ Shows a fluorite type crystal structure, which is very similar to the diamond structure of single crystal silicon. Moreover, NiSi ₂ Has a lattice constant of 0.5406 nm, which is very close to the lattice constant of 0.5430 nm in the diamond structure of crystalline silicon. Therefore, NiSi ₂ Is the best as a template for crystallizing an amorphous silicon film, and it is most preferable to use Ni as the catalyst element in the present invention.
[0073]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.
[0074]
(Embodiment 1)
FIG. 1 and FIG. 2 show a first embodiment showing a step of manufacturing an N-channel TFT (N-type TFT) by the method of the present invention. Hereinafter, the manufacturing process will be described in the order of progress of the steps (A) to (F) in FIG.
[0075]
First, as shown in FIG. 2A, the surface of a quartz glass substrate 101 is washed with about 1% hydrofluoric acid, and then a thickness of 25 nm or less is formed on the substrate 101 by a low pressure CVD method or a plasma CVD method. An intrinsic (I-type) amorphous silicon film (a-Si film) 102 having a thickness of 100 nm, for example, 50 nm is formed, and an insulating thin film 103 such as a silicon oxide film or a silicon nitride film is further deposited thereon. The insulating thin film 103 serves as a mask film when a catalytic element is introduced later. In the first embodiment, a silicon oxide film is used, TEOS (Tetra Ethoxy Ortho Silicate) is used as a raw material, and RF plasma is used together with oxygen. Decomposed and deposited by the CVD method. The thickness of the mask silicon oxide film 103 is desirably 50 nm to 250 nm. If the thickness is smaller than this, the catalytic element diffuses to the lower layer. If the thickness is larger than this, crystal growth cannot be performed well. Therefore, in the first embodiment, the thickness of the silicon oxide film 103 is set to 150 nm.
[0076]
Next, a mask is formed by patterning the silicon oxide film 103. Here, the a-Si film 102 is exposed in a slit shape through the through hole of the mask 103. That is, when the state of FIG. 2A is viewed from above, as shown in FIG. 1, the a-Si film 102 is exposed in a slit shape in a region 100 by a through hole, and the other portions are masked. It has become.
[0077]
After the mask 103 is provided, as shown in FIG. 2A, the substrate 101 is held so that the ethanol solution in which the nickel 104 is dissolved is in contact with the region 100 where the surface of the a-Si film 102 is exposed. . In the first embodiment, nickel acetate was used as the solute, and the nickel concentration in the ethanol solution was adjusted to 10 ppm. After that, an aqueous solution is uniformly spread on the substrate 101 by a spinner and dried to add a small amount of nickel 104 to the surfaces of the silicon oxide film 103 and the a-Si film 102 on the substrate 101. By this step, nickel 104 is selectively introduced into the portion of the a-Si film 102 exposed in the region 100. Then, this is subjected to a pre-annealing treatment in an inert atmosphere, for example, a nitrogen atmosphere at a treatment temperature of 500 ° C. to 550 ° C. for a treatment time of 10 minutes to 30 minutes. In the first embodiment, the heat treatment was performed at 530 ° C. for 20 minutes.
[0078]
In this pre-annealing process, as shown in FIG. 2B, in the region 100, crystallization of the silicon film 102 occurs in the direction perpendicular to the substrate 101 with the nickel 104 added to the surface of the a-Si film as a nucleus. Then, a crystalline silicon film 102a is formed. Further, the region other than the distribution region 100 does not reach the crystal growth and remains as an a-Si region 102c in an amorphous state. At this time, the nickel 104 on the mask film 103 is blocked by the mask film 103 under the above annealing conditions, and cannot reach the underlying a-Si film 102.
[0079]
Next, the silicon oxide film 103 used as a mask is removed by etching. The etching was performed by wet etching using 1:10 buffered hydrofluoric acid (BHF) having sufficient selectivity with the lower silicon film 102 as an etchant. After that, the substrate 101 is again subjected to heat treatment (first heat treatment) at a temperature of 540 ° C. to 620 ° C. for several hours to several tens of hours in an inert atmosphere, for example, a nitrogen atmosphere. In the first embodiment, as an example, the treatment was performed at 580 ° C. for 11 hours.
[0080]
In this heat treatment, crystal growth from the peripheral region of the previously crystallized region 100 (102a) in the lateral direction (direction parallel to the substrate) from the region 100 as shown by an arrow H1 in FIG. This is performed to form a crystalline silicon film 102b that has grown laterally. The other region 102 remains as an amorphous silicon film region 102c. The nickel concentration in the laterally grown crystalline silicon film 102b is 8 × 10 ¹⁶ atoms / cm ³ The nickel concentration in the crystalline silicon film 102a in the region 100 in which nickel is directly introduced and crystal growth is performed is 1 × 10 5 ¹⁸ atoms / cm ³ It was about.
[0081]
In the above crystal growth, the distance of crystal growth in the direction parallel to the substrate indicated by arrow H1 was about 130 μm. When this state is viewed from above the substrate, the nickel 104 is formed at the boundary 102d between the catalytic element introduction region 102a (100) in FIG. 1 and the crystalline silicon film region 102b and the amorphous silicon film region 102c which have grown in the lateral direction. Is localized.
[0082]
Next, as shown in FIG. 2D, unnecessary portions of the silicon film 102 are removed to perform element isolation. The etching at this time was performed by wet etching using so-called 1: 100 hydrofluoric-nitric acid in which hydrofluoric acid and nitric acid were mixed at a ratio of 1: 100. By this etching process, the nickel 104 is etched together with the silicon film even in the regions 102a and 102d where a large amount of nickel 104 is present, so that a clean substrate surface with no etching residue can be obtained. That is, a large amount of nickel 104 has already been removed outside the substrate by this etching process. Then, through the above steps, an island-shaped crystalline silicon film 102f to be a source region, a drain region, and a channel region of the TFT later, that is, an active region is formed, and the state of FIG. 2D is obtained.
[0083]
Next, in the state of FIG. 2D, a second heat treatment is performed to improve the crystallinity of the island-shaped crystalline silicon film 102f. As the second heat treatment, heat treatment is performed at a temperature of 800 ° C. to 1100 ° C. for several tens minutes to several hours in an oxidizing atmosphere containing a halide. In the first embodiment, a mixed gas of HCl and oxygen is used, the flow ratio of HCl is set to 3% of the total gas flow, and the heat treatment is performed at a substrate temperature of 950 ° C. for 25 minutes. By this step, the surface of the crystalline silicon film 102f is uniformly oxidized, and the thickness of the crystalline silicon film 102f is reduced to about 35 nm. In addition, the crystallinity of the crystalline silicon film 102f is significantly improved, and nickel remaining in the film is reduced. Actually, the nickel concentration in the silicon film after the second heat treatment is 5 × 10 ^Fifteen atoms / cm ³ Reduced to below. At this time, in the island-shaped crystalline silicon film 102f, no fine holes, which have conventionally been a problem, are not generated.
[0084]
Next, after the surface oxide film of the crystalline silicon film 102f is removed by etching with 1:10 BHF, as shown in FIG. 2E, a thickness of 20 nm is formed so as to cover the crystalline silicon film 102f serving as the active region. A silicon oxide film with a thickness of 150 nm, here 100 nm, is formed as the gate insulating film 106. For the formation of this silicon oxide film, TEOS was used as a raw material here, and it was decomposed and deposited by RF plasma CVD at a substrate temperature of 150 ° C. to 600 ° C., preferably 300 ° C. to 450 ° C. together with oxygen. . The substrate may be formed by using TEOS as a raw material together with ozone gas by a low pressure CVD method or a normal pressure CVD method so that the substrate temperature is in the range of 350 ° C. to 600 ° C., preferably 400 ° C. to 550 ° C. After film formation, in order to improve the bulk characteristics of the gate insulating film itself and the interface characteristics between the crystalline silicon film and the gate insulating film, the processing time is set within a range of 800 ° C. to 1000 ° C. in an oxidizing gas atmosphere. Annealing treatment was performed within a range of minutes to 60 minutes.
[0085]
Next, an aluminum film having a thickness of 400 nm to 800 nm, for example, 600 nm is formed by a sputtering method. Then, the gate electrode 107 is formed by patterning the aluminum film. Further, the surface of the aluminum electrode is anodized to form an oxide layer 108 on the surface. This state corresponds to FIG. The anodization is performed in an ethylene glycol solution containing tartaric acid at 1% to 5%, and the voltage is first increased to 220 V at a constant current, and the state is maintained for 1 hour to complete the process. The thickness of the obtained oxide layer 108 is 200 nm. Note that since the oxide layer 108 has a thickness for forming an offset gate region in a later ion doping process, the length of the offset gate region can be determined in the anodic oxidation process.
[0086]
Next, impurities (phosphorus) are implanted into the active region by ion doping using the gate electrode 107 and the oxide layer 108 around the gate electrode 107 as a mask. Phosphine (PH) as doping gas ₃ ), The acceleration voltage is in the range of 60 kV to 90 kV, for example, 80 kV, and the dose is 1 × 10 ^Fifteen cm ^-2 ~ 8 × 10 ^Fifteen cm ^-2 , For example, 2 × 10 ^Fifteen cm ^-2 And By this step, the regions 110 and 111 into which the impurities are implanted later become the source and drain regions of the TFT, respectively. Area. When this state is viewed from above the substrate, as shown in FIG. 1, the moving direction of the carriers in the TFT is the distribution direction of the source distribution 110 and the drain distribution 111, and is the horizontal direction on the paper of FIG. On the other hand, the crystal growth direction of the silicon film forming the channel portion 109 is the direction of H1, and is arranged so as to be substantially parallel to the moving direction of the carrier. With such an arrangement, a TFT having a particularly high mobility can be realized.
[0087]
Next, as shown in FIG. 2E, an annealing process is performed by irradiation with a laser beam L1 to activate the ion-implanted impurities and, at the same time, to crystallize a portion where crystallinity is deteriorated in the above-described impurity introducing step. Improve sex. At this time, a XeCl excimer laser (wavelength: 308 nm, pulse width: 40 nsec) was used as the laser to be used, and the energy density was 150 mJ / cm. ² ~ 400mJ / cm ² Within the range, preferably 200 mJ / cm ² ~ 250mJ / cm ² Irradiation was performed within the range. The sheet resistance of the N-type impurity (phosphorus) regions 110 and 111 thus formed was in the range of 200Ω / □ to 800Ω / □.
[0088]
Next, a silicon oxide film or a silicon nitride film having a thickness of about 600 nm is formed as the interlayer insulating film 113. When a silicon oxide film is used, if TEOS is used as a raw material and formed by a plasma CVD method with oxygen or a reduced pressure CVD method or a normal pressure CVD method with ozone, a good interlayer insulation with excellent step coverage can be obtained. A film is obtained. In addition, SiH ₄ And NH ₃ Using a silicon nitride film formed by a plasma CVD method using hydrogen as a source gas supplies hydrogen atoms to the interface between the active region and the gate insulating film, and has the effect of reducing dangling bonds that degrade TFT characteristics. .
[0089]
Next, a contact hole is formed in the interlayer insulating film 113, and electrodes / wirings 114 and 115 of the TFT are formed using a metal material, for example, a two-layer film of titanium nitride and aluminum. The titanium nitride film is provided as a barrier film for preventing aluminum from diffusing into the semiconductor layer. Finally, annealing is performed at 350 ° C. for 30 minutes in a hydrogen atmosphere at 1 atm to complete the TFT 117 shown in FIG. This annealing treatment is performed for the purpose of terminating crystal defects in the silicon film remaining until the end, in particular, dangling bonds by terminating them with hydrogen.
[0090]
When the TFT 117 is used as an element for switching a pixel electrode, the electrode 114 or 115 is connected to a pixel electrode made of a transparent conductive film such as ITO, and a signal is input from the other electrode. When the TFT 117 is used for a thin film integrated circuit, a contact hole may be formed also on the gate electrode 107 and a necessary wiring may be provided. Further, a protective film made of a silicon nitride film may be provided on the TFT 117 as needed.
[0091]
The N-type TFT 117 manufactured according to the first embodiment has a field-effect mobility of 150 cm. ² / Vs ~ 250cm ² / Vs, and a threshold voltage of 1 V to 1.5 V, showing very high-performance electrical characteristics. In addition, there is no microhole in the active region, which has conventionally occurred, and especially in an active matrix substrate for liquid crystal display for driving hundreds of thousands of pixel TFTs, pixel defects due to the above-mentioned causes can be solved, and very high definition can be achieved. A liquid crystal display device with high display quality can be obtained. Further, the substrate 101 under the introduction region 100 was hardly damaged by nickel, and as a result, the disconnection failure of the bus line was reduced, and the manufacturing yield was improved. Also, in the TFT characteristics, the leakage current in the TFT off region where the catalytic element is particularly problematic could be reduced to about 2 pA which is not a problem as compared with the conventional 10 pA to 15 pA.
[0092]
This TFT can be used not only as a driver circuit and a pixel portion of an active matrix type liquid crystal display device but also as an element constituting a CPU on the same substrate. It goes without saying that the TFT can be applied not only to a liquid crystal display device but also to a thin film integrated circuit which is generally called.
[0093]
(Embodiment 2)
FIGS. 3 and 4 show a second embodiment of the present invention, which shows a step of manufacturing a circuit having a CMOS structure in which an N-type TFT and a P-type TFT are configured in a complementary manner on a quartz glass substrate. Hereinafter, the manufacturing steps will be described in the order of progress of the steps (A) to (E) in FIG.
[0094]
First, as shown in FIG. 4A, the surface of a quartz glass substrate 201 is washed with about 1% hydrofluoric acid, and then a thickness of 25 nm or less is formed on the substrate 201 by a low pressure CVD method or a plasma CVD method. An intrinsic (I-type) amorphous silicon film (a-Si film) 202 having a thickness of 100 nm, for example, 50 nm is formed.
[0095]
Next, a photosensitive resin (photoresist) is applied on the a-Si film 202, and is exposed and developed to form a mask 203. The a-Si film 202 is exposed in a slit shape in the region 200 by the through hole of the photoresist mask 203. That is, when the state of FIG. 4A is viewed from above, the a-Si film 202 is exposed in the region 200 as shown in FIG. 3, and the other parts are masked by the photoresist. I have.
[0096]
After providing the mask 203, a thin film of nickel 204 is deposited on the surface of the substrate 201 as shown in FIG. In the second embodiment, the thickness of the nickel thin film 204 is controlled to be 1 nm or less by increasing the distance between the deposition source and the substrate and lowering the deposition rate. At this time, the surface density of nickel 204 on substrate 201 was actually measured to be 2 × 10 ^Thirteen atoms / cm ² It was about.
[0097]
Next, as shown in FIG. 4B, by removing the photoresist mask 203, the nickel thin film 204 on the mask 203 is lifted off, and the nickel 204 is selectively removed in the a-Si film 202 in the region 200. This means that a very small amount was introduced. Then, this is annealed in an inert atmosphere, for example, a nitrogen atmosphere at a heating temperature of 540 ° C. to 620 ° C., for example, 580 ° C. for 11 hours to be crystallized.
[0098]
At this time, in the region 200, the silicon film 202 is crystallized in a direction perpendicular to the substrate 201 with the nickel 204 added to the surface of the a-Si film 202 as a nucleus, and a crystalline silicon film 202a is formed.
[0099]
Next, in the peripheral region of the region 200, as shown by an arrow H2 in FIG. 4B, crystal growth is performed in a lateral direction (a direction parallel to the substrate) from the region 200, and A silicon film 202b is formed. The other region 202 remains as it is as the amorphous silicon film region 202c. The nickel concentration in the laterally grown crystalline silicon film 202b is 1 × 10 ¹⁷ atoms / cm ³ And the nickel concentration in the crystalline silicon film 202a in the region 200 in which crystal growth is performed by directly adding nickel is 2 × 10 ¹⁸ atoms / cm ³ It was about.
[0100]
In the above crystal growth, the distance of crystal growth in a direction parallel to the substrate indicated by arrow H2 is about 130 μm. When this state is viewed from above the substrate, as shown in FIG. 3, nickel is present at the boundary 202d between the catalytic element introduction region 202a (200) and the crystalline silicon film region 202b and the amorphous silicon film region 202c that have grown in the lateral direction. 204 is localized.
[0101]
Next, as shown in FIG. 4 (C), the crystalline silicon film which will later become the active regions (semiconductor device regions) 202n and 202P of the TFT is left, and the other regions are removed by etching to perform device isolation. As the etching at this time, BCl ₃ And Cl ₂ Was performed by the RIE method using RF plasma using a mixed gas of The etching conditions are BCl ₃ Flow rate 15 sccm, Cl ₂ The flow rate was set to 70 sccm, and RF pressure of 1300 W was applied under reduced pressure of about 8 mTorr.
[0102]
By this etching process, even in the regions 202a and 202d where a large amount of nickel 204 is present, the nickel 204 is etched together with the silicon film, so that a clean substrate surface with no etching residue can be obtained, and when wet etching is used. Further fine processing can be performed. Through the above steps, island-shaped crystalline silicon films 202n and 202p to be the source region, the drain region, and the channel region of the TFT later, that is, the active regions are formed, and the state of FIG. 4C is obtained.
[0103]
Next, a second heat treatment is performed in the state of FIG. 4C to improve the crystallinity of the island-shaped crystalline silicon films 202n and 202P. As the second heat treatment, heat treatment is performed in an oxidizing atmosphere containing a halide at a temperature of 800 ° C. to 1100 ° C. for several tens minutes to several hours. In the second embodiment, a mixed gas of HCl and oxygen is used, the flow ratio of HCl is set to 3% of the total gas flow, and the heat treatment is performed at a substrate temperature of 950 ° C. for 25 minutes.
[0104]
By this step, the surfaces of the silicon films 202n and 202p are uniformly oxidized, and the thickness of the crystalline silicon films 202n and 202p is reduced to about 35 nm. Further, the crystallinity of the crystalline silicon films 202n and 202p is greatly improved, and nickel remaining in the films is reduced. Actually, the nickel concentration in the silicon film after the second heat treatment is 5 × 10 ^Fifteen atoms / cm ³ Reduced to below. At this time, in the island-shaped crystalline silicon films 202n and 202p, no fine holes, which had been a problem in the past, were generated.
[0105]
Next, after the surface oxide films of the island-shaped crystalline silicon films 202n and 202p are removed by etching with 1:10 BHF, a silicon oxide film having a thickness of 100 nm is formed so as to cover the crystalline silicon films 202n and 202p serving as the active regions. The film is formed as the gate insulating film 206. In the second embodiment, as a method for forming the gate insulating film 206, TEOS is used as a raw material, and is decomposed and deposited by RF plasma CVD at a substrate temperature of 350 ° C. together with oxygen.
[0106]
Next, as shown in FIG. 4D, aluminum (including 0.1% to 2% of silicon) having a thickness of 400 nm to 800 nm, for example, 500 nm is formed by a sputtering method. By patterning, gate electrodes 207n and 207p are formed.
[0107]
Next, impurities (phosphorus and boron) are implanted into the active regions 202n and 202p using the gate electrodes 207n and 207p as masks by ion doping. Phosphine (PH) as doping gas ₃ ) And diborane (B ₂ H ₆ In the former case, the acceleration voltage is set in the range of 60 kV to 90 kV, for example, 80 kV, and in the latter case, the acceleration voltage is set in the range of 40 kV to 80 kV, for example, 65 kV, and the dose is 1 × 10 ^Fifteen cm ^-2 ~ 8 × 10 ^Fifteen cm ^-2 For example, phosphorus is 2 × 10 ^Fifteen cm ^-2 , Boron 5 × 10 ^Fifteen cm ^-2 And
[0108]
By this step, the regions which are masked by the gate electrodes 207n and 207p and into which the impurities are not implanted become channel regions 209n and 209p of the TFT later. At the time of doping, each element is selectively doped by covering a region not requiring doping with a photoresist. As a result, N-type impurity regions 210n and 211n and P-type impurity regions 210p and 211p are formed, so that an N-type TFT 217 and a P-type TFT 218 can be formed as shown in FIG.
[0109]
Next, as shown in FIG. 4D, annealing is performed by irradiation with a laser beam L2 to activate the ion-implanted impurities. As a laser beam, a XeCl excimer laser (wavelength: 308 nm, pulse width: 40 nsec) was used, and the laser beam was irradiated under an energy density of 250 mJ / cm. ² Irradiated 10 shots per location.
[0110]
Next, as shown in FIG. 4E, a silicon oxide film having a thickness of 600 nm is formed as an interlayer insulating film 213 by a plasma CVD method, a contact hole is formed in the silicon oxide film, and a metal material such as titanium nitride is formed. The electrodes / wirings 214, 215 and 216 of the TFT are formed by a two-layer film of aluminum. Finally, annealing is performed at 350 ° C. for one hour in a hydrogen atmosphere at 1 atm to complete a CMOS circuit using the N-type TFT 217 and the P-type TFT 218.
[0111]
In the CMOS structure circuit manufactured according to the second embodiment, the field-effect mobility of each TFT is 200 cm for an N-type TFT. ² / Vs ~ 300cm ² / Vs, 150cm with P-type TFT ² / Vs ~ 200cm ² / Vs, and the threshold voltage of the N-type TFT is 0.5V to 1V, and the threshold voltage of the P-type TFT is -2V to -3V, which is very good. Further, the leakage current in the TFT off region is suppressed to 5 pA for the N-type TFT and about 3 pA for the P-type TFT, which are lower than those of the conventional method. In addition, there was no generation of micro holes in the active region, which was a problem, and the production yield was greatly improved. Further, since the TFT size can be set smaller than that of the conventional method by etching by the RIE method, high integration is possible.
[0112]
(Other embodiments)
The present invention is not limited to the above-described two embodiments, and various modifications based on the technical idea of the present invention are possible.
[0113]
For example, in the above two embodiments, as a method for introducing nickel, a method of applying an ethanol solution in which a nickel salt is dissolved on the surface of an amorphous silicon film or a method of forming a nickel thin film by a vapor deposition method is selected. A method in which a trace amount of nickel is added and crystal growth is performed is employed. However, before the amorphous silicon film is formed, nickel may be selectively introduced into the surface of the base film, and nickel may be diffused from the lower layer of the amorphous silicon film to perform crystal growth. That is, crystal growth may be performed from the upper surface side or the lower surface side of the amorphous silicon film.
[0114]
Various other methods can be used as a method for introducing nickel. For example, water may be used simply as a solvent for dissolving a nickel salt, or SiOG may be used as a solvent using an SOG (spin-on-glass) material as a solvent. ₂ There is also a method of diffusing from a film. Further, a method of forming a thin film by a sputtering method or a plating method, a method of directly introducing a thin film by an ion doping method, and the like can also be used.
[0115]
Further, the same effect can be obtained by using cobalt, palladium, platinum, copper, silver, gold, indium, tin, aluminum or antimony other than nickel as the impurity metal element that promotes crystallization.
[0116]
Although the second heat treatment is performed in an HCl atmosphere, the second heat treatment is effective in a dry oxygen atmosphere, a nitrogen atmosphere, or the like from the viewpoint of improving crystallinity. In addition, the step of etching the silicon film in the region containing a large amount of the catalytic element is of course effective even by a method other than the above-described two embodiments. In particular, the method is such that nickel silicide can be etched simultaneously with the silicon film. If there is no problem.
[0117]
Further, as an application of the present invention, in addition to an active matrix type substrate for a liquid crystal display, for example, a contact type image sensor, a thermal head with a built-in driver, an optical writing device with a built-in driver using an organic EL or the like as a light emitting element , A display element, a three-dimensional IC, and the like. By using the present invention, high performance such as high speed and high resolution of these elements is realized. Further, the present invention is not limited to the MOS transistor described in the above embodiment, and can be widely applied to all semiconductor processes including a bipolar transistor using a crystalline semiconductor as an element material and an electrostatic induction transistor.
[0118]
In the above two embodiments, quartz glass is used as the insulating substrate. However, the present invention is not limited to this. If the substrate having an insulating surface or the entire substrate is insulating, Any may be used.
[0119]
【The invention's effect】
According to the present invention described above, a catalyst element is selectively introduced into an amorphous silicon film formed on an insulating substrate, and the first heat treatment laterally crystallizes from the catalyst element introduction region to the peripheral region. After the growth, prior to the second heat treatment step for improving the crystallinity of the crystalline silicon film region, a step of removing the specific silicon film region where the catalytic element is localized is performed. It is possible to prevent re-diffusion of the catalytic element which has occurred conventionally by the heat treatment of No. 2.
[0120]
For this reason, it is possible to solve the above-described problem such as generation of minute holes in the crystalline silicon film, and to realize a very high performance thin film semiconductor device. Moreover, a high-performance semiconductor device with a high degree of integration can be obtained by a simple manufacturing process.
[0121]
Further, the non-defective product rate can be greatly improved in the manufacturing process, and the cost of the product can be reduced. In particular, in a liquid crystal display device having several hundred thousand TFT elements, it is possible to dramatically improve the non-defective product rate, to improve the switching characteristics of the pixel switching TFT required for the active matrix substrate, and to use a peripheral drive circuit unit. High performance and high integration required for the constituent TFTs can be satisfied at the same time.
[0122]
Therefore, it is possible to realize a driver monolithic active matrix substrate that forms an active matrix portion and a peripheral drive circuit portion on the same substrate, and it is possible to reduce the size, performance, and cost of the module.
[0123]
In particular, The silicon film region left in the third step is at least a region where the catalyst element is introduced in the first step and a crystal growth boundary formed by crystal growth in the second step. Then In addition, the main uneven distribution region of the catalyst element can be removed, and the re-diffusion of the catalyst element generated in the second heat treatment can be prevented.
[0124]
Also, In particular, The silicon film region left in the third step is defined as a semiconductor device region. Then In addition to shortening the process, all unnecessary regions can also be removed, so that the amount of diffusion of the catalytic element into the semiconductor element region can be further reduced.
[0125]
Also, In particular, The third step is performed by etching, and the silicon film portion, the catalytic element and the silicide compound of the catalytic element contained in the silicon film portion are removed together by the etching. Then In addition, the problem that the catalyst element remains and re-diffuses when the silicon film is removed can be solved.
[0126]
In particular, when this etching is performed using a mixed solution of hydrofluoric acid and nitric acid, the catalyst element can be simultaneously etched together with the silicon film, and a clean surface state without residue in the removal region can be obtained. When dry etching is performed by RIE using a chlorine gas or a chlorine-based gas, a clean surface state with no residue in a removed region can be obtained, which is effective for fine processing.
[0127]
Also, In particular, The step of selectively introducing the catalyst element in the first step is performed by forming a mask at a position corresponding to a region where the catalyst element is not introduced in the amorphous silicon film. When you do By removing the catalytic element present on the mask before the first heat treatment for crystallization, it is possible to prevent a phenomenon in which the catalytic element is diffused from the mask. In addition, at the time of the first heat treatment, the total amount of catalyst elements on the substrate to be put into the heat treatment furnace can be significantly reduced, so that contamination of the heat treatment furnace due to the catalyst elements can be reduced.
[0128]
Also, In particular, The step of selectively introducing the catalyst element in the first step is performed by depositing the catalyst element in a thin film on the surface of the amorphous silicon film by a sputtering method or a vacuum evaporation method using a photoresist as a mask. By removing the resist and lifting off the catalytic element on the mask When you do In addition, the selective introduction of the catalyst element can be completed. Further, it is not necessary to form a mask film such as a silicon oxide film, so that the process can be shortened.
[0129]
Also, In particular, In the step of selectively introducing the catalyst element in the first step, using a silicon oxide film or a silicon nitride film as a mask, a solution in which the catalyst element is dissolved is applied to the surface of the amorphous silicon film and dried. By pre-annealing and removing the silicon oxide or silicon nitride film mask When you do By controlling the concentration of the catalytic element in the solution in which the catalytic element is dissolved, it is possible to control the amount of the catalytic element introduced on the substrate to a very small amount. Further, the problem that the catalyst element is removed simultaneously by removing the mask can be solved.
[0130]
In particular, when an acetate or nitrate of a catalytic element is used as a solute of this solution, and an alcohol is used as a solvent of the solution, stable crystal growth can be obtained over the entire substrate, and excellent in-plane uniformity can be obtained on a large substrate such as a liquid crystal. Sex can be obtained. Further, when the step of applying and drying the solution on the surface of the amorphous silicon film is performed by spin coating and spin drying using a spin coater, the catalytic element can be uniformly added to the substrate surface.
[0131]
In addition, in this pre-annealing process, at least a part of the region where the catalytic element is selectively introduced in the amorphous silicon film is heated in a heating state satisfying a condition for crystal growth, for example, in a processing temperature range of 500 ° C. to 550 ° C. If the treatment time is within the range of 10 to 30 minutes, the catalytic element can be added only to the desired region, so that the selective introduction region of the catalytic element in the amorphous silicon film is further limited. To grow crystals.
[0132]
Also, In particular, The temperature of the second heat treatment is higher than the temperature of the first heat treatment. Then In the first heat treatment, a crystalline silicon film can be formed by stable crystal growth, and in the second heat treatment, crystal defects generated in the crystallization step of the first heat treatment can be significantly reduced. Thus, the quality of the crystalline silicon film formed by the first heat treatment can be further improved.
[0133]
In particular, when the temperature of the first heat treatment is in the range of 540 ° C. to 620 ° C. and the temperature of the second heat treatment is in the range of 800 ° C. to 1100 ° C., in the first heat treatment, Spontaneous crystal growth irrespective of the catalytic element generated outside the introduction region can be suppressed, and stable crystal growth can be obtained. In addition, in the second heat treatment, crystal defects can be efficiently reduced, and each of the columnar crystals in the lateral crystal growth region forming the semiconductor element region is recombined into very high quality single crystal silicon. A comparable highly crystalline silicon film can be obtained.
[0134]
Also, In particular, The second heat treatment is performed in an oxidizing atmosphere containing a halide. When you do In addition, the impurity gettering effect of the halide can greatly reduce the concentration of the catalyst element used for crystal growth in the film. Further, by supplying supersaturated Si atoms generated by the oxidizing action into the silicon film, crystal defects, in particular, dangling bonds (unpaired bonds) can be eliminated more efficiently. In particular, when HCl gas is used as a halide, the catalyst element can be chlorided and vaporized, and the catalyst element can be efficiently removed from the silicon film.
[0135]
Also, In particular, In the second step, the direction in which the amorphous silicon film is crystal-grown from the region where the catalytic element is introduced to the peripheral region is substantially parallel to the direction in which carriers move in the semiconductor device. Then In theory, there is no crystal grain boundary serving as a trap when carriers move in the moving direction, so that a semiconductor device having higher mobility can be obtained.
[0136]
Also, In particular, As a catalyst element, one or more elements among Ni, Co, Pd, Pt, Cu, Ag, Au, In, Sn, Al and Sb When used The effect of promoting crystallization is obtained with a small amount.
[0137]
In particular, when at least Ni is used as this catalyst element, Ni bonds to the silicon film and silicide NiSi ₂ As a result, the crystal structure acts as a kind of template when the amorphous silicon film is crystallized, so that it has a further effect of promoting the crystallization of the amorphous silicon film.
[Brief description of the drawings]
FIG. 1 is a plan view illustrating a manufacturing process according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1 showing the manufacturing process of Embodiment 1 of the present invention.
FIG. 3 is a plan view illustrating a manufacturing process according to a second embodiment of the present invention.
FIG. 4 is a cross-sectional view taken along the line BB ′ of FIG. 3 illustrating the manufacturing process of Embodiment 2 of the present invention.
FIG. 5 is a view showing a state in which minute holes are generated in a silicon film due to re-diffusion of a catalyst element in a second heat treatment in a conventional example. A plan view after the crystal growth is shown, and a plan view after the second heat treatment is shown in FIG.
FIG. 6 is a diagram showing a state of diffusion of a catalytic element in a first heat treatment in a conventional example.
FIG. 7 is a photograph showing a state in which minute holes are generated on the surface of a silicon film due to re-diffusion of a catalytic element in a second heat treatment in a conventional example.
[Explanation of symbols]
101, 201 quartz glass substrate
102,202 Silicon film
103, 203 mask film
104, 204 catalytic element
106, 206 Gate insulating film
107, 207 Gate electrode
108 Anodized layer
109, 209 channel area
110, 210 source area
111, 211 drain region
113, 213 interlayer insulating film
114, 115, 214, 215, 216 Electrode and wiring
117,217 N-channel TFT
218 P-channel TFT

Claims (7)

A first step of forming an amorphous silicon thin film on an insulating substrate, and selectively introducing a catalyst element that promotes crystallization of the amorphous silicon film into the amorphous silicon film;
A second step of performing a first heat treatment at a temperature of 540 to 620 ° C. to cause the amorphous silicon film to grow in a lateral direction from the region where the catalytic element is introduced to a peripheral region thereof;
As the specific silicon film region where the catalyst element is localized, at least a region where the catalyst element is introduced in the first step and a crystal growth boundary formed by the crystal growth in the second step. A third step of removing the portion together with the catalyst element and the silicide compound of the catalyst element contained in those portions by etching using a mixed solution of hydrofluoric acid and nitric acid ;
In an oxidizing atmosphere containing a halide, a second heat treatment is performed at a temperature of 800 to 1100 ° C. higher than the temperature of the first heat treatment, and the crystalline silicon film region left in the third step And a fourth step of removing the catalytic element while improving the crystallinity of the semiconductor device. 2. The method according to claim 1, wherein the silicon film region left in the third step is a semiconductor element region. 3. The method according to claim 1 , wherein the step of selectively introducing the catalyst element in the first step is performed by forming a mask at a position corresponding to a region where the catalyst element is not introduced in the amorphous silicon film. 13. The method for manufacturing a semiconductor device according to item 5. In the step of selectively introducing the catalyst element in the first step, the catalyst element is deposited in a thin film on the surface of the amorphous silicon film by a sputtering method or a vacuum evaporation method using a photoresist as a mask. 3. The method of manufacturing a semiconductor device according to claim 1 , wherein the photoresist is peeled off and the catalyst element on the mask is lifted off. The step of selectively introducing the catalyst element in the first step includes, using a silicon oxide film or a silicon nitride film as a mask, applying a solution in which the catalyst element is dissolved on the surface of the amorphous silicon film and drying the solution. 3. The method of manufacturing a semiconductor device according to claim 1 , wherein the method is performed by performing a pre-annealing process after removing the mask to remove a mask of the silicon oxide film or the silicon nitride film. 4. In the second step,
Any one of claims 1 to 5 for the amorphous silicon film from the catalytic element is introduced region and its surrounding region and the direction of crystal growth, and substantially parallel to the moving direction of carriers in a semiconductor device 13. The method for manufacturing a semiconductor device according to item 5. 7. The catalyst element according to claim 1 , wherein one or more of Ni, Co, Pd, Pt, Cu, Ag, Au, In, Sn, Al and Sb are used. Manufacturing method of a semiconductor device.

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