JPH11186164A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent generation of fine holes in a crystalline silicon film, by laterally crystal-growing an amorphous silicon film from a region into which catalyst elements are introduced to its peripheral region by first heat treatment, eliminating a specified silicon film in which catalyst elements partially exisist, and performing second heat treatment. SOLUTION: Crystal growth is laterally performed from a peripheral region of a region 100 (102a) which is crystallized by first heat treatment, and a crystalline silicon film 102b which is laterally crystal-grown is formed. Nickel 104 partially exsists in an interface 102d between the catalyst elements introduced region 102a (100), the crystalline silicon film 102b which is laterally crystal- grown and an amorphous silicon film region 102c. When a silicon film 102 of an unnecessary part is eliminated and element isolation is performed, nickel 104 is etched together with the silicon film 102, in the regions 102a and 102d in which a great deal of nickel 104 exists. Second heat treatment is performed, and crystallinity of a crystalline silicon film 102f is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a crystalline silicon film obtained by crystallizing an amorphous silicon film is used as an active region.

[0002]

2. Description of the Related Art In recent years, large and high resolution liquid crystal display devices have been developed.
High-speed, high-resolution contact image sensor, 3D IC
In order to realize such a technique, attempts have been made to form a high-performance semiconductor element on an insulating substrate such as glass or on an insulating film. In general, a thin film silicon semiconductor is used for a semiconductor element used in these devices. As the thin film silicon semiconductor, an amorphous silicon semiconductor (a-Si)
And those composed of crystalline silicon semiconductors.

[0003] Amorphous silicon semiconductors are most commonly used because they have a low production temperature and can be produced relatively easily by a gas phase method and have high mass productivity. However,
Since physical properties such as conductivity are inferior to crystalline silicon semiconductors, in order to obtain even higher speed characteristics in the future, it is strongly required to establish a method for manufacturing a semiconductor device made of crystalline silicon semiconductor. Was. In addition, as a silicon semiconductor having crystallinity, polycrystalline silicon, microcrystalline silicon, amorphous silicon containing a crystalline component, semi-amorphous silicon having an intermediate state between crystalline and amorphous, and the like are known. .

The following methods are known as conventional methods for obtaining these crystalline silicon semiconductors in the form of thin films.

(1) A film having crystallinity is directly formed at the time of film formation.

(2) An amorphous semiconductor film is formed,
Crystallinity is imparted by the energy of laser light.

(3) An amorphous semiconductor film is formed in advance,
Crystallinity is imparted by applying heat energy.

However, in the method (1), crystallization proceeds simultaneously with the film formation step, so that it is necessary to increase the thickness of the silicon film in order to obtain crystalline silicon having a large grain size. It is technically difficult to uniformly form a film having the above on the substrate over the entire surface.

In the method (2), the crystallization phenomenon in the melt-solidification process is used, so that the grain boundaries are favorably processed in spite of the small grain size, and a high-quality crystalline silicon film can be obtained. Taking a generally used excimer laser as an example, a sufficiently stable one has not yet been obtained.
Therefore, it is difficult to uniformly treat the entire surface of a large-area substrate, and further technical improvement in hardware is desired.

Further, the method (3) comprises the steps (1) and (2)
Compared to the method described above, it is advantageous in terms of uniformity and stability in the substrate, and is used for ultra-small high-definition liquid crystal panels using a quartz substrate. However, in this case, after the crystal is grown by heat treatment at 600 ° C. for a long time of about 30 hours, heat treatment for improving the crystallinity at a higher temperature, for example, about 1000 ° C. for several tens minutes to several hours is performed. Is going. That is, there is a problem that the processing time is long and the throughput is low, and the field effect mobility of a TFT (thin film transistor) is 100 cm ² as a device characteristic.
/ Vs only.

In contrast to these methods, a method of improving the above method (3) to obtain a high-quality crystalline silicon film has been proposed in JP-A-7-94757 and JP-A-9-148245. In these methods, the use of a catalytic element that promotes crystallization of the amorphous silicon film aims at lowering the heating temperature, shortening the processing time, and improving the crystallinity.

Specifically, a minute amount of a metal element such as nickel or palladium is introduced into the surface of the amorphous silicon film, and then heating is performed. The mechanism of this low-temperature crystallization is understood from the fact that crystal nucleus generation with a metal element as a nucleus occurs early, and then the metal element serves as a catalyst to promote crystal growth, and crystallization proceeds rapidly. . In this sense, these metal elements are hereinafter referred to as catalyst elements.
Crystalline silicon films grown by the promotion of crystallization by these catalytic elements have a twin structure in one grain of the crystalline silicon film crystallized by the ordinary solid phase growth method. The inside of the grain is composed of a number of columnar crystal networks, and the inside of each columnar crystal is in an almost ideal single crystal state.

Further, in the above publication, the catalyst element is selectively introduced into a part of the amorphous silicon film and heated, so that the other part is left in the state of the amorphous silicon film and selectively. By crystallizing only the region into which the element has been introduced, and further extending the heating time, the crystal is grown in a lateral direction (a direction parallel to the substrate) from the introduction region. Inside this lateral crystal growth region, columnar crystals whose growth directions are almost aligned in one direction are crowded, and the crystallinity is lower than that of the region where the catalytic element is directly introduced and crystal nuclei are generated randomly. It is a better area. Therefore, by using the crystalline silicon film in the lateral crystal growth region as the active region of the semiconductor device, the performance of the semiconductor device can be improved.

According to Japanese Patent Application Laid-Open No. 7-94757, such a high-quality crystalline silicon film is further irradiated with strong light such as laser light in an atmosphere containing a chloride gas or a fluoride gas. Further improve its crystallinity,
We manufacture high-performance semiconductor devices. Also, Japanese Patent Laid-Open No. 9-1
In Japanese Patent No. 48245, the high-quality crystalline silicon film is subjected to a second heat treatment at a temperature higher than the crystallization annealing temperature to further improve its crystallinity, and is used as a semiconductor element region.

[0015]

However, the above-mentioned conventional method for crystallizing a silicon film using a catalytic element has problems concerning the film quality and impurities of the crystalline silicon film.

With respect to the film quality, experiments conducted by the present inventors have revealed that each columnar crystal has good crystallinity, but contains crystal defects (dislocations) having a considerably high density as a whole. I have. Therefore, since the active region of the semiconductor device is formed with approximately one crystal orientation, a relatively high mobility can be obtained. On the other hand, the threshold voltage and the leak current are hardly reduced due to the high defect density.

Actually, when an N-channel TFT is manufactured using a crystalline silicon film crystallized using a catalytic element, the field effect mobility is 60 cm ² / Vs to 80 cm ^2.
/ Vs. However, this value is about twice as large as that of a conventional silicon film formed by solid phase growth without using a catalytic element, but is still not a sufficient value in view of application to a thin film integrated circuit and the like.

Regarding impurities, the catalytic element itself becomes a problem. That is, the catalyst element as described above greatly contributes to the crystallization of the amorphous silicon film, but thereafter is mainly localized at the crystal grain boundaries and remains in the crystalline silicon film. The presence of a large amount of these catalytic elements in the crystalline silicon film that forms the active region (semiconductor element region) of a semiconductor device impairs the reliability and electrical stability of devices using these semiconductors. And, of course, not preferred.

Particularly, an element such as nickel or palladium which efficiently acts as a catalyst for promoting crystallization of an amorphous silicon film forms an impurity level near the center of a band gap in silicon. Therefore, when a TFT is manufactured using a silicon film crystallized with these catalyst elements, phenomena such as an increase in leakage current and a decrease in reliability mainly during a TFT-off operation appear as the effects. That is, the catalyst element improves the current driving capability such as the field-effect mobility, the on-current, and the on-current rise coefficient (S coefficient) in the TFT element in order to improve the crystallinity of the channel region. As a price, the off characteristic and the reliability are deteriorated.

A method for solving these problems is disclosed in the above-mentioned JP-A-7-94757 and JP-A-9-148245.
It is proposed in the gazette.

In Japanese Patent Application Laid-Open No. 7-94757, the crystalline silicon film crystallized using a catalytic element is irradiated with strong light such as laser light to further improve its crystallinity. The problem of insufficient film quality is being solved.

However, in such a case, the problems of uniformity and stability conventionally associated with the laser annealing technique are added. That is, good film quality uniformity, which is a merit of solid-phase crystallization, is impaired, and the intended high-performance semiconductor device cannot be realized.

Regarding the problem of the catalytic element, it is stated that laser light irradiation is performed in an atmosphere containing a chloride gas or a fluoride gas to chlorinate or fluoridate the catalyst element to remove gettering. However, as a result of actual experiments by the present inventors by the same method, almost no gettering effect is obtained in such instantaneous laser annealing, and the catalytic element concentration in the silicon film cannot be significantly reduced. It was confirmed that.

On the other hand, Japanese Patent Application Laid-Open No. 9-148245 discloses a method of improving the crystallinity by performing a heat treatment at a higher temperature after crystallization annealing using a catalytic element. It has been confirmed from experiments conducted by the present inventors that a very high-quality crystalline silicon film can be obtained by this method. According to this method, an ultra-high performance TFT having a field effect mobility exceeding 300 cm ² / Vs is actually obtained. The device is being manufactured. Further, by performing the second heat treatment in an oxidizing atmosphere such as HCl, the gettering and removal of the catalyst element in the silicon film can be efficiently performed in addition to the improvement of the crystallinity.
Therefore, this method is very effective as a method for manufacturing a high performance thin film semiconductor device.

However, in this method, a new problem has arisen in conducting a trial production of TFTs in mass production. A new problem is the generation of microscopic holes in the silicon film. Actually, as shown in the photograph of FIG. 7, a hole 509 is generated in a portion where the silicon film has been lost. Initially, the present inventors found that as long as the catalyst element in the silicon film was gettered, the hole was removed from the silicon film by the removal of the catalyst element.
9 was expected in advance, and the position of the hole 509 was controlled, but the hole 509 was found in an unexpected region, that is, in the element formation region.

Here, the above problem will be described in detail with reference to FIG. FIG. 5A is a schematic plan view after solid phase crystal growth by selective addition of a catalytic element, and FIG. 5B is a schematic plan view after a problematic second heat treatment.

In FIG. 5A, regions 501 and 502 are shown.
Is the region into which the catalytic element is introduced. The catalytic element selectively introduced into this region crystallizes the regions 501 and 502 first, and causes crystal growth to the periphery thereof. As a result, crystal growth of the regions 503 and 504 is performed. At this time, in the regions 501 and 502, crystal growth is caused by random nucleation by the introduced catalyst element,
In the regions 503 and 504, crystal growth is performed in the direction of H3, and the growth directions are aligned in a pseudo one-dimensional manner. The region 505 which has not reached the crystal growth remains in the amorphous silicon state.

Due to the mechanism of crystal growth, the catalytic element moves at the tip of crystal growth, that is, at the boundary between the crystallized region and the amorphous region, and successively crystallizes the amorphous silicon film beyond that. . Therefore, the position where the catalyst element is unevenly distributed is the crystal grain boundary where the crystal growth has collided and the tip of the crystal growth. That is, in FIG. 5A, nucleation occurs randomly, and the inside of the catalyst element introduction regions 501 and 502 where the crystal grains collide with the lateral crystal growth regions (lateral growth regions) 503 and 504. A boundary 507 and a boundary 508 between the lateral growth regions 503 and 504 and the amorphous region 505
Are unevenly distributed in the three regions. Therefore, the semiconductor element region is formed using the lateral growth regions 503 and 504, for example, in an arrangement like the region 510.

However, after the second heat treatment, FIG.
As shown in (B), the presence of minute holes 509 with a substantially uniform density was observed over the entire surface of the film. That is, the lateral growth regions 503 and 504 to be used as the semiconductor element region 510
Such a hole 509 is also generated inside,
Holes 509 also occurred in the region 505 where the crystal growth by the catalytic element did not reach. When a semiconductor device is manufactured in such a state, a very high-performance semiconductor element can be locally realized. However, when the hole 509 covers an element region, a defect occurs in the element. Also, such a hole 50
No. 9 causes damage to a lower layer in a later etching step or the like, which leads to a decrease in reliability as a whole. Therefore, when this method is used, the yield in the semiconductor device manufacturing process is extremely low, and the application to a semiconductor device in which hundreds of thousands of TFTs are arranged on a substrate, such as an active matrix substrate for a liquid crystal display, is almost impossible. Impossible.

The present invention solves the above-mentioned problems of the prior art. In the second heat treatment for improving the crystallinity, re-diffusion of the catalytic element can be prevented. It is an object of the present invention to provide a method for manufacturing a semiconductor device which can solve a problem such as generation of a hole and can manufacture a semiconductor device having very high performance and high reliability with high yield.

[0031]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming an amorphous silicon thin film on an insulating substrate; A first step of selectively introducing a catalyst element that promotes the formation of a catalyst, and a first heat treatment, whereby the amorphous silicon film is laterally moved from a region where the catalyst element is introduced to a peripheral region thereof. A second step of performing crystal growth, a third step of removing a specific silicon film region in which the catalyst element is localized, and a second heat treatment, which are left in the third step. And a fourth step of improving the crystallinity of the crystalline silicon film region, thereby achieving the above object.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the present invention, the silicon film region to be removed in the third step is at least a region where the catalytic element is introduced in the first step. It is configured to be a crystal growth boundary formed by the crystal growth in the second step.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the third aspect, the silicon film region left in the third step is:
It is configured to be a semiconductor element region.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the present invention, the third step is performed by etching, and by this etching, the corresponding silicon film portion, the catalyst element contained in the portion, and the The catalyst element is configured to remove a silicide compound.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to the present invention, the step of selectively introducing the catalyst element in the first step is performed by using a region in the amorphous silicon film where the catalyst element is not introduced. Is formed by forming a mask at a position corresponding to.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the present invention, the step of selectively introducing the catalyst element in the first step is performed by a sputtering method or a vacuum evaporation method using a photoresist as a mask. After depositing the catalyst element in the form of a thin film on the surface of the amorphous silicon film, the photoresist is removed, and the catalyst element on the mask is lifted off.

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the present invention, the step of selectively introducing the catalyst element in the first step is performed by using a silicon oxide film or a silicon nitride film as a mask. Is applied to the surface of the amorphous silicon film and dried, and then pre-annealed to remove the mask of the silicon oxide film or the silicon nitride film.

According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor device, the temperature of the second heat treatment is set to be higher than the temperature of the first heat treatment.

According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device, the second heat treatment is performed in an oxidizing atmosphere containing a halide.

According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the second aspect, in the second step, a direction in which the amorphous silicon film is crystal-grown from a region where the catalytic element is introduced to a peripheral region thereof. And the moving direction of the carrier in the semiconductor device is made substantially parallel.

According to a eleventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the present invention, Ni, Co, Pd, P
It is configured to use one or more of t, Cu, Ag, Au, In, Sn, Al and Sb.

Hereinafter, the gist and operation of the present invention will be described.

Regarding the above-mentioned problem, the inventors of the present invention have conducted experiments and found that the above-mentioned minute holes are caused by the uneven distribution of the catalyst element, and the catalyst element is selectively oxidized and etched. It was confirmed. The problem is in Figure 5
Growth regions 503 and 504 and the amorphous region 50 in FIG.
5 means that a large amount of catalytic element is present such that holes are formed. It was confirmed that the main cause was re-diffusion of the catalytic element during the second heat treatment.

That is, after the crystallization annealing (first heat treatment) in FIG.
01 and 502 and the crystal growth boundaries 507 and 508, the catalyst element is unevenly distributed, but the catalyst element is re-diffused during the second heat treatment for further improving the crystallinity, and the lateral growth regions 503 and 504 and the catalyst are The catalytic element is also present at the same level in the region 505 that has not been grown by the element. As a result, the lateral growth region 5 where the element is to be formed is formed.
That is, a minute hole also occurs in 03 and 504.

Accordingly, the gist of the present invention is to selectively introduce a catalytic element into an amorphous silicon film formed on an insulating substrate,
After the crystal growth in the lateral direction from the catalytic element introduction region to the peripheral region by the first heat treatment, the catalytic element is localized before the second heat treatment step for improving the crystallinity of the silicon film. And removing a specific silicon film region. That is, before the catalyst element is re-diffused by the second heat treatment, in other words, while the catalyst element is unevenly distributed, the unevenly distributed region of the catalyst element is removed. As a result, the main source of the re-diffusion of the catalyst element generated in the second heat treatment is cut off, so that the above problem can be solved and a high-performance semiconductor device can be obtained with a high yield. .

That is, in the method of manufacturing a semiconductor device according to the present invention, at least the first step is to form an amorphous silicon thin film on an insulating substrate and to crystallize the amorphous silicon film on the amorphous silicon film. Is selectively introduced, and a first heat treatment is performed in the second step to grow the amorphous silicon film laterally from the region where the catalyst element is introduced to the peripheral region. The third step removes the silicon film in a specific region where the catalytic element is localized, performs the second heat treatment in the fourth step, and removes the crystallinity remaining in the third step. The crystallinity of the silicon film region is improved.

The silicon film in the region where the catalytic element is localized means a catalytic element introducing region where uneven distribution of the catalytic element is observed after crystallization annealing due to its growth mechanism, and a crystal growth boundary portion, that is, The main region is a boundary between the crystallized region and the uncrystallized region and a boundary where crystal growth has collided, and it is desirable that at least these regions be removed. That is, when the crystal growth is performed with the introduction pattern as shown in FIG. 5, the catalyst element introduction regions 501 and 502, the boundary 507 where the lateral crystal growths collide, the region crystallized by the lateral crystal growth. 50 between amorphous region and amorphous region
It is only necessary that at least three points of 8 have been removed. And
After that, the second heat treatment is performed.

In particular, it is desirable to perform patterning so that the silicon film region left in the third step becomes a semiconductor element region (active region of a semiconductor device). By removing the localized region of the catalyst element in this way, not only can the process be shortened, but also all unnecessary regions are removed.
For this reason, the diffusion amount of the catalyst element into the semiconductor element region can be further reduced. Of course, the semiconductor element region is formed, for example, at a position indicated by a region 510 using only the lateral growth regions 503 and 504 in FIG.

Here, in the step of removing the silicon film in the region where the catalytic element is localized, including the step of forming the semiconductor element region, it is important that the etching property between the target silicon film and the catalytic element is important. Become. That is, if the catalyst element remains without being etched even after the silicon film is removed, the substrate surface is re-diffused from there, and the effect of the present invention is impaired. In addition, damage to the lower layer,
This may cause disconnection of a bus line or the like formed thereon, lower reliability of the semiconductor element, and the like. Further, the present inventors have investigated and found that many catalytic elements exist in the silicon film as silicide compounds. Therefore, as the third step of removing the specific silicon film region where the catalyst element is localized in the present invention, at the same time as the silicon film, the catalyst element and the silicide compound of the catalyst element are removed. Most preferably, it is performed by etching.

As a specific method for removing the silicon film in the region where the catalyst element is localized, it is desirable to remove the silicon film by etching using a mixed solution of hydrofluoric acid and nitric acid.
In this removal step, as described above, in addition to the silicon film, the catalytic element or its silicide compound must be etched at the same time. For that purpose, etching using a mixed solution of hydrofluoric acid and nitric acid is optimal, and the catalyst element is simultaneously etched together with the silicon film, so that a clean state with no residue in the removal area is obtained.

When microfabrication is desired, dry etching by plasma is effective. However, dry etching with a chlorofluorocarbon-based gas such as CF ₄ gas and an oxygen-based gas conventionally used for etching a silicon film is not effective. Although the silicon film is etched, the silicide compound is not etched, and the silicide compound due to the catalytic element remains on the substrate surface as a residue. If these silicide compounds remaining on the substrate cause re-diffusion during the second heat treatment, the effectiveness of the present invention is impaired.

Therefore, in dry etching, in addition to the silicon film, the catalyst element or its silicide compound must be etched at the same time. For this purpose, chlorine gas or chlorine-based gas such as BCl ₃ or HCl is used. The conventional RIE (reactive ion etching) method is very effective. By using such an RIE method, a clean state with no residue in the removal area can be obtained,
Fine processing becomes possible.

The main cause of the fine holes observed after the second heat treatment is the re-diffusion of the catalytic element during the second heat treatment as described above. However, as a result of repeating the experimental research by the present inventors, in addition to the above-mentioned causes, the lateral growth regions (503, 504 in FIG. 5) of the silicon film on which the semiconductor element region is provided can also be obtained by the introduction treatment of the catalytic element. ) And an amorphous region (505 in FIG. 5) which has not been grown by the catalyst element.

That is, as a conventional method for introducing a catalyst element,
As shown in FIG. 6A, a catalytic element 604 is introduced over the entire surface of a substrate mainly using a silicon oxide film 603 as a mask film, and then a first heat treatment for crystallization is performed. Here, reference numeral 601 denotes a substrate, and 602 denotes an amorphous silicon film. However, in such a conventional method, the first method is used.
6B, the introduction region 605 in contact with the catalyst element is crystallized and furthermore, as shown in FIG.
While the crystal growth proceeds, the silicon oxide film 6 serving as a mask
03 diffuses through the silicon oxide film 603 as indicated by an arrow H5, and the lower silicon film 6
02 has been reached.

Since the diffusion coefficient of the catalyst element in the silicon oxide film is much smaller than that in the silicon film, the catalyst element 604 is removed after the lateral crystal growth.
The catalyst element is present in a region that reaches the surface 02b and where the catalyst element should not normally exist. The catalyst element also exists in the amorphous region 602c where the crystal growth has not been reached for the same reason. In this case, after the first heat treatment for crystallization, the lateral growth region 6 has already been formed.
This is because the catalytic element exists in the region 02b and the amorphous region 602c which has not grown, and the effect and effectiveness of the present invention are greatly impaired.

Therefore, in order to maximize the effects of the present invention, the first step of selectively introducing a catalytic element into an amorphous silicon film is performed by using a silicon oxide film, a silicon nitride film, a photoresist, or the like. The first heat treatment is performed after covering the amorphous silicon film in a portion where the catalytic element is not introduced with the mask film, and after removing the mask film after introducing the catalytic element, the first heat treatment is performed. It is desirable to allow the film to grow in the lateral direction from the region where the catalytic element is introduced to the peripheral region. By this step, the catalyst element present on the mask is removed before the first heat treatment for crystallization, and the phenomenon that the catalyst element diffuses from the mask is completely eliminated. As a secondary effect, the first
In the heat treatment, the overall amount of the catalytic element on the substrate to be put into the heat treatment furnace is greatly reduced, so that contamination of the heat treatment furnace by the catalyst element can be reduced.

As a specific step of selectively introducing a catalyst element into an amorphous silicon film, a photoresist is used as a mask,
This is performed by depositing a catalyst element in a thin film on the surface of the amorphous silicon film by a sputtering method or a vacuum evaporation method, peeling off a photoresist mask, and lifting off the catalyst element on the mask. It is desirable to perform the heat treatment. Since the catalyst element formed in a thin film on the amorphous silicon film by the sputtering method or the vacuum evaporation method is not removed in the photoresist stripping step, the selective introduction of the catalyst element by this method should be completed. Becomes possible. In addition, there is no need to form a mask film such as a silicon oxide film, and the number of steps can be reduced.

As another method, using a silicon oxide film or a silicon nitride film as a mask, a solution in which a catalytic element is dissolved is applied to the substrate surface and dried, and then a pre-annealing treatment is performed before the first heat treatment. After performing, after removing the mask of this silicon oxide film or silicon nitride film,
The method of performing the first heat treatment is also effective. In this method, since a solution in which a catalytic element is dissolved is used, by controlling the concentration of the catalytic element in the solution, it becomes possible to control the amount of the catalytic element introduced on the substrate to a very small amount. However, the catalytic element applied on the silicon film has a weaker bond with the silicon film so that the catalyst element can be removed only by washing with water. Therefore,
In this method, the catalyst element is diffused into the silicon film in the introduction region by applying a solution to the substrate surface and drying it, and then performing a pre-annealing process. Therefore, even if the mask film is removed, the catalyst in the introduction region is removed. Elements are not removed.

However, since this pre-annealing requires a certain high temperature, a simple photoresist mask cannot be used, and a mask made of a silicon oxide film or a silicon nitride film is required. In addition, in the pre-annealing treatment, it is meaningless that the catalyst element diffuses in the silicon oxide film or the silicon nitride film and reaches the underlying silicon film. It is necessary to set conditions so as not to reach the lower silicon film. According to this method, the problem of generation of micro holes during the above-described second heat treatment can be solved, and a trace amount of the catalyst element can be controlled.

Here, in the solution in which the catalytic element is dissolved in the above method, it is desirable to use an acetate or nitrate of the catalytic element as a solute and to use an alcohol such as ethanol or isopropyl alcohol (IPA) as a solvent. By using such a solution, stable crystal growth can be obtained over the entire surface of the substrate. In particular, excellent in-plane uniformity can be obtained for a large substrate such as a liquid crystal substrate. When the acetate of the catalyst element used is insoluble in alcohol, the acetate may be first dissolved with a very small amount of water and then mixed with the alcohol as the main solvent.

Further, the step of applying the solution in which the catalyst element is dissolved on the substrate surface and drying it is desirably performed by spin coating and spin drying using a spin coater. According to this method, the catalyst element can be uniformly added to the substrate surface. Actually, in the experiments of the present inventors, the application and drying of a solution by this method on a glass substrate of 320 mm × 400 mm size resulted in a distribution of the surface concentration of the catalytic element within a range of approximately ± 10%. It was confirmed that.

The pre-annealing performed before the first heat treatment includes a step of removing a mask film in a later step.
It is necessary that the catalyst element in the introduction region is not removed. Hydrofluoric acid is generally used to remove a silicon oxide film or a silicon nitride film used as a mask film, but most of the catalytic elements are removed by this etchant.

That is, in the pre-annealing treatment performed before the first heat treatment in the present invention, it is necessary to sufficiently diffuse the catalyst element into the silicon film in the catalyst element introduction region. At least a part of the selective introduction region of the catalytic element in the porous silicon film needs to be crystal-grown. Therefore, it is preferable that the pre-annealing performed before the first heat treatment be performed at a heating temperature and a heating time that satisfy the above conditions. Then, the catalyst element is not simultaneously removed by removing the mask, and sufficient crystal growth is performed by the first heat treatment.

The present invention is characterized in that the second heat treatment is performed after the first heat treatment. However, the heat treatment temperatures of these heat treatments are higher than the first heat treatment temperature. It is necessary that the heat treatment temperature of No. 2 is at least higher. That is, the first heat treatment aims at crystallization of the amorphous silicon film, and the second heat treatment aims at further improving the crystallinity of the silicon film crystallized by the first heat treatment. The so-called crystallinity improving process is performed.

For this purpose, the first heat treatment needs to be performed at a relatively low temperature. This is because, when the first heat treatment is performed at a high temperature, the crystallization speed is too high, so that crystal nuclei are randomly generated over the entire surface of the substrate, and the crystal growth direction branches in various ways, so that stable crystal growth can be expected. Absent. As the second heat treatment, it is necessary to apply energy at least equal to or higher than the first heat treatment in order to further improve the quality of the crystalline silicon film formed in the first heat treatment. Crystal defects generated in the crystallization step of the first heat treatment can be significantly reduced.

Specifically, the temperature of the first heat treatment is 5
The second heat treatment is preferably performed at a temperature in the range of 40 ° C to 620 ° C and a temperature of 800 ° C to 1100 ° C. If the first heat treatment is performed in such a temperature range,
Spontaneous crystal growth that does not depend on the catalytic element generated outside the catalytic element introduction region can be suppressed, and stable crystal growth can be obtained. When the second heat treatment is performed in the above temperature range, crystal defects can be efficiently reduced, and each of the columnar crystals in the lateral crystal growth region forming the semiconductor element region is recombined. A highly crystalline silicon film comparable to high quality single crystal silicon is obtained.

In addition, by applying the above-mentioned catalyst element solution to the substrate surface, the first method in the method of adding a catalyst element is used.
Pre-annealing performed before the heat treatment of
It is desirable to perform the heating for 10 to 30 minutes within the range of from 550 to 550 ° C. By this pre-annealing treatment, at least a part of the selective introduction region of the catalyst element can be grown in the amorphous silicon film.

Here, the second heat treatment is preferably performed in an oxidizing atmosphere containing a halide. By performing the second heat treatment in such an atmosphere, the impurity gettering action of the halide allows
The concentration of the catalyst element used for crystal growth in the film can be greatly reduced. In addition, the supersaturated S generated by the oxidation action
By supplying i atoms into the silicon film, crystal defects, in particular, dangling bonds (unpaired bonds) can be eliminated more efficiently.

Further, it is desirable to use HCl gas as the oxidizing atmosphere containing a halide in the second heat treatment. By using HCl gas, the catalyst element can be chlorided and vaporized, and the catalyst element can be efficiently removed from the silicon film.

In the present invention, in order to realize a semiconductor device with higher mobility and higher performance, the direction of crystal growth of the silicon film by the catalytic element and the direction of carrier movement in the semiconductor device should be substantially parallel. desirable. This allows
A grain boundary that becomes a trap when carriers move is theoretically not present in the moving direction,
A semiconductor device having higher mobility can be obtained. Actually, some bending or branching of the columnar crystal occurs in the lateral crystal growth region, but with such a configuration, the trap amount such as the crystal grain boundary in the carrier moving direction is reduced. Will definitely drop.

The types of catalyst elements that can be used in the present invention include Ni, Co, Pd, Pt, Cu, Ag, Au, and I.
n, Sn, Al, and Sb can be used. One or a plurality of elements selected from these elements have an effect of promoting crystallization in a small amount.

Among them, the most remarkable effect can be obtained particularly when Ni is used. The following model can be considered for this reason. The catalyst element does not act alone, but acts on crystal growth by bonding to the silicon film to form silicide. The model is such that the crystal structure at that time acts like a kind of template when the amorphous silicon film is crystallized, and promotes the crystallization of the amorphous silicon film. Ni forms silicide of _two Si and NiSi2. Ni
Si ₂ exhibits a fluorite-type crystal structure, which is very similar to the diamond structure of single crystal silicon. Moreover, NiSi ₂ has a lattice constant of 0.540.
6 nm, which is very close to the lattice constant of 0.5430 nm in the crystalline silicon diamond structure. Therefore, NiSi ₂ is the best as a template for crystallizing an amorphous silicon film, and Ni is most preferably used as a catalyst element in the present invention.

[0073]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below with reference to the drawings.

(Embodiment 1) FIGS. 1 and 2 show Embodiment 1 showing a process of manufacturing an N-channel TFT (N-type TFT) by the method of the present invention. Hereinafter, the manufacturing steps will be described in the order of progress of the steps (A) to (F) in FIG.

First, as shown in FIG. 2A, the surface of the quartz glass substrate 101 is cleaned with about 1% hydrofluoric acid, and then the substrate 101 is subjected to a low pressure CVD method or a plasma CV method.
According to the D method, the thickness is 25 nm to 100 nm, for example, 50 nm.
nm (I-type) amorphous silicon film (a-Si film) 1 nm
02, and an insulating thin film 103 such as a silicon oxide film or a silicon nitride film is deposited thereon. The insulating thin film 103 serves as a mask film when a catalytic element is introduced later. In the first embodiment, a silicon oxide film is used, and TEOS (Tetra Ethoxy Ortho) is used.
(Silicate) as a raw material, and was decomposed and deposited by RF plasma CVD together with oxygen. The thickness of the mask silicon oxide film 103 is desirably 50 nm to 250 nm. If the thickness is smaller than this, the catalytic element diffuses to the lower layer. If the thickness is larger than this, crystal growth cannot be performed well. Therefore, in the first embodiment, the thickness of the silicon oxide film 103 is set to 150
nm.

Next, a mask is formed by patterning the silicon oxide film 103. Here, the mask 10
A-Si film 1 in a slit shape through the through hole 3
02 is exposed. That is, when the state of FIG. 2A is viewed from above, as shown in FIG.
At 0, it is exposed in a slit shape by a through hole, and the other portions are in a masked state.

After providing the mask 103, the mask 103 shown in FIG.
As shown in FIG. 1A, a substrate 101 is held so that an ethanol solution in which nickel 104 is dissolved is in contact with a region 100 where the surface of an a-Si film 102 is exposed. In the first embodiment, nickel acetate was used as the solute, and the nickel concentration in the ethanol solution was adjusted to 10 ppm. After that, the aqueous solution is uniformly spread on the substrate 101 by a spinner and dried, so that nickel 104 is formed on the surface of the silicon oxide film 103 and the a-Si film 102 on the substrate 101.
Is added in a trace amount. By this step, nickel 104 is selectively applied to the portion of the a-Si film 102 exposed in the region 100.
Has been introduced. Then, this is treated in an inert atmosphere, for example, in a nitrogen atmosphere, at a processing temperature of 500 ° C. to 550.
A pre-annealing treatment is performed within a range of 10 ° C. for 10 minutes to 30 minutes. In the first embodiment, the heat treatment was performed at 530 ° C. for 20 minutes.

In this pre-annealing process, FIG.
As shown in (B), in the region 100, a-Si
Substrate 10 with nickel 104 added to the film surface as a nucleus
Crystallization of the silicon film 102 occurs in a direction perpendicular to the direction 1, and a crystalline silicon film 102a is formed. In addition, the region other than the distribution region 100 does not reach the crystal growth and remains as an a-Si region 102c in an amorphous state. At this time, the nickel 104 on the mask film 103 is blocked by the mask film 103 under the above annealing conditions, and the underlying a-Si film 10
2 cannot be reached.

Next, the silicon oxide film 1 used as a mask
03 is removed by etching. The etching was performed by wet etching using a 1:10 buffered hydrofluoric acid (BHF) having sufficient selectivity with the lower silicon film 102 as an etchant. Thereafter, the substrate 101 is again heated to 540 ° C. to 620 ° C. in an inert atmosphere, for example, in a nitrogen atmosphere.
A heat treatment (first heat treatment) is performed at a temperature of several hours to several tens of hours. In the first embodiment, for example, the treatment was performed at 580 ° C. for 11 hours.

In this heat treatment, as shown by an arrow H1 in FIG. 2C, the region 100 (102a) in the lateral direction (in a direction parallel to the substrate) extends from the peripheral region of the previously crystallized region 100 (102a). Crystal growth is performed to form a crystalline silicon film 102b that has grown horizontally. The other 102 regions are the amorphous silicon film regions 1 as they are.
02c. The nickel concentration in the laterally grown crystalline silicon film 102b is 8 × 10 ¹⁶ atoms.
The concentration of nickel in the crystalline silicon film 102a in the region 100 in which nickel is directly introduced and crystal-grown, which is also referred to as the seed region, is 1 × 10 ¹⁸ a / cm ^3.
It was about toms / cm ³ .

In the above crystal growth, the distance of crystal growth in the direction parallel to the substrate indicated by arrow H1 is 130 μm.
It was about. When this state is viewed from above the substrate, nickel 10 is formed at the catalyst element introduction region 102a (100) in FIG. 1 and at the boundary 102d between the crystalline silicon film region 102b and the amorphous silicon film region 102c that have grown in the lateral direction.
4 are localized.

Next, as shown in FIG. 2D, an unnecessary portion of the silicon film 102 is removed to perform element isolation. As the etching at this time, hydrofluoric acid and nitric acid are mixed at a ratio of 1: 1.
This was carried out by wet etching using so-called 1: 100 hydrofluoric and nitric acid mixed at 00. By this etching process, 102a and 102a where a large amount of nickel 104 is present
Also in the region d, the nickel 104 is etched together with the silicon film, so that a clean substrate surface with no etching residue can be obtained. That is, by this etching process,
A large amount of nickel 104 has already been removed outside the substrate. Through the above steps, an island-shaped crystalline silicon film 102f to be a source region, a drain region, and a channel region of a TFT, that is, an active region is formed.
(D) state is obtained.

Next, in the state of FIG. 2D, a second heat treatment is performed to improve the crystallinity of the island-shaped crystalline silicon film 102f. As the second heat treatment, heat treatment is performed at a temperature of 800 ° C. to 1100 ° C. for several tens minutes to several hours in an oxidizing atmosphere containing a halide. In the first embodiment,
Using a mixed gas of HCl and oxygen, the flow ratio of HCl was set to 3% of the total gas flow rate, and a heat treatment was performed at a substrate temperature of 950 ° C. for 25 minutes. By this step, the crystalline silicon film 102
The surface of f is oxidized uniformly, and the thickness of the crystalline silicon film 102f is reduced to about 35 nm. In addition, the crystallinity of the crystalline silicon film 102f is greatly improved, and nickel remaining in the film is reduced. Actually, the nickel concentration in the silicon film after the second heat treatment is 5 × 10 ¹⁵ atom
ms / cm ³ or less. At this time, in the island-shaped crystalline silicon film 102f, no fine holes, which have conventionally been a problem, are not generated.

Next, after removing the surface oxide film of the crystalline silicon film 102f by etching at 1:10 BHF, FIG.
As shown in (E), a thickness of 20 nm to 150 nm is formed so as to cover the crystalline silicon film 102f serving as the active region.
Here, a silicon oxide film of 100 nm is formed on the gate insulating film 10.
6 is formed. For the formation of this silicon oxide film, TEOS is used as a raw material here, and a substrate temperature of 150 is used together with oxygen.
C. to 600 C., preferably 300 C. to 450 C.
Within the range, was decomposed and deposited by RF plasma CVD.
It should be noted that TEOS is used as a raw material and the decompression
The substrate temperature is set at 350 ° C.
It may be formed in the range of 600 ° C., preferably in the range of 400 ° C. to 550 ° C. After the film formation, in order to improve the bulk characteristics of the gate insulating film itself and the interface characteristics between the crystalline silicon film and the gate insulating film, the process is performed at a processing temperature of 800 ° C. to 1000 ° C. in an oxidizing gas atmosphere for 30 hours. Annealing was performed within a range of minutes to 60 minutes.

Next, a thickness of 4
An aluminum film is formed in a range of 00 nm to 800 nm, for example, 600 nm. Then, the gate electrode 107 is formed by patterning the aluminum film. further,
The surface of this aluminum electrode is anodized to form an oxide layer 108 on the surface. This state corresponds to FIG. Anodization is performed in an ethylene glycol solution containing tartaric acid at 1% to 5%, and is initially 220V at a constant current.
The voltage is increased until the voltage is maintained for one hour. The thickness of the obtained oxide layer 108 is 200 nm. Since the oxide layer 108 has a thickness for forming an offset gate region in a later ion doping step, the length of the offset gate area can be determined in the anodic oxidation step.

Next, an impurity (phosphorus) is implanted into the active region by ion doping using the gate electrode 107 and the surrounding oxide layer 108 as a mask. Phosphine (PH ₃ ) is used as the doping gas, the acceleration voltage is in the range of 60 kV to 90 kV, for example, 80 kV, and the dose is in the range of 1 × 10 ¹⁵ cm ⁻² to 8 × 10 ¹⁵ cm ⁻² , for example, 2 ×. It shall be 10 ¹⁵ cm ^-2 . By this step, the regions 110 and 111 into which the impurities have been implanted,
The source and drain regions of T form a gate electrode 1
A region 109 which is masked by 07 and its surrounding oxide layer 108 and into which impurities are not implanted later becomes a channel region of the TFT. When this state is viewed from above the substrate, as shown in FIG. 1, the carrier movement direction in the TFT is the distribution direction of the source distribution 110 and the drain distribution 111.
The horizontal direction on the paper. On the other hand, the crystal growth direction of the silicon film forming the channel portion 109 is the direction of H1, and is arranged so as to be substantially parallel to the moving direction of the carrier. With such an arrangement, a TFT having a particularly high mobility can be realized.

Next, as shown in FIG. 2E, annealing treatment was performed by irradiation with laser light L1 to activate the ion-implanted impurities, and at the same time, the crystallinity deteriorated in the above-described impurity introduction step. Improve the crystallinity of the part. At this time, a XeCl excimer laser (wavelength: 308 nm, pulse width: 40 nsec) was used as a laser, and the energy density was 150 mJ / cm ^{2 to} 400 mJ /.
cm ² , preferably 200 mJ / cm ² to 250
Irradiation was performed within the range of mJ / cm ² . The sheet resistance of the N-type impurity (phosphorus) regions 110 and 111 thus formed was in the range of 200Ω / □ to 800Ω / □.

Next, a silicon oxide film or a silicon nitride film having a thickness of about 600 nm is formed as the interlayer insulating film 113.
When a silicon oxide film is used, if TEOS is used as a raw material and formed by a plasma CVD method with oxygen, or a reduced pressure CVD method or a normal pressure CVD method with ozone, a good interlayer insulation with excellent step coverage can be obtained. A film is obtained.
Plasma CVD using SiH ₄ and NH ₃ as source gases
The use of the silicon nitride film formed by the method has an effect of supplying hydrogen atoms to the interface between the active region and the gate insulating film and reducing dangling bonds that deteriorate TFT characteristics.

Next, a contact hole is formed in the interlayer insulating film 113, and a metal material, for example, a two-layer film of titanium nitride and aluminum is used to form a TFT electrode / wiring 114, 1
15 are formed. The titanium nitride film is provided as a barrier film for preventing aluminum from diffusing into the semiconductor layer. Finally, in a hydrogen atmosphere of 1 atm.
Annealing at 30 ° C. for 30 minutes is performed, and T shown in FIG.
FT117 is completed. This annealing treatment is performed for the purpose of terminating crystal defects in the silicon film remaining until the end, in particular, dangling bonds by terminating with hydrogen.

When this TFT 117 is used as an element for switching a pixel electrode, the electrode 114 or 11
5 is connected to a pixel electrode made of a transparent conductive film such as ITO,
A signal is input from the other electrode. Also, this TFT
When 117 is used for a thin film integrated circuit, the gate electrode 1
Further, a contact hole may be formed on the substrate 07 and a necessary wiring may be provided. Further, a protective film made of a silicon nitride film may be provided on the TFT 117 as needed.

The N-type T fabricated according to the first embodiment
FT117 has a field-effect mobility of 150 cm ² / Vs or more.
Very high-performance electrical characteristics of 250 cm ² / Vs and a threshold voltage of 1 V to 1.5 V were exhibited. Further, there is no microhole in the active region, which has conventionally occurred, and especially in an active matrix substrate for a liquid crystal display for driving hundreds of thousands of pixel TFTs, pixel defects due to the above-mentioned causes can be solved, and very high definition can be achieved. A liquid crystal display device with high display quality can be obtained. In addition, the substrate 101 under the introduction region 100 was hardly damaged by nickel, and as a result, the disconnection failure of the bus line was reduced, and the production yield was improved. Also, T
TFTs in which catalyst elements are particularly problematic in FT characteristics
The leakage current in the off region is 10 pA to 15 pA in the related art.
Was reduced to about 2 pA, which is not a problem.

Note that this TFT can be used not only as a driver circuit and a pixel portion of an active matrix type liquid crystal display device but also as an element constituting a CPU on the same substrate. Further, it goes without saying that the TFT can be applied not only to a liquid crystal display device but also to a thin film integrated circuit which is generally called.

(Embodiment 2) FIGS. 3 and 4 show a C-type TFT in which an N-type TFT and a P-type TFT are configured to be complementary by the method of the present invention.
Embodiment 2 is a diagram illustrating Embodiment 2 illustrating a process of manufacturing a circuit having a MOS structure on a quartz glass substrate. Hereinafter, the manufacturing process will be described in the order of progress of the steps (A) to (E) in FIG.

First, as shown in FIG. 4A, the surface of a quartz glass substrate 201 is washed with about 1% hydrofluoric acid, and then the substrate 201 is subjected to a low pressure CVD method or a plasma CVD method.
D method, an intrinsic (I-type) amorphous silicon film (a-S) having a thickness in the range of 25 nm to 100 nm, for example, 50 nm
An i film 202 is formed.

Next, a photosensitive resin (photoresist) is applied on the a-Si film 202, and is exposed and developed to form a mask 2
03. The a-Si film 202 is exposed in a slit shape in the region 200 by the through hole of the photoresist mask 203. That is, when the state of FIG. 4A is viewed from above, the a-Si film 2 is formed in the region 200 as shown in FIG.
02 is exposed, and the other portions are masked by the photoresist.

After providing the mask 203, FIG.
As shown in (1), a thin film of nickel 204 is deposited on the surface of the substrate 201. In the second embodiment, the thickness of the nickel thin film 204 is controlled to be 1 nm or less by increasing the distance between the deposition source and the substrate to a value larger than usual and decreasing the deposition rate. At this time, the surface density of the nickel 204 on the substrate 201 was actually measured to be 2 × 10 ¹³ at.
oms / cm ² .

Next, as shown in FIG. 4B, by removing the photoresist mask 203, the nickel thin film 204 on the mask 203 is lifted off, and the a-Si film 202 in the region 200 is selectively removed. This means that a very small amount of nickel 204 has been introduced. Then, this is heated under an inert atmosphere, for example, under a nitrogen atmosphere, at a heating temperature of 540 ° C.
Annealing is performed at 620 ° C., for example, at 580 ° C. for 11 hours to crystallize.

At this time, in the region 200, a-Si
Crystallization of the silicon film 202 occurs in a direction perpendicular to the substrate 201 with the nickel 204 added to the surface of the film 202 as a nucleus, and a crystalline silicon film 202a is formed.

Next, in the peripheral area of the area 200, FIG.
In (B), as indicated by an arrow H2, crystal growth is performed in a lateral direction (a direction parallel to the substrate) from the region 200, and a crystalline silicon film 202b is formed by lateral crystal growth. The other region 202 remains as it is as the amorphous silicon film region 202c. The nickel concentration in the laterally grown crystalline silicon film 202b is 1 × 10 ¹⁷
a atoms / cm ³ or so, the nickel concentration of the crystalline silicon film 202a in region 200 is added directly to the nickel crystal growth was about 2 × 10 ¹⁸ atoms / cm ^3.

In the above crystal growth, the crystal growth distance in the direction parallel to the substrate indicated by arrow H2 is 130 μm.
It is about. When this state is viewed from above the substrate, in FIG. 3, nickel is formed at the boundary 202d between the catalytic element introduction region 202a (200) and the crystalline silicon film region 202b and the amorphous silicon film region 202c which have grown in the lateral direction. 20
4 is localized.

Next, as shown in FIG.
The crystalline silicon film to be the active regions (semiconductor device regions) 202n and 202P of T is left, and other regions are removed by etching to perform device isolation. The etching at this time was performed by an RIE method using RF plasma using a mixed gas of BCl ₃ and Cl ₂ . As the etching conditions, the flow rate of BCl ₃ was 15 sccm, and the flow rate of Cl ₂ was 70 sccm.
cm, under a reduced pressure of about 8 mTorr, 1300 W
RF power was applied.

By this etching process, nickel 20
Even in the regions 202a and 202d where a large amount of 4 is present, the nickel 204 is etched together with the silicon film, so that a clean substrate surface with no etching residue can be obtained, and further fine processing can be performed as compared with the case where wet etching is used. it can. Through the above steps, the island-shaped crystalline silicon films 202n and 202p to be the source region, the drain region, and the channel region of the TFT, that is, the active regions later, are formed, and the state of FIG. 4C is obtained.

Next, a second heat treatment is performed in the state of FIG. 4C to improve the crystallinity of the island-shaped crystalline silicon films 202n and 202P. The second heat treatment is performed at a temperature of 800 ° C. to 11 ° C. in an oxidizing atmosphere containing a halide.
The heat treatment is performed within a range of 00 ° C. for several tens minutes to several hours.
In the second embodiment, a mixed gas of HCl and oxygen is used,
The flow rate ratio of Cl was set to 3% of the total gas flow rate, and the substrate temperature was set to 9%.
Heat treatment was performed at 50 ° C. for 25 minutes.

By this step, the silicon films 202n, 202
The surface of p is oxidized uniformly, and the thicknesses of the crystalline silicon films 202n and 202p are reduced to about 35 nm. Further, the crystallinity of the crystalline silicon films 202n and 202p is significantly improved, and nickel remaining in the films is reduced. Actually, the nickel concentration in the silicon film after the second heat treatment was reduced to 5 × 10 ¹⁵ atoms / cm ³ or less. At this time, the island-shaped crystalline silicon films 202n, 20
In 2p, no microhole, which had been a problem in the past, was generated at all.

Next, the island-shaped crystalline silicon films 202n, 2n
After the 02p surface oxide film is removed by etching with 1:10 BHF, the crystalline silicon film 202n serving as the above active region is formed.
And a silicon oxide film having a thickness of 100 nm is formed as the gate insulating film 206 so as to cover the gate insulating film 206p. Embodiment 2
In this example, TEOS was used as a film formation method for forming the gate insulating film 206, and was decomposed and deposited by RF plasma CVD at a substrate temperature of 350 ° C. together with oxygen.

Next, as shown in FIG. 4D, aluminum having a thickness of 400 nm to 800 nm, for example, 500 nm, for example, 500 nm (0.1% to 2%) is formed by sputtering.
Is formed, and an aluminum film is patterned to form gate electrodes 207n and 207p.

Next, the gate electrodes 207n and 207 are formed in the active regions 202n and 202p by the ion doping method.
Impurities (phosphorus and boron) are implanted using p as a mask. Phosphine (PH ₃ ) and diborane (B ₂ H ₆ ) are used as the doping gas. In the former case, the acceleration voltage is in the range of 60 kV to 90 kV, for example, 80 kV, and in the latter case, it is in the range of 40 kV to 80 kV. For example, 65k
V and the dose is 1 × 10 ¹⁵ cm ⁻² to 8 × 10 ¹⁵ cm
In the range of ^-2 for example phosphorus 2 × 10 ¹⁵ cm ^-2, the boron and 5 × 10 ¹⁵ cm ^-2.

By this step, the gate electrodes 207n, 207n,
The region which is masked at 07p and is not doped with impurities
FT channel regions 209n and 209p are obtained. At the time of doping, each element is selectively doped by covering a region not requiring doping with a photoresist. As a result, N-type impurity region 210n
311n and P-type impurity regions 210p and 211p are formed, and as shown in FIG.
T218 can be formed.

Next, as shown in FIG. 4D, annealing is performed by irradiation with a laser beam L2 to activate the ion-implanted impurities. XeCl as laser light
Excimer laser (wavelength 308 nm, pulse width 40 ns
Using ec), the laser beam was irradiated at an energy density of 250 mJ / cm ² for 10 shots at one location.

Next, as shown in FIG.
A 0 nm silicon oxide film is formed as an interlayer insulating film 213 by a plasma CVD method, a contact hole is formed in the interlayer insulating film 213, and a metal material, for example, a two-layer film of titanium nitride and aluminum is used to form a TFT electrode / wiring 214, 215.
And 216 are formed. Finally, annealing is performed at 350 ° C. for one hour in a hydrogen atmosphere at 1 atm to complete a CMOS circuit including the N-type TFT 217 and the P-type TFT 218.

The CMO fabricated according to the above-described Embodiment 2
In S configuration circuit, the field effect mobility of each TFT, an N-type TFT 200cm ² / Vs~300cm ² /
Vs, 150cm in the P-type TFT ² / Vs~200cm ² /
Vs, the threshold voltage is 0.5 V to 1 V for an N-type TFT,
P-type TFT shows very good characteristics of -2V to -3V. Furthermore, the leakage current in the TFT off region is also reduced by N-type TF.
The values are 5 pA for T and 3 pA for the P-type TFT, which are lower values than the conventional method. Further, there was no generation of micro holes in the active region, which was a problem, and the production yield was greatly improved. Further, since the TFT size can be set smaller than that of the conventional method by etching by the RIE method, high integration is possible.

(Other Embodiments) The present invention is not limited to the above two embodiments, and various modifications based on the technical idea of the present invention are possible.

For example, in the above two embodiments, as a method of introducing nickel, a method of applying an ethanol solution in which a nickel salt is dissolved on the surface of an amorphous silicon film, or a method of forming a nickel thin film by a vapor deposition method Therefore, a method of selectively adding a trace amount of nickel and performing crystal growth was adopted. However, before the amorphous silicon film is formed, nickel may be selectively introduced into the surface of the base film, and nickel may be diffused from a lower layer of the amorphous silicon film to perform crystal growth. That is, crystal growth may be performed from the upper surface side or the lower surface side of the amorphous silicon film.

Various other techniques can be used for introducing nickel. For example, water may be simply used as a solvent for dissolving a nickel salt, or SOG (spin-on-glass) material may be used as a solvent for Si.
There is also a method of diffusing from an O ₂ film. Further, a method of forming a thin film by a sputtering method or a plating method, a method of directly introducing a thin film by an ion doping method, and the like can also be used.

Further, the same effect can be obtained by using cobalt, palladium, platinum, copper, silver, gold, indium, tin, aluminum or antimony in addition to nickel as an impurity metal element for promoting crystallization.

Although the second heat treatment is performed in an HCl atmosphere, the second heat treatment is effective in a dry oxygen atmosphere or a nitrogen atmosphere from the viewpoint of improving the crystallinity. In addition, the step of etching the silicon film in the region containing a large amount of the catalytic element is of course effective even in a method other than the above two embodiments, and in particular, a method in which nickel silicide can be etched simultaneously with the silicon film. If there is no problem.

Further, as an application of the present invention, in addition to the active matrix type substrate for liquid crystal display, for example, a contact type image sensor, a thermal head with a built-in driver, a driver built-in type using an organic EL as a light emitting element, etc. An optical writing element, a display element, a three-dimensional IC, and the like can be considered. By using the present invention, high performance such as high speed and high resolution of these elements is realized. Furthermore, the present invention
The present invention can be applied not only to the MOS transistor described in the above embodiment but also to a wide variety of semiconductor processes including a bipolar transistor using a crystalline semiconductor as an element material and an electrostatic induction transistor.

In the above two embodiments, quartz glass is used as an insulating substrate. However, the present invention is not limited to this, and a substrate having an insulating surface or a substrate having an insulating surface as a whole is used. Any may be used.

[0119]

According to the present invention, a catalytic element is selectively introduced into an amorphous silicon film formed on an insulating substrate,
After the crystal growth is performed in the lateral direction from the catalytic element introduction region to the peripheral region by the first heat treatment, before the second heat treatment step for improving the crystallinity of the crystalline silicon film region,
Since the step of removing the specific silicon film region where the catalytic element is localized is performed, re-diffusion of the catalytic element, which has conventionally occurred in the second heat treatment, can be prevented.

Therefore, it is possible to solve the above-mentioned problem that a minute hole is generated in the crystalline silicon film, and to realize a very high performance thin film semiconductor device. Moreover, a high-performance semiconductor device with a high degree of integration can be obtained by a simple manufacturing process.

Further, the non-defective product rate can be greatly improved in the manufacturing process, and the cost of the product can be reduced. In particular, in a liquid crystal display device having hundreds of thousands of TFT elements, the yield can be dramatically improved,
The switching characteristics of the pixel switching TFT required for the active matrix substrate can be improved, and the high performance and high integration required for the TFTs constituting the peripheral drive circuit can be satisfied at the same time.

Accordingly, a driver monolithic active matrix substrate constituting an active matrix portion and a peripheral drive circuit portion on the same substrate can be realized, and the module can be made compact, high-performance, and low in cost.

In particular, according to the method of manufacturing a semiconductor device of the second aspect, the silicon film region left in the third step is
Since at least a region where the catalytic element is introduced in the first step and a crystal growth boundary formed by crystal growth in the second step, a main unevenly distributed region of the catalytic element is removed,
It is possible to prevent the catalyst element from being re-diffused due to the second heat treatment.

According to the method of manufacturing a semiconductor device of the third aspect, the silicon film region left in the third step is used as a semiconductor element region. Since all necessary regions can be removed, the amount of diffusion of the catalytic element into the semiconductor element region can be further reduced.

According to the method of manufacturing a semiconductor device according to the fourth aspect, the third step is performed by etching, and by the etching, the corresponding silicon film portion, the catalyst element contained in the portion, and the Since the silicide compound of the catalyst element is also removed, the problem that the catalyst element remains and re-diffuses when the silicon film is removed can be solved.

In particular, if this etching is performed using a mixed solution of hydrofluoric acid and nitric acid, the catalyst element can be etched simultaneously with the silicon film, and a clean surface state free of residues in the removed area can be obtained. it can. Further, this etching is performed by using RI using chlorine gas or chlorine-based gas.
When dry etching is performed by the E method, a clean surface state without residue can be obtained in the removal region, which is effective in performing fine processing.

According to the method for manufacturing a semiconductor device of the present invention, the step of selectively introducing a catalytic element in the first step corresponds to the region of the amorphous silicon film where the catalytic element is not introduced. Since the mask is formed at a position where the catalyst element is formed, the catalytic element present on the mask is removed before the first heat treatment for crystallization, and the catalytic element is diffused from the mask. Generation can be prevented. In addition, at the time of the first heat treatment, the total amount of catalyst elements on the substrate to be put into the heat treatment furnace can be significantly reduced, so that contamination of the heat treatment furnace due to the catalyst elements can be reduced.

According to the method of manufacturing a semiconductor device according to the sixth aspect, the step of selectively introducing the catalyst element in the first step is performed by a sputtering method or a vacuum evaporation method using a photoresist as a mask. After depositing the catalyst element in the form of a thin film on the surface of the amorphous silicon film, the photoresist is peeled off and lift-off of the catalyst element on the mask is performed, so that the selective introduction of the catalyst element is completed. be able to. Further, it is not necessary to form a mask film such as a silicon oxide film, and the process can be shortened.

According to the method for manufacturing a semiconductor device of the present invention, the step of selectively introducing the catalyst element in the first step is performed by using the silicon oxide film or the silicon nitride film as a mask. After applying the dissolved solution to the surface of the amorphous silicon film and drying, the pre-annealing treatment is performed to remove the mask of the silicon oxide film or the silicon nitride film. By controlling the concentration of the catalyst element therein, it is possible to control the amount of the catalyst element introduced on the substrate to a very small amount.
In addition, the problem that the catalyst element is simultaneously removed by removing the mask can be solved.

In particular, when an acetate or nitrate of a catalytic element is used as a solute of this solution and an alcohol solvent is used as a solvent of the solution, stable crystal growth can be obtained over the entire surface of the substrate, which is excellent for a large substrate such as a liquid crystal. In-plane uniformity can be obtained. Further, when the step of applying and drying the solution on the surface of the amorphous silicon film is performed by spin coating and spin drying using a spin coater, the catalyst element can be uniformly added to the substrate surface.

The pre-annealing is performed by heating at least a part of the region of the amorphous silicon film into which the catalytic element has been selectively introduced, in a heating state satisfying the conditions for crystal growth, for example, at a processing temperature of 500 ° C. to 550 ° C. When the treatment is performed within the range of 10 minutes to 30 minutes within the range of ° C., the catalytic element can be added only to a desired region,
Crystal growth can be achieved by further limiting the selective introduction region of the catalyst element in the amorphous silicon film.

According to the method of manufacturing a semiconductor device of the present invention, since the temperature of the second heat treatment is higher than the temperature of the first heat treatment, the first heat treatment is stable. A crystalline silicon film can be formed by crystal growth. In the second heat treatment, crystal defects generated in a crystallization step of the first heat treatment can be significantly reduced. The quality of the obtained crystalline silicon film can be further improved.

Particularly, the temperature of the first heat treatment is set to 540
° C to 620 ° C and the temperature of the second heat treatment is 8
When the temperature is in the range of 00 ° C. to 1100 ° C., in the first heat treatment, spontaneous crystal growth irrespective of the catalyst element generated outside the catalyst element introduction region can be suppressed, and stable crystal growth can be obtained. . In addition, in the second heat treatment, crystal defects can be efficiently reduced, and each of the columnar crystals in the lateral crystal growth region forming the semiconductor element region is recombined to form very high-quality single crystal silicon. A comparable highly crystalline silicon film can be obtained.

According to the method of manufacturing a semiconductor device of the ninth aspect, since the second heat treatment is performed in an oxidizing atmosphere containing a halide, the crystal growth is performed by the impurity gettering action of the halide. The concentration of the catalyst element used in the film in the film can be greatly reduced. Further, by supplying supersaturated Si atoms generated by the oxidizing action into the silicon film, crystal defects, in particular, dangling bonds (unpaired bonds) can be eliminated more efficiently. In particular, when HCl gas is used as the halide, the catalyst element can be chlorided and vaporized, and the catalyst element can be efficiently removed from the silicon film.

According to the semiconductor device manufacturing method of the present invention, in the second step, the direction of crystal growth of the amorphous silicon film from the region into which the catalytic element has been introduced to the peripheral region may be determined. Since the direction of movement of carriers in the semiconductor device is substantially parallel, a crystal grain boundary serving as a trap when the carriers move is theoretically not present in the direction of movement, and has a higher mobility. A semiconductor device can be obtained.

According to the semiconductor device manufacturing method of the present invention, Ni, Co, P is used as the catalyst element.
d, Pt, Cu, Ag, Au, In, Sn, Al and S
Since one or more of the elements b are used, the effect of promoting crystallization can be obtained in a small amount.

In particular, at least N
When i is used, Ni bonds to the silicon film to form silicide Ni.
Although it becomes Si ₂ and acts on crystal growth, its crystal structure acts like a kind of template at the time of crystallization of the amorphous silicon film, so a further effect of promoting crystallization of the amorphous silicon film is provided. Play.

[Brief description of the drawings]

FIG. 1 is a plan view illustrating a manufacturing process according to a first embodiment of the present invention.

FIG. 2A is a view showing a manufacturing process according to the first embodiment of the present invention;
It is sectional drawing in the -A 'cross section.

FIG. 3 is a plan view illustrating a manufacturing process according to a second embodiment of the present invention.

FIG. 4B illustrates a manufacturing process according to a second embodiment of the present invention.
It is sectional drawing in the -B 'cross section.

FIG. 5 is a view showing a state in which a fine hole is generated in a silicon film by re-diffusion of a catalyst element in a second heat treatment in a conventional example. A plan view after the crystal growth is shown, and a plan view after the second heat treatment is shown in FIG.

FIG. 6 is a diagram showing a state of diffusion of a catalytic element in a first heat treatment in a conventional example.

FIG. 7 is a photograph showing a state in which minute holes are generated on the surface of a silicon film due to re-diffusion of a catalyst element in a second heat treatment in a conventional example.

[Explanation of symbols]

 101, 201 quartz glass substrate 102, 202 silicon film 103, 203 mask film 104, 204 catalytic element 106, 206 gate insulating film 107, 207 gate electrode 108 anodized layer 109, 209 channel region 110, 210 source region 111, 211 drain Region 113, 213 Interlayer insulating film 114, 115, 214, 215, 216 Electrode / wiring 117, 217 N-channel TFT 218 P-channel TFT

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hiromi Sakamoto 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (72) Inventor Tsukasa Shibuya 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside the corporation

Claims (11)

[Claims] A first step of forming an amorphous silicon thin film on an insulating substrate, and selectively introducing a catalyst element for promoting crystallization to the amorphous silicon film; A second step of performing a heat treatment of 1 to cause the amorphous silicon film to grow in a lateral direction from the region where the catalytic element is introduced to a peripheral region thereof; and A third step of removing a specific silicon film region, and a fourth step of performing a second heat treatment to improve the crystallinity of the crystalline silicon film region left in the third step. Semiconductor device manufacturing method. 2. The silicon film region to be removed in the third step is formed by at least a region where the catalyst element is introduced in the first step and the crystal growth in the second step. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a crystal growth boundary. 3. The method according to claim 1, wherein the silicon film region left in the third step is a semiconductor element region. 4. The method according to claim 1, wherein the third step is performed by etching, and the silicon film portion, the catalyst element and the silicide compound of the catalyst element contained in the silicon film portion are removed by the etching. Item 4. A method for manufacturing a semiconductor device according to any one of Items 3. 5. The step of selectively introducing the catalyst element in the first step is performed by forming a mask at a position corresponding to a region of the amorphous silicon film where the catalyst element is not introduced. A method for manufacturing a semiconductor device according to claim 1. 6. The step of selectively introducing the catalytic element in the first step, wherein the catalytic element is formed on the surface of the amorphous silicon film by a sputtering method or a vacuum deposition method using a photoresist as a mask. After being deposited in a thin film,
The method of manufacturing a semiconductor device according to claim 1, wherein the photoresist is peeled off, and the catalyst element on the mask is lifted off. 7. The step of selectively introducing the catalyst element in the first step includes, using a silicon oxide film or a silicon nitride film as a mask, applying a solution in which the catalyst element is dissolved to the amorphous silicon film. The method for manufacturing a semiconductor device according to claim 1, wherein the method is performed by applying a pre-annealing treatment after coating and drying the surface, and removing the mask of the silicon oxide film or the silicon nitride film. . 8. The temperature of the second heat treatment is changed to the first heat treatment.
The method for manufacturing a semiconductor device according to claim 1, wherein the temperature is higher than the temperature of the heat treatment. 9. The method of manufacturing a semiconductor device according to claim 1, wherein said second heat treatment is performed in an oxidizing atmosphere containing a halide. 10. In the second step, a direction in which the amorphous silicon film is crystal-grown from a region where the catalytic element is introduced to a peripheral region thereof is substantially parallel to a carrier moving direction in the semiconductor device. Claim 1
A method for manufacturing a semiconductor device according to claim 9. 11. Ni, Co, P as the catalyst element
d, Pt, Cu, Ag, Au, In, Sn, Al and S
(b) using one or more elements of b.
A method for manufacturing a semiconductor device according to claim 10.