JP2016206462A - Dot matrix type display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow extremely low power consumption to attain a display formed by combining a still image display and a rewriting display.SOLUTION: A dot matrix type display device includes: pixel electrode sections P11 to Pmn that are formed at a crossing section of a gate signal line GLn and an image signal line DLn, and include a drive section circuit 64 selecting any of a rewriting drive and a still image drive; a gate signal line drive circuit 3 that arbitrarily selects one line of a plurality of gate signal lines GL1 to GL128 to turn on the selected signal line; and an image signal line drive circuit 4 that arbitrarily selects one line of a plurality of image signal lines DL1 to DL128 to turn on the selected signal line. The drive selection circuit 64 includes a holding circuit 62 for subjecting the non-selected pixel electrode part Pmn, to the still image drive. The holding circuit 62 is an SRAM, and n-channel TFT element and p-channel TFT element of the holding circuit 62 are controlled so that an off-leak current value is low.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a dot matrix display device in which a large number of pixel electrode portions including thin film transistor (TFT) elements are formed on a substrate.

  Conventionally, for example, a liquid crystal display (LCD) has a TFT array side substrate on which a large number of pixel electrode portions including TFT elements are formed and a color filter side substrate on which a color filter and a black matrix are formed. Then, the substrates are bonded together at a predetermined interval, and liquid crystal is filled and sealed between the substrates.

  An example of a basic configuration of a conventional active matrix liquid crystal display device is shown in FIG. For example, the TFT array side substrate has a plurality of gate signal lines G1, G2, G3,... Gm formed in a first direction (row direction) thereon and a second crossing the first direction. A plurality of image signal lines S1, S2, S3,... Sn formed to intersect the gate signal line in the direction (column direction), and formed at the intersection of the gate signal line and the image signal line, This includes a TFT element 101 and pixel electrode portions P11, P12, P13,... Pmn including pixel electrodes (not shown). Further, a common electrode (also referred to as a reference electrode; not shown) and a common voltage line 102 that supplies a common voltage (Vcom) to the common electrode generate a vertical electric field applied to the liquid crystal between the pixel electrode. In order to form, it is provided on the color filter side substrate. In FIG. 12, 103 is a gate signal driving circuit, 104 is an image signal (source signal) driving circuit, 110 is a display unit, and 111 is a liquid crystal display panel.

  The TFT element 101 includes a semiconductor film made of, for example, amorphous silicon (a-Si), and has a three-terminal portion including a gate electrode portion, a source electrode portion, and a drain electrode portion. Then, a switching element (gate transfer element) that causes a current to flow through the semiconductor film (channel) between the source electrode part and the drain electrode part by applying a voltage of a predetermined potential (for example, 3V, 6V) to the gate electrode part. Function as. The pixel electrode is generally composed of a transparent conductor layer made of indium tin oxide (ITO) or the like.

  Further, the color filter side substrate is formed with red (R), green (G), and blue (B) color filters corresponding to the respective pixels on the surface on which the common electrode and the common voltage line are formed. A black matrix that prevents light passing through each pixel from interfering with each other is formed so as to surround the outer periphery of the color filter. Note that the color filter and the black matrix may be omitted if color display is not performed. In the case of a transmissive LCD, a backlight is provided, and in the case of a reflective LCD, there is no need for a backlight.

  In such an LCD, in order to reduce power consumption of external circuits, signal line drive circuits, etc. when displaying still images, each pixel has a storage circuit such as a static random access memory (SRAM) and a D circuit. A configuration having a / A (Digital / Analog) conversion circuit has been proposed (see, for example, Patent Documents 1 and 2 below). In other words, an SRAM (inverted logic circuit) such as a CMOS (Complementary Metal Oxide Semiconductor) inverter connected in a loop and a digital signal of n bits (n is a natural number) can be displayed in grayscale. D / A converter circuit that converts the signal to a simple analog signal. During the still image display period, only the DAC (Digital to Analog Converter) controller is driven to repeatedly read the digital video signal stored in the memory circuit. The analog signal gradation signal is obtained by performing D / A conversion, and a still image is displayed by the analog signal gradation signal. Then, the source signal line driver circuit and the gate signal line driver circuit are stopped when a still image is displayed. With this configuration, power consumption of an external circuit, a signal line driver circuit, and the like when displaying a still image can be reduced.

Japanese Patent Laid-Open No. 2002-162947 JP 2002-196306 JP

  However, the LCD having the conventional configuration describes a configuration for switching between a normal operation mode (analog operation mode) for displaying a moving image and a digital display mode (memory operation mode) for displaying a still image. However, there is no disclosure about the point of performing display that combines still image display and moving image display with lower power consumption.

An SRAM as a storage circuit used in the conventional LCD or the like is configured by connecting in series two inverters each having a drain connected to a p-channel TFT element and an n-channel TFT element. As shown in FIG. 13, the off-leakage current value (drain current value when the gate voltage is 0 V) in the gate voltage-drain current (Vgs-Ids) curve 113 of the p-channel TFT element and the Vgs of the n-channel TFT element. -Ids curve 112 has a relatively large off-leakage current value of about 1 × 10 ⁻¹¹ A to 1 × 10 ⁻¹⁰ A (10 picoamperes to 100 picoamperes), respectively, so that when the gate voltage is 0 V, for example, a still image Also in the case of driving, the power of the bias power supply (for example, 3 V) of the p-channel TFT element and the n-channel TFT element is consumed. This has been one of the obstacles to making the power consumption of the LCD extremely low.

  Accordingly, the present invention has been completed in view of the above-described conventional problems, and an object of the present invention is to provide a dot matrix display device capable of executing display with a combination of still image display and moving image display with extremely low power consumption. It is to do.

  The dot matrix type display device of the present invention includes a plurality of gate signal lines formed in a predetermined direction on a substrate and a plurality of gate signal lines formed so as to cross the gate signal lines in a direction crossing the predetermined direction. An image signal line, a pixel electrode unit that includes a drive selection circuit that is formed at an intersection of the gate signal line and the image signal line and selects either rewrite driving or still image driving, and a plurality of the gates A dot matrix type having a gate signal line driving circuit that arbitrarily turns on one of the signal lines and an image signal line driving circuit that arbitrarily turns on one of the plurality of image signal lines In the display device, the drive selection circuit includes a pixel electrode control circuit that rewrites the selected pixel electrode portion at an intersection between the gate signal line in the on state and the image signal line in the on state, and a non-selection circuit The picture of A holding circuit for driving the electrode portion to a still image, and the holding circuit is a static memory including an n-channel thin film transistor element and a p-channel thin film transistor element. The channel contains a p-type impurity that reduces the off-leakage current value, and the p-channel thin film transistor element has an n-type impurity that reduces the off-leakage current value.

In the dot matrix type display device according to the present invention, preferably, the n-channel thin film transistor element includes a p-type impurity in a channel of 1 × 10 ¹¹ cm ^{−2 to} 3 × 10 ¹² cm ^−2, and the p-channel thin film transistor element. The channel contains 1 × 10 ¹¹ cm ⁻² to 1 × 10 ¹² cm ^{−2 of} n-type impurities.

  In the dot matrix display device of the present invention, preferably, the p-type impurity is boron and the n-type impurity is phosphorus.

In the dot matrix type display device of the present invention, preferably, each of the n-channel thin film transistor element and the p-channel thin film transistor element has a channel made of low-temperature polycrystalline silicon having an off-leakage current value of 10 ⁻¹¹ A or less. .

  The dot matrix type display device of the present invention is formed by crossing a plurality of gate signal lines formed in a predetermined direction on the substrate and the gate signal lines in a direction crossing the predetermined direction. A plurality of image signal lines; a pixel electrode unit including a drive selection circuit formed at an intersection of the gate signal line and the image signal line, for selecting either rewrite driving or still image driving; and A dot matrix type having a gate signal driving circuit that arbitrarily turns on one of the gate signal lines and an image signal driving circuit that arbitrarily turns on one of the plurality of image signal lines In the display device, the drive selection circuit includes a pixel electrode control circuit that rewrites the selected pixel electrode portion at an intersection between the gate signal line in the on state and the image signal line in the on state, and a non-selection circuit Of the above A holding circuit for driving the element electrode portion to a still image, and the holding circuit is a static memory including an n-channel thin film transistor element and a p-channel thin film transistor element. The channel contains a p-type impurity that raises the first threshold voltage, and the p-channel thin film transistor element contains an n-type impurity that lowers the second threshold voltage. .

In the dot matrix type display device according to the present invention, preferably, the n-channel thin film transistor element includes a p-type impurity in a channel of 1 × 10 ¹¹ cm ^{−2 to} 3 × 10 ¹² cm ^−2, and the p-channel thin film transistor element. The channel contains 1 × 10 ¹¹ cm ⁻² to 1 × 10 ¹² cm ^{−2 of} n-type impurities.

  In the dot matrix display device of the present invention, preferably, the p-type impurity is boron and the n-type impurity is phosphorus.

  In the dot matrix type display device of the present invention, it is preferable that a voltage difference between the first threshold voltage of the n-channel thin film transistor element and the second threshold voltage of the p-channel thin film transistor element is 2.0V-3. 5V.

  The dot matrix type display device of the present invention includes a plurality of gate signal lines formed in a predetermined direction on a substrate and a plurality of images formed by crossing the gate signal lines in a direction crossing the predetermined direction. A pixel electrode portion including a signal selection line, a drive selection circuit for selecting either rewrite driving or still image driving, formed at an intersection of the gate signal line and the image signal line, and one gate signal line A dot signal display device having a gate signal line driving circuit that arbitrarily turns on and an image signal line driving circuit that arbitrarily turns on one of a plurality of image signal lines, The drive selection circuit includes a pixel electrode control circuit that rewrites a selected pixel electrode portion at an intersection of an on-state gate signal line and an on-state image signal line, and a non-selected pixel electrode portion for driving a still image Holding circuit The holding circuit is a static memory composed of an n-channel thin film transistor element and a p-channel thin film transistor element, and the n-channel thin film transistor element contains a p-type impurity whose channel reduces an off-leakage current value. The p-channel thin film transistor element has a configuration in which the channel contains an n-type impurity that reduces the off-leakage current value. With this configuration, the gate signal line and the image signal line are turned off in the pixel electrode portion that is driven for still image, and the gate signal line and the image signal line are selectively turned on only in the pixel electrode portion that is driven for rewriting. Power consumption can be kept extremely low. In addition, since the n-channel thin film transistor element and the p-channel thin film transistor element constituting the holding circuit are controlled so that their off-leakage current values are low, when the gate voltage is 0 V, for example, in the case of still image driving. The power consumption of the bias power supply (for example, the power supply voltage 3 V) of the p-channel thin film transistor element and the n-channel thin film transistor element can be kept small. As a result, the power consumption of the dot matrix display device can be further reduced.

In the dot matrix type display device of the present invention, the channel of the n-channel thin film transistor element contains 1 × 10 ¹¹ cm ^{−2 to} 3 × 10 ¹² cm ^{−2 of} p-type impurities, and the channel of the p-channel thin film transistor element is When n-type impurities are contained in an amount of 1 × 10 ¹¹ cm ⁻² to 1 × 10 ¹² cm ⁻² , the respective off-leakage current values of the n-channel thin film transistor element and the p-channel thin film transistor element constituting the holding circuit are 10 It can be set to a desired low value of about 1 / min or less.

  In the dot matrix type display device of the present invention, when the p-type impurity is boron and the n-type impurity is phosphorus, boron and phosphorus are not toxic as impurities when implanted into the channel by an ion implantation method. Since it is the lightest element, the efficiency of ion implantation is good, and the handling workability is also good, which is advantageous in terms of ease of manufacture.

In the dot matrix type display device of the present invention, when the n-channel thin film transistor element and the p-channel thin film transistor element each have a channel made of low-temperature polycrystalline silicon having an off-leakage current value of 10 ⁻¹¹ A or less, a holding circuit is provided. The off-leakage current value of each of the n-channel thin film transistor element and the p-channel thin film transistor element to be configured becomes extremely low, which is about 1/10 or less of the conventional one. In addition, low-temperature polycrystalline silicon has a carrier mobility of 100 to ²⁰⁰ cm ² / Vs or higher and higher than 0.5 cm ² / Vs of amorphous silicon, so that a current can flow through the channel even with a low driving voltage. Accordingly, the power consumption of the holding circuit can be further reduced, and as a result, the power consumption of the dot matrix display device can be further reduced.

  The dot matrix display device of the present invention includes a plurality of gate signal lines formed in a predetermined direction on a substrate and a plurality of gate signal lines formed so as to intersect with the gate signal lines in a direction crossing the predetermined direction. An image signal line, a pixel electrode portion formed at an intersection of the gate signal line and the image signal line, including a drive selection circuit for selecting either rewrite driving or still image driving, and a plurality of gate signal lines A dot matrix type display device comprising: a gate signal driving circuit that arbitrarily selects one to turn on; and an image signal driving circuit that arbitrarily turns on one of a plurality of image signal lines, The drive selection circuit includes a pixel electrode control circuit that rewrites a selected pixel electrode portion at an intersection of an on-state gate signal line and an on-state image signal line, and a non-selected pixel electrode portion for driving a still image A holding circuit of The holding circuit is a static memory composed of an n-channel thin film transistor element and a p-channel thin film transistor element, and the n-channel thin film transistor element contains a p-type impurity that increases the first threshold voltage of the channel. In addition, the p-channel thin film transistor element has a configuration in which the channel contains an n-type impurity that lowers the second threshold voltage. With this configuration, the gate signal line and the image signal line are turned off in the pixel electrode portion that is driven for still image, and the gate signal line and the image signal line are selectively turned on only in the pixel electrode portion that is driven for rewriting. Power consumption can be kept extremely low. Further, the n-channel thin film transistor element constituting the holding circuit is controlled so that the first threshold voltage is increased, and the p-channel thin film transistor element is controlled so that the second threshold voltage is decreased. The value of the current flowing through the channel of the n-channel thin film transistor element and the channel of the p-channel thin film transistor element can be made lower than that before impurities in the entire operating voltage range. As a result, the power consumption of the dot matrix display device can be further reduced. Further, since the n-channel thin film transistor element and the p-channel thin film transistor element constituting the holding circuit have a low off-leakage current value, when the gate voltage is 0 V, for example, in the case of still image driving, The power consumption of the bias power supply (for example, power supply voltage 3V) of the channel thin film transistor element can be suppressed. As a result, the power consumption of the dot matrix display device can be further reduced.

In the dot matrix type display device of the present invention, the channel of the n-channel thin film transistor element contains 1 × 10 ¹¹ cm ^{−2 to} 3 × 10 ¹² cm ^{−2 of} p-type impurities, and the channel of the p-channel thin film transistor element is When n-type impurities are contained in an amount of 1 × 10 ¹¹ cm ⁻² to 1 × 10 ¹² cm ⁻² , the n-channel thin film transistor element constituting the holding circuit is controlled so as to increase the first threshold voltage. The p-channel thin film transistor element is controlled so that the second threshold voltage is lowered, and the voltage difference between the threshold voltages is about 2.0 V to 3.5 V, which is larger than the conventional one.

  In the dot matrix type display device of the present invention, when the p-type impurity is boron and the n-type impurity is phosphorus, boron and phosphorus are not toxic as impurities when implanted into the channel by an ion implantation method. Since it is the lightest element, the efficiency of ion implantation is good, and the handling workability is also good, which is advantageous in terms of ease of manufacture.

  The dot matrix type display device according to the present invention has an n-channel when the voltage difference between the first threshold voltage of the n-channel thin film transistor element and the second threshold voltage of the p-channel thin film transistor element is 2.0V to 3.5V. It is possible to ensure that the value of the current flowing through the channel of the thin film transistor element and the channel of the p channel thin film transistor element is lower than that before the impurities are contained within the entire operating voltage range. In addition, the off-leakage current value of the n-channel thin film transistor element and the off-leakage current value of the p-channel thin film transistor element constituting the holding circuit can be reliably reduced to about 1/10 or less of the conventional one.

FIG. 1 is a diagram showing an example of an embodiment of a dot matrix type display device of the present invention, and is a block circuit diagram of a basic configuration of the dot matrix type display device. FIG. 2 is a diagram showing an example of an embodiment of the dot matrix type display device of the present invention, and a p-channel TFT element and an n-channel TFT element constituting a holding circuit included in a pixel electrode portion of the dot matrix type display device. It is a graph which shows a Vgs-Ids curve. FIG. 3 is a circuit diagram showing a detailed configuration of the gate signal line driving circuit in the dot matrix type display device of the present invention. FIG. 4 is a circuit diagram showing a detailed configuration of the image signal line driving circuit in the dot matrix type display device of the present invention. FIG. 5A is a block circuit diagram of a drive circuit unit for turning on and off one gate signal line in the gate signal line drive circuit, and FIG. 5B is a circuit diagram showing details of FIG. FIG. 6A is a block circuit diagram of a drive circuit unit for turning on / off one image signal line in the image signal line drive circuit, and FIG. 6B is a circuit diagram showing details of FIG. FIG. 7 is a block circuit diagram showing an embodiment of a pixel electrode unit including a drive selection circuit having a holding circuit and a pixel electrode control circuit. FIG. 8 is a detailed circuit diagram taking into account the connection relation of the TFT element groups constituting each block circuit of FIG. FIG. 9 is a detailed circuit diagram illustrating the connection relationship of the TFT element groups constituting the pixel electrode control circuit. FIG. 10 is a truth table describing an output (Y) of an exclusive OR logic gate circuit in which the common voltage Vcom (A) and the image signal data (B) are binary input. FIG. 11 is a plan view of a display panel of a digital display wristwatch to which the dot matrix display device of the present invention is applied. FIG. 12 is a block circuit diagram showing a basic configuration of a conventional dot matrix display device. FIG. 13 is a graph showing Vgs-Ids curves of a p-channel TFT element and an n-channel TFT element of a memory circuit included in a pixel electrode portion of a conventional liquid crystal display device or the like.

  Hereinafter, embodiments of a dot matrix display device of the present invention will be described with reference to the drawings. However, the drawings referred to below show the main members necessary for explaining the configuration of the present invention among the components of the dot matrix display device of the present invention. Therefore, the dot matrix display device according to the present invention may include well-known components such as wiring conductors, circuit boards, control ICs, and control LSIs that are not shown in the drawings.

  An embodiment of a dot matrix type display device of the present invention will be described with reference to FIGS. The dot matrix type display device of the present invention has a plurality of gate signal lines GL1 to GL128 formed in a predetermined direction (for example, row direction) on a substrate such as a glass substrate and a direction (for example, crossing the predetermined direction) , In the column direction) formed by intersecting the gate signal lines GL1 to GL128 with a plurality of image signal lines DL1 to DL128 and the gate signal lines GL1 to GL128 and the image signal lines DL1 to DL128, Pixel electrode portions P11 to Pmn including a drive selection circuit for selecting either rewrite driving or still image driving, and a gate signal line driving circuit for arbitrarily selecting one of a plurality of gate signal lines GL1 to GL128 and turning them on 3 and an image signal line driving circuit 4 that arbitrarily turns on one of the plurality of image signal lines DL1 to DL128, and the drive selection circuit is in an on state. Gate signal line GLn (on) and on-state image signal line DLn (on) A pixel electrode control circuit that rewrites the selected pixel electrode portion Pmn (select) at the intersection of the two and a holding circuit for driving a non-selected pixel electrode portion Pmn (non-select) to a still image The holding circuit is a static memory (SRAM) composed of an n-channel TFT element and a p-channel TFT element, and the n-channel TFT element contains a p-type impurity that reduces the off-leakage current value. The p-channel TFT element has an n-type impurity that reduces the off-leakage current value. With this configuration, in the pixel electrode portion Pmn (non-select) for driving a still image, the gate signal line GLn and the image signal line DLn are turned off, and the gate signal is selectively applied only in the pixel electrode portion Pmn (select) to be driven for rewriting. Since the line GLn and the image signal line DLn are turned on, the power consumption can be kept extremely low. Further, since the n-channel TFT element and the p-channel TFT element constituting the holding circuit are controlled so that their off-leakage current values are low, when the gate voltage is 0 V, for example, in the case of still image driving. The power consumption of the bias power supply (for example, power supply voltage 3V) of the p-channel TFT element and the n-channel TFT element can be suppressed to a small value. As a result, the power consumption of the dot matrix display device can be further reduced. The holding circuit is, for example, a static memory configured by connecting two inverting logic circuits (CMOS inverters) each having an n-channel TFT element and a p-channel TFT element connected in common to each other in series and connected in a loop. (SRAM).

FIG. 2 is a diagram showing an example of an embodiment of the dot matrix type display device of the present invention, and is an SRAM which is a holding circuit (indicated by reference numeral 62 in FIG. 8) included in the pixel electrode portion of the dot matrix type display device. 5 is a graph showing a Vgs-Ids curve 12 of an n-channel TFT element and a Vgs-Ids curve 13 of a p-channel TFT element. For the Vgs-Ids curve 12 of the n-channel TFT element, a predetermined amount (for example, 1 × 10 ¹¹ atoms cm ^{−2 to} 3 × 10 ¹² atoms cm ⁻² ) of boron or the like whose channel is p-type impurity (hereinafter, “atoms” is omitted). ) By including, the off-leakage current value is about 6 × 10 ⁻¹² A (6 picoamperes) lower than the value of about 9 × 10 ⁻¹¹ A (90 picoamperes) in the pre-contained Vgs-Ids curve 112 It is controlled. In FIG. 2, 12a is the amount of decrease in the off-leakage current value in the Vgs-Ids curve 12 with respect to the off-leakage current value in the Vgs-Ids curve 112 of the n-channel TFT element. Further, with respect to the Vgs-Ids curve 13 of the p-channel TFT element, by containing a predetermined amount (for example, 1 × 10 ¹¹ cm ^{−2 to} 1 × 10 ¹² cm ⁻² ) of phosphorus or the like whose channel is an n-type impurity. The off-leakage current value is controlled to be a value of about 3 × 10 ⁻¹³ A (0.3 picoamperes) lower than the value of about 3 × 10 ⁻¹¹ A (30 picoamperes) in the Vgs-Ids curve 113 before containing. In FIG. 2, 13a is the amount of decrease in the off-leakage current value in the Vgs-Ids curve 13 with respect to the off-leakage current value in the Vgs-Ids curve 113 of the p-channel TFT element. The off-leakage current value is a current value that flows through the channel when the gate voltage applied to the gate electrode portion of the TFT element is 0V.

In the dot matrix type display device of the present invention, the n-channel TFT element constituting the holding circuit 62 has a channel containing 1 × 10 ¹¹ cm ^{−2 to} 3 × 10 ¹² cm ^{−2 of} p-type impurities. In the p-channel TFT element constituting n, it is preferable that the channel contains an n-type impurity in the range of 1 × 10 ¹¹ cm ⁻² to 1 × 10 ¹² cm ⁻² . In this case, the off-leakage current values of the n-channel TFT element and the p-channel TFT element constituting the holding circuit 62 can be made as low as about 1/10 or less of the conventional one.

  In the dot matrix display device of the present invention, it is preferable that the p-type impurity is boron (B) and the n-type impurity is phosphorus (P). In this case, since boron and phosphorus are the lightest impurities as impurities when they are implanted and contained in the channel by ion implantation, the efficiency of ion implantation is good and the handling workability is also good. This is advantageous in terms of ease of operation. Examples of p-type impurities include aluminum (Al), gallium (Ga), and indium (In) in addition to boron. Examples of n-type impurities include arsenic (As), antimony (Sb), and bismuth (Bi) in addition to phosphorus.

In the dot matrix type display device of the present invention, each of the n-channel TFT element and the p-channel TFT element has a channel made of low-temperature polycrystalline silicon (LTPS) having an off-leakage current value of 10 ⁻¹¹ A or less. It is preferable to have. In this case, each of the n-channel TFT element and the p-channel TFT element constituting the holding circuit 62 has an extremely low off-leakage current value of about 1/10 or less. Further, since LTPS has a carrier mobility of 100 to ²⁰⁰ cm ² / Vs or higher and higher than 0.5 cm ² / Vs of amorphous silicon, a current can flow through the channel even with a low driving voltage. Accordingly, the power consumption of the holding circuit 62 can be further reduced, and as a result, the power consumption of the dot matrix display device can be further reduced.

  In addition, since n-channel TFT elements and p-channel TFT elements can be formed using LTPS, a drive circuit based on a CMOS circuit, an SRAM circuit, a D / A converter, an image display unit, etc. are integrated on a glass substrate. It can be integrated. Therefore, an LCD equipped with an audio processing circuit and a microprocessor can also be manufactured using LTPS. Since the liquid crystal display panel and its peripheral drive circuit can be integrally formed on the glass substrate, the electrical reliability is improved. In other words, the number of electrical connections between the liquid crystal display panel and the driving circuit can be greatly reduced, and it is resistant to vibrations and light in weight, which is suitable for a portable information terminal. In addition, since the current driving capability is high, an LCD having high-definition pixels and pixels with a high aperture ratio can be manufactured.

The manufacturing method of LTPS is shown below. First, an amorphous silicon film is formed on a glass substrate by a plasma CVD (Chemical Vapor Deposition) method. Next, in order to polycrystallize the amorphous silicon film, the amorphous silicon film is irradiated with excimer laser light at a temperature of a glass substrate of 450 ° C. or lower. As the excimer laser device, for example, a gas laser light source that uses ArF (wavelength 193 nm), KrF (wavelength 248 nm), or the like, which oscillates ultraviolet light having a large absorption of the amorphous silicon film can be used. Amorphous silicon film is irradiated with pulsed laser light with a laser oscillation frequency of about 300 Hz, laser light energy of about 300 W, pulse width of about 20 ns to about 60 ns, and irradiation energy density of about 500 mJ / cm ^{2 to 1} J / cm ^2. It is solidified after being melted and supercooled. As a result, the film changes to a polycrystalline silicon film having an average grain size of about 0.3 μm.

In the dot matrix type display device of the present invention, the source electrode portion of the n-channel TFT element and the p-channel TFT element is about 1 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁵ cm ⁻² of phosphorus, and the drain electrode portion is 1 of boron. Ion implantation is performed at about × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁵ cm ⁻² . Further, the n-channel TFT element and the p-channel TFT element of the holding circuit 62 constitute a CMOS inverter, and the holding circuit 62 has a configuration in which two CMOS inverters are connected in series and in a loop. In the n-channel TFT element and the p-channel TFT element constituting the CMOS inverter, the source electrode portion and the drain electrode portion have an LDD (Lightly Doped Drain) portion in order to improve the operation reliability of the transistor. Also good. Furthermore, the n-channel TFT element preferably has an LDD portion at the end on the drain side of the channel in order to reduce leakage current when reverse bias is applied. The leak current is determined by the rate at which electrons and holes are generated at the defect level in the depletion layer near the drain electrode when a reverse bias is applied, and this rate can be reduced by forming the LDD portion. The LDD portion can be formed by ion implantation of phosphorus at about 1 × 10 ¹² cm ⁻² to 1 × 10 ¹³ cm ⁻² . The ion energy of ion implantation is about 5 keV to 400 keV.

  As the ion implantation apparatus, a mass separation type is preferably used. This mass separation type ion implantation apparatus has a problem in that dose control becomes difficult due to ion neutralization and hydrogen ion mixing caused by ion implantation in a low vacuum region, and a substrate caused by mixing hydrogen ions and other impurity ions. Problems of the non-mass-separated ion implantation apparatus, such as temperature rise and resist burnout, can be solved. The basic configuration of the mass separation type ion implantation apparatus includes, for example, an ion chamber including a plasma ion source, an ion species extraction electrode installed on the ion species output port side of the ion chamber, and an ion species output of the ion chamber. The magnet unit is connected to the mouth and travels in a curved orbit on the ion species, and the acceleration electrode is installed near the ion species output port of the magnet unit.

  A dot matrix type display device according to another invention of the present invention crosses a plurality of gate signal lines GL1 to GL128 formed in a predetermined direction (for example, a row direction) on a substrate such as a glass substrate in a predetermined direction. A plurality of image signal lines DL1 to DL128 formed to intersect with the gate signal lines GL1 to GL128 in the direction (for example, the column direction), and the intersection of the gate signal lines GL1 to GL128 and the image signal lines DL1 to DL128 The formed pixel electrode portions P11 to Pmn including a drive selection circuit for selecting either rewrite driving or still image driving, and a gate for arbitrarily selecting one of the plurality of gate signal lines GL1 to GL128 and turning them on A dot matrix type display device having a signal line driving circuit 3 and an image signal line driving circuit 4 that arbitrarily turns on one of a plurality of image signal lines DL1 to DL128. The gate signal line GLn (on) in the on state and the image in the on state A pixel electrode control circuit that rewrites the selected pixel electrode portion Pmn (select) at the intersection with the signal line DLn (on) and a holding circuit for driving a non-selected pixel electrode portion Pmn (non-select) in a still image The holding circuit 62 is a static memory (SRAM) composed of an n-channel TFT element and a p-channel TFT element, and the channel of the n-channel TFT element has a first threshold voltage. The p-channel TFT element is configured to contain an n-type impurity that lowers the second threshold voltage. With this configuration, in the pixel electrode portion Pmn (non-select) for driving a still image, the gate signal line GLn and the image signal line DLn are turned off, and the gate signal is selectively applied only in the pixel electrode portion Pmn (select) to be rewritten. Since the line GLn and the image signal line DLn are turned on, the power consumption can be kept extremely low. Further, the n-channel TFT element constituting the holding circuit 62 is controlled so that the first threshold voltage is increased, and the p-channel TFT element is controlled so that the second threshold voltage is decreased. Thus, the value of the current flowing through the channel of the n-channel TFT element and the channel of the p-channel TFT element can be made lower than that before the impurities are contained within the entire operating voltage range. As a result, the power consumption of the dot matrix display device can be further reduced. Further, since the n-channel TFT element and the p-channel TFT element constituting the holding circuit 62 have a low off-leakage current value, when the gate voltage is 0 V, for example, in the case of still image driving, the p-channel TFT element and The power consumption of the bias power supply (for example, power supply voltage 3 V) of the n-channel TFT element can be kept small. As a result, the power consumption of the dot matrix display device can be further reduced.

As shown in FIG. 2, with respect to the Vgs-Ids curve 12 of the n-channel TFT element, a predetermined amount (for example, 1 × 10 ¹¹ cm ^{−2 to} 3 × 10 ¹² cm ⁻² ) of boron or the like whose channel is a p-type impurity. ), The first threshold voltage (Vthn) is controlled to be about 1.3 V, which is higher than the value about 0.8 V in the Vgs-Ids curve 112 before the inclusion. Further, with respect to the Vgs-Ids curve 13 of the p-channel TFT element, by containing a predetermined amount (for example, 1 × 10 ¹¹ cm ^{−2 to} 1 × 10 ¹² cm ⁻² ) of phosphorus or the like whose channel is an n-type impurity. The second threshold voltage (Vthp) is controlled to be a value of about -1.4 V, which is lower than the value of about -0.8 V in the Vgs-Ids curve 113 before containing. As a result, the voltage difference (ΔVth) between the first threshold voltage (Vthn) and the second threshold voltage (Vthp) is about 2.7 V, which is larger than the voltage difference (ΔVth) before impurity inclusion (about 1.6 V). Vthn is a gate voltage at which the n-channel TFT element is turned on, that is, a gate voltage that functions as a switching element when a predetermined amount of current flows through the channel. For example, a current of about 0.5 μA to 0.6 μA flows through the channel. Is the gate voltage when. The channel current value at Vthn is appropriately set depending on the configuration of the TFT element. Vthp is similarly determined.

In the dot matrix type display device of the present invention, the n-channel TFT element constituting the holding circuit 62 has a channel containing 1 × 10 ¹¹ cm ^{−2 to} 3 × 10 ¹² cm ^{−2 of} p-type impurities. In the p-channel TFT element constituting n, it is preferable that the channel contains an n-type impurity in the range of 1 × 10 ¹¹ cm ⁻² to 1 × 10 ¹² cm ⁻² . In this case, the n-channel TFT elements constituting the holding circuit 62 are controlled so that the first threshold voltage (Vthn) is high, and the p-channel TFT elements are low so that the second threshold voltage (Vthp) is low. In addition to being controlled, the voltage difference (ΔVth) between the threshold voltages is about 2.0 V to 3.5 V, which is larger than the conventional one.

  In the dot matrix display device of the present invention, it is preferable that the p-type impurity is boron (B) and the n-type impurity is phosphorus (P) for the reasons described above.

  Further, the dot matrix type display device of the present invention has a voltage difference (ΔVth) between the first threshold voltage (Vthn) of the n-channel TFT element constituting the holding circuit 62 and the second threshold voltage (Vthp) of the p-channel TFT element. ) Is preferably 2.0V to 3.5V. In this case, the value of the current flowing through the channel of the n-channel TFT element and the channel of the p-channel TFT element can be reliably reduced within the entire operating voltage range (for example, −3 V to 3 V) than before the impurity inclusion. Become. In addition, the off-leakage current value of the n-channel TFT element and the off-leakage current value of the p-channel TFT element constituting the holding circuit 62 can be reliably reduced to about 1/10 or less of the conventional one.

  The dot matrix display device of the present invention can provide a plurality of display regions each having an optimum rewrite cycle in one display panel. In this case, the power consumption can be controlled by setting a very long period between rewriting in one display area and setting a short period between rewriting in the other display area. Can be performed with high accuracy. As a result, power consumption can be further reduced.

  The overall configuration of the dot matrix display device of the present invention will be described below. FIG. 1 is a block circuit diagram of a basic configuration of a dot matrix type display device, and a display panel is a monochrome display LCD having a number of pixels of 16384 dots (vertical 128 dots × horizontal 128 dots). In FIG. 1, a gate signal line drive circuit 3 is provided on one side of the LCD panel, and an image signal (source signal) line drive circuit 4 is provided on the lower side of the LCD panel. In FIG. 1, 1 is a TFT element, 2 is a common voltage line for supplying a common voltage Vcom to the common electrode of the pixel electrode section, 10 is a display section, and 11 is an LCD panel.

  FIG. 3 is a circuit diagram showing a detailed configuration of the gate signal line driving circuit 3. The gate signal line driving circuit 3 is an inverted gate selection signal line for transmitting an inverted output from an inverter 21 composed of a CMOS inverter or the like for generating inverted signals of the gate selection signal lines GS1 to GS7 and the gate selection signal lines GS1 to GS7. 7 signals out of 14 signals consisting of iGS1 to iGS7 (in FIG. 3, the inverted symbol of the superscript bar is attached), gate selection signal lines GS1 to GS7 and inverted gate selection signal lines iGS1 to iGS7 NOR gate (NOR) logic gate circuit 22 and the booster circuit (level shifter) for operating the TFT element on the gate signal line GLn side of the pixel electrode section by boosting the voltage amplitude of the output of the logic gate circuit 22 (Level / Shifter: L / S)) 23, and an inverter 24 composed of a CMOS inverter or the like for inverting the output of the booster circuit 23. In FIG. 2, reference numeral 10 denotes a display unit.

In this gate signal line driving circuit 3, the logic gate circuit 22 is high (“H”) when all of the seven signals input thereto are low (represented by “L”, for example, a signal of 0V). For example, 3V signal). There are 2 ⁷ = 128 combinations of wirings of the gate selection signal lines GS1 to GS7 and the inverted gate selection signal lines iGS1 to iGS7, which are input to the logic gate circuit 22, and are input to the gate selection signal lines GS1 to GS7 7 One logic gate circuit 22 can be selected by one set of signals. Thereby, one of the gate signal lines GL1 to GL128 can be arbitrarily selected and turned on. Note that control of a set of seven signals input to the gate selection signal lines GS1 to GS7 can be performed by a control LSI (Large Scale Integrated Circuit) provided on the LCD panel 11 or externally.

  FIG. 4 is a circuit diagram showing a detailed configuration of the image signal line driving circuit 4. The image signal line driving circuit 4 includes an image selection signal line SS1 to SS7, an inverter 31 including a CMOS inverter that generates an inverted signal of each of the image selection signal lines SS1 to SS7, and an inverted image that transmits an inverted output from the inverter 31. A logic gate circuit 32 of a logical sum negation (NOR) to which seven signals out of 14 signals composed of the selection signal lines iSS1 to iSS7, the image selection signal lines SS1 to SS7, and the inverted image selection signal lines iSS1 to iSS7 are input. A booster circuit (L / S) 33 for operating the TFT element on the image signal line DLn side of the pixel electrode section by boosting the voltage amplitude of the output of the logic gate circuit 32, and a CMOS inverter for inverting the output of the booster circuit 33 And so on. Further, an image signal line 36 that transmits an image signal (Data), a TFT element 35 that is turned on by the output from the inverter 34 and is a transfer gate element that outputs the image signal Data from the image signal line 36 to the pixel electrode unit. Have.

In the image signal line driving circuit 4, the logic gate circuit 32 outputs H (for example, a 3V signal) when all of the seven signals input thereto are L (for example, a 0V signal). Then, there are 2 ⁷ = 128 combinations of wirings of the image selection signal lines SS1 to SS7 and the inverted image selection signal lines iSS1 to iSS7, which are input to the logic gate circuit 32, and are input to the image selection signal lines SS1 to SS7 7 One logic gate circuit 32 can be selected by one set of signals. Thereby, one of the image signal activation lines SL1 to SL128 can be arbitrarily selected and turned on. The control of a set of seven signals input to the image selection signal lines SS1 to SS7 can be performed by a control LSI or the like provided on the LCD panel 11 or outside.

  Further, one arbitrarily selected image signal activation line SLn turns on one TFT element 35, and the TFT element 35 transmits one image signal Data on the image signal line 36 to the pixel electrode unit. Communicate. Such input control of the image signal Data can be controlled by the control LSI or the like.

  FIGS. 5A and 5B are circuit diagrams showing an embodiment of a drive circuit unit for turning on and off one gate signal line GL128 in the gate signal line drive circuit 3. FIG. Each of the inverted gate selection signal lines iGS1 to iGS6 (in FIG. 5A and FIG. 5B, the symbol is indicated by the inverted symbol of the superscript bar) and the gate selection signal line GS7 are respectively connected to the p-channel TFT element 41 and n. An inverter composed of a channel TFT element 42 is connected.

  Each of these seven inverters has a common gate connection point connected to one of the inverted gate selection signal lines iGS1 to iGS6 and the gate selection signal line GS7, and the seven common drain connection points are connected in common. Yes. Accordingly, only when the L signal is input to all of the inverted gate selection signal lines iGS1 to iGS6 and the gate selection signal line GS7, the H signal is output from the seven commonly connected drain connection points. In other words, it functions as a logical gate circuit 22 for logical sum negation (NOR).

  The output (H signal) of the NOR logic gate circuit 22 includes an inverter 43, a transfer gate circuit 44 in which a p-channel TFT element and an n-channel TFT element are connected in series with a common drain electrode, and a p-channel circuit. The voltage is input to a booster circuit (L / S) 23 comprising a transfer gate circuit 45 in which a TFT element and an n-channel TFT element are connected in series with a common drain electrode. The common drain connection point of one transfer gate circuit 44 is connected to the gate electrode portion of the p-channel TFT element of the other transfer gate circuit 45. The common drain connection point of the other transfer gate circuit 45 is connected to the gate electrode portion of the p-channel TFT element of the one transfer gate circuit 44.

  When an H signal is input to the gate electrode portion of the n-channel TFT element of one transfer gate circuit 44, a current flows through the n-channel TFT element, and the common drain connection point of one transfer gate circuit 44 is 0V. Potential (L). This potential of 0V is input to the gate common connection point of the inverter 24. As a result, an H signal (6 V) is input from the drain common connection point of the inverter 24 to the gate signal line GL128. At this time, a potential (L) of 0V is applied to the gate electrode portion of the p-channel TFT element of the other transfer gate circuit 45, the p-channel TFT element is turned on, and the drain electrode portion of the p-channel TFT element is set to a potential of 6V. However, this potential is not transmitted to the inverter 24. Further, since the L signal is input to the gate electrode portion of the n-channel TFT element of the other transfer gate circuit 45 from the drain common connection point of the inverter 43, the n-channel TFT element is turned off.

  6A and 6B are circuit diagrams showing an embodiment of a drive circuit unit for turning on / off one image signal activation line SL128 in the image signal line drive circuit 4. FIG. An inverter composed of a p-channel TFT element 51 and an n-channel TFT element 52 is connected to each of the inverted image selection signal lines iSS1 to iSS6 and the image selection signal line SS7.

  Each of these seven inverters has a common gate connection point connected to each of the inverted image selection signal lines iSS1 to iSS6 and the image selection signal line SS7, and the seven drain common connection points are commonly connected. Yes. Thereby, only when the L signal is input to all of the inverted image selection signal lines iSS1 to iSS6 and the image selection signal line SS7, the H signal is output from the seven commonly connected drain connection points. In other words, it functions as a logical gate circuit 32 of a logical sum negation (NOR).

  The output (H signal) of the NOR logic gate circuit 32 includes an inverter 53, a transfer gate circuit 54 in which a p-channel TFT element and an n-channel TFT element are connected in series with a common drain electrode, and a p-channel. The voltage is input to a booster circuit (L / B) 33 including a transfer gate circuit 55 in which a TFT element and an n-channel TFT element are connected in series with a common drain electrode portion. The common drain connection point of one transfer gate circuit 54 is connected to the gate electrode portion of the p-channel TFT element of the other transfer gate circuit 55. The common drain connection point of the other transfer gate circuit 55 is connected to the gate electrode portion of the p-channel TFT element of the one transfer gate circuit 54.

  When an H signal is input to the gate electrode portion of the n-channel TFT element of one transfer gate circuit 54, a current flows through the n-channel TFT element, and the common drain connection point of one transfer gate circuit 54 is 0V. Potential (L). This 0 V potential is input to the common gate connection point of the inverter 34. As a result, an H signal (6 V) is input from the common drain connection point of the inverter 34 to the image signal activation line SL128. At this time, a potential (L) of 0V is applied to the gate electrode portion of the p-channel TFT element of the other transfer gate circuit 55, the p-channel TFT element is turned on, and the drain electrode portion of the p-channel TFT element is set to a potential of 6V. However, this potential is not transmitted to the inverter 34. Further, since the L signal is input to the gate electrode portion of the n-channel TFT element of the other transfer gate circuit 55 from the common drain connection point of the inverter 53, the n-channel TFT element is turned off.

  Further, an n-channel TFT element 35 is connected to the image signal activation line SL128, and a signal transmitted through the image signal activation line SL128 is used as a control input to the gate electrode portion. The source electrode portion of the n-channel TFT element 35 is connected to the image signal activation line SL128. Is connected with an image signal line 36. Thus, when the signal transmitted through the image signal activation line SL128 is H, the n-channel TFT element 35 is turned on, and the image signal Data is transmitted to the pixel electrode portion through the image signal line DL128.

  7 and 8 are circuit diagrams showing an embodiment of a pixel electrode unit including a drive selection circuit 64 having a holding circuit 62 and a pixel electrode control circuit 63. FIG. FIG. 7 is a block circuit diagram, and FIG. 8 is a detailed circuit diagram in which TFT element groups constituting each block circuit are taken. The drive selection circuit 64 is a circuit that selects either still image drive or rewrite drive, and includes a holding circuit 62 and a pixel electrode control circuit 63.

  As shown in FIGS. 7 and 8, the input unit 61 at the front stage of the drive selection circuit 64 is provided with a transfer gate circuit formed by connecting two n-channel TFT elements 61a and 61b in series. In the n-channel TFT element 61a on the image signal line DLn side, a signal transmitted through the image signal activation line SLn is controlled and input to the gate electrode portion. When the signal is H, the n-channel TFT element 61a is turned on, and when the signal is L, the n-channel TFT element 61a is turned off. In another n-channel TFT element 61b on the gate signal line GLn side, a signal transmitted through the gate signal line GLn is controlled and input to the gate electrode portion. When the signal is H, the n-channel TFT element 61b is turned on, and when the signal is L, the n-channel TFT element 61b is turned off. Therefore, the transfer gate circuit is closed in an equivalent circuit state only when the signal transmitted through the gate signal line GLn is H and the signal transmitted through the image signal activation line SLn is H. Thus, the signal transmitted through the image signal line 37 is transmitted to the holding circuit 62.

In the dot matrix type display device of the present invention, the pixel electrode section includes a first n-channel TFT element 61a in which the gate electrode section is electrically connected to the image signal activation line SLn before the drive selection circuit 64; The first and second n-channels have an input unit 61 formed by serially connecting a second n-channel TFT element 61b whose gate electrode part is electrically connected to the gate signal line GLn. The TFT elements 61a and 61b preferably each have a channel made of low-temperature polycrystalline silicon having an off-leakage current value of 10 ⁻¹¹ A or less. In this case, the off-leakage current values of the first and second n-channel TFT elements 61a and 61b are extremely low, about 1/10 or less of the conventional one. In addition, low-temperature polycrystalline silicon has a carrier mobility of 100 to ²⁰⁰ cm ² / Vs or higher and higher than 0.5 cm ² / Vs of amorphous silicon, so that a current can flow through the channel even with a low driving voltage. Accordingly, the power consumption of the input portion of the pixel electrode portion can be kept low, and as a result, the power consumption of the dot matrix display device can be further reduced.

  The holding circuit 62 is configured by, for example, a static memory (SRAM) formed by connecting two inverters each including a CMOS inverter or the like in a loop shape. FIG. 8 shows the configuration of the static memory. The holding circuit 62 connects two first and second inverters 62a and 62b in series, and outputs the output from the common drain connection point of the second (rear stage) inverter 62b to the first (previous stage) inverter. Feedback input is made to the gate common connection point of 62a. Thus, when an H signal is input to the gate common connection point of the first inverter 62a, an L signal is then output from the drain common connection point of the first inverter 62a, and the L signal is then output. The signal is input to the common gate connection point of the second inverter 62b, then the H signal is output from the common drain connection point of the second inverter 62b, and then the H signal is connected to the common gate connection of the first inverter 62a. Feedback input to point. As a result, H, L, and H signals are always held on the loop-shaped transmission line. That is, the holding circuit 62 functions as a memory circuit.

  FIG. 9 is a circuit diagram depicting the connection relationship of the TFT element groups constituting the pixel electrode control circuit 63. As shown in FIG. The pixel electrode control circuit 63 shares the first inverter 62a of the holding circuit 62, and outputs the inverted signal iB of the image signal B (in the figure, the inverted symbol of the superscript bar is added). 1 inverter 62a, a p-channel TFT element 81a, and an n-channel TFT element 81b. The common voltage Vcom (A), the image signal data (B), and the output (iB) of the first inverter 62a are input for reference. This comprises a first binary selection circuit 81 for outputting binary data, a p-channel TFT element 82a and an n-channel TFT element 82b, and a common voltage Vcom (A), image signal data (B) and first A second binary selection circuit that outputs binary data when the output (iB) of the inverter 62a is referred to and is connected in parallel to the output line of the first binary selection circuit 81. 82. The output of the first binary selection circuit 81 and the output of the second binary selection circuit 82 are the exclusive OR (EXOR) of the common voltage Vcom (A) and the image signal data (B). Configures the logic gate output.

  The first binary selection circuit 81 is an inverter in which a p-channel TFT element 81a and an n-channel TFT element 81b are connected in common to the gate electrode portion and the drain electrode portion, and the image signal data (B) is H. Only when the signal is (1), binary data (Y) is output. On the other hand, when the image signal data (B) is a signal of L (0), the first binary selection circuit 81 does not function as an inverter and is in a high impedance state, that is, in an open state in terms of an equivalent circuit. Therefore, binary data (Y) is not output.

  The second binary selection circuit 82 is a four-terminal transfer gate circuit in which a p-channel TFT element 82a and an n-channel TFT element 82b are connected to each other between source electrode portions and drain electrode portions, and an n-channel TFT element 82b. The output (iB) of the first inverter 62a input to the gate electrode portion is used as a control input. Only when the output (iB) of the first inverter 62a is the H signal (1), that is, when the image signal data (B) is the L signal (0), the binary data (Y) is obtained. Output. On the other hand, when the output (iB) of the first inverter 62a is the L signal (0), the second binary selection circuit 82 does not function as a transfer gate circuit and is in a high impedance state, that is, equivalent circuit-like. Open (open) state, and binary data (Y) is not output.

  Since the output line of the second binary selection circuit 82 is connected in parallel to the output line of the first binary selection circuit 81 in this way, the output of the first binary selection circuit 81 and the second The output of the binary selection circuit 82 constitutes an exclusive OR logic gate output for the common voltage Vcom (A) and the image signal data (B). That is, the pixel electrode control circuit 63 is a logic gate circuit that performs an exclusive OR operation on the common voltage Vcom (A) and the image signal data (B).

In the dot matrix type display device of the present invention, as shown in FIG. 9, the pixel electrode control circuit 63 is exclusively composed of a plurality of TFT elements having channels composed of LTPS having an off-leakage current value of 10 ⁻¹¹ A or less. It is preferable that the logical gate circuit is a logical sum. In this case, the off-leakage current value of the TFT element is extremely low, about 1/10 or less of the conventional one. Further, since LTPS has a carrier mobility of 100 to ²⁰⁰ cm ² / Vs or higher and higher than 0.5 cm ² / Vs of amorphous silicon, a current can flow through the channel even with a low driving voltage. Accordingly, the power consumption of the pixel electrode control circuit 63 can be kept low, and as a result, the power consumption of the dot matrix display device can be further reduced.

  FIG. 10 is a truth table describing the output (Y) of an exclusive-OR logic gate circuit in which the common voltage Vcom (A) and the image signal data (B) are binary input. When the image signal data (B) is input to the pixel electrode portion, that is, when the image signal data (B) is a signal of H (3V: “1”), the pixel voltage Pixel and the common voltage Vcom (A) In the normally white mode, black is displayed, and in the normally black mode, white is displayed. Thus, even if the common voltage Vcom (A) is driven to be inverted, the potential difference between the pixel voltage Pixel and the common voltage Vcom (A) is maintained. AC drive for liquid crystal to prevent deterioration is realized. On the other hand, when the image signal data (B) is not input to the pixel electrode portion, that is, when the image signal data (B) is a signal of L (0 V: “0”), the pixel voltage Pixel and the common voltage Vcom (A). There is no potential difference between the two and the white display in the normally white mode, and the black display in the normally black mode. Thus, even if the common voltage Vcom (A) is inverted and driven, a state in which there is no potential difference between the pixel voltage Pixel and the common voltage Vcom (A) is maintained, so that display in the pixel electrode portion is maintained. This realizes AC driving for the liquid crystal to prevent deterioration of the liquid crystal.

  Further, when rewriting the display in the pixel electrode section, a transfer gate circuit formed by connecting two n-channel TFT elements 61a and 61b in series in the input section 61 in the previous stage of the drive selection circuit 64 shown in FIG. 7 is turned on. To do. That is, the signal transmitted through the gate signal line GLn is set to H, and the signal transmitted through the image signal activation line SLn is set to H. In this state, the signal (data) transmitted through the image signal line 37 is transmitted to the holding circuit 62. For example, when the signal (data) is H, the holding circuit 62 holds the H signal (data). Then, a display corresponding to the case where data (B) in FIG. That is, the display of the pixel electrode portion is black in the normally white mode and white in the normally black mode. On the other hand, when the signal (data) is L, the holding circuit 62 holds the L signal (data). Then, a display corresponding to the case where data (B) in FIG. 10 is L is executed on the pixel electrode portion. That is, the display of the pixel electrode portion is rewritten so that white display is performed in the normally white mode and black display is performed in the normally black mode.

  With the above-described configuration, the dot matrix display device of the present invention can perform rewrite driving in the display area for each pixel (dot), and can drive all other pixels as still images. The power can be very low. For example, in a conventional black and white display LCD for a wristwatch, the power consumption of about 100 μW when performing still image driving and rewriting driving by full screen scanning is 10 μW in the dot matrix type display device of the present invention. It can be suppressed to about less than or equal to about 3 μW. As a result, even with an LCD having a complicated display configuration, for example, it is possible to extend the drivable period by 10 times or more by replacing the battery once. Further, in the dot matrix type display device of the present invention, the n-channel TFT element constituting the holding circuit 62 is controlled so that the off-leakage current value of the channel is low, and the p-channel TFT element constituting the holding circuit 62 is Since the channel is controlled to have a low off-leakage current value, the power consumption can be reduced to about 0.3 μW or less.

  Furthermore, the dot matrix type display device of the present invention is preferably provided with a plurality of display regions to which the rewrite drive is applied with different rewrite cycles, and the ratio of the different rewrite cycles is 10 times or more. With this configuration, the power consumption can be reduced by setting the period between rewriting and the next rewriting to be very long in one display area and setting the period between the rewriting and the next rewriting to be short in other display areas. The control can be performed with fine and high accuracy. As a result, power consumption can be further reduced. Furthermore, the effect of further reducing power consumption is enhanced by setting the ratio of different rewrite cycles to 10 times or more.

  FIG. 11 shows a display panel of a digital display wristwatch to which the dot matrix type display device of the present invention is applied.As shown in FIG. 11, for example, in the display panel, a display area 91 for displaying time, The rewrite cycle can be greatly different between the display area 92 for displaying the minute and the display area 93 for displaying the second. In the display area 93 for displaying seconds, rewriting is driven every second, whereas in the display area 92 for displaying minutes, rewriting is driven every minute and in the display area 91 for displaying time, every hour. The rewriting drive may be performed. Accordingly, the display area other than the display areas 91 to 93 is a still image display area 94. As a preferred embodiment, the ratio of the rewrite drive cycle of the display area 92 for displaying minutes and the display area 93 for displaying seconds is 60 times. In other words, it can be said to be 1/60. Further, in the display area 91 for displaying the time, the rewriting drive may be performed every hour, so the ratio of the rewriting driving cycle of the display area 93 for displaying the second and the display area 91 for displaying the time is 3600 times. . In other words, it can be said to be 1/3600. In the display areas 91 to 93, the rewrite drive can be performed for each pixel (dot), but the rewrite drive may be performed for each of a plurality of pixels. In the display areas 91 to 93, all the pixels may be rewritten, or only the pixels necessary for rewriting may be rewritten. For example, in the case where the display of “5” is rewritten to “6” in one display region, it is possible to distinguish between pixels that do not need to be rewritten and pixels that need to be rewritten, so that only the pixels that need to be rewritten can be rewritten.

  In addition, when a wristwatch receives a radio signal for incoming mail from a mobile phone, smartphone, tablet terminal, personal computer, etc., the pixel selection drive system described above displays the mail reception on the display panel consisting of the wristwatch's LCD, etc. This can be done by rewriting driving. Such a complicated display function can be performed with extremely low power consumption. For example, temperature, humidity, altitude, direction, illuminance, barometric pressure, water depth, water pressure, weather forecast, time difference with foreign countries, pedometer, tide time, sunrise / sunset time, blood pressure, pulse, email content, breaking news, Notifications such as earthquake early warnings can be displayed at their optimum rewriting cycle or at an arbitrary timing. In addition, the rewrite cycle or display timing can be controlled by an external input or change by a person. The rewrite cycle change, control, or display timing control can be performed by a control LSI or the like provided around the dot matrix display device.

  In the dot matrix type display device of the present invention, the rewriting period corresponding to the rewriting cycle of the display area includes an operation period in which rewriting is performed and other rewriting suspension periods, and the rewriting suspension period is longer than the operation period. Is preferred. With this configuration, the display switching operation by rewriting becomes quick and the display switching process is not visually recognized, so that the display switching is easy to see. For example, when rewriting the clock seconds display, the rewrite period is 1 second, the rewrite operation period is about 0.1 to 0.3 seconds (10% to 30%), and the other period is about 0.7 to 0.9 seconds. A rewriting suspension period may be used.

  Also, the number of pixels in a display area with a short rewrite cycle, such as a display area that displays the seconds of a clock, is made smaller than the number of pixels in a display area with a long rewrite cycle, such as a display area that displays the time for the clock It is preferable. Thereby, power consumption can be further reduced. For example, the number of pixels in the display region with a short rewrite cycle is preferably 30% or less, more preferably 10% or less, of the number of pixels in the display region with a long rewrite cycle.

  As described above, as a preferred embodiment, since the pixel electrode control circuit 63 shares the first inverter 62a of the holding circuit 62, the number of TFT elements is reduced, resulting in a reduction in power consumption. As the effect increases, the aperture ratio of the pixel electrode portion increases.

  Further, the dot matrix type display device of the present invention is preferably a reflection type LCD having a pixel electrode as a reflection type electrode. In this case, the holding circuit 62 and the like can be disposed below the pixel electrode, and a decrease in light reflectance due to the holding circuit 62 and the like can be eliminated. On the other hand, in a transmissive LCD, if the transparent pixel electrode and the holding circuit 62 are arranged so as to overlap with each other, the TFT elements constituting the holding circuit 62 and the like may malfunction due to the transmitted light. For this reason, it is necessary to cover the gate electrode portion of the TFT element with a light-shielding film, and the aperture ratio tends to decrease. In addition, since the reflective LCD does not require a backlight, it is effective in reducing power consumption. Further, the dot matrix type display device of the present invention may be a transflective liquid crystal display device provided with a reflective region having the reflective electrode and a transmissive region having a transmissive electrode in the region of the pixel electrode.

  In addition, the number of bits held by the holding circuit 62 is preferably 1 or more. When the number of bits is increased to a plurality of bits, gradation display can be performed during still image display. Further, if the holding circuit 62 for storing analog signals is used, full-color display can be performed during still image display.

  Further, as shown in the truth table of FIG. 10, the pixel electrode control circuit 63 performs the still image driving and the rewriting driving for any of the H / L signals of the common voltage Vcom. That is, when the common voltage Vcom (A) is H (3 V) and the image signal data (B) is H (3 V), there is a potential difference between the common voltage Vcom (A) and the pixel voltage Pixel (L: 0 V). Similarly, when the common voltage Vcom (A) is L (0 V) and the image signal data (B) is H (3 V), the common voltage Vcom (A) and the pixel voltage Pixel (H: 3 V) are similarly generated. A potential difference is formed between them, and the liquid crystal is AC driven. Thereby, for example, the H / L of the common voltage Vcom (A) can be inverted every second in accordance with the rewriting cycle of the second display, and deterioration of the liquid crystal molecules can be suppressed. That is, when a DC voltage component is applied to the liquid crystal molecules for a long time, it is possible to prevent the liquid crystal molecules from causing a bias of positive and negative charges (fixation of a small amount of impurities) on the pixel electrode surface and shortening the lifetime.

  As described above, it is preferable to periodically invert the H / L inversion of the common voltage Vcom in conjunction with the rewrite cycle. In this case, compared with the case where the H / L inversion of the common voltage Vcom is not linked to the rewrite cycle, it is not necessary to add a control circuit or the like for individually controlling the common voltage Vcom, and the power consumption is further reduced. It is effective for. Further, the H / L inversion driving of the common voltage Vcom includes inversion driving for suppressing deterioration of liquid crystal molecules, and a pixel voltage control signal as a control input of the pixel electrode control circuit 63 constituting the EXOR logic gate circuit. This contributes to further reduction in power consumption.

  In the dot matrix display device of the present invention, it is preferable to periodically invert the high / low of the common voltage supplied to each pixel electrode portion in a display region to which still image driving is applied. Thereby, the deterioration of the liquid crystal molecules is suppressed not only in the display area to which the rewrite drive is applied but also in the area to which the still image drive is applied.

  Further, the periodic period of inversion of the common voltage Vcom can be appropriately set by the control LSI or the like every second, every several tens of seconds, minutes, or hours. Further, the inversion cycle of the common voltage Vcom may be set every n seconds (n is a natural number). In this case, the rewrite cycle of the second display can be used as a base for controlling the inversion of the common voltage Vcom. It becomes easy to control the inversion.

  In the dot matrix display device of the present invention, an auxiliary capacitor of about 1 to 3 pF may be connected in parallel between the pixel electrode control circuit 63 and the pixel electrode. As a result, when rewriting driving is performed, it is possible to suppress the pixel voltage from gradually decreasing and becoming difficult to hold for one field period, and to hold the pixel voltage for one field period.

  In addition, when the pixel electrode has translucency, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide added with silicon oxide (ITSO), zinc oxide (ZnO), phosphorus or boron It can be formed using a light-transmitting conductive material such as silicon (Si).

  Display elements placed in the pixel electrode section include LCD elements, organic EL (Electro Luminescence) elements, inorganic EL elements, FED (Field Emitting Display) elements, SED (Surface-conduction Electron-emitter Display) elements, and GLV (Grating Light). Display elements such as a Valve element, a PDP (Plasma Display) element, an electronic paper display element, a DMD (Digital micro Mirror Device) element, and a piezoelectric ceramic display element can be used. The dot matrix type display device of the present invention is preferably of an in-plane switching (IPS) system or a fringe field switching (FFS) system. In this case, the common voltage is controlled for each pixel electrode part by forming the common electrode for each pixel electrode part on the main surface of the array side substrate on which the pixel electrode is formed (the substrate on which the TFT element is formed). It can be done independently.

  Further, the dot matrix display device of the present invention can be applied to various electronic devices. The electronic devices include digital display watches such as smart watches, automobile route guidance systems (car navigation systems), ship route guidance systems, aircraft route guidance systems, smartphone terminals, mobile phones, tablet terminals, and personal digital assistants (PDAs). Video cameras, digital still cameras, electronic notebooks, electronic books, electronic dictionaries, personal computers, copying machines, terminal devices for game machines, televisions, product display tags, price display tags, industrial programmable display devices, car audio, There are a head-up display, a digital audio player, a facsimile, a printer, a copier, an automated teller machine (ATM), a vending machine, a head mounted display device (HMD), and the like.

1 TFT element 2 Common voltage line 3 Gate signal line drive circuit 4 Image signal line drive circuit
10 Display section
11 LCD panel
21,31 inverter
22,32 NOR logic gate circuit
23,33 Booster circuit (level shifter)
24,34 inverter
35 n-channel TFT device
36,37 Image signal line
41,51 p-channel TFT device
42,52 n-channel TFT device
43,53 inverter
44,54 One transfer gate circuit
45,55 Transfer gate circuit on the other side
61 Input section
61a n-channel TFT element on the image signal line side
61b n-channel TFT element on the gate signal line side
62 Holding circuit
62a First inverter
62b Second inverter
63 Pixel electrode control circuit
64 Drive selection circuit
81 First binary selection circuit
81a p-channel TFT device
81b n-channel TFT device
82 Second binary selection circuit
82a p-channel TFT device
82b n-channel TFT device
91 Display area for displaying time
Display area displaying 92 minutes
Display area displaying 93 seconds
94 Display area for displaying still images

Claims (8)

  A plurality of gate signal lines formed in a predetermined direction on the substrate; a plurality of image signal lines formed to intersect the gate signal lines in a direction intersecting the predetermined direction; and the gate signal lines And a pixel electrode unit including a drive selection circuit for selecting either rewrite driving or still image driving formed at an intersection of the image signal lines and one of the plurality of gate signal lines. And a gate signal line driving circuit that is turned on, and an image signal line driving circuit that arbitrarily turns on one of the plurality of image signal lines, and the drive selection circuit. A pixel electrode control circuit for rewriting the selected pixel electrode portion at the intersection of the gate signal line in the on state and the image signal line in the on state, and driving the non-selected pixel electrode portion in a still image Holding circuit for The holding circuit is a static memory composed of an n-channel thin film transistor element and a p-channel thin film transistor element, and the n-channel thin film transistor element has a p-type impurity whose channel reduces an off-leakage current value. The p-channel thin film transistor element is a dot matrix display device in which the channel contains an n-type impurity that reduces an off-leakage current value. The n-channel thin film transistor element has a p-type impurity of 1 × 10 ¹¹ cm ^{−2 to} 3 × 10 ¹² cm ⁻² in the channel, and the p-channel thin film transistor element has an n-type impurity of 1 × 10 ¹¹ The dot matrix type display device according to claim 1, which contains cm ⁻² to 1 × 10 ¹² cm ⁻² .   The dot matrix type display device according to claim 1, wherein the p-type impurity is boron and the n-type impurity is phosphorus. 4. The dot according to claim 1, wherein each of the n-channel thin film transistor element and the p-channel thin film transistor element has a channel made of low-temperature polycrystalline silicon having an off-leakage current value of 10 ⁻¹¹ A or less. Matrix type display device.   A plurality of gate signal lines formed in a predetermined direction on the substrate; a plurality of image signal lines formed to intersect the gate signal lines in a direction intersecting the predetermined direction; and the gate signal lines And a pixel electrode unit including a drive selection circuit for selecting either rewrite driving or still image driving formed at an intersection of the image signal lines and one of the plurality of gate signal lines. And a gate signal line driving circuit that is turned on, and an image signal line driving circuit that arbitrarily turns on one of the plurality of image signal lines, and the drive selection circuit. A pixel electrode control circuit for rewriting the selected pixel electrode portion at the intersection of the gate signal line in the on state and the image signal line in the on state, and driving the non-selected pixel electrode portion in a still image Holding circuit for The holding circuit is a static memory composed of an n-channel thin-film transistor element and a p-channel thin-film transistor element, and the n-channel thin-film transistor element has a p-channel whose channel increases the first threshold voltage. A dot matrix type display device, wherein the p-channel thin film transistor element contains an n-type impurity that lowers a second threshold voltage. The n-channel thin film transistor element has a p-type impurity of 1 × 10 ¹¹ cm ^{−2 to} 3 × 10 ¹² cm ⁻² in the channel, and the p-channel thin film transistor element has an n-type impurity of 1 × 10 ¹¹ The dot matrix type display device according to claim 5, which contains cm ⁻² to 1 × 10 ¹² cm ⁻² .   The dot matrix type display device according to claim 5, wherein the p-type impurity is boron, and the n-type impurity is phosphorus.   The voltage difference between the first threshold voltage of the n-channel thin film transistor element and the second threshold voltage of the p-channel thin film transistor element is 2.0V to 3.5V. The dot matrix display device described.