JP2002299265A - Forming method for polycrystalline semiconductor membrane and manufacturing method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for forming a high quality polycrystalline semiconductor membrane of polycrystalline silicon or the like at a high crystallization rate easily formed at low cost over a wide area, and a device for conducting this method. SOLUTION: In the forming method for the polycrystalline semiconductor membrane or the manufacturing method for the semiconductor device, when forming a polycrystalline semiconductor membrane 7 such as polycrystalline silicon membrane having the high crystallization rate and a large grain size on a substrate 1, or when manufacturing the semiconductor device having the polycrystalline semiconductor membrane 7 on the substrate 1, a recessed part 190 having a step of prescribed form and dimension is formed on the substrate 1, and after silicon or carbon hyperfine-grains 100A are stuck inside this recessed part, cleaning is performed by bias catalytic AHA treatment. Then,the polycrystalline semiconductor membrane 7 is provided with a vapor phase growth process (further repeating bias catalytic AHA treatment and bias catalytic CVD or the like) for growing the polycrystalline semiconductor membrane by a bias catalytic CVD method or the like, with such a carbon hyperfine- grain 100B of cleaned silicon and/or diamond structure as a seed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for forming a polycrystalline semiconductor thin film such as polycrystalline silicon on a substrate and a method for manufacturing a semiconductor device having the polycrystalline semiconductor thin film on a substrate. is there.

[0002]

2. Description of the Related Art Conventionally, MOSFETs (Metal-Oxide-Semi
conductor Field Effect Transistor)
When forming the source, drain and channel regions of an OSTFT (Thin Film Transistor = Thin Film Insulated Gate Field Effect Transistor) with a polycrystalline silicon film, plasma CVD (Chemical Vapor Deposition) or PVD (Chemical Vapor Deposition) is used. PVD: Physical Vapor Depo
sition = physical vapor phase epitaxy), low pressure CVD, or the like.

For example, according to Japanese Patent Application Laid-Open No. 5-283726, on a substrate polished with silicon powder, fine particles of silicon powder attached to the substrate are used as nuclei.
There has been proposed a method of forming a polycrystalline silicon film by repeating a process of forming an amorphous silicon film by a plasma CVD or PVD method and then exposing the amorphous silicon film to hydrogen plasma of an ECR discharge using a permanent magnet for a predetermined time.

In addition, plasma CVD, low pressure CVD, etc.
The amorphous or polycrystalline silicon formed by
Kaihei 7-131030, JP-A-9-116156,
As seen in Japanese Patent Publication No. Hei 7-118443, simply high temperature
Annealing or excimer laser annealing (ELA: Exci
mer Laser Anneal) treatment to produce polycrystalline silicon
The carrier mobility of the thin film has been improved.
Then 80-120cm ^Two/ V · sec carrier transfer
Mobility was the limit. However, plasma CVD
Obtained by ELA of amorphous silicon thin film
Electron mobility of MOSTFT using polycrystalline silicon thin film
Is 100cm^Two/ V · sec, for higher definition
Recently, polycrystalline silicon integrated with a drive circuit has been developed.
LCD (Liquid Crystal Dis
play = liquid crystal display device) (Japanese Patent Laid-Open No. 6-2)
No. 42433).

[0005]

However, none of the above-mentioned methods can avoid the following disadvantages.

(1) In the above-mentioned method using silicon powder, in order to control the particle diameter, polishing with silicon powder or a paste containing silicon powder, or dispersion of silicon powder in an organic solvent, Although the time is controlled by using a sonic cleaning machine, it is not possible to control the adhesion to an arbitrary designated place on the substrate. For this reason, for example, since a TFT formation region on a substrate cannot be designated, a high-performance / high-quality TFT cannot be formed and its integrated circuit substrate cannot be formed freely.

(2) The control of the silicon grain size in this method is not sufficient, and the film quality of the polycrystalline silicon on the substrate varies, resulting in characteristic variations and yield and quality problems. In addition, during the adhesion and dispersion of the silicon powder, an oxide film and an organic dirt coating are easily formed on the surface thereof.
It is unlikely to be a seed for polycrystalline silicon crystal growth.

(3) The hydrogen plasma of the ECR discharge using the permanent magnet has a higher effect than the hydrogen plasma of the RF / VHF plasma, and thus has a high effect. The productivity of the substrate processing of the area is low, and the ECR apparatus is expensive and has low versatility.

Further, when an excimer laser is used, there are many problems such as stability of output, productivity, increase in apparatus price due to increase in size, and decrease in yield / quality.
In the case of a large glass substrate of mx 1 m, the above-mentioned problems are magnified, and it becomes more difficult to improve performance / quality and reduce costs.

Also, polycrystalline silicon M by a solid phase growth method is used.
In the manufacturing method of the OSTFT, annealing for more than 10 hours at 600 ° C. or more and formation of a gate SiO ₂ for thermal oxidation at about 1000 ° C. are required, so that a semiconductor manufacturing apparatus has to be employed. For this reason, the substrate size should be wafer size 8 ~
The limit is 12 inches φ, and expensive heat-resistant and expensive quartz glass must be adopted, which makes it difficult to reduce the cost and limits its use to EVF and data / AV projectors.

Recently, a catalytic CVD method, which is an excellent thermal CVD method capable of forming a polycrystalline silicon film, a silicon nitride film and the like at a low temperature on an insulating substrate such as a glass substrate, has been developed (JP-B-63-40314). No., Tokuhei 8-250438
No.), and studies for practical use are being promoted. Catalytic CVD
In the method, 30 cm ² / V without crystallization annealing
・ Carrier mobility of about sec, but high quality M
It is still not enough to make OSTFT devices.
When a polycrystalline silicon film is formed on a glass substrate, an initial amorphous silicon transition layer (5 to 10 nm in thickness) is likely to be formed depending on the film formation conditions. Mobility is difficult to obtain. Generally, an LCD using a polycrystalline silicon MOSTFT integrated with a driving circuit is a bottom gate type MOFET.
Although STFTs are easy to manufacture in terms of yield and productivity, this problem is a bottleneck.

An object of the present invention is to provide a method capable of easily forming a polycrystalline semiconductor thin film such as polycrystalline silicon with a high crystallization rate and high quality over a large area at a low cost.

It is another object of the present invention to provide a method of manufacturing a semiconductor device such as a MOSTFT having such a polycrystalline semiconductor thin film as a constituent part.

[0014]

That is, the present invention relates to a method for forming a polycrystalline semiconductor thin film on a substrate or manufacturing a semiconductor device having the polycrystalline semiconductor thin film on the substrate. A step of forming a concave portion having a step having an appropriate shape / dimension, a step of attaching ultrafine particles made of silicon and / or carbon in at least the concave portion, and bringing hydrogen or a hydrogen-containing gas into contact with the heated catalyst. Cleaning by applying the hydrogen-based active species generated thereby to the ultrafine particles under the action of an electric field or / and a magnetic field of a glow discharge starting voltage or less, and at least a part of the raw material gas and hydrogen or a hydrogen-containing gas. Is brought into contact with the heated catalyst body to catalytically decompose, and at least the reactive species such as radicals and ions generated by this are reduced to a glow discharge starting voltage or less. A step of crystal-growing the ultrafine particles as seeds under the action of an electric field or / and a magnetic field to vapor-phase-grow a semiconductor material thin film to obtain the polycrystalline semiconductor thin film, a method of forming a polycrystalline semiconductor thin film, Alternatively, the present invention relates to a method for manufacturing a semiconductor device.

According to the present invention, when forming a polycrystalline semiconductor thin film on a substrate, a concave portion having a step of an appropriate shape / dimension is formed on the substrate, and at least silicon and / or carbon are formed in the concave portion. Hydrogen or a hydrogen-containing gas is brought into contact with the heated catalyst body, and the hydrogen-based active species generated thereby is subjected to the action of an electric field or / and a magnetic field of a glow discharge starting voltage or less. The semiconductor material thin film is vapor-grown by crystal growth using the ultrafine particles as a seed, so that the following remarkable functions and effects (1) to (7) can be obtained. Can be

(1) A concave portion having a step having an appropriate shape and dimensions is formed at an arbitrary designated place on a substrate, and ultrafine particles such as silicon powder are adhered and dispersed therein, and a bias catalyst A is formed.
By the action of the hydrogen-based active species in the HA treatment, the amorphous component of the ultrafine particles can be selectively removed by etching, and furthermore, the oxide film and organic dirt on the surface of the ultrafine particles can be removed. As a nucleus (seed), a polycrystalline silicon thin film or the like having a small particle size and a large particle size can be formed in a designated region by bias or non-bias catalytic CVD, high-density bias catalytic CVD, or the like.
Bias catalyst A compared to hydrogen plasma treatment of ECR discharge
The HA treatment has a wide effective area of strong energy (can be freely set by the size of the catalyst body) and its variation is small, so that the productivity of large-area substrate treatment is high, and the versatility is high because it is inexpensive. . Here, hydrogen-based active species (high-temperature hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions, etc.) generated by bringing hydrogen or a hydrogen-containing gas into contact with the heated catalyst body are equal to or lower than the glow discharge starting voltage (that is, A bias catalyst, AHA (Atomic Hyd), is used to perform the treatment under the action of the electric field and / or the magnetic field of the plasma generation voltage according to Paschen's law.
rogen Anneal) treatment, but this bias catalyst AH
By the A treatment, hydrogen-based active species such as high-temperature hydrogen-based molecules, hydrogen-based atoms, and active hydrogen ions are applied to the ultrafine particles by spraying or the like. In addition, the organic substance and oxide film on the surface of the ultrafine particles can be removed, and can be effectively used as a seed for crystal growth of a polycrystalline semiconductor thin film.

(2) A high-performance, high-quality TFT can be formed at any designated place on the insulating substrate, and the integrated circuit substrate can be freely formed. Then, if necessary, the surface in which the large-grain polycrystalline silicon film is embedded in the concave portion having a step having an appropriate size and shape in the TFT forming region on the insulating substrate is polished to obtain a flat large-grain. Since a substrate having a polycrystalline silicon film surface with a diameter can be obtained, high-performance, high-quality polycrystalline silicon semiconductor devices, electro-optical devices, and the like can be manufactured.

(3) This bias catalyst AHA treatment is performed under reduced pressure (for example, a hydrogen-based carrier gas pressure of 10 to 50 Pa).
The hydrogen is converted to a high-temperature catalyst (800 to 2000
C., for example, 1500-2000 ° C. for tungsten), and a large amount of high-temperature hydrogen-based active species (hydrogen-based molecules,
When hydrogen atoms and activated hydrogen ions are generated and sprayed on silicon and / or carbon ultrafine particles formed on the substrate (the substrate temperature is particularly 300 to 400).
° C), sufficient thermal energy of a large amount of high-temperature hydrogen-based active species (hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions, etc.), and sufficient directional kinetic energy in the accelerating electric field or / and magnetic field by the electric field. , The temperature is locally increased, the organic substances and oxide film on the surface of the ultrafine particles are etched and removed by the action of hydrogen-based active species, and the ultrafine particles (cluster) are reliably stabilized. This can be effectively used as a nucleus (seed) for the next crystal growth of polycrystalline silicon or the like.

(4) The ultrafine particles obtained by the bias catalyst AHA treatment are used as seeds, and a semiconductor material thin film is formed thereon by bias catalyst CVD or high density Bias catalyst CVD (high density plasma CVD and bias catalyst CV
D), it is easy to grow (as a polycrystalline semiconductor thin film) in a state where it is easily polycrystallized, and in particular, by the following bias catalyst AHA treatment and bias catalyst CVD, etc. Crystallization of the phase-grown silicon film or the like is promoted by using the polycrystalline semiconductor thin film as a seed, so that a desired polycrystalline semiconductor thin film having a high crystallization rate and high quality can be obtained. That is, the silicon film grown in vapor phase on the ultrafine particles by the bias catalyst AHA treatment is more easily converted into a polycrystalline silicon film by using the underlying ultrafine particles as a seed (nucleus) for crystal growth, and a large amount of high-temperature hydrogen-based active species Thermal energy of the accelerating electric field or /
And move to the film etc. by sufficient directional kinetic energy by the magnetic field, locally raise the temperature of the film etc.,
The amorphous silicon thin film and the microcrystalline silicon thin film are polycrystallized, and the polycrystalline silicon thin film is highly crystallized, so that a polycrystalline silicon thin film having a high crystallization rate and a large grain size can be formed. For example, if silicon having an amorphous structure is present in a silicon thin film formed by bias catalyst CVD, the silicon thin film is etched and removed by bias catalyst AHA treatment, and silicon is polycrystallized thereon to easily grow. Further, when the same bias catalyst AHA treatment and bias catalyst CVD are repeated, a polycrystalline silicon thin film having a higher crystallization rate and a larger grain size, which is more polycrystallized, can be formed. As a result, not only the top gate type but also the bottom gate type and the dual gate type MOS TFT can obtain a polycrystalline silicon thin film having a high crystallinity with a high carrier (electron / hole) mobility and a large grain size. In addition, a high-speed, high-current-density semiconductor device, an electro-optical device, and a high-efficiency solar cell using the high-performance semiconductor thin film such as polycrystalline silicon can be manufactured.

(5) Conventional RF / VHF plasma CVD
Compared with the bias catalytic CVD, the source gas is efficiently thermally decomposed and catalyzed by high energy, so that the utilization efficiency of the source gas is high and the film forming speed is high, so that the productivity is high and the cost can be reduced.

(6) Since bias catalyst CVD and bias catalyst AHA treatment can be performed without generating plasma,
It is possible to realize a simple and inexpensive apparatus which is not damaged by plasma and which is simpler than the plasma AHA processing.

(7) In the bias catalyst AHA treatment, even if the substrate temperature is lowered, the energy of the hydrogen-based active species is large, so that the target ultrafine particles of silicon and / or diamond-structured carbon are reliably and stably formed. Therefore, even if the substrate temperature is lowered to 300 to 400 ° C. in particular, the polycrystalline semiconductor thin film grows efficiently with the ultrafine particles as seeds, and thus is a large and inexpensive low strain point insulating substrate (glass substrate, Heat-resistant resin substrate) can be used, and the cost can be reduced also in this regard.

In the present invention, the ultrafine particles of silicon and / or carbon formed by the above-mentioned bias catalyst AHA treatment have a particle diameter of 1 nm or more (preferably 10 to 10 nm).
(0 nm), and it is desirable that they are scattered at an area ratio of 1 / μm ² or more (preferably 1 to 100 / μm ² ).
In addition, the above-mentioned polycrystalline semiconductor thin film is based on a polycrystal having a large grain size (normally several hundred nm or more in grain size) from which an amorphous component may be removed or a trace amount thereof may be present. Consists of a structure containing In addition, the above-mentioned semiconductor material thin film which becomes the polycrystalline semiconductor thin film is a low-crystalline semiconductor thin film other than polycrystal, and has a structure based on microcrystal containing an amorphous component, for example, a microcrystalline silicon thin film. , Referred to as microcrystalline carbon thin film, or amorphous containing microcrystals
Are referred to as, for example, an amorphous silicon thin film and an amorphous carbon thin film. This is because the carbon fine particles become carbon having a diamond structure due to the action of hydrogen-based active species and the like in the bias catalyst AHA treatment, and these serve as seeds for crystal growth to form a polycrystalline silicon thin film.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the method of the present invention, a general-purpose photolithography and etching technique is preferably used to form a recess having an appropriate size and a step on a substrate such as a glass substrate. Step (depth) 5
It is preferable to form a recess of 0 to 500 nm, 10 μm in length × 30 μm in width. In this case, RIE (Reactive Ion Etchi
ng), plasma etching with CF ₄ gas, or wet etching with a hydrofluoric acid-based etchant may be performed.

Then, in order to adhere and disperse silicon powder or carbon powder or fine particles in which these are mixed into the concave portion, polishing is performed with silicon powder or carbon powder or a paste containing silicon powder and carbon powder. Fine particles of silicon powder or carbon powder or silicon powder and carbon powder may be attached and dispersed. In addition, silicon powder or carbon powder or a powder in which these are mixed with an organic solvent (acetone, ethyl alcohol,
(E.g., ethyl alcohol / acetone), and silicon powder or carbon powder, or fine particles in which these are mixed may be adhered and dispersed in the recesses by controlling the power and time of the ultrasonic cleaner. These powder particle sizes are 10n
m to 10 μm, for example 50 to 200 nm, especially 10 to 5
0 nm is desirable. In the case where polishing is not performed, a particle size smaller than the size of the concave step is desirable.

The surface of the silicon powder and / or carbon powder adhering to the recesses is cleaned by the bias catalyst AHA treatment to remove foreign films such as oxide films and organic dirt, and at the same time, to remove silicon and carbon having an amorphous structure. Is selectively etched to form silicon fine particles and carbon fine particles having a diamond structure,
Used as a seed for polycrystalline growth. The bias catalyst AHA treatment may be performed as a continuous operation before forming a polycrystalline semiconductor thin film by the next bias catalyst CVD, high density bias catalyst CVD, or the like.

This polycrystalline semiconductor thin film is preferably formed by a vapor phase growth method (biased or non-biased catalytic CVD method, high-density bias CVD method, etc .; hereinafter the same). In this case, it is desirable that the temperature be lower than the melting point (800 to 2).
The raw material gas and at least a part of hydrogen or a hydrogen-containing gas are brought into contact with the catalyst body heated to 000 ° C., for example, 1600 ° C. to 1800 ° C., to catalytically decompose, and the reaction of radicals and ions generated thereby. Species are deposited on the heated substrate under the action of an electric or / and magnetic field below the glow discharge onset voltage and the thin film is applied to a bias catalyst CV.
It is preferable to perform vapor phase growth with D. At this time, silicon powder or carbon powder in the concave portion provided on the substrate (particularly, carbon fine particles having a diamond structure: the same applies hereinafter).
Alternatively, fine particles containing a mixture of silicon powder and carbon powder are used as nuclei (seed) for crystal growth, for example, tin containing 10 ¹⁸
It is possible to form a polycrystalline silicon thin film having a large grain size containing 10 to ²⁰ atoms / cc. Then, if necessary, the semiconductor material thin film is preferably polished to flatten the surface including the thin film surface, and the polycrystalline silicon thin film can be embedded in the recess in the TFT region of the substrate.

After the vapor phase growth, the supply of the raw material gas is stopped continuously, and preferably, a catalyst heated to a temperature lower than the melting point (this is preferably the same as the catalyst) Is contacted with at least a part of the hydrogen or the hydrogen-containing gas, and hydrogen-based molecules such as high-temperature hydrogen-based molecules, hydrogen-based atoms, and activated hydrogen ions are generated. It is preferable that the seed is allowed to act on the semiconductor material thin film under the action of an electric field and / or a magnetic field equal to or lower than the glow discharge starting voltage, and annealing is performed by bias catalyst AHA treatment.

In this case, the supply amount of hydrogen or the hydrogen-containing gas during the annealing is set to be larger than the supply amount of hydrogen or the hydrogen-containing gas during the vapor phase growth. For example, the hydrogen-based carrier gas used during vapor phase growth is hydrogen or a mixed gas of hydrogen and an inert gas (argon, helium, xenon, krypton, radon, etc., which have good thermal conductivity and contribute to the improvement of reactivity). In the case of mixed gas, the hydrogen content ratio is 50 mol%
With the above, oxidation deterioration of the catalyst body can be prevented. The hydrogen or the hydrogen-containing gas used in the bias catalyst AHA treatment may be the same as the hydrogen-based carrier gas used in the vapor phase growth.
CCM (Standard cc per minute), gas pressure 10-50
It is preferable to increase the pressure to Pa (the gas pressure at the time of bias or non-bias catalytic CVD is 0.1 to several Pa) to increase the heat conduction by the gas and increase the generation amount of the hydrogen-based active species.

Further, after the vapor phase growth of the semiconductor material thin film, hydrogen or a hydrogen-containing gas is continuously brought into contact with the heated catalyst to generate high-temperature hydrogen-based molecules,
Hydrogen-based active species such as hydrogen-based atoms and activated hydrogen ions are allowed to act on the semiconductor material thin film under the action of an electric field and / or a magnetic field equal to or lower than a glow discharge starting voltage, and annealing is performed. It is desirable to repeat the same vapor phase growth of a semiconductor material thin film and the annealing as described above. To this end, it is preferable to have control means for controlling the raw material gas supply means and the hydrogen or hydrogen-containing gas supply means.

That is, the step of further vapor-phase growing a semiconductor material thin film on the polycrystalline semiconductor thin film obtained by the bias catalyst AHA treatment and the annealing step are repeated until the target film thickness is reached, ie, two steps or so. By the above-described multi-catalyst bias AHA treatment, the semiconductor material thin film is easily grown on the base film already polycrystallized by the bias catalyst AHA treatment in a state where it is easily polycrystallized by using this as a seed. A high-quality polycrystalline semiconductor film having a crystallization ratio and a predetermined thickness can be obtained. That is, by multi bias catalyst AHA processing in which bias catalyst CVD and bias catalyst AHA processing are repeated, for example, polycrystalline silicon formed on silicon or diamond ultrafine carbon particles by bias catalyst CVD is seeded by bias catalyst AHA processing. , Bias catalyst CVD on this
Vapor-phase growth of a semiconductor material thin film by using
By performing the HA treatment, a polycrystalline silicon film or the like having a high crystallization rate and a large grain size can be formed.

More specifically, in a silicon film, thermal energy of a large amount of high-temperature hydrogen-based active species or the like is transferred with sufficient directional energy in the accelerating electric field and / or magnetic field by the electric field. Temperature is locally increased, the amorphous component is etched by the reduction action of hydrogen-based active species, the microcrystalline silicon thin film and the like are polycrystallized, and the polycrystalline silicon thin film is highly crystallized and has a large grain size polycrystalline. A silicon thin film is easily formed, and a polycrystalline silicon thin film to be vapor-phase grown thereon is further crystallized and has a large grain size, thereby improving carrier mobility.

In addition, when silicon oxide is present on or in the polycrystalline silicon thin film, or in the film or at the grain boundaries, hydrogen-based active species react with the silicon oxide to generate SiO and evaporate and remove it. Silicon oxide on or in a thin film can be reduced / removed, and carrier mobility can be improved.

The bias catalyst CVD, the high-density bias catalyst CVD, and the subsequent bias catalyst AHA
In the case of the treatment, depending on the bias condition of the electric field or / and the magnetic field, the type and temperature of the catalyst, the substrate heating temperature, the vapor deposition conditions, the type of the source gas, the n or p-type impurity concentration to be added, etc.
Since a polycrystalline silicon thin film having a wide range of n or p-type impurity concentration can be easily obtained, and a polycrystalline silicon thin film having a large particle size can be formed by the bias catalyst AHA treatment.
V _th (threshold) adjustment is easy with high carrier mobility, and high-speed operation with low resistance is possible.

When the CVD is performed by the bias catalyst CVD under the action of the electric field and / or the magnetic field (further, when the bias catalyst AHA treatment and the bias catalyst CVD are repeated), the raw material gas is decomposed by the catalyst. Since the accelerating electric field and / or magnetic field by the above-mentioned voltage is given to the generated reactive species (deposited species or its precursor and radical ions) in addition to the catalytic action of the catalytic body and its thermal energy, the directional kinetic energy increases, In addition to being efficiently guided on the substrate, the migration on the substrate and the diffusion in the film during the production process become sufficient, so that the adhesion of the generated film to the substrate, the density of the generated film, the uniformity of the generated film or the smoothness of the generated film are improved. In addition, it is possible to improve the embedding property into a via hole and the like and the step coverage, to further lower the substrate temperature, to control the stress of the formed film, and the like. In addition, the effects (6) and (7) described above by the bias catalyst AHA treatment can be obtained together. Therefore, as compared with the conventional catalytic CVD method, the kinetic energy of the reaction species generated by the catalyst body can be independently controlled by an electric field and / or a magnetic field, so that the above-described effect can be improved and the reaction gas can be improved. Use efficiency is high, generation speed is increased, and costs can be reduced.

In the vapor phase growth by the bias catalyst CVD, specifically, the catalyst is heated at 800 to 2000 ° C.
And heating to a temperature below its melting point (eg, by energizing the catalyst body and heating by its own resistance heating),
The reaction species generated by performing a catalytic reaction or a thermal decomposition reaction of at least a part of the raw material gas and / or the hydrogen-based carrier gas (hydrogen or a hydrogen-containing gas or the like) by the heated catalyst is subjected to a glow discharge starting voltage. Temperature below the strain point of the substrate under the action of the following electric and / or magnetic fields, for example 200
Thin films can be deposited on substrates heated to -800C, especially 300-400C. Such a catalyst body temperature and the following catalyst body material are also the same at the time of the bias catalyst AHA treatment.

Here, if the heating temperature of the catalyst is less than 800 ° C., the catalytic reaction or the thermal decomposition reaction of the raw material gas becomes insufficient and the deposition rate tends to decrease. Constituent materials are mixed into the deposited film to inhibit the electrical characteristics of the film, resulting in deterioration of the film quality, and heating above the melting point of the catalyst body is not preferable because the morphological stability is lost. The heating temperature of the catalyst body is lower than the melting point of the constituent material and is preferably 1100 ° C to 1800 ° C.

The catalyst body is formed of at least one material selected from the group consisting of tungsten, thoria-containing tungsten, molybdenum, platinum, palladium, vanadium, silicon, alumina, ceramics having metal attached thereto, and silicon carbide. Can be.

The purity of the catalyst and the support for supporting the catalyst is 99.99 wt% (4 N) or more, preferably 99.999 wt% (5 N) or more, thereby forming the polycrystalline material. Heavy metal contamination of the semiconductor thin film can be reduced.

The substrate temperature is preferably lower than the strain point of the substrate, for example, 200 to 800 ° C., and more preferably 300 to 400 ° C., so that efficient and high quality film formation can be performed. If the substrate temperature is high, inexpensive borosilicate glass and aluminosilicate glass cannot be used, and the doping concentration distribution of impurities tends to change due to the influence of heat.

As the electric field in the bias catalyst AHA treatment (or bias catalyst CVD), a DC voltage equal to or lower than a glow discharge starting voltage (that is, equal to or lower than a plasma generation voltage determined by Paschen's law, for example, equal to or lower than 1 kV,
(0 V or more) is desirably applied to direct the reactive species or the hydrogen-based active species toward the substrate.

As the electric field, a voltage that is equal to or lower than the glow discharge starting voltage and is obtained by superimposing an AC voltage (high-frequency voltage and / or low-frequency voltage) on a DC voltage (DC) (ie,
Below the plasma generation voltage determined by Paschen's law,
For example, when a voltage of 1 kV or less and several tens of volts or more are applied, the directional kinetic energy in a slight electric field change can be given to the hydrogen-based active species (or the reactive species) by the AC voltage superimposed on the DC voltage. In addition to the function and effect, films of various shapes can be effectively and sufficiently annealed, or the surface of a substrate having a complicated shape (such as an uneven step or a via hole with a high aspect ratio) has good step coverage. A uniform film having high adhesion and high density can be formed. A similar effect is obtained when an AC voltage (high-frequency voltage and / or low-frequency voltage) is applied as a voltage for forming the electric field (the absolute value of which is equal to or lower than the glow discharge starting voltage). can get. Note that, in the above description, the AC voltage means only a high-frequency voltage, only a low-frequency voltage, or a voltage obtained by superimposing a high-frequency voltage on a low-frequency voltage.

In the above case, the AC voltage is converted to a high frequency voltage (RF / VHF) and / or a low frequency voltage (AC / LF).
But the frequency of the high-frequency voltage is 1 to 100 MHz.
z, the frequency of the low frequency voltage is preferably less than 1 MHz.

The electric field is applied by applying a DC positive voltage or a low frequency (or high frequency) voltage to the electrode or a voltage obtained by superposing a low frequency (or high frequency) voltage on the DC positive voltage, or a DC negative (or high) voltage to the susceptor (substrate). A method of applying a ground) voltage, or a ground potential on an electrode, a DC negative voltage or a low frequency (or high frequency) voltage on a susceptor (substrate), or a voltage obtained by superimposing a low frequency (or high frequency) voltage on a DC negative voltage. May be applied. This may be determined according to the device structure, the type of power supply, the bias effect, and the like.

The catalyst can be provided between the base or the susceptor and the electrode or / and the magnetic pole for applying the electric or / and magnetic field. In this case, a gas supply port for leading out the hydrogen-based carrier gas and the source gas is preferably formed in the electrode and / or the magnetic pole.

The catalyst and the electrode and / or magnetic pole for applying an electric field may be provided between the substrate or the susceptor and the gas supply means. The electrode and / or the magnetic pole are desirably formed of a high heat-resistant material, for example, a material having a melting point equal to or higher than that of the catalyst body (the same applies hereinafter).

The catalyst body or the electrodes and / or magnetic poles for applying an electric field may be formed in a coil shape, a wire shape, a mesh shape or a perforated plate shape, and a plurality or a plurality of them are arranged along a gas flow. May be. Thereby, while effectively forming the gas flow, the contact area between the catalyst body and the gas can be increased, and the catalytic reaction can be sufficiently generated. When a plurality or a plurality are arranged along the gas flow, catalysts, electrodes, and / or magnetic poles made of the same material or different materials may be used. The same electric field may be applied to each of a plurality of or a plurality of catalyst bodies, or different electric fields, for example, DC and AC / DC, DC and RF / DC, AC
/ DC and RF / DC or the like may be applied to control each of them independently.

The above-described bias catalyst AHA treatment can be performed by the following methods (1) to (3). (1) Electric field application Under the action of an appropriate electric field below the glow discharge starting voltage, the catalyst A
When the HA treatment, that is, the so-called electric field bias catalyst AHA treatment, is performed, a hydrogen-based active species or the like generated by performing a catalytic reaction or a catalytic cracking reaction of a hydrogen gas or a hydrogen-based gas (hydrogen + inert gas) with the electric field is converted into an electric field. Interact and point in a certain direction,
Directional kinetic energy is applied and acts on fine particles or semiconductor thin films on the substrate.

(2) Application of a magnetic field When a catalyst AHA treatment, that is, a so-called magnetic field bias catalyst AHA treatment is performed under the action of an appropriate magnetic field, hydrogen gas or a hydrogen-based gas (hydrogen + inert gas) is subjected to catalytic reaction or contact of the catalyst. Hydrogen-based active species and the like generated by the decomposition reaction interact with a magnetic field and are directed in a certain direction, impart directional kinetic energy and act on fine particles or semiconductor thin films on a substrate.

(3) Application of Electric Field and Magnetic Field When a catalyst AHA treatment, that is, a so-called electric field / magnetic field bias catalyst AHA treatment is performed by simultaneously applying an appropriate electric field equal to or lower than the glow discharge starting voltage and an appropriate magnetic field, hydrogen gas or hydrogen is applied. Hydrogen-based active species and the like generated by the catalytic reaction or catalytic cracking reaction of the catalytic body of hydrogen-based gas (hydrogen + inert gas) are directed in a certain direction by the interaction of electric and magnetic fields, and the directional kinetic energy is reduced. It is applied and acts on fine particles or semiconductor thin films on the substrate.

Due to the bias effect as described above, a large amount of high-temperature hydrogen-based active species (hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions) and the like can efficiently and selectively form the amorphous component in the lower crystalline semiconductor thin film. Etching, for example, amorphous silicon-containing microcrystalline silicon and microcrystalline silicon-containing amorphous silicon are etched and polycrystalline amorphous components, amorphous silicon and microcrystalline silicon-containing polycrystalline silicon are highly crystallized,
A polycrystalline silicon film is formed efficiently.

The above-described bias catalytic CVD method can be performed by the following methods (1) to (3). (1) Electric field application Catalytic CVD under the action of an electric field lower than the glow discharge starting voltage,
When the so-called electric field bias catalytic CVD is performed, the deposited species generated by the catalytic reaction or catalytic decomposition reaction of the catalytic body, for example, the electron spin of silicon atom, interacts with the electric field and turns in a certain direction, and in this state, the substrate spins on the substrate. The crystal orientations of the deposited polycrystalline silicon are aligned.

(2) Application of magnetic field When catalytic CVD, that is, so-called magnetic field bias catalytic CVD is performed under the action of an appropriate magnetic field, the deposited species generated by the catalytic reaction or catalytic decomposition reaction of the catalytic body, for example, the electron spin of silicon atoms, Interacting with the magnetic field, it is directed in a certain direction, and in this state, the crystal orientation of the polycrystalline silicon deposited on the substrate becomes uniform.

(3) Application of electric field and magnetic field When an appropriate electric field equal to or lower than the glow discharge starting voltage and an appropriate magnetic field are simultaneously applied to perform catalytic CVD, so-called electric field / magnetic field bias catalytic CVD, the catalytic reaction of the catalyst body or Deposition species generated by the catalytic decomposition reaction, for example, electron spins of silicon atoms are directed in a certain direction by the interaction of electric field and magnetic field, and in this state, the crystal orientation of polycrystalline silicon deposited on the substrate is aligned. Become.

By the bias effect as described above, (1) Since the crystal orientation of the crystallized film is substantially uniform, the electron potential barrier of the grain boundary is lowered and the carrier mobility is increased. (2) Since the crystal grains are aligned, the surface of the polycrystalline silicon thin film has no irregularities, and the thin film surface is flattened. Therefore, the interface state between the thin film and the gate insulating film formed in contact with the thin film is good. The carrier mobility is improved, the breakdown voltage is improved, and the TFT characteristics are improved. The effect is obtained.

In the case where a polycrystalline silicon film is formed by a normal thermal CVD method, the substrate temperature must be about 600 to 900 ° C. Instead, thermal CVD at low temperature as described above
It is very advantageous that this is possible. Since the substrate temperature during the bias catalytic CVD according to the present invention is low as described above, the strain point of the substrate, for example, a glass substrate is 470 to 470.
Glass such as borosilicate glass or aluminosilicate glass as low as 670 ° C., a heat-resistant resin substrate, or the like can be used. This is inexpensive, easy to thin, and large (1
m × 1 m or more), and a long rolled glass plate can be produced. For example, a thin film can be continuously or discontinuously formed on a long rolled glass plate using the above-described method.

The source gas used for forming the lower crystalline semiconductor thin film by vapor phase growth by bias or non-bias catalytic CVD according to the present invention is silicon hydride or a derivative thereof,
A mixture of silicon hydride or a derivative thereof and hydrogen, a gas containing germanium, carbon or tin, a mixture of silicon hydride or a derivative thereof and a gas containing an impurity consisting of an element of Group III or Group V of the periodic table, Examples include a mixture of silicon hydride or a derivative thereof, a gas containing hydrogen, germanium, carbon, or tin, and a gas containing an impurity consisting of a Group III or Group V element in the periodic table.

By using the raw material gas as described above, a polycrystalline silicon film as a polycrystalline semiconductor thin film,
A polycrystalline germanium film, a polycrystalline silicon-germanium film, or a polycrystalline silicon carbide film can be formed.

At the time of or after the growth of the semiconductor material thin film, a proper amount of at least one of Group IV elements such as tin, germanium, and lead (10 ¹⁵ atoms / cc or more, for example, 10 ¹⁸ to 10 ²⁰ atoms / cc). ) (In this state, the annealing step by the catalytic AHA treatment is performed), thereby reducing irregularities present at the crystal grain boundaries of the polycrystalline semiconductor thin film, reducing the film stress, and increasing the carrier mobility and the high carrier mobility. A polycrystalline semiconductor of high quality is easily obtained. Since these group IV elements do not generate electrons or holes in the silicon film, they do not impair TFT characteristics and do not need to be gettered. In order to form a large-grain polycrystalline silicon film by accelerating the growth of crystal nuclei, for example, 30 keV and 10 ¹⁵ atom
After injecting silicon ions into the lower crystalline silicon film at ms / cm ² (raw material is SiF ₄ ), the bias catalyst AHA
May be processed. The group IV element can be mixed as a gas component in the source gas, or can be contained in the semiconductor material thin film by ion implantation or ion doping. The concentration of oxygen, nitrogen, and carbon in the polycrystalline semiconductor film formed according to the present invention is 1 × 10 ¹⁹ atoms.
s / cc or less, preferably 5 × 10 ¹⁸ atoms / cc
The hydrogen concentration is preferably as follows, and the hydrogen concentration is preferably at least 0.01 atomic%. The sodium (Na) concentration is preferably 1 × 10 ¹⁸ atoms / cc or less in the SIMS minimum concentration region.

Before the catalytic CVD (or the bias catalytic CVD), it is preferable to heat (bake) the catalyst in a hydrogen-based gas atmosphere. This is because, when the heat treatment of the catalyst body is insufficient, the constituent material of the catalyst body is released and may be mixed into the formed film,
Such incorporation can be eliminated by baking and heating the catalyst body before film formation in a hydrogen-based gas atmosphere.
Therefore, in a state where the film-forming chamber is filled with a hydrogen-based gas, the temperature of the catalyst body is higher than that at the time of film-forming (for example, 22% for tungsten).
(200 to 2500 ° C.) after baking for a predetermined time,
Temperature during normal film formation (for example, 1700 for tungsten)
° C), and then a source gas (a so-called reaction gas) is preferably supplied using a hydrogen-based gas as a carrier gas. Note that, depending on the purity and the material of the catalyst, this baking treatment is performed only at the beginning, and does not necessarily need to be performed for each film formation.

The bias catalyst AHA treatment has a function of selectively etching an amorphous component in the polycrystalline semiconductor thin film by a high-temperature hydrogen-based active species, and has a high crystallization ratio and a large grain size (particularly, a grain size). Is several hundred nm
The above is a process for forming a thin film based on polycrystal and activating carrier impurities in the film. At this time, the catalyst temperature is 1600 to 1800 ° C., and the distance between the substrate and the catalyst is The processing time is shortened by increasing the hydrogen-based carrier gas flow rate (gas pressure) higher than that of the bias or non-bias catalytic CVD to increase the number of hydrogen-based active species and the like. To improve the effect,
It may be changed arbitrarily.

A channel, a source and a drain region, a wiring, a resistor, a capacitor, an electron emitter and the like of a MOSTFT can be formed by the polycrystalline semiconductor thin film obtained by the process of the present invention. In this case, after the formation of the channel, source and drain regions, these regions may be subjected to a bias catalyst AHA treatment if necessary.
The ion activation of the n-type or p-type impurities can be performed.

In order to reduce the intrusion of oxygen from the outside into the polycrystalline semiconductor thin film such as polycrystalline silicon, for example, a crystal is formed from the gate insulating film side to the outside in the polycrystalline silicon thin film or the like. It is preferable to increase the density by reducing the particle size, or to coat the polycrystalline silicon thin film with an amorphous silicon thin film or an amorphous silicon thin film containing microcrystalline silicon. In this case, the microcrystalline silicon or amorphous silicon thin film can be removed by general-purpose photolithography and etching techniques to form source and drain electrodes in contact with the polycrystalline silicon thin film.

The present invention relates to a silicon semiconductor device, a silicon semiconductor integrated circuit device, a silicon-germanium semiconductor device, a silicon-germanium semiconductor integrated circuit device, a compound semiconductor device, a compound semiconductor integrated circuit device, a silicon carbide semiconductor device, and a silicon carbide semiconductor integrated device. Circuit device, liquid crystal display device, organic or inorganic electroluminescence (EL) display device, field emission display (FE)
D) It is suitable for forming thin films for devices, light-emitting polymer displays, light-emitting diode displays, CCD area / linear sensor devices, MOS sensor devices, and solar cell devices.

In this case, at the time of manufacturing a semiconductor device having an internal circuit and a peripheral circuit, a solid-state image pickup device, an electro-optical device, etc., the channel, source and drain regions of the MOSTFT constituting at least a part of these devices are made of the polycrystalline semiconductor. It may be formed of a thin film, or may be a structure integrated with peripheral circuits such as a driving circuit, a video signal processing circuit, and a memory circuit.

Also, the MOS layer is formed below the organic or inorganic electroluminescent layer (EL layer) for each color.
An EL element structure having a cathode or an anode connected to the drain or the source of the TFT is preferable.

In this case, if the cathode also covers the active elements such as the MOSTFT and the diode, the light-emitting area is increased in the structure having the anode on the upper part, and the light is emitted from the active element by the light-shielding action of the cathode. To generate a leak current. Further, if the cathode or the anode is attached to the entire surface of each layer of the organic or inorganic EL layers for each color and between the layers, the organic EL which is vulnerable to moisture is covered by the entire surface by the cathode or the anode. Long life, high quality, and high reliability can be prevented by preventing layer deterioration and electrode oxidation. Also, when covered with a cathode, the heat dissipation effect increases, so the structural change of the thin film due to heat generation (melting or recrystallization) , And a long life, high quality, and high reliability can be achieved. Further, since a high-precision, high-quality, full-color organic EL layer can be formed with high productivity, the cost can be reduced.

The organic or inorganic EL for each of the colors
When a black mask layer such as chromium or chromium dioxide is formed between layers, light leakage between colors or between pixels is prevented, and contrast is improved.

When the present invention is applied to a field emission display (FED) device, its emitter (field emission cathode) is connected to the drain of the MOSTFT via the polycrystalline semiconductor thin film and N-type polycrystalline semiconductor film grown on the thin film, polycrystalline diamond film, nitrogen-containing or non-containing carbon thin film, or multiple fine protrusion structures formed on the surface of nitrogen-containing or non-containing carbon thin film (for example, carbon nanotubes) ) Or the like.

In this case, a metal shielding film having a ground potential is formed on the active element such as the MOSTFT and the diode by using the same material and the same process as the gate lead electrode of the FED device. Is formed, the gas in the airtight container is positively ionized by the electrons emitted from the emitter and charged up on the insulating layer, and this positive charge is unnecessary inversion for the active element below the insulating layer. A runaway of an emitter current caused by forming a layer or an excess current flowing through the inversion layer can be prevented. Also, when the phosphor emits light due to the collision of electrons emitted from the emitter, the light causes TF
It is also possible to prevent generation of electrons and holes in the T gate channel and generation of a leak current.

Next, the present invention will be described in more detail with reference to preferred embodiments.

First Embodiment A first embodiment of the present invention will be described with reference to FIGS.

In this embodiment, a top gate type polycrystalline silicon CMOS (Complementary MOS) T
This is applied to FT.

<Bias Catalyst CVD Method and Bias Catalyst AHA Processing and Apparatus> First, the bias catalyst CVD method and the bias catalyst AHA processing used in the present embodiment will be described. In the bias catalytic CVD method, a reactive gas composed of a hydrogen-based carrier gas and a source gas such as silane gas is brought into contact with a heated catalyst such as tungsten, and the radical deposition species or its precursor generated thereby and activated hydrogen are activated. A high directivity energy is given to hydrogen-based active species such as ions under the action of an electric field and / or a magnetic field lower than a glow discharge starting voltage, and a polycrystalline semiconductor thin film such as polycrystalline silicon is vapor-phase grown on a substrate. . Then, after this film formation, the supply of the source gas is stopped or only the hydrogen-based carrier gas is supplied to perform the bias catalyst AHA treatment on the polycrystalline semiconductor thin film or the silicon ultrafine particles on the substrate (that is, Selectively reducing etching of amorphous silicon or the like under the action of an electric field and / or a magnetic field lower than a glow discharge starting voltage by a hydrogen-based active species such as a high-temperature hydrogen-based molecule, a hydrogen-based atom, or an activated hydrogen ion; or The oxide film on the surface of silicon ultra-fine particles and the like, foreign materials such as organic dirt are removed, and carbon ultra-fine particles with a diamond structure are formed. To form a crystalline silicon thin film, or to remove oxide films on the surface of silicon ultra-fine particles and other foreign films such as organic dirt, To form particles. Repeat and these bias catalysts AHA treatment and bias catalyst CVD, to obtain a polycrystalline semiconductor thin film such as polycrystalline silicon thin film having a predetermined thickness in a more large grain size.

In the bias catalyst AHA treatment and the bias catalyst CVD, a DC voltage (a DC voltage determined by Paschen's law, for example, a voltage of 1 kV or less) is applied between the substrate and the counter electrode, which is equal to or less than a glow discharge starting voltage. The hydrogen-based active species, or the radical deposition species or its precursor and radical hydrogen ions are directed toward the substrate. Hereinafter, the AHA treatment and the CVD method according to the present embodiment will be referred to as a DC bias catalyst AHA treatment and a DC bias catalyst CVD method, but the same applies to, for example, an AC bias (RF) or an AC / DC superimposed bias (RF / DC). It is.

The bias catalyst CVD and the bias catalyst AHA process are performed using a vacuum apparatus as shown in FIGS.

According to this apparatus, a hydrogen-based carrier gas and a source gas 40 such as silicon hydride (for example, monosilane, disilane, trisilane) (and B ₂ H ₆ or PH
Also includes doping gas such as ₃ . ) Is introduced from a supply conduit 41 through a supply port (not shown) of a shower head 42 into a chamber 44 for film formation or annealing. Inside the film forming chamber 44, a susceptor 45 for supporting the substrate 1 such as glass, and a shower head 42 having good heat resistance (preferably a material having a melting point equal to or higher than that of the catalyst body 46) are provided. , For example, a coil-shaped catalyst body 46 such as tungsten, and a shutter 4 that can be opened and closed
7 are arranged. Although not shown,
A magnetic seal 52 is provided between the susceptor 45 and the film forming chamber 44, and the film forming chamber 44 is followed by a front chamber 53 for performing a pre-process, and is evacuated via a valve 55 by a turbo molecular pump or the like. .

The substrate 1 is heated by a heating means such as a heater wire in the susceptor 45, and the catalyst body 46 is, for example, a resistance wire having a melting point or lower (especially 800 to 2000 ° C., in the case of tungsten, about 1600 to 1800 ° C.). Is activated by heating. Both terminals of the catalyst body 46 are connected to a DC or AC catalyst power supply 48, and are heated to a predetermined temperature by energization from the power supply.

Then, the substrate 1 is heated by a heating means such as a heater wire 51 in the susceptor 45, and the catalyst body 46 is, for example, a resistance wire having a melting point or less (especially 800 to 2000 ° C.,
It is heated to about 1600 to 1800 ° C. in the case of tungsten to be activated. Both terminals of the catalyst body 46 are connected to a DC or AC catalyst power supply 48, and are heated to a predetermined temperature by energization from the power supply. Also, the shower head 42
Is connected to the positive electrode side of a variable DC power supply (1 kV or less, for example, 500 V) 49 via a conduit 41 as an accelerating electrode, and has a DC bias voltage of 1 kV or less between itself and the susceptor 45 on the negative electrode side (accordingly, the substrate 1). Is applied.

To implement the bias catalytic CVD method,
5, the degree of vacuum in the film forming chamber 44 was set to 1.33 × 10^-Four
~ 1.33 × 10^-6Pa, for example, hydrogen carrier gas
The catalyst is supplied at a predetermined temperature by supplying 50 to 100 SCCM.
Activated by heating to silicon hydride (e.g.
Silane) gas 1-20 SCCM (and B if necessary) _Two
H₆And PH_ThreeDoping gas. )
Source gas 40 from the supply conduit 41 to the shower head 42
Through the supply port 43 to reduce the gas pressure from 0.133 to
The pressure is set to 13.3 Pa, for example, 1.33 Pa. Where water
Elementary carrier gas is hydrogen, hydrogen + argon, hydrogen +
Lium, hydrogen + neon, hydrogen + xenon, hydrogen + kryp
Tons, etc., and a suitable amount of inert gas mixed with hydrogen.
Any method may be used (hereinafter, the same applies). In addition, raw material gas
Depending on the type or material of the catalyst body, hydrogen-based
No rear gas is needed.

Then, the shutter 47 is opened as shown in FIG. At least a part of the hydrogen-based carrier gas and the raw material gas 40 or the hydrogen-based carrier gas is catalytically decomposed in contact with the catalyst body 46, and ions or radicals of silicon or the like having high energy by a catalytic decomposition reaction or a thermal decomposition reaction. Forming a population of reactive species (ie, deposited species or precursors thereof and radical hydrogen ions), or hot hydrogen-based molecules,
A hydrogen-based active species such as a hydrogen-based atom or an activated hydrogen ion is formed, and a reaction species such as an ion or a radical thus generated is generated.
Glow discharge starting voltage (about 1 kV) or less, for example, 500
A direct current electric field is applied by a DC power supply 49 of V to give directional kinetic energy, and the directional kinetic energy is directed to the substrate 1 side. A predetermined thin film such as crystalline silicon is vapor-phase grown by DC bias catalytic CVD. Alternatively, a directional kinetic energy is given to the hydrogen-based active species, and the substrate 1 maintained at a temperature lower than the strain point of the substrate, for example, 300 to 400 ° C.
A DC bias catalyst AHA treatment is performed by acting on the above thin film.

Thus, without generating plasma,
The catalytic action of the catalyst body 46 and the directional kinetic energy obtained by applying the acceleration energy by the DC electric field to the thermal energy thereof are given to the reactive species or the hydrogen-based active species. Thermal CVD uniformly on 1
Can be deposited. Since the deposited species 56 migrates on the substrate 1 and diffuses in the thin film, it is possible to form a dense, flat and uniform thin film with good step coverage. Or,
Hydrogen-based active species generated from hydrogen-based carrier gas
It can efficiently act on the VD film with high energy.

In the present embodiment, the DC bias catalyst C
When VD is applied, compared to the control factors of conventional catalytic CVD, such as substrate temperature, catalyst body temperature, gas pressure (reaction gas flow rate), and source gas type, the thin film formation is controlled by an independent DC electric field. It is a feature to add what you do. For this reason, including the adhesion of the generated film to the substrate, the density of the generated film, the uniformity or smoothness of the generated film, the incorporation into via holes and the like and the step coverage are improved, the substrate temperature is further lowered, and the Stress control and the like can be performed, and a high-quality film (for example, a silicon film or a metal film having physical properties close to bulk) can be obtained. Moreover,
Since the reactive species generated by the catalyst body 46 can be independently controlled by a DC electric field and efficiently deposited on the substrate, the utilization efficiency of the reactive gas is high, the generation speed is increased, the cost is improved by improving the productivity and reducing the reactive gas. Can be down. In addition, not only a DC voltage but also an electric field bias catalyst CV such as an AC voltage.
D, and the same effect as described above can be obtained in bias catalyst CVD using a magnetic field or bias catalyst CVD using an electric field and a magnetic field.

Also, in the DC bias catalyst AHA treatment, the annealing can be controlled by an arbitrary independent DC electric field similarly to the above. This is possible while improving the processing speed and reducing the cost. In addition, not only the DC voltage but also the bias catalyst AH of the electric field such as the AC voltage.
In the A treatment, and also in the bias catalyst AHA treatment using a magnetic field or the bias catalyst AHA treatment using an electric field and a magnetic field,
The same effects as above can be obtained.

Further, even if the substrate temperature is lowered, the energy of the deposited species is large, so that a desired high-quality film can be obtained.
A large and inexpensive insulating substrate (a glass substrate such as borosilicate glass or aluminosilicate glass, a heat-resistant resin substrate such as polyimide, etc.) can be used, and the cost can be reduced in this regard. In addition, since the shower head 42 for gas supply can be used as an electrode for directional acceleration of the above-described reactive species and hydrogen-based active species, the structure is simplified.

Also, needless to say, since no plasma is generated, there is no damage due to the plasma and a low-stress generated film can be obtained, and a much simpler and less expensive device can be realized as compared with the plasma CVD method. I do.

In this case, under reduced pressure (for example, 0.133
The operation can be performed at 1.33 Pa) or at normal pressure, but the normal pressure type realizes a simpler and less expensive device than the reduced pressure type. And even the normal pressure type, the conventional normal pressure CVD
A high quality film having better density, uniformity and adhesion can be obtained. Also in this case, the normal pressure type has higher throughput, higher productivity, and cost reduction than the pressure reduction type.

In the case of the decompression type, the DC voltage depends on the gas pressure (gas flow rate), the type of gas, and the like. In the case of normal pressure type, discharge is not performed, but exhaust gas should be adjusted so that exhaust gas flow does not come in contact with the substrate so that the flow of source gas and reactive species or active species does not adversely affect the film thickness and film quality. Is desirable.

The above-described biased or non-biased catalytic CVD
Alternatively, in the bias catalyst AHA treatment, the substrate temperature rises due to the sub-radiation generated by the catalyst body 46. However, as described above, the substrate heating heater 51 may be provided as necessary. Further, the catalyst body 46 has a coil shape (a mesh, a wire, a perforated plate may be used in addition to the above shape). Is good. In this CVD, since the substrate 1 is disposed above the shower head 42 on the lower surface of the susceptor 45, particles generated in the film forming chamber 44 may fall and adhere to the substrate 1 or a film thereon. There is no.

<Bias Catalyst AHA Treatment and Apparatus> In the present embodiment, the above apparatus is used as it is, and after the vapor phase growth by bias catalyst CVD, the supply of the source gas is stopped, and the bias catalyst CVD is started. Supply only a hydrogen-based carrier gas into the film forming chamber 44 at a large flow rate,
Alternatively, with a similar hydrogen-based carrier gas, a bias catalyst AHA treatment is performed on the semiconductor material thin film or fine particles,
By the selective reduction of a large amount of high-temperature hydrogen-based active species,
Etching of amorphous silicon, annealing for more polycrystallization, or cleaning of an organic substance, etc., and bias catalyst CVD and bias catalyst AHA treatment are repeated on the semiconductor material thin film a predetermined number of times to obtain a target film. A polycrystalline semiconductor thin film such as a thick polycrystalline silicon thin film is formed.

In the bias catalyst AHA treatment, the directional kinetic energy is applied to a large amount of high-temperature hydrogen-based active species generated by catalytic decomposition of the hydrogen-based carrier gas by the heating catalyst body by the action of an electric field and / or a magnetic field. To remove organic substances and oxides on the surface of silicon or carbon ultrafine particles, to facilitate polycrystallization using a semiconductor material thin film as a seed, to provide a high crystallization rate and a large grain size (particularly, a grain size of several hundred nm or more). A polycrystalline-based thin film can be formed, and a semiconductor material thin film can be formed by etching its amorphous component and forming a polycrystalline semiconductor thin film thereon in a state where it can be more easily crystallized. In addition, this is a process for activating carrier impurities in the film. At this time, the catalyst temperature was set to 1600 to 1800 ° C., the distance between the substrate and the catalyst was set to 20 to 50 mm, the substrate temperature was set to 300 to 400 ° C., and the hydrogen-based carrier gas was hydrogen or hydrogen and an inert gas (argon) as described above. , Helium, xenon, krypton, radon, etc.), and in the case of a mixed gas, the oxidative deterioration of the catalyst can be prevented by setting the hydrogen content to 50 mol% or more. Also, the bias catalyst AHA
The hydrogen or the hydrogen-containing gas used in the treatment may be the same as the hydrogen-based carrier gas during the vapor phase growth of the bias or non-bias catalytic CVD, but the gas flow rate is 300 to 1000 S
It is preferable to increase the CCM and gas pressure to 10 to 50 Pa (0.1 to several Pa in the case of bias or non-bias catalytic CVD) to increase heat conduction by gas and increase the generation amount of hydrogen-based active species. .

According to the present invention, according to the crystallization treatment of a semiconductor thin film under the action of a bias, an electric field and / or a magnetic field is applied, and annealing (hydrogen-based active species) is performed under this action. In order to carry out catalytic AHA treatment) or vapor phase growth of deposited species (bias catalytic CVD), the crystal orientation of the crystal grains can be made uniform, so that the electron potential barrier of the grain boundary is lowered and the carrier mobility is increased. . Further, since the surface of the polycrystalline silicon thin film has no irregularities and is flattened, the state of the interface with the gate insulating film formed in contact with the thin film is improved, and the carrier mobility can be improved. The following summarizes the above-mentioned DC bias catalyst AHA treatment and DC bias catalyst CVD including the above.

First, FIG. 8 shows a case where catalytic CVD, so-called bias catalytic CVD, is performed under the action of the above-mentioned electric field. ) Are applied, and an electric field is applied by the electrodes.

At this time, in the case of the bias catalytic CVD, the electron spin of the silicon atom of the deposited species generated by the catalytic reaction or catalytic decomposition reaction of the catalyst body 46 interacts with the electric field and turns in a certain direction. When depositing on a substrate,
Crystallization is performed in a certain direction, and the crystal orientation of silicon becomes uniform. Since the crystallized thin film has almost the same crystal orientation, the electron potential barrier of the grain boundary is lowered and the carrier mobility is increased. At this time, it is important to align the crystal orientation in a certain direction. Depending on the structure of the outer shell orbit of the silicon atom, the crystal may be aligned in the vertical direction of the obtained polycrystalline silicon thin film 7 or in the horizontal direction. In some cases, the crystal orientation may be uniform. By aligning the crystal grains in a certain direction, the surface of the polycrystalline silicon thin film has no irregularities, and the surface of the thin film is flattened. The interface state becomes good, and the carrier mobility improves.

FIG. 9 shows a case in which a magnetic field is applied instead of an electric field. Permanent magnets 202 and 203 or an electromagnet 204 are provided around a vacuum vessel 44 containing the substrate 1, and a magnetic field is applied by this.

Thus, as in the case of the electric field described above,
Crystal grains are aligned in a certain direction by the action of a magnetic field, carrier mobility is improved, and surface irregularities are reduced.

FIG. 10 shows an example in which a magnetic field is simultaneously applied together with the above-described electric field. An electrode 200 for applying a high frequency voltage (or a DC voltage, or both) 49;
The electric field by 201 is simultaneously applied.

At this time, the electron spin of the silicon atom is oriented in a certain direction due to the interaction of the magnetic field and the electric field. It will be. Therefore, the crystal grains are more easily aligned in a certain direction, the carrier mobility is further improved, and the unevenness on the surface is further reduced.

The bias method shown in FIGS. 8 to 10 is similarly applied to the bias catalyst AHA treatment, and the hydrogen-based active species can be efficiently applied to the fine particles and the silicon thin film by the action of an electric field and / or a magnetic field. Acting with sufficient energy, the AHA treatment effect is improved, and the amorphous component can be sufficiently etched to promote the formation of a polycrystalline silicon film.

FIG. 11 shows the introduction times and timings of the hydrogen-based carrier gas and the source gas in the above-mentioned bias catalyst CVD and bias catalyst AHA processing in the case of forming a polycrystalline silicon thin film, and FIG. 1 shows a gas introduction system incorporating a (MFC), a regulating valve, and the like.

First, before forming a film, the substrate 1 is carried into a chamber (film forming chamber) 44 through a gate valve and placed on a susceptor 45, and then the inside of the chamber 44 is operated by operating an exhaust system. Exhaust to the pressure and
The substrate 1 is heated to a predetermined temperature by operating a heater incorporated in the substrate 5.

Then, depending on the gas introduction system, first, a hydrogen-based carrier gas of 300 to 1000 SCCM, for example, 500
The SCCM is introduced into the chamber 1. Part of the introduced hydrogen gas becomes a hydrogen-based active species such as activated hydrogen ions by a catalytic decomposition reaction by the heating catalyst 46, reaches the substrate surface, and cleans the surface of the substrate 1. Thereafter, the hydrogen-based carrier gas is set to 150 SCCM.

As described above, while the hydrogen-based carrier gas is being supplied into the chamber 44, the gas introduction system is operated to introduce the source gas (methane or monosilane 15 SCCM) into the chamber 44. The introduced source gas etc.
Deposited species are generated by a thermal catalytic reaction and a thermal decomposition reaction of the heating catalyst body 46, and are vapor-phase grown on the substrate surface as a polycrystalline silicon thin film or the like.

Thereafter, the introduction of the source gas is stopped, the source gas is discharged from the chamber 44, and only the hydrogen-based carrier gas is supplied at 300 to 1000 SCCM, for example, 500 S.
Introduced at a flow rate of CCM, whereby hydrogen-based active species such as activated hydrogen ions generated by the catalytic decomposition reaction by the heated catalyst act on the polycrystalline silicon thin film and the like to etch the amorphous component thereof, A polycrystalline silicon grain from which an amorphous component has been removed can be formed, and a polycrystalline silicon thin film having a high crystallization rate and a large grain size, in which crystallization is promoted, can be obtained by using the grain as a seed.

The thus-obtained polycrystalline silicon thin film is further subjected to a bias catalyst AHA treatment, and the above-mentioned bias catalyst CVD is again performed thereon. Using the polycrystalline silicon thin film as a seed, a polycrystalline silicon thin film is formed thereon. Grow,
Further, by repeatedly performing the bias catalyst AHA treatment and the bias catalyst CVD, the thickness of the polycrystalline silicon thin film is controlled, and the polycrystallinity having a high crystallization rate and a large grain size is finally obtained at a target thickness. A silicon thin film can be formed.

As described above, due to the radical action of the hydrogen-based active species of sufficient energy accelerated by the bias electric field and / or magnetic field, thermal energy moves to the film to locally increase the temperature, and the semiconductor thin film becomes thin. The amorphous component is etched to promote crystallization, and a polycrystalline film having a large grain size can be obtained. As a result, a high-carrier mobility, high-quality polycrystalline semiconductor thin film can be obtained. Alternatively, when silicon oxide is present in the film, a reduction reaction occurs with the silicon oxide to generate SiO and the like, and the silicon oxide is reduced / removed on the thin film or in the film. A high-quality polycrystalline silicon thin film having high mobility can be obtained.

The amorphous silicon-containing amorphous silicon or the amorphous silicon-containing microcrystalline silicon thin film is crystallized by using the underlying ultrafine particles as seeds. A polycrystalline silicon film is formed. Moreover, since the amorphous silicon contained in the film is etched by the action of the hydrogen-based active species, a polycrystalline silicon thin film having a high crystallization rate and a large grain size is formed.

At the time of this bias catalyst AHA treatment, carrier impurities present in the semiconductor thin film are activated at a high temperature, so that an optimum carrier impurity concentration can be obtained in each region, and a large amount of high-temperature hydrogen-based active species can be obtained. (Hydrogen molecules, hydrogen atoms and activated hydrogen ions) can be cleaned (reduction and removal of adsorbed gas and organic residue etc. on the substrate etc.), and the catalyst body becomes difficult to be oxidized and deteriorated,
Further, by hydrogenation, for example, silicon dangling bonds in the semiconductor film are eliminated, and characteristics are improved.

Annealing by such bias catalyst AHA treatment and bias or non-bias catalyst CV of the semiconductor thin film
This semiconductor thin film is already formed by bias catalyst AH
It is easy to grow on the base film polycrystallized by the A treatment in a state easily polycrystallized, and it is possible to obtain a target high crystallization rate and high quality polycrystalline semiconductor thin film with a predetermined thickness. .
That is, by multi bias catalyst AHA processing in which bias catalyst CVD and bias catalyst AHA processing are repeated, for example, microcrystalline silicon-containing amorphous silicon or amorphous silicon and microcrystalline silicon-containing polycrystalline silicon thin film formed by bias or non-bias catalytic CVD Into a polycrystalline silicon thin film by bias catalyst AHA treatment,
The polycrystalline silicon thin film has a high crystallinity, and the polycrystalline silicon thin film is used as a seed for bias catalytic CVD to grow a polycrystalline silicon thin film in vapor phase.
Since the HA treatment is repeated, a polycrystalline silicon thin film having a high crystallization rate and a large grain size can be formed.

Since both the above-described bias catalyst CVD and bias catalyst AHA treatment can be performed without generating plasma, there is no damage due to plasma, and a low-stress formed film can be obtained. And an inexpensive device can be realized.

FIG. 13 shows the Raman spectrum of the polycrystalline silicon thin film obtained by the above-described multi-bias catalyst AHA treatment (repetition of the bias catalyst CVD and the bias catalyst AHA treatment) according to the present embodiment according to the number of repetitions and the like. It is shown. According to this result, catalytic CVD
Gas flow rate during silicon deposition (depo) by Si
H ₄ : H ₂ = 5: 500 SCCM, catalyst temperature = 1800
2000 ° C., substrate temperature = 400 ° C., bias catalyst A
When the conditions of the HA treatment were various and the number of repetitions was changed, when the number of repetitions was increased, the treatment time was increased, and the hydrogen flow rate during the treatment was increased, the sample # 1 →
It is clear that in the order of # 2 → # 3 → # 4, amorphous (amorphous) silicon and microcrystalline silicon decrease and polycrystalline silicon increases (that is, the grain size increases and the crystallinity increases). is there. Here, AHA1 may be a cleaning process of silicon and / or carbon fine particles on the substrate surface before film formation, and the original bias catalyst AHA process is AHA.
2-4.

FIG. 14 shows the crystallization ratio of each sample in comparison with the presence or absence of polycrystal in the polycrystalline silicon thin film. According to this, it is understood that the crystallization ratio increases in the order of samples # 1 → # 2 → # 3 → # 4, and that the ratio including microcrystals (Im) increases.

These results show that the treatment according to the present invention is a very excellent method for forming a polycrystalline semiconductor thin film having a high crystallization rate and a large grain size.

In the present embodiment, in the above-mentioned bias catalytic CVD, for example, a 0.4 mmφ tungsten wire catalyst and a 0.8 mm tungsten wire supporting the same are supported.
Although the purity of the support (not shown) of the mmφ molybdenum wire is a problem, the conventional purity: 3N (99.9 wt%)
Is 4N (99.99 wt%) or more, preferably 5N (9
It has been demonstrated that increasing the purity to 9.999 wt%) or more can reduce heavy metal contamination such as iron, nickel, and chromium in a polycrystalline silicon thin film by bias catalytic CVD. FIG. 15 (A) shows the concentration of heavy metals such as iron, nickel and chromium in the film at a purity of 3N. By increasing this to 5N, heavy metals such as iron, nickel and chromium as shown in FIG. It has been found that the concentration can be significantly reduced. Thereby, the TFT characteristics can be improved.

<Manufacture of Top Gate Type CMOS TFT>
Next, the top gate type CMOSTF according to the present embodiment
The production example of T is shown.

First, a bias or non-bias catalyst C is placed on an insulating substrate 1 such as quartz glass, crystallized glass, borosilicate glass, or
VD or the like, silicon nitride film 100 to 200 nm thick,
A silicon oxide film having a thickness of 100 to 200 nm is formed as a base protective film, and a depth (step) of 50 to 2 is formed at least in a TFT formation region by general-purpose photolithography and etching technology.
A recess 190 having a size of 00 nm and a length of 10 μm × a width of 30 μm is formed. At this time, it is preferable to leave at least a silicon nitride film on the bottom surface of the concave portion in order to prevent intrusion of impurities (such as Na ⁺ ) from the glass substrate. At this time, plasma etching of CF ₄ gas or RIE (Reactive Ion Etching)
Wet etching with a hydrofluoric acid-based etchant may be performed.

When a heat-resistant resin substrate is used as the substrate 1, at least TF
In order to form a concave portion having a step of a predetermined shape and size in the T forming region, for example, a polyimide substrate having a thickness of 100 μm is formed by:
For example, a height of 50 to 200 nm, a length of 10 μm × a width of 30 μm
Is stamped to form a recess having a step having the same shape and dimensions as the mold. Alternatively, a heat-resistant resin film of polyimide or the like having a thickness of 5 to 10 μm is formed on a metal plate such as stainless steel as a reinforcing material by coating, screen printing, or the like, and the film is, for example, 50 to 200 nm in height, 10 μm in length × horizontal. A mold having a predetermined shape and dimensions of 30 μm is stamped to at least TF
A concave portion having a step having the same shape and dimensions as the mold may be formed in the T forming region. Alternatively, at least a depth of 1 to 2 μm and a length of 10
A step having a predetermined shape and dimensions of 30 μm × width of 30 μm may be formed by etching, and a heat-resistant resin film such as polyimide may be coated to form a recess having a predetermined shape and dimensions.

In this case, the glass material of the substrate 1 is properly used depending on the process temperature for forming the TFT. In the case of a low temperature of 200 to 500 ° C .: a glass substrate (500 × 600 × 0.5) of borosilicate, aluminosilicate glass or the like
〜1.1 μm thick), and a heat-resistant resin substrate may be used. In the case of a high temperature of 600 to 1000 ° C: a heat-resistant glass substrate (6 to 12 inches φ, 70
0-800 μm thick).

Next, as shown in FIG. 1B, silicon powder, carbon powder, or ultrafine particles 100A in which both are mixed are adhered and dispersed in the concave portion 190. For example, by polishing with silicon powder or carbon powder or a paste containing silicon powder and carbon powder, ultrafine particles of silicon powder or carbon powder or silicon powder and carbon powder may be adhered and dispersed in the concave portions. Alternatively, silicon powder or carbon powder or a powder mixed with them is dispersed in an organic solvent (acetone, ethyl alcohol, ethyl alcohol / acetone, etc.), and the silicon powder or carbon powder is placed in the recess by controlling the power and time of the ultrasonic cleaner. Alternatively, ultrafine particles in which these are mixed may be adhered and dispersed. It is desirable that these powders 100A have a size smaller than the concave portion 190, for example, 50 to 200 nm.

Next, as shown in (3) of FIG. 1, the action of the hydrogen-based active species in the bias catalyst AHA treatment causes
Silicon powder and / or carbon powder 100A
Is cleaned to remove an extraneous film such as an oxide film and organic dirt, thereby obtaining a cleaned ultrafine carbon particle 100B having a silicon or diamond structure. This bias catalyst AHA treatment may be performed as an integral part of a continuous operation before film formation by the next bias catalyst CVD or high-density bias catalyst CVD.

This bias catalyst AHA treatment is a treatment in which a source gas is not supplied in the bias catalyst CVD method. Specifically, a hydrogen-based carrier gas is supplied under reduced pressure to bring the catalyst into a predetermined temperature ( About 1600 to 1800
° C, for example, set at about 1700 ° C), for example, 300
1 to 1000 SCCM of hydrogen-based carrier gas
At a gas pressure of 0 to 50 Pa, a large amount of high-temperature hydrogen-based active species (eg, activated hydrogen ions) are generated and sprayed onto the ultrafine particles 100A. As a result, a large amount of high-temperature hydrogen-based active species (eg, activated hydrogen ions) move under the action of directional kinetic energy due to a bias electric field and / or a magnetic field, thereby locally increasing the temperature and causing the hydrogen-based active species and the like to move. The organic substance on the surface of the ultrafine particles is cleaned by etching by the action of, and the silicon ultrafine particles or carbon ultrafine particles (diamond structure) 100B are formed by selective etching of the amorphous component, which is used as a nucleus for polycrystalline silicon growth. .

[0122] Then, as shown in (4) in FIG. 1, the bias catalytic CVD continuously (or multi-bias catalyst AHA treatment), for example, periodic table group IV element, such as tin and 10 ¹⁸ ~10 ²⁰ atoms / The polycrystalline silicon thin film 7 doped with cc (this may be doped by ion implantation at the time of CVD or after film formation) is coated with the ultrafine particles 100.
B is vapor-grown to a thickness of 50 to 100 nm, for example, 50 nm as a seed. However, this tin doping is not always necessary (the same applies hereinafter). This bias catalytic CVD
When carrying out, in order to prevent the catalyst from being oxidized and degraded, a hydrogen-based carrier gas is supplied to bring the catalyst into a predetermined temperature (about 1600 to 1
It is necessary to heat to 800 ° C., for example, 1700 ° C.), cool the catalyst body after the film formation to a temperature at which there is no problem, and cut off the hydrogen-based carrier gas.

At this time, if necessary, n is added to the monosilane.
-Type impurities (phosphorus, arsenic, antimony) or p-type impurities (boron, etc.) are added in an appropriate amount, for example, 10 ¹⁵ to 10 ¹⁸ atoms.
/ Cc to form an n-type or p-type polycrystalline silicon thin film. After growing a microcrystalline silicon or polycrystalline silicon thin film to a thickness of 10 to 30 nm on the ultrafine particles 100B by bias catalytic CVD,
A bias catalyst AHA treatment is performed, and a polycrystalline silicon thin film is grown thereon by bias catalyst CVD to a thickness of 10 to 30 nm. Grown to a thickness of ３０30 nm, and a bias catalyst AHA
May be processed. By this method, a thicker polycrystalline silicon thin film having a larger grain size can be formed.

In this case, for example, a tin-doped polycrystalline silicon thin film is vapor-phase-grown by the above-described bias catalyst CVD under the following conditions using the apparatus shown in FIGS. Performs catalytic AHA treatment and anneals to make the polycrystalline silicon thin film more polycrystalline,
The bias catalyst CVD and the bias catalyst AHA treatment may be repeated to form a 50 nm-thick polycrystalline silicon thin film 7. For example, 10 to 3 by bias catalyst CVD
After growing a film having a thickness of 0 nm, performing a bias catalyst AHA treatment, growing a film having a thickness of 10 to 30 nm by bias catalyst CVD, and further performing a bias catalyst AHA treatment, growing a film having a thickness of 10 to 30 nm by bias catalyst CVD. Finally, a polycrystalline silicon thin film having a desired film thickness is obtained.

Film formation of tin-containing polycrystalline silicon by bias catalyst CVD: hydrogen (H ₂ ) as carrier gas, monosilane (SiH ₄ ) as raw material gas, tin hydride (SnH ₄ )
Are formed by mixing in appropriate ratios. H ₂ flow rate: 50~150S
CCM, SiH ₄ flow rate: 1~20SCCM, SnH ₄ flow rate: 1~20SCCM. At least a part of these source gases are catalytically decomposed by contact with the catalyst body, and a group of reactive species such as ions or radicals such as silicon having high energy (ie, deposited) by a catalytic decomposition reaction or a thermal decomposition reaction. Species or its precursor and radical hydrogen ion) to form
A directional kinetic energy is applied to the reaction species such as ions and radicals thus generated by applying a DC electric field and / or a magnetic field by a DC power supply of a glow discharge starting voltage (about 1 kV) or less, for example, 500 V, and directing them toward the substrate. Then, a predetermined thin film of lower crystalline silicon or the like is vapor-phase grown on the substrate 1 maintained at a temperature lower than the strain point of the substrate, for example, 300 to 400 ° C. by DC bias catalytic CVD. At this time, by mixing an appropriate amount of n-type phosphorus, arsenic, antimony, or the like, or a suitable amount of p-type boron, etc., into a silane-based gas (silane, disilane, trisilane, or the like) as a raw material gas, Alternatively, a tin-containing polycrystalline silicon thin film having a p-type impurity carrier concentration may be formed. In the case of n-type conversion: phosphine (PH ₃ ), arsine (As)
H _3), stibine (SbH ₃₎ for p-type: diborane (B ₂ H ₆₎

Bias catalyst AHA treatment: bias catalyst A
The HA treatment is a method in which a raw material gas is not supplied in the bias catalytic CVD. Specifically, a hydrogen-based carrier gas is supplied under a reduced pressure at a gas flow rate of 300 to 1000 SCCM and a gas pressure of 10 to 50 Pa to set a predetermined catalyst body. Temperature (about 16
(To about 1700 ° C., for example, about 1700 ° C.) to generate a large amount of high-temperature hydrogen-based active species, which are formed on a substrate under the action of an electric field and / or a magnetic field that is lower than the glow discharge starting voltage. Spray on crystalline silicon thin film.
As a result, thermal energy of a large amount of high-temperature hydrogen-based active species is transferred to those films, raising the temperature of those films. When amorphous silicon or microcrystalline silicon is contained, the reduction action of hydrogen-based active species causes The amorphous components are selectively etched and these become polycrystalline,
The polycrystalline silicon thin film is highly crystallized to form a tin-containing polycrystalline silicon film having a large grain size. Irregularity and stress existing at the crystal grain boundaries are reduced by the effect of a group IV element such as tin, and high carrier mobility is achieved. A high quality and high quality tin-containing polycrystalline silicon thin film can be formed.

The above-mentioned hydrogen-based active species, when silicon oxide exists on or in a thin film of polycrystalline silicon or the like, undergoes a reduction reaction with the silicon oxide to produce SiO or the like and is evaporated and removed. Silicon oxide on or in those films can be reduced / removed, and high carrier mobility and high quality polycrystalline silicon thin films can be formed. This bias catalyst AHA treatment is performed by a gate channel / source /
When performed after the formation of the drain, a large amount of thermal energy of the high-temperature hydrogen-based active species moves to the films, increases the temperature of the films, and is injected into the gate channel / source / drain simultaneously with the promotion of crystallization, Carrier impurities (phosphorus, arsenic, boron, etc.) are ion-activated.

The bias electric field at the time of the bias catalyst AHA treatment (or the bias catalyst CVD) can be formed by applying any one of the following voltages. 1) DC voltage (for example, 500 V) 2) Low frequency voltage (for example, 500 V _PP / 26 kHz) 3) High frequency voltage (for example, 500 V _PP /13.56 MH)
z) 4) A voltage obtained by superimposing a high-frequency voltage on a low-frequency voltage (for example, 500 V _PP / 26 kHz + 200 V _PP /13.56 M)
5) A voltage obtained by superimposing a low-frequency voltage on a DC voltage (for example, 5
00V + 200V _PP / 26kHz) 6) A voltage obtained by superimposing a high-frequency voltage on a DC voltage (for example, 5
00V + 200V _PP /13.56 MHz) 7) A voltage obtained by superposing a low frequency voltage and a high frequency voltage on a DC voltage (for example, 500V + 100V _PP / 26kHz + 10)
0V _PP /13.56MHz)

An example in which a silicon nitride film, a silicon oxide film, and a tin-containing polycrystalline silicon thin film are continuously formed by electric field bias catalytic CVD will be described. First, when each of the above films is formed in the same chamber, a hydrogen-based carrier gas is constantly supplied, the catalyst is heated to a predetermined temperature, a predetermined electric field is applied, and a standby is performed. May be processed as follows.

Ammonia is mixed with monosilane at an appropriate ratio to form a silicon nitride film having a predetermined thickness. After the previous source gas is sufficiently exhausted, monosilane and He-diluted O ₂ are continuously mixed at an appropriate ratio. After a silicon oxide film having a predetermined thickness is formed by exhausting the previous source gas and the like, monosilane and SnH ₄ are mixed at an appropriate ratio to form a bias catalyst CV.
By D, a tin-containing polycrystalline silicon thin film having a predetermined thickness is formed. After the film formation, the raw material gas is cut, and the catalyst body is cooled to a temperature at which there is no problem, and the hydrogen-based carrier gas is cut. Note that the source gas at the time of forming the insulating film may be reduced or increased in inclination to form an inclined junction insulating film.

Alternatively, in the case of forming the chambers in independent chambers, a hydrogen-based carrier gas is constantly supplied into each chamber, the catalyst is heated to a predetermined temperature, and a predetermined electric field is applied to stand by. The following processing may be performed. The mixture is transferred to the chamber A, and ammonia is mixed with monosilane at an appropriate ratio to form a silicon nitride film having a predetermined thickness.
Next, the chamber is moved to the B chamber, and He-diluted O ₂ is mixed with monosilane at an appropriate ratio to form a silicon oxide film. Next, the substrate is moved to the C chamber, and monosilane and SnH ₄ are mixed at an appropriate ratio to form a polycrystalline silicon thin film containing tin. Then, the silicon oxide film is transferred to the chamber B if necessary, and He diluted O ₂ is mixed with monosilane at an appropriate ratio to form a silicon oxide film.
After the film formation, the raw material gas is cut, and the catalyst body is cooled to a temperature at which there is no problem, and the hydrogen-based carrier gas is cut. At this time, the hydrogen-based carrier gas and the respective source gases may be constantly supplied into the respective chambers so as to be in a standby state.

Here, the film forming conditions for each film are as follows (however,
The conditions for forming the polycrystalline silicon thin film were omitted because they were described above), and a hydrogen-based carrier gas (hydrogen, argon + hydrogen, helium + hydrogen, neon + hydrogen, etc.) was constantly flowed into the chamber, and the flow rate, pressure, and susceptor temperature were adjusted. It is controlled to the following predetermined value. Chamber pressure: about 1 to 15 Pa, for example, 10 Pa Susceptor temperature: 300 to 400 ° C. Hydrogen carrier gas flow rate (in the case of mixed gas, hydrogen is 70
-80 mol% or more): 50-150 SCCM

Further, the silicon nitride film has a thickness of 50
It is formed to a thickness of 200 nm. Hydrogen (H ₂ ) is used as a carrier gas, and monosilane (SiH ₄ ) is mixed with ammonia (NH ₃ ) at an appropriate ratio as a source gas. Hydrogen (H ₂ ) flow rate: 50 to 150 SCCM, SiH ₄ flow rate: 1 to 20 SCCM, NH ₃ flow rate: 5 to 60
SCCM

The silicon oxide film has a thickness of 10 under the following conditions.
It is formed to a thickness of 0 to 200 nm. Hydrogen (H ₂ ) is used as a carrier gas and a raw material gas, and monosilane (SiH ₄ ) is converted to H.
e Formed by mixing diluted O ₂ in appropriate ratio. Hydrogen (H ₂ ) flow rate: 50 to 150 SCCM, SiH ₄ flow rate: 1 to ₂₀ SCCM, He diluted O ₂ flow rate: 1
~ 2 SCCM

As described above, after growing the polycrystalline silicon thin film 7 in the concave portion 190 using the ultrafine particles 100B as a seed, the substrate surface is optically polished to remove the polycrystalline silicon thin film in the region other than the concave portion. It may be removed. As a result, a substrate having a flat surface in which the tin-containing or non-tin-containing large grain polycrystalline silicon thin film is embedded in the concave portion is formed. However, at this time, an oxide film and an organic dirt film are formed on the surface of the optically polished tin-containing or non-containing large-diameter polycrystalline silicon thin film. It is good to carry out the processing of.

Then, a MOSTFT using the polycrystalline silicon thin film 7 as a source, channel and drain region
Is made.

That is, as shown in (5) of FIG. 2, after the polycrystalline silicon thin film 7 is formed into islands by general-purpose photolithography and etching, the threshold (V _th) by controlling the impurity concentration of the channel region for the nMOS TFT is obtained. )
In order to optimize the above, the pMOSTFT portion is masked with a photoresist 9 and a p-type impurity ion (for example, boron ion) 10 is doped by ion implantation or ion doping at a dose of, for example, 5 × 10 ¹¹ atoms / cm ² . The acceptor concentration is set to 1 × 10 ¹⁷ atoms / cc, and the polycrystalline silicon thin film 7 is made to be a p-type polycrystalline silicon thin film 11.

Next, as shown in FIG.
By controlling the impurity concentration of the channel region for the OSTFT
V_thIn order to optimize the
Mask with photoresist 12 and perform ion implantation or ion doping.
N-type impurity ions (eg, phosphorus ions) 13
For example 1 × 10¹²atoms / cm^TwoOf dose
2 × 10¹⁷Donors concentration of atoms / cc
And the conductivity type of the polycrystalline silicon thin film 7 is changed to n-type.
The polycrystalline silicon thin film 14 is obtained. In addition, polycrystalline silicon
If there is a silicon oxide film on the thin film 7, remove it.
And the threshold (V _th) Optimization of ion implantation or ion
It may be doped.

Next, as shown in FIG. 3 (7), if necessary, the above-mentioned bias catalyst AHA treatment is performed to promote crystallization and activate the impurities in the film, and then the gate is formed by bias catalyst CVD or the like. Insulating silicon oxide film 50nm
After forming the thickness 8, a phosphorus-doped polycrystalline silicon film 15 as a gate electrode material is formed, for example, by a PSC of 2 to 20 SCCM.
It is deposited to a thickness of, for example, 400 nm by the same catalytic CVD method as described above, while supplying monosilane of H ₃ and 20 SCCM.

Next, as shown in FIG. 3 (8), a photoresist 16 is formed in a predetermined pattern, and using this as a mask, the phosphorus-doped polycrystalline silicon film 15 is patterned into a gate electrode shape. After removing the photoresist 16, as shown in FIG. 3 (9), a silicon oxide film 17 as a gate electrode protective film is formed to a thickness of 20 to 30 nm by, for example, catalytic CVD or the like.

Next, as shown in FIG.
The MOSTFT portion is masked with a photoresist 18 and, for example, phosphorus ions 19 which are n-type impurities are ion-implanted or ion-doped, for example, at 1 × 10 ¹⁵ atoms / cm.
Doping with a dose of ² and 2 × 10 ²⁰ atoms /
By setting the donor concentration to cc, the n ⁺ -type source region 20 and the drain region 21 of the nMOS TFT are formed.

Next, as shown in (11) of FIG.
The MOSTFT portion is masked with a photoresist 22, and for example, boron ions 23, which are p-type impurities, are ion-implanted or ion-doped, for example, at 1 × 10 ¹⁵ atoms / cm 2.
doping with a dose of cm ² , 2 × 10 ²⁰ atoms
An acceptor concentration of s / cc is set, and a p ⁺ type source region 24 and a drain region 25 of the pMOSTFT are formed.

The gate, the source and the drain are formed in this manner, and these can be formed by a method other than the above-described process.

That is, after the step (4) in FIG. 1, the polycrystalline silicon thin film 7 is formed into islands in the pMOSTFT and nMOSTFT regions, and n-type impurities, for example, phosphorus ions are implanted into the pMOSTFT region by ion implantation or ion doping.
Doping is performed at a dose of × 10 ¹² atoms / cm ² , a donor concentration of 2 × 10 ¹⁷ atoms / cc is set, and a p-type impurity, for example, boron ion is dosed at a dose of 5 × 10 ¹¹ atoms / cm ² in the nMOSTFT region. To set the acceptor concentration to 1 × 10 ¹⁷ atoms / cc, and to control the impurity concentration of each channel region,
V _th is optimized.

Then, each source / drain region is formed by a general-purpose photolithography technique using a photoresist mask. In the case of an nMOS TFT, an n-type impurity such as arsenic
Phosphorus ions are doped at a dose of 1 × 10 ¹⁵ atoms / cm ² and a donor concentration of 2 × 10 ²⁰ atoms / cc is set. In the case of a pMOS TFT, a p-type impurity such as boron At a dose of 1 × 10 ¹⁵ atoms / cm ² and an acceptor concentration of 2 × 10 ²⁰ atoms / cc.

After that, if necessary, a bias catalyst AHA treatment is performed to activate impurities in the film, and then a silicon oxide film is formed as a gate insulating film. Then, a silicon oxide film is formed. That is, if necessary, the silicon oxide film 8 is formed to a thickness of 20 to 30 nm by mixing the hydrogen-based carrier gas and monosilane with He diluted O ₂ at an appropriate ratio by the bias catalyst CVD method continuously after the bias catalyst AHA treatment. Then, if necessary, a hydrogen-based carrier gas and monosilane are mixed with NH ₃ at an appropriate ratio to form a silicon nitride film having a thickness of 10 to 20 nm.
m thickness. Thereafter, a gate electrode is formed by the same bias catalytic CVD method and photolithography technique as described above.

After the gate, source and drain are formed, as shown in FIG. 4 (12), the hydrogen-based carrier gas 1 is formed on the entire surface by the same bias catalytic CVD method as described above.
Using 50 SCCM in common, O ₂ of helium gas dilution of 1 to ₂ SCCM, the silicon oxide film 26 is, for example, 100 to 200 nm thick under supply of monosilane of 15 to 20 SCCM, PH ₃ of 1 to 20 SCCM, and helium dilution of 1 to 2 SCCM. A phosphine silicate glass (PSG) film 27 is formed to a thickness of 300 to 400 nm under supply of O ₂ and 15 to 20 SCCM of monosilane, and a silicon nitride film 28 is formed under supply of 50 to 60 SCCM of NH ₃ and 15 to 20 SCCM of monosilane. It is formed to a thickness of 100 to 200 nm, and a laminated insulating film is formed. Then, for example, about 100
RTA (Rapid Thermal Anneal) for 20-30 seconds at 0 ° C
The ions are activated by the treatment, and the carrier impurity concentration is set in each region.

Next, as shown in (13) of FIG. 4, a contact window is opened at a predetermined position of the insulating film, and an electrode material such as aluminum containing 1% Si is sputtered on the entire surface including each contact hole by sputtering or the like. To a thickness of 1 μm,
By patterning this, pMOSTFT and nMOS
Each source or drain electrode 29 (S or D) of the TFT and a gate extraction electrode or wiring 30 (G) are formed to form a top gate type CMOS TFT. Thereafter, hydrogenation and sintering are performed at 400 ° C. for 1 hour in a forming gas.

It should be noted that instead of the formation of the gate electrode,
Sputtered film 40 of heat-resistant metal such as Mo-Ta alloy on the entire surface
A thickness of 0 to 500 nm is formed, and nMOSTFT and pMOS are formed by general-purpose photolithography and etching technology.
A gate electrode of a TFT may be formed.

As described above, according to the present embodiment,
The following excellent effects (a) to (l) can be obtained.

(A) A concave portion having a step having an appropriate shape and dimensions is formed at an arbitrary designated place on a substrate, and ultrafine particles such as silicon powder are adhered and dispersed therein, and an oxide film and an organic film on the surface of the ultrafine particles are formed. Since dirt and the like can be removed, the ultrafine particles are used as a nucleus (seed) for crystal growth, and a polycrystalline silicon film or the like having a large particle size with little variation is designated by bias or non-bias catalytic CVD, high density bias catalytic CVD, or the like. Can be formed in the defined area.

(B) A high-performance and high-quality TFT can be formed at any designated place on an insulating substrate, and the integrated circuit substrate can be formed freely.

(C) If necessary, TF on the insulating substrate
The surface in which the large-grain polycrystalline silicon film is buried in the concave portion having a step having an appropriate size and shape in the T formation region is polished to obtain a flat substrate having a large-grain polycrystalline silicon film surface. Therefore, high-performance, high-quality polycrystalline silicon semiconductor devices, electro-optical devices, and the like can be manufactured.

(D) The bias catalyst A was applied to the polycrystalline semiconductor thin film formed on the substrate using the ultrafine particles as seeds for crystal growth.
When the HA treatment is performed, a large amount of thermal energy of a high-temperature hydrogen-based active species or the like is converted into an electric field equal to or lower than a glow discharge starting voltage or /
And moves to the film or the like under the action of the magnetic field to locally increase the temperature of the film or the like. As a result, the amorphous component is etched, so that the amorphous silicon and the microcrystalline silicon thin film are polycrystallized, the polycrystalline silicon thin film has a high crystallization rate, and the polycrystalline silicon thin film having a large grain size and a high crystallization rate is obtained. Formed to improve carrier mobility.
Further, a similar semiconductor thin film is further grown on this thin film by vapor phase growth, and when these bias catalyst AHA treatment and vapor phase growth are repeated, polycrystalline silicon or the like is highly crystallized, having a high crystallization rate and a large grain size. Can be formed. As a result, not only the top gate type but also the bottom gate type and the dual gate type MOS TFT can obtain a polycrystalline silicon thin film having a high crystallinity with a high carrier (electron / hole) mobility and a large grain size. In addition, a high-speed, high-current-density semiconductor device, an electro-optical device, and a high-efficiency solar cell using the high-performance semiconductor thin film such as polycrystalline silicon can be manufactured.

(E) Further, when silicon oxide is present on or in a film such as a polycrystalline silicon thin film or at a grain boundary,
Since SiO is formed and vaporized in response to this, silicon oxide in the polycrystalline silicon film can be reduced or removed, and the mobility can be improved.

(F) Bias catalytic CVD, high density via
When performing film formation by the catalytic CVD method,
Temperature, substrate heating temperature, vapor deposition conditions, source gas species
Type, n or p-type impurity concentration, etc.
Polycrystalline silicon film with n or p-type impurity concentration is easy and easy
Obtained and further increased by bias catalyst AHA treatment
It is possible to form a polycrystalline silicon film with a high crystallinity at a grain size.
At high carrier mobility and V _thEasy to adjust and high with low resistance
High-speed operation becomes possible.

(G) Amorphous or microcrystalline or polycrystalline containing tin or other group IV elements (lead, germanium, etc.), for example, tin at 10 ¹⁸ to 10 ²⁰ atoms / cc by catalytic CVD, high-density catalytic CVD, or the like. Since a polycrystalline silicon film having a large grain size can be formed by forming a crystalline silicon film and then performing a catalytic AHA treatment, the effect of tin inclusion reduces crystal irregularities existing at the polycrystalline silicon grain boundaries and reduces internal stress. Thus, a polycrystalline silicon thin film having a large mobility can be formed.

(H) Compared to the hydrogen plasma treatment of the ECR discharge, the bias catalyst AHA treatment has a large effective area of strong energy (can be set freely by the size of the catalyst) and its variation is small, so that the large area Since the productivity of substrate processing is high and the cost is low, the versatility is high.

(I) Conventional RF / VHF plasma CVD
In contrast, bias catalytic CVD efficiently thermally decomposes and catalyzes a raw material gas with high energy, so that the utilization efficiency of the raw material gas is high, and since the formation is performed at a low temperature (300 to 400 ° C.), the cost and the size are increased. Easy low-strain-point glass, heat-resistant resin substrate, etc. can be adopted, and cost can be reduced.

(J) Since the bias catalyst CVD and the bias catalyst AHA processing can be performed without generating plasma, there is no damage by plasma, and a simple and inexpensive apparatus can be realized as compared with the plasma AHA processing.

(K) In the bias catalyst AHA treatment, even if the substrate temperature is lowered, the energy of the hydrogen-based active species is large, so that the target ultrafine particles of silicon and / or diamond-structured carbon are reliably and stably formed. Therefore, even when the substrate temperature is lowered to 300 to 400 ° C. in particular, the polycrystalline semiconductor thin film grows efficiently with the ultrafine particles as seeds, and thus is a large and inexpensive low strain point insulating substrate (glass substrate, glass substrate, Heat-resistant resin substrate) can be used, and the cost can be reduced in this respect as well.

(L) Bias catalyst A for n or p-type impurities added to gate channel / source / drain regions
Depending on conditions, a bias catalytic CVD apparatus can also be used for ion activation in the HA treatment, so that capital investment can be reduced and cost can be reduced by improving productivity.

Second Embodiment <Manufacturing Example 1 of LCD> In this embodiment, the present invention is applied to an LCD (Liquid Crystal Display) using a polycrystalline silicon MOSTFT by a high-temperature process. The production example is shown in FIG.
The present invention can be similarly applied to a display device such as an ED).

First, as shown in FIG. 16A, in the pixel portion and the peripheral circuit portion, a heat-resistant insulating substrate 61 (strain point of about 800 to 1100) made of quartz glass, crystallized glass or the like is used.
C., 50 μm to several mm thick) on one main surface by the above-described bias catalytic CVD method or the like to form a base protective film (not shown).
After the formation of the recesses 190, recesses 190 (not shown here; the same applies hereinafter) are formed in the same manner as described above, and silicon and / or
Alternatively, ultrafine carbon particles 100A are attached.

Next, as shown in FIG. 16 (2), the ultrafine particles 100A are cleaned by the above-mentioned bias catalyst AHA treatment, and silicon or / and the like from which organic substances and the like have been removed are removed.
And ultrafine particle layer 100B of carbon having a diamond structure
To be modified.

Next, as shown in FIG. 16C, the ultrafine particle layer 10 is formed by the above-described bias catalytic CVD method or the like.
Using 0B as a seed, a polycrystalline silicon thin film 67 is formed in the concave portion to a thickness of, for example, 50 nm. This polycrystalline silicon thin film may be formed by the above-described multi-bias catalytic AHA treatment.

Then, as shown in FIG. 17D, a polycrystalline silicon thin film 67 is formed using a photoresist mask.
(Islanding), for example, the nMOSTFT part in the display area and the nMOSTF in the peripheral drive circuit area
Active layers of transistors such as a T section and a pMOS TFT section, active elements such as diodes, and passive elements such as resistors, capacitors, and inductances are formed.

Next, the channel of the transistor active layer 67 is
V by controlling the impurity concentration in the tunnel region _thFor optimization
Ion injection of a predetermined impurity such as boron or phosphorus as described above
After the insertion, as shown in (5) of FIG.
Polycrystalline silicon by the same catalytic CVD method as above
A gate insulating film having a thickness of, for example, 50 nm on the surface of the thin film 67.
A silicon oxide film 68 is formed. By catalytic CVD method etc.
When forming a silicon oxide film 68 for a gate insulating film,
Substrate temperature and catalyst temperature are the same as above
However, the oxygen gas flow rate is 1-2 SCCM, monosilane gas flow
The amount is 15 to 20 SCCM, and the hydrogen-based carrier gas is 150
It may be SCCM. The impurity concentration of the channel region
Before or after controlling, for example, at about 1000 ° C. for 30 minutes
Silicon oxide film 6 for gate insulating film by high temperature thermal oxidation
8 may be formed.

Next, as shown in FIG. 17 (6), as a material for the gate electrode and the gate line, for example, Mo-
A Ta alloy is deposited to a thickness of, for example, 400 nm by sputtering, or a phosphorus-doped polycrystalline silicon film is deposited, for example, in a hydrogen-based carrier gas of 150 SCCM, 2-2.
0 SCCM phosphine (PH ₃ ) and 20 SCCM
Catalytic CVD as described above under supply of monosilane gas
It is deposited to a thickness of, for example, 400 nm by a method or the like. Then, the gate electrode material layer is patterned into the shape of the gate electrode 75 and the gate line by general-purpose photolithography and etching technology. In the case of a phosphorus-doped polycrystalline silicon film, a protective silicon oxide film (10 to 20 nm thick) may be formed on the surface by catalytic CVD or the like.

Next, as shown in (7) of FIG.
The MOSTFT portion is masked with a photoresist 78, and an n-type impurity such as arsenic (or phosphorus) ion 79 is, for example, 1 × 10 ¹⁵ a by ion implantation or ion doping.
doping at a dose of toms / cm ² , 2 × 10
The donor concentration was set to ²⁰ atoms / cc and the nMOST
An FT n ⁺ type source region 80 and a drain region 81 are formed.

Next, as shown in FIG. 18 (8), n
The MOSTFT portion is masked with a photoresist 82 and, for example, boron ions 83 which are p-type impurities are ion-implanted or ion-doped, for example, at 1 × 10 ¹⁵ atoms.
Doped with a dose of ^{/ cm 2, 2 × 10 20} ato
ms / cc acceptor concentration, pMOSTFT
The p ⁺ type source region 84 and the drain region 85 are respectively formed.

Next, as shown in FIG. 18 (9), by using the same bias-catalyzed CVD method or the like as described above, a hydrogen-based carrier gas of 150 to 200 SCCM is used in common, and He diluted O _{2 of 1 to 2} SCCM, 15-20S
Under the supply of CCM monosilane, the silicon oxide film is
To a thickness of 00 to 200 nm, furthermore, phosphine (PH ₃ ) of 1 to ₂₀ SCCM, He diluted O ₂ of 1 to ₂ SCCM,
A phosphine silicate glass (PSG) film is formed to a thickness of 300 to 400 nm under a supply of monosilane of 5 to 20 SCCM, and ammonia (NH ₃ ) of 50 to 60 SCCM is formed.
A silicon nitride film is formed to a thickness of, for example, 100 to 200 nm under a supply of monosilane of 15 to 20 SCCM. An interlayer insulating film 86 is formed by stacking these insulating films. Note that such an interlayer insulating film may be formed by another ordinary method different from the above. After this, for example 900 ° C., annealing or 1000 ° C. in N ₂ for 5 min, 20-30 seconds N ₂
The ions are activated by the RTA process in the inside, and the carrier impurity concentration is set in each region.

Next, as shown in (10) of FIG.
A contact window is opened at a predetermined position of the insulating film 86, and an electrode material such as aluminum is deposited to a thickness of 1 μm on the entire surface including each contact hole by a sputtering method or the like, and is patterned to form an nMOS TFT of a pixel portion. Source electrode 87, data line, pMOST of peripheral circuit section
Source electrodes 88 and 90 and drain electrodes 89 and 91 of FT and nMOSTFT and wiring are formed, respectively. Thereafter, for example, hydrogenation and sintering are performed at 400 ° C. for 1 hour in a forming gas to improve the interface state and the ohmic contact.

Next, after an interlayer insulating film 92 such as a silicon oxide film is formed on the surface by a CVD method or the like, (1) in FIG.
As shown in 1), contact holes are formed in the interlayer insulating films 92 and 86 in the nMOSTFT drain region of the pixel portion, and for example, ITO (Indium) having a thickness of 130 to 150 nm is formed.
A tin oxide (a transparent electrode material in which tin is doped into indium oxide) is deposited on the entire surface by a vacuum evaporation method or the like, and is patterned to form a transparent pixel electrode 93 connected to the drain region 81 of the nMOS TFT. Thereafter, annealing is performed, for example, in a forming gas at 250 ° C. for 1 hour to obtain I
The ohmic contact with the TO film is improved, and the transparency of the ITO film is improved.

Thus, an active matrix substrate (hereinafter, referred to as a TFT substrate) is manufactured, and a transmission type LCD can be manufactured. This transmission type LCD has an alignment film 9 on a transparent pixel electrode 93 as shown in FIG.
4, liquid crystal 95, alignment film 96, transparent electrode 97, counter substrate 9
8 are laminated.

The above-described steps can be similarly applied to the manufacture of a reflection type LCD. FIG. 24A shows an example of this reflection type LCD.
Reference numeral 1 denotes a reflection film deposited on the roughened insulating film 92, which is connected to the drain of the MOSTFT.

When manufacturing the liquid crystal cell of this LCD by surface assembly (suitable for medium / large liquid crystal panels of 2 inch size or more), first, a TFT substrate 61 and a solid IT
Counter substrate 98 provided with O (Indium Tin Oxide) electrode 97
The polyimide alignment films 94 and 96 are formed on the element formation surface. This polyimide alignment film is formed to a thickness of 50 to 100 nm by roll coating, spin coating, etc.
Cure with h.

Next, the TFT substrate 61 and the counter substrate 98 are subjected to rubbing or optical alignment processing. Rubbing buff materials include cotton and rayon, but cotton is more stable in terms of buff residue (garbage) and retardation.
Photoalignment is a technique for aligning liquid crystal molecules by non-contact linearly polarized ultraviolet irradiation. In addition, the orientation other than rubbing,
A polymer alignment film can be formed by obliquely entering polarized light or non-polarized light (such a polymer compound includes, for example, a polymethyl methacrylate-based polymer having azobenzene).

Next, after cleaning, a common agent is applied to the TFT substrate 61 side, and a sealing agent is applied to the counter substrate 98 side.
Wash with water or IPA (isopropyl alcohol) to remove rubbing buff debris. Common agent is acrylic or epoxy acrylate containing conductive filler,
Alternatively, the sealant may be an acrylic adhesive, an epoxy acrylate, or an epoxy adhesive. Any of heat curing, ultraviolet irradiation curing, ultraviolet irradiation curing and heat curing can be used, but from the viewpoint of overlay accuracy and workability, the ultraviolet irradiation curing and heat curing type is preferable.

Next, spacers for obtaining a predetermined gap are sprayed on the counter substrate 98 side, and are superposed on the TFT substrate 61 at a predetermined position. After the alignment mark on the counter substrate 98 and the alignment mark on the TFT substrate 61 are precisely aligned, the sealant is temporarily cured by irradiating with ultraviolet light, and then heat-cured collectively.

Next, a scribe break is performed to
A single liquid crystal panel in which the substrate 61 and the counter substrate 98 are overlapped is created.

Next, the liquid crystal 95 is injected into the gap between the two substrates 61-98, and the injection port is sealed with an ultraviolet adhesive, and then subjected to IPA cleaning. Any type of liquid crystal may be used, but for example, a high-speed response TN (twisted nematic) mode using a nematic liquid crystal is generally used.

Next, the liquid crystal 95 is oriented by heating and quenching.

Next, a flexible wiring is connected to the panel electrode take-out portion of the TFT substrate 61 by thermocompression bonding of an anisotropic conductive film, and a polarizing plate is bonded to the counter substrate 98.

In the case of a single liquid crystal panel surface assembly (suitable for a small liquid crystal panel having a size of 2 inches or less), a polyimide alignment film 94 is formed on the element forming surfaces of the TFT substrate 61 and the counter substrate 98 in the same manner as described above. , 96, and both substrates are subjected to rubbing or non-contact linear polarization ultraviolet light alignment treatment.

Next, the TFT substrate 61 and the opposing substrate 98 are divided into single pieces by dicing or scribe break, and washed with water or IPA. A common agent is applied to the TFT substrate 61, a sealing agent containing a spacer is applied to the counter substrate 98,
Lay both substrates together. Subsequent processes follow the above.

In the above-mentioned LCD, the counter substrate 98 is a CF (color filter) substrate, in which a color filter layer (not shown) is provided below the ITO electrode 97. The incident light from the counter substrate 98 side may be efficiently reflected by, for example, the reflection film 93 and may be emitted from the counter substrate 98 side.

On the other hand, when the TFT substrate 61 is a TFT substrate having an on-chip color filter (OCCF) structure in which a color filter is provided on the TFT substrate 61, the counter substrate 98 is provided with a solid ITO electrode (or a black mask). The ITO electrode is solid).

In the case of a transmission type LCD, an on-chip color filter (OCCF) structure and an on-chip black (OCB) structure can be manufactured as follows.

That is, as shown in FIG. 19 (13), the insulating film 8 of phosphine silicate glass / silicon oxide
The drain portion of No. 6 was also opened to form an aluminum buried layer for the drain electrode, and then a photoresist 99 in which each color of R, G, and B was dispersed in a pigment for each segment to a predetermined thickness (1 to 1.5 μm). After the formation, the color filter layers 99 (R), 99 (G), and 99 are patterned by a general-purpose photolithography technique to leave only predetermined positions (each pixel portion).
(B) is formed (on-chip color filter structure).
At this time, the window of the drain part is also opened. In addition, an opaque ceramic substrate, glass with low transmittance, and a heat-resistant resin substrate cannot be used.

Next, in a contact hole communicating with the drain of the display TFT, a light-shielding layer 100 'serving as a black mask layer is formed on the color filter layer by metal patterning. For example, a molybdenum film having a thickness of 200 to 250 nm is formed by sputtering,
Patterning into a predetermined shape that covers T and shields light (on-chip black structure).

Next, a flattening film 92 made of a transparent resin is formed, and further, an ITO transparent electrode 93 is formed in a through hole provided in the flattening film so as to be connected to the light shielding layer 100 '.

As described above, by forming the color filter 99 and the black mask 100 'on the display array portion, the aperture ratio of the liquid crystal display panel is improved, and the power consumption of the display module including the backlight is reduced. Is realized.

FIG. 20 shows the above-mentioned top gate type MOST.
1 schematically shows the entirety of an active matrix liquid crystal display device (LCD) configured with a drive circuit integrated by incorporating an FT. This active matrix LCD has a flat panel structure in which a main substrate 61 (which constitutes an active matrix substrate) and a counter substrate 98 are bonded via a spacer (not shown).
Liquid crystal (not shown) is sealed between 1-98. On the surface of the main substrate 61, a display unit including pixel electrodes 93 arranged in a matrix, a switching element for driving the pixel electrodes, and a peripheral drive circuit unit connected to the display unit are provided. .

The switching element of the display unit is n
It is composed of a MOS, pMOS or CMOS top-gate MOSTFT having an LDD structure. In the peripheral drive circuit section, the above-mentioned top gate type M
OSTFT CMOS or nMOS or pMOSTFT
Alternatively, a mixture of these is formed. Note that one of the peripheral drive circuit units is a horizontal drive circuit that supplies a data signal to drive the TFT of each pixel for each horizontal line, and the other peripheral drive circuit unit connects the gate of the TFT of each pixel for each scan line. , And are usually provided on both sides of the display unit. These drive circuits can be configured in either a dot-sequential analog system or a line-sequential digital system.

As shown in FIG. 21, at the intersection of the orthogonal gate bus line and data bus line, the MOSTF
T is disposed, and a liquid crystal capacitance (C
_LC ) Writes image information and holds the charge until the next information comes. In this case, it is not enough to hold the TFT channel resistance alone. To compensate for this, a storage capacitor (auxiliary capacitor) (C _S ) is added in parallel with the liquid crystal capacitor to compensate for a decrease in the liquid crystal voltage due to leak current. May be. In such a MOSTFT for LCDs, the required performance differs between the characteristics of the TFT used for the pixel portion (display portion) and the characteristics of the TFT used for the peripheral drive circuit. Is an important issue. For this reason, by providing a TFT having an LDD structure as described later in the display portion, an effective electric field applied to the channel region is reduced as a structure in which an electric field is hardly applied between the gate and the drain, and an off current is reduced. Can be reduced. However, the process becomes complicated, the element size becomes large, and problems such as a decrease in on-current occur. Therefore, an optimum design is required for each purpose of use.

Usable liquid crystals include TN liquid crystal (nematic liquid crystal used for TN mode of active matrix drive), STN (super twisted nematic), GH (guest / host), PC
(Phase change), FLC (ferroelectric liquid crystal), A
Liquid crystals for various modes such as FLC (antiferroelectric liquid crystal) and PDLC (polymer dispersed liquid crystal) may be employed.

<Manufacturing Example 2 of LCD> Next, an example of manufacturing an LCD (liquid crystal display device) using a polycrystalline silicon MOSTFT of a low-temperature process according to the present embodiment will be described. The present invention is similarly applicable to a display device of an FED and the like.

In this manufacturing example, aluminosilicate glass, borosilicate glass or the like is used as the substrate 61 in the above-mentioned manufacturing example 1, and (1), (2) and (3) in FIG.
Is performed in the same manner. That is, a tin-containing (or non-containing) polycrystalline silicon thin film 67 is formed on a substrate 61 by a bias catalyst CVD and a bias catalyst AHA treatment to form an island, and the nMOSTFT portion in the display region and the nMOSTFT in the peripheral drive circuit region And a pMOSTFT part are formed. In this case, at the same time, a diode, a capacitor,
An area such as an inductance and a resistance is formed.

Next, as shown in (1) of FIG. 22 (however, the underlayer protective film and the concave portion 190 are not shown; the same applies hereinafter), the _Vth is optimized by controlling the carrier impurity concentration of each MOSTFT gate channel region. In order to achieve the above, the nMOSTFT part in the display area and the nMOST
The FT portion is covered with a photoresist 82, and an n-type impurity 79 such as phosphorus or arsenic is added to the pMOSTFT portion in the peripheral drive circuit region by ion implantation or ion doping.
Doping was performed at a dose of × 10 ¹² atoms / cm ² , the donor concentration was set to 2 × 10 ¹⁷ atoms / cc, and as shown in FIG. Then, a p-type impurity 83 such as boron, for example, is implanted into the nMOSTFT portion of the display region and the nMOSTFT portion of the peripheral drive circuit region by 5 × 10 ¹¹ by ion implantation or ion doping.
doping at a dose of atoms / cm ² , 1 × 1
0 ¹⁷ Set the acceptor concentration of atoms / cc.

Next, as shown in (3) of FIG. 22, an n ^- type LDD (Lightly D
In order to form an oped drain) portion, the gate portion of the nMOSTFT in the display region and all the pMOSTFTs and nMOSTFTs in the peripheral driving region are covered with a photoresist 82 by a general-purpose photolithography technique, and n in the exposed display region is formed.
An n-type impurity 7 such as phosphorus is implanted into the source / drain region of the MOSTFT by ion implantation or ion doping.
9 is doped at a dose of 1 × 10 ¹³ atoms / cm ² and the donor concentration is set to 2 × 10 ¹⁸ atoms / cc to form an n ⁻ -type LDD portion.

Next, as shown in FIG. 23D, the nMOSTFT portion in the display area and the nM TFT in the peripheral drive circuit area are used.
The entire OSTFT portion is covered with a photoresist 82,
A p-type impurity 83 such as boron, for example, is ion-implanted or ion-doped into the source and drain regions exposed by covering the gate portion of the pMOSTFT portion of the peripheral drive circuit region with the photoresist 82 at 1 × 10 ¹⁵ atoms / s.
doping with a dose of cm ² , 2 × 10 ²⁰ atoms
A source portion 84 and a drain portion 85 of p ⁺ type are formed at an acceptor concentration of s / cc.

Next, as shown in FIG. 23 (5), the pMOSTFT portion in the peripheral drive circuit region is
2, the gate of the nMOSTFT in the display area and the LDD part and the gate part of the nMOSTFT part in the peripheral drive circuit area are covered with a photoresist 82, and the exposed source and drain areas of the nMOSTFT in the display area and the peripheral drive area are For example, an n-type impurity 79 such as phosphorus or arsenic is doped with 1 × 10 ¹⁵ atoms by ion implantation or ion doping.
ion doping at a dose of s / cm ² ,
^At a donor concentration of ²⁰ atoms / cc, an n ⁺ -type source portion 80 and a drain portion 81 are formed.

Next, as shown in FIG. 23 (6), plasma CVD, TEOS plasma CVD, catalytic CVD
As a gate insulating film 68, a silicon oxide film 40 to 50 nm thick, a silicon nitride film 10 to 20 nm thick,
A silicon oxide film having a thickness of 40 to 50 nm is formed.
Then, RTA treatment with a halogen lamp or the like is performed, for example, at about 1000 ° C. for 10 to 30 seconds, and the added n or p-type impurities are ion-activated to obtain each set carrier impurity concentration.

Thereafter, a 400-500 nm-thick aluminum sputtered film containing 1% Si is formed on the entire surface, and the gate electrodes 75 and gate lines of all the TFTs are formed by general-purpose photolithography and etching. Further, thereafter, an insulating film 86 composed of a stacked film having a silicon oxide film thickness of 100 to 200 nm, a phosphine silicate glass (PSG) film of 200 to 300 nm, and a silicon nitride film of 100 to 200 nm thickness by plasma CVD, catalytic CVD, or the like.
To form

Next, the windows of the source / drain portions of all the TFT portions and the source portion of the display nMOSTFT portion of the peripheral drive circuit are opened by general-purpose photolithography and etching techniques. The silicon nitride film is plasma-etched with CF ₄ , and the silicon oxide film and the phosphosilicate glass film are etched with a hydrofluoric acid-based etchant.

Next, as shown in FIG. 23 (7), an aluminum sputtered film containing 1% Si having a thickness of 400 to 500 nm is formed on the entire surface, and the source of all the TFTs of the peripheral drive circuit is formed by general-purpose photolithography and etching techniques. ,
At the same time as forming the drain electrodes 88, 89, 90 and 91, the source electrode 87 and the data line of the display nMOSTFT are formed.

Next, although not shown, the plasma CV
D, silicon oxide films 100 to 2 by catalytic CVD, etc.
00 nm thick phosphine silicate glass film (PSG
Film) 200 to 300 nm thick, silicon nitride films 100 to 3
A 00 nm thickness is formed on the entire surface as an interlayer insulating film (92 described above), and hydrogenation and sintering are performed in a forming gas at about 400 ° C. for 1 hour. After that, the display nMOST
A window for contacting the drain portion of the FT is opened.

Here, when the LCD is of a transmission type, the silicon oxide film, the phosphine silicate glass film and the silicon nitride film at the pixel opening are removed.
It is not necessary to remove the silicon oxide film, the phosphine silicate glass film, and the silicon nitride film in the pixel openings and the like (this is the same in the above-described or later-described LCD).

In the case of the transmission type, an acrylic transparent resin flattening film having a thickness of 2 to 3 μm is formed on the entire surface by spin coating or the like as in (10) of FIG. After forming a transparent resin window opening on the drain side of the TFT for
An ITO sputtered film with a thickness of nm is formed, and nMOSTF for display is formed by general-purpose photolithography and etching technology.
An ITO transparent electrode in contact with the drain of T is formed. Further heat treatment (200 to 25 in forming gas)
0 ° C., 1 hour) to reduce contact resistance and reduce IT
O To improve transparency.

In the case of the reflection type, a photosensitive resin film having a thickness of 2 to 3 μm is formed on the entire surface by spin coating or the like, and a concavo-convex pattern is formed at least in the pixel portion by general-purpose photolithography and etching techniques, and reflow is performed. To form a concave and convex reflecting lower portion. At the same time, a photosensitive resin window opening at the drain of the display nMOS TFT is formed. Thereafter, an aluminum sputtered film containing 1% Si with a thickness of 300 to 400 nm is formed on the entire surface, the aluminum film other than the pixel portion is removed by general-purpose photolithography and etching technology, and the irregularities connected to the drain electrode of the display nMOS TFT are formed. An aluminum reflector having a shape is formed. Then,
Sintering is performed at 300 ° C. for 1 hour in a forming gas.

In the above, if the bias catalyst AHA treatment is performed after the formation of the source and drain of the nMOS TFT, the film temperature of the polycrystalline silicon thin film is locally increased, crystallization is further promoted, and high mobility is obtained. And forming a high quality polycrystalline silicon thin film. At the same time, thermal energy of high-temperature hydrogen molecules, hydrogen atoms, activated hydrogen ions, etc. is transferred to the film to locally increase the film temperature, so that phosphorus and arsenic implanted in the gate channel / source / drain regions , Boron ions and the like are activated.

When an amorphous silicon-containing microcrystalline silicon thin film is formed by the plasma CVD method,
Although the film contains 10 to 20% of hydrogen, it can be reduced / removed by the bias catalyst AHA treatment to form a polycrystalline silicon film, forming a high mobility and high quality polycrystalline silicon thin film. . In addition, when silicon oxide is present on or in the polycrystalline silicon thin film, a reduction reaction is performed with the silicon oxide to generate SiO and evaporate and remove it, so that the silicon oxide on or in those films is reduced. / Removed, and a high mobility and high quality polycrystalline silicon thin film can be formed.

<Bottom gate type or dual gate type M
For example, in an LCD incorporating OSTFT> MOSTFT, a transmissive type L composed of a bottom gate type and a dual gate type MOSTFT is used instead of the above-described top gate type.
An example of manufacturing a CD will be described (however, the same applies to a reflective LCD).

As shown in FIG. 24B, a bottom gate type nMOSTFT is provided in the display portion and the peripheral portion.
Alternatively, as shown in FIG. 24C, a dual gate type nMOS TFT is provided in each of the display portion and the peripheral portion. Of these bottom gate type and dual gate type MOS TFTs, especially in the case of the dual gate type, the driving capability is improved by the upper and lower gate portions, suitable for high-speed switching, and selectively using one of the upper and lower gate portions. Depending on the case, it can be operated as a top gate type or a bottom gate type.

The bottom gate type MOSTF shown in FIG.
In the figure, reference numeral 102 denotes a gate electrode made of a Mo—Ta alloy or the like, 103 denotes a silicon nitride film, and 104 denotes a silicon oxide film to form a gate insulating film. A channel region and the like using a polycrystalline silicon thin film 67 similar to the MOSTFT are formed. Further, the dual gate type M shown in FIG.
In the OSTFT, the lower gate portion is a bottom gate type M
Similar to the OSTFT, except that the upper gate portion is formed by forming a gate insulating film 106 with a laminated film of a silicon oxide film and a silicon nitride film, and further, if necessary, a silicon oxide film, and providing an upper gate electrode 75 thereon. I have.

<Manufacture of Bottom Gate Type MOSTFT> First, a 300-400 nm-thick Mo-Ta alloy sputtered film is formed on the entire surface of the glass substrate 61, and this is formed by general-purpose photolithography and etching techniques for 20-45 nm.
The gate line is formed at the same time as the bottom gate electrode 102 is formed at least in the TFT formation region by taper etching. The selection of the glass material is in accordance with the above-mentioned top gate type.

Next, the silicon nitride film 10 for the gate insulating film and the protective film is formed by a vapor phase growth method such as plasma CVD, TEOS plasma CVD, catalytic CVD, and low pressure CVD.
3 and a silicon oxide film 104, and at least TF
A concave portion having a step having an appropriate shape / dimension is formed in the T formation region, silicon or / and carbon ultrafine particles are adhered, and silicon / or / diamond structure carbon ultrafine particles cleaned by bias catalyst AHA treatment are removed. Form. Using this as a seed, a polycrystalline silicon thin film containing or not containing tin is formed in the concave portion by bias catalyst CVD or the like, and a bias catalyst AHA treatment is repeated to form a large grain size polycrystalline silicon thin film 67 having a high crystallization rate. Form. These vapor deposition conditions are based on the above-mentioned top gate type. Note that the bottom gate insulating film and the silicon nitride film for the protective film are provided in expectation of the Na ion stopper function from the glass substrate, but are unnecessary in the case of synthetic quartz glass.

The subsequent processes are the same as those described above. However, since the gate electrode has already been formed in the above-described steps, the steps of forming a polycrystalline silicon film for a gate electrode, forming a gate electrode, and oxidizing a gate polycrystalline silicon are performed here. Is unnecessary.

Then, as described above, the pMOS
The TFT and nMOS TFT regions are made islands (however,
Only one region is shown: the same applies hereinafter), and an appropriate amount of n-type or p-type impurities is mixed by ion implantation or ion doping to control the carrier impurity concentration in each channel region to optimize _Vth . Later, each MOSTF
In order to form T source and drain regions, an appropriate amount of n-type or p-type impurities is mixed by ion implantation or ion doping. Thereafter, annealing of a bias catalyst AHA process or an RTA process is performed to activate impurities.

[0221] The subsequent processes are the same as those described above.

<Manufacture of Dual Gate MOSTFT>
Similarly to the above bottom gate type, the bottom gate electrode 10
2. The gate insulating films 103 and 104, and the polycrystalline silicon thin film 67 having a high crystallization rate and a large grain size and formed in the concave portion using ultrafine particles of silicon or / and diamond-structured carbon as seeds, respectively. However, the silicon nitride film 103 for the bottom gate insulating film and the protective film is provided in expectation of the Na ion stopper function from the glass substrate, but is unnecessary in the case of synthetic quartz glass.

Then, as described above, the pMOS
In order to optimize the V _th by controlling the carrier impurity concentration of each channel region by forming the islands of the TFT and nMOS TFT regions, an appropriate amount of n-type or p-type impurities are mixed by ion implantation or ion doping, and then, Each M
In order to form the source and drain regions of the OSTFT, an appropriate amount of n-type or p-type impurities is mixed by ion implantation or ion doping.

Next, a stacked film of a silicon oxide film and a silicon nitride film for the top gate insulating film 106 and, if necessary, a silicon oxide film are further formed. The vapor phase growth conditions are based on the above-mentioned top gate type. After that, RTA annealing is performed to activate the impurities.

Thereafter, an aluminum sputtered film containing 1% Si with a thickness of 400 to 500 nm is formed on the entire surface, and top gate electrodes 75 and gate lines of all TFTs are formed by general-purpose photolithography and etching techniques. Thereafter, an insulating film 86 made of a silicon oxide film having a thickness of 100 to 200 nm, a phosphine silicate glass (PSG) film having a thickness of 200 to 300 nm, or the like is formed by plasma CVD, catalytic CVD, or the like. Next, using general-purpose photolithography and etching technology, all MOS
TFT source / drain electrode part, display part nMO
A window is opened in the source electrode portion of the STFT.

Next, a 400 to 500 nm thick 1
An aluminum sputtered film containing% Si is formed, and source and drain aluminum electrodes 87, 88 and 89, a source line and a wiring are formed by general-purpose photolithography and etching techniques. Next, plasma C
VD, catalytic CVD method, etc.
200 nm thick phosphine silicate glass film (PS
G film) 200-300 nm thick, silicon nitride film 100-
A 300 nm thick interlayer insulating film 92 is formed on the entire surface, and is subjected to hydrogenation and sintering at about 400 ° C. for 1 hour in a forming gas. Thereafter, a drain contact window of the display nMOSTFT is opened to form a pixel electrode 93 of ITO or the like.

As described above, according to the present embodiment,
As in the first embodiment, the bias catalyst CVD is performed.
And the bias catalyst AHA treatment, the gate channel, the source and the drain region of the MOSTFT of the LCD display unit and the peripheral drive circuit unit, V _th with high carrier mobility
A polycrystalline silicon film having a large crystallization rate and a large grain size, which can be easily adjusted and can operate at a high speed with a low resistance, can be formed. A top gate made of this polycrystalline silicon thin film,
A liquid crystal display device using a bottom-gate or dual-gate MOSTFT has a display unit having an LDD structure with high switching characteristics and low leakage current, and a CM with high driving capability.
A configuration in which an OS or nMOS or pMOS peripheral drive circuit, a video signal processing circuit, a memory circuit, and the like are integrated becomes possible, and a high-quality, high-definition, narrow frame, high-efficiency, and inexpensive liquid crystal panel can be realized. .

Since it can be formed at a low temperature (300 to 400 ° C.), it is possible to use a low strain point glass which is inexpensive and easy to increase in size, and the cost can be reduced. In addition, by forming a color filter and a black mask on the array portion, the aperture ratio and luminance of the liquid crystal display panel are improved, a color filter substrate is not required, and cost reduction is achieved by improving productivity and the like.

Third Embodiment In the present embodiment, the present invention is applied to an organic or inorganic electroluminescence (EL) display device, for example, an organic EL display device. An example of the structure and a manufacturing example are shown below.

<Structure Example I of Organic EL Element> FIG.
As shown in (A) and (B), according to this structural example I,
A MOS transistor for switching is formed on a substrate 111 made of glass or the like by a polycrystalline silicon thin film having a high crystallization rate and a large grain size formed in the step 190 by the method described above according to the present invention.
The gate channel 117, the source region 120, and the drain region 121 of the TFT1 and the current driving MOSTFT2 are formed. Further, a gate electrode 115 is formed on the gate insulating film 118, and a source electrode 127 and drain electrodes 128 and 131 are formed on the source and drain regions. The drain of the MOSTFT1 and the gate of the MOSTFT2 are connected via a drain electrode 128, and a capacitor C is formed between the drain of the MOSTFT2 and the source electrode 127 of the MOSTFT2 via an insulating film 136.
The drain electrode 131 of the TFT 2 is the cathode 1 of the organic EL element.
It extends to 38.

Each MOSTFT is covered with an insulating film 130,
On this insulating film, for example, a green organic light emitting layer 132 (or a blue organic light emitting layer 133,
Further, a red organic light emitting layer (not shown) is formed, an anode (first layer) 134 is formed so as to cover the organic light emitting layer, and a common anode (second layer) 135 is formed on the entire surface. In addition, a peripheral driving circuit composed of a CMOS TFT,
The method of manufacturing the video signal processing circuit, the memory circuit, and the like conforms to the above-described liquid crystal display device (the same applies hereinafter).

In the organic EL display portion having this structure, the organic EL light emitting layer is connected to the drain of the current driving MOSTFT 2, and the cathode (Li-Al, Mg-Ag, etc.) 138 is attached to the surface of the substrate 111 such as glass. Then, the anodes (ITO films and the like) 134 and 135 are provided on the upper portion thereof, and therefore, the top emission 136 ′ is obtained. The cathode is MOSTF
In the case where T is covered, the light emitting area becomes large. At this time, the cathode serves as a light-shielding film, and the emitted light does not enter the MOSTFT, so that no leak current is generated and the TFT characteristics are not deteriorated.

Further, as shown in FIG. 25C, a black mask portion (chromium, chromium dioxide, etc.) 140 is formed around each pixel portion.
Is formed, light leakage (such as crosstalk) can be prevented, and the contrast can be improved.

It should be noted that green, blue and red colors are displayed on the pixel display portion.
Either a method using a color light-emitting layer, a method using a color conversion layer, or a method using a color filter for a white light-emitting layer can realize a good full-color EL display device, and a polymer that is a light-emitting material for each color. Long-life, high-precision, high-quality, high-reliability full-color organic EL even in compound spin coating or metal complex vacuum evaporation
Since the parts can be created with high productivity, the cost can be reduced (the same applies hereinafter).

A conventional organic EL of this type uses an amorphous or microcrystalline silicon MOSTFT.
_{Even if th} fluctuates, the current value easily fluctuates, and the image quality fluctuates easily. In addition, since the mobility is low, the current that can be driven with high speed response is limited, and it is difficult to form a p-channel, and even a small-scale CMOS circuit configuration is difficult. Therefore, it is desirable to use a polycrystalline silicon MOSTFT which is relatively easy to increase in area, has high reliability, has high carrier mobility, and can form a CMOS circuit. An amorphous silicon film is formed by a plasma CVD method at 300 to 400 [deg.] C. and excimer laser annealing is performed to form a polycrystalline silicon film. 2) 430-500 ° C amorphous silicon film
Formed by LPCVD method at 600 ° C./5
Solid phase growth is carried out at 20 hours and 850 ° C./0.5 to 3 hours to form a polycrystalline silicon film.

However, 1) adopts an expensive excimer laser device, and uses TFTs due to instability of the excimer laser.
Cost increases due to characteristic unevenness, quality problems, and reduced productivity. 2) The general-purpose glass substrate cannot be used due to the long-term heat treatment at 600 ° C. or higher and 15 to 20 hrs,
Since quartz glass is used, the cost is increased. In the full-color organic EL layer, in the microfabrication process, the electrode is oxidized, the organic EL material is exposed to oxygen and moisture, or the structure is changed by heating (dissolution or recrystallization).
Therefore, it is difficult to form each color light emitting region with high accuracy.

Next, the manufacturing process of the organic EL device according to the present embodiment will be described. First, as shown in FIG. 26A, the source region 120 made of a polycrystalline silicon thin film is subjected to the above-described steps. After forming the channel region 117 and the drain region 121, a gate insulating film 118 is formed, and the gate electrodes 11 of the MOSTFTs 1 and 2 are formed thereon.
5 is formed by sputtering a Mo—Ta alloy or the like, photolithography and etching techniques.
A gate line connected to the gate electrode of the STFT 1 is formed by sputtering film formation, photolithography, and etching technology (the same applies hereinafter). Then, after an overcoat film (silicon oxide or the like) 137 is formed by a vapor phase growth method such as catalytic CVD (the same applies hereinafter), the overcoat film 137 is formed at 1000 ° C.
Ion activation is performed by RTA treatment such as 0 to 30 seconds. Then, the source electrode 127 and the ground line of the MOSTFT 2 are formed, and the overcoat film (silicon oxide /
136 is formed.

Next, as shown in FIG. 26 (2), M
After opening the windows of the source / drain portion of the OSTFT1 and the gate portion of the MOSTFT2, as shown in (3) of FIG. 26, the MOSTFT1 is formed by sputtering Al containing 1% Si and general-purpose photolithography and etching techniques.
1% S between the drain electrode of
connected with the Al wiring 128 containing i,
Source electrode and A containing 1% Si connected to this electrode.
1 is formed. Then, an overcoat film (silicon oxide / phosphine silicate glass / silicon nitride laminated film) 130 is formed, and a MOS
Open the window of the drain part of TFT2, MOSTFT2
The cathode 138 of the light-emitting part connected to the drain part of FIG.

Next, as shown in FIG. 26 (4), an organic light emitting layer 132 and the like and anodes 134 and 135 are formed.

In the above description, the green (G) light emitting organic EL layer, the blue (B) light emitting organic EL layer, and the red (R) light emitting organic EL layer are each formed to a thickness of 100 to 200 nm. The layer is formed by a vacuum heating evaporation method in the case of a low molecular weight compound, and in the case of a high molecular weight compound, a method of arranging R, G, B light emitting polymers by an application method such as dipping coating or spin coating or an inkjet method is used. . In the case of a metal complex, a sublimable material is formed by a vacuum heating evaporation method.

The organic EL layer includes a single-layer type, a two-layer type, a three-layer type, and the like. Here, an example of a three-layer type of a low molecular compound is shown. Single layer type; anode / bipolar light emitting layer / cathode, double layer type; anode / hole transporting layer / electron transporting light emitting layer / cathode, or anode / hole transporting light emitting layer / electron transporting layer / cathode, three layer type; Anode / hole transporting layer / light emitting layer / electron transporting layer / cathode, or anode / hole transporting light emitting layer / carrier blocking layer / electron transporting light emitting layer / cathode

In the element of FIG. 25B, if a known light emitting polymer is used instead of the organic light emitting layer, it can be configured as a passive matrix or active matrix driven light emitting polymer display device (LEPD) (hereinafter, referred to as a LEPD). And similar).

<Structural Example II of Organic EL Device> FIG.
As shown in (A) and (B), according to this structural example II,
On a substrate 111 made of glass or the like, similar to the above structure example I,
The gate channel 117, the source region 120, and the drain region 121 of the switching MOSTFT1 and the current driving MOSTFT2 are formed by the polycrystalline silicon thin film having a high crystallization rate and a large grain size formed by the above-described method according to the present invention. Have been. Then, the gate insulating film 1
A gate electrode 115 is formed on the source electrode 18, and a source electrode 127 and drain electrodes 128 and 131 are formed on the source and drain regions. MOSTFT1 drain and MOST
The gate of the FT2 is connected via the drain electrode 128 and the drain electrode 131 of the MOSTFT2.
And a capacitor C is formed via an insulating film 136, and the source electrode 127 of the MOSTFT 2 is an organic
It extends to the anode 144 of the L element.

Each MOSTFT is covered with an insulating film 130,
On the insulating film, for example, a green organic light emitting layer 132 (or a blue organic light emitting layer 133,
Further, a red organic light emitting layer (not shown) is formed, a cathode (first layer) 141 is formed so as to cover the organic light emitting layer, and a common cathode (second layer) 142 is formed on the entire surface.

In the organic EL display section having this structure, the organic EL light emitting layer is connected to the source of the current driving MOSTFT 2,
An organic EL light emitting layer is formed so as to cover the anode 144 attached to the surface of the substrate 111 such as glass, a cathode 141 is formed so as to cover the organic EL light emitting layer, and a cathode 142 is formed over the entire surface. Therefore, bottom emission 136 'is obtained. Further, the cathode covers the organic EL light emitting layer and the MOSTFT. That is, after forming, for example, a green light emitting organic EL layer on the entire surface by a vacuum heating evaporation method or the like, the green light emitting organic EL layer is formed.
The portion is formed by photolithography and dry etching, and a blue and red light-emitting organic EL portion is continuously formed in the same manner. Finally, a cathode (electron injection layer) 141 is entirely formed of a magnesium: silver alloy or aluminum: lithium alloy. Form. Since the entire surface is sealed with a cathode (electron injection layer) further formed, the invasion of moisture from the outside to the organic EL layer is particularly prevented by the cathode 142 deposited on the entire surface, and the deterioration of the organic EL layer which is weak to moisture and the electrode are prevented. Prevents oxidation, long life,
High quality and high reliability are possible (the same is true for the structural example I in FIG. 25 since the entire surface is covered with the anode). In addition, since the heat radiation effect is enhanced by the cathodes 141 and 142, a structural change (melting or recrystallization) of the thin film due to heat generation is reduced, and a long life, high quality, and high reliability can be achieved. In addition, since a high-precision, high-quality, full-color organic EL layer can be produced with high productivity, the cost can be reduced.

Further, as shown in FIG. 27C, a black mask portion (chromium, chromium dioxide, etc.) 140 is formed around each pixel portion.
Is formed, light leakage (such as crosstalk) can be prevented, and the contrast can be improved. Note that the black mask portion 140 is covered with a silicon oxide film 143 (this may be formed simultaneously with the gate insulating film 118 using the same material).

Next, the manufacturing process of the organic EL device will be described. First, as shown in FIG. 28A, a polycrystalline silicon thin film having a high crystallization rate and a large grain size is formed through the above-described steps. Source region 120 and channel region 117
After forming the drain region 121 and the bias catalyst C
A gate insulating film 118 is formed by a vapor phase growth method such as VD, and sputtering is performed using a Mo-Ta alloy or the like, and M is formed thereon by general-purpose photolithography and etching techniques.
The gate electrodes 115 of the OSTFTs 1 and 2 are formed.
A gate line connected to the gate electrode of the MOSTFT 1 is formed by sputtering film formation of an o-Ta alloy or the like and general-purpose photolithography and etching techniques. Then, after forming an overcoat film (silicon oxide or the like) 137 by a vapor phase growth method such as bias catalyst CVD, 1000
Ion activation is performed by RTA treatment at 10 ° C. for 10 to 30 seconds. Then, M is formed by sputtering film formation of Al containing 1% Si and general-purpose photolithography and etching technology.
The drain electrode 131 and the _Vdd line of the OSTFT 2 are formed, and an overcoat film (silicon oxide / silicon nitride laminated film) 136 is formed by a vapor phase growth method such as bias catalytic CVD.

Next, as shown in FIG. 28 (2), the MOS is formed by general-purpose photolithography and etching techniques.
After opening the windows of the source / drain portion of the TFT 1 and the gate portion of the MOSTFT2, as shown in FIG.
The drain of FT1 and the gate of MOSTFT2 are 1% Si
A source line made of Al containing 1% Si and connected to the source of the MOSTFT 1 at the same time is formed. Then, an overcoat film (silicon oxide / phosphine silicate glass / silicon nitride laminated film, etc.) 130 is formed, a window of the source portion of the MOSTFT 2 is opened by general-purpose photolithography and etching technology, and sputtering such as ITO and general-purpose photolithography are performed. And MOSTFT2 by etching technology
The anode 144 of the light emitting portion connected to the source portion of the light emitting device is formed.

Next, as shown in FIG. 28D, the organic light emitting layer 132 and the cathodes 141 and 142 are formed as described above.
To form

The constituent materials and forming methods of each layer of the organic EL described below are applied to the example of FIG. 27, but may be similarly applied to the example of FIG.

In the case where a low molecular compound is used for the green light emitting organic EL layer, an I (contact) source which is in contact with a source portion of a current driving MOSTFT which is an anode (hole injection layer) on a glass substrate.
It is formed on the TO transparent electrode by a continuous vacuum heating evaporation method. 1) The hole transport layer is made of an amine compound (for example, a triarylamine derivative, an arylamine oligomer, an aromatic tertiary amine, etc.) 2) The light emitting layer is made of tris (8-hydroxyxylino) Al which is a green light emitting material Complex (Alq), etc. 3) The electron transport layer is made of 1,3,4-oxadiazole derivative (OXD), 1,2,4-triazole derivative (TA
Z) etc. 4) The electron injection layer serving as the cathode is preferably made of a material having a work function of 4 eV or less. For example, 10 to 30 nm thickness of a 10: 1 (atomic ratio) magnesium: silver alloy 10 to 30 nm thickness of an aluminum: lithium (concentration 0.5 to 1%) alloy Here, silver has an adhesive property with an organic interface. 1 to 10 atomic% is added to magnesium for increasing, and lithium is added to aluminum at a concentration of 0.5 to 1% for stabilization.

To form a green pixel portion, the green pixel portion
Mask with photoresist and CCl _FourGas plasma
The aluminum of the electron injection layer which is the cathode by the etching:
Remove lithium alloy, continuously electron transport layer, light emitting layer,
The low-molecular compound and the photoresist in the hole transport layer are acidified.
Removed by elementary plasma etching to form a green pixel
You. At this time, the aluminum under the photoresist:
Photoresist is etched due to lithium alloy
There is no problem if it is done. At this time, the electron transport layer,
Layer, hole transport layer, low-molecular compound layer, hole injection layer
Area larger than the ITO transparent electrode of
Electron injection layer of the cathode 142 (magnesium: silver
Alloy, etc.).

Next, when the blue light-emitting organic EL layer is formed of a low-molecular compound, the blue light-emitting organic EL layer is continuously formed on the ITO transparent electrode which is in contact with the source of the current driving TFT which is the anode (hole injection layer) on the glass substrate. And formed by vacuum heating evaporation. 1) The hole transport layer is an amine compound (for example, a triarylamine derivative, an arylamine oligomer, an aromatic tertiary amine, etc.) 2) The light emitting layer is a distyryl derivative such as DTVBi which is a blue light emitting material 3) The electron transport layer is composed of a 1,3,4-oxadiazole derivative (TAZ), a 1,2,4-triazole derivative (TA
Z) etc. 4) The electron injection layer serving as the cathode is preferably made of a material having a work function of 4 eV or less. For example, 10 to 30 nm thickness of a 10: 1 (atomic ratio) magnesium: silver alloy 10 to 30 nm thickness of an aluminum: lithium (concentration 0.5 to 1%) alloy Here, silver has an adhesive property with an organic interface. 1 to 10 atomic% is added to magnesium for increasing, and lithium is added to aluminum at a concentration of 0.5 to 1% for stabilization.

To form a blue pixel portion, the blue pixel portion
Mask with photoresist and CCl _FourGas plasma
Of the electron injection layer which is the cathode in the etching: Li
Alloy, and the electron transport layer, light emitting layer,
Oxygen-transporting the low molecular weight compound and photoresist in the
It is removed by plasma etching to form a blue pixel portion. This
At the time of the photoresist under the aluminum: Lithium
The photoresist is etched
No problem. At this time, the electron transport layer, the light emitting layer,
The low-molecular compound layer of the hole transport layer is made of ITO of the hole injection layer.
Make the area larger than the transparent electrode and form it over the entire surface in a later process
Electron injection layer of the cathode 142 (magnesium: silver alloy, etc.)
And electrical shorts.

When the red light-emitting organic EL layer is formed of a low-molecular compound, the red light-emitting organic EL layer is continuously formed on the ITO transparent electrode in contact with the source of the current driving TFT which is the anode (hole injection layer) on the glass substrate. Formed by vacuum heating evaporation. 1) The hole transport layer is made of an amine compound (for example, a triarylamine derivative, an arylamine oligomer, an aromatic tertiary amine, etc.) 2) The light emitting layer is made of Eu (Eu (DBM)) which is a red light emitting material
₃ ) (Phen)) 3) The electron transport layer is made of a 1,3,4-oxadiazole derivative (OXD), a 1,2,4-triazole derivative (TA
Z) etc. 4) The electron injection layer serving as the cathode is preferably made of a material having a work function of 4 eV or less. For example, a 10: 1 (atomic ratio) magnesium: silver alloy having a thickness of 10 to 30 nm, an aluminum: lithium (concentration of 0.5 to 1%) alloy having a thickness of 10 to 30 nm, silver is used to increase the adhesion to an organic interface. 1 to 10 atomic% is added to magnesium, and lithium is added to aluminum at a concentration of 0.5 to 1% for stabilization.

To form a red pixel portion, the red pixel portion
Mask with photoresist and CCl _FourGas plasma
Of the electron injection layer which is the cathode in the etching: Li
Alloy, and the electron transport layer, light emitting layer,
Oxygen-transporting the low molecular weight compound and photoresist in the
It is removed by plasma etching to form a red pixel portion. This
At the time of the photoresist under the aluminum: Lithium
The photoresist is etched
No problem. At this time, the electron transport layer, the light emitting layer,
The low-molecular compound layer of the hole transport layer is made of ITO of the hole injection layer.
Make the area larger than the transparent electrode and form it over the entire surface in a later process
Electron injection layer of the cathode 142 (magnesium: silver alloy, etc.)
And electrical shorts. After this, the common
The electron injection layer (magnesium: silver alloy, etc.) of the cathode 142
Formed over the entire surface.

The electron injection layer serving as a cathode is preferably made of a material having a work function of 4 eV or less. For example,
10 to 3 of 10: 1 (atomic ratio) magnesium: silver alloy
0 nm thick, or aluminum: lithium (concentration is 0.5
１1%) The thickness of the alloy is 10 to 30 nm. Here, silver is added to magnesium in magnesium in order to increase adhesiveness with an organic interface.
10 atomic% is added, and lithium is added to aluminum at a concentration of 0.5 to 1% for stabilization. Note that the film may be formed by sputtering.

Fourth Embodiment In this embodiment, the present invention is applied to a field emission type (field emission) display device (FED: Field Emission).
Display). An example of the structure and a manufacturing example are shown below.

<Structure Example I of FED> FIG.
As shown in (B) and (C), according to this structural example I,
A switching MOS TFT is formed on a substrate 111 made of glass or the like by using a polycrystalline silicon thin film having a high crystallization rate and a large grain size formed in a step by the above-described method according to the present invention.
1 and gate channel 11 of current driving MOSTFT2
7, a source region 120 and a drain region 121 are formed. Then, the gate electrode 115 is formed on the gate insulating film 118, and the source electrode 127 is formed on the source and drain regions.
And a drain electrode 128 are formed. MOSTF
The drain of T1 and the gate of MOSTFT2 are connected via a drain electrode 128, and
A capacitor C is formed between the source electrode 127 of T2 and the insulating film 136 via the insulating film 136, and the drain region 121 of the MOSTFT2 is extended as it is to the FEC (field emission cathode) of the FED element and functions as the emitter region 152. are doing.

Each MOSTFT is covered with an insulating film 130,
On this insulating film, an FEC gate extraction electrode 150 is formed.
A metal shielding film 151 for grounding is formed of the same material and in the same step, and covers each MOSTFT. In the FEC, an emitter region 1 made of a polycrystalline silicon thin film is used.
An n-type polycrystalline silicon film 153 serving as a field emission emitter is formed on 52, and insulating films 118 and 13 are formed so as to have openings for partitioning into m × n emitters.
7, 136 and 130 are patterned, and a gate lead-out electrode 150 is deposited on the upper surface thereof.

A substrate 157 such as a glass substrate formed with a phosphor 156 having a back metal 155 as an anode is provided opposite to the FEC, and a high vacuum is maintained between the substrate and the FEC.

In the FEC having this structure, the n-type polycrystalline silicon film 153 grown on the polycrystalline silicon thin film 152 formed according to the present invention is exposed below the opening of the gate extraction electrode 150. , Each function as a thin-film type emitter that emits electrons 154. That is, the polycrystalline silicon thin film 152 serving as the base of the emitter
Is composed of grains having a large grain size (a grain size of several hundred nm or more). When the n-type polycrystalline silicon film 153 is grown thereon by bias catalytic CVD or the like as a seed, the polycrystalline silicon Membrane 153
Grows with a larger particle size, and the surface is formed so as to generate fine irregularities 158 which are advantageous for electron emission. At this time, a polycrystalline diamond film, a carbon thin film containing or not containing nitrogen, and an electron emitter (emitter) having a large number of fine projection structures (for example, carbon nanotubes) on the surface of the carbon thin film containing or not containing nitrogen may also be used. Good.

Therefore, since the emitter is of a surface emission type composed of a thin film, it can be easily formed, the emitter performance is stabilized, and the life can be extended.

A ground potential metal shielding film 151 (this metal shielding film is formed of a gate lead-out electrode 150) is placed on top of all active elements (including a peripheral driving circuit and a MOSTFT and a diode of a pixel display section). The same material (Nb, Ti / Mo, etc.) is formed in the same step, which is convenient for the process.) Therefore, the following (1),
The advantage of (2) can be obtained.

(1) The gas in the airtight container is the emitter 1
The electrons emitted from the electrons 53 are positively ionized and charged up on the insulating layer.
An unnecessary inversion layer is formed in the OSTFT, and an extra current flows through an unnecessary current path including the inversion layer.
Runaway of the emitter current occurs. However, since the metal shielding film 151 is formed on the insulating layer on the MOSTFT and dropped to the ground potential, charge-up can be prevented, and runaway of the emitter current can be prevented.

(2) The phosphor 156 emits light due to the collision of the electrons emitted from the emitter 153, and this light generates electrons and holes in the gate channel of the MOSTFT, resulting in a leak current. However, since the metal shielding film 151 is formed on the insulating layer on the MOSTFT, the MOST
Light incidence on the FT is prevented, and no operation failure of the MOSTFT occurs.

Since an electron emitter such as an n-type polycrystalline silicon film is formed at least in a continuous manner at least in the drain region of the polycrystalline silicon MOSTFT by bias catalytic CVD or the like, the junction property is improved. Good and highly efficient emitter characteristics are possible.

If the electron emitter (emitter) region of one pixel display section is divided into a plurality of parts and each of them is connected to a MOSTFT of a switching element, one MOS transistor is formed.
Even if the TFT fails, the other MOSTFT operates, so that one pixel display unit always emits electrons, so that high quality, high yield, and cost reduction can be achieved. or,
Among these MOSTFTs, there is no problem with the MOSTFT having an electrically open defect,
Since TFTs can be separated by laser repair, high quality, high yield, and cost reduction can be achieved.

On the other hand, in the conventional FED, since a silicon single crystal substrate is used, the substrate cost is high, and it is difficult to increase the area over the wafer size. It has been proposed to form an electron emitter by forming a conductive polycrystalline silicon film on the cathode electrode surface by low pressure CVD or the like and forming a crystalline diamond film on the surface by plasma CVD or the like. Film forming temperature during low pressure CVD is 63
Since the temperature is as high as 0 ° C. and a glass substrate cannot be employed, cost reduction is difficult. Then, the polycrystalline silicon film formed by the low pressure CVD has a small particle size, and the crystalline diamond film on the polycrystalline silicon film also has a small particle size, so that the characteristics of the electron emitter are not good. Furthermore, since plasma CVD has insufficient reaction energy, it is difficult to obtain a good crystalline diamond film.
In addition, since the bonding property between the conductive polycrystalline silicon film and the transparent electrode or the cathode electrode of a metal such as Al, Ti, and Cr is poor,
Good electron emission characteristics cannot be obtained.

Next, the manufacturing process of the FED according to the present embodiment will be described. First, as shown in FIG.
17 are formed, MOSTFT1, MOSTFT2, and an emitter region are formed into islands by general-purpose photolithography and etching techniques.
A protective silicon oxide film 159 is formed on the entire surface by a VD method or the like.

Next, in order to optimize V _th by controlling the gate channel impurity concentration of the MOSTFTs 1 and 2,
The whole surface is doped with boron ions 83 at a dose of 5 × 10 ¹¹ atoms / cm ² by ion implantation or ion doping to set an acceptor concentration of 1 × 10 ¹⁷ atoms / cc.

Next, as shown in FIG. 30 (2), using the photoresist 82 as a mask, phosphorus ions 79 are applied to the source / drain portions and the emitter regions of the MOSTFTs 1 and 2 by 1 × 10 5 by ion implantation or ion doping. ^Fifteen
doping at a dose of atoms / cm ² , 2 × 1
After setting the donor concentration to 0 ²⁰ atoms / cc and forming the source region 120, the drain region 121, and the emitter region 152, the silicon oxide film for protecting the emitter region is removed by general-purpose photolithography and etching techniques.

Next, as shown in FIG. 30C, monosilane and a dopant such as PH ₃ are mixed at an appropriate ratio using a polycrystalline silicon thin film 152 for forming an emitter region by bias or non-bias catalytic CVD as a seed. The surface has fine irregularities 158, and the dopant is, for example, 5 × 1
An n-type polycrystalline silicon film 153 containing 0 ²⁰ to 1 × 10 ²¹ atoms / cc is formed in the emitter region to a thickness of 1 to 5 μm, and at the same time, the other silicon oxide film 159 and the n-type amorphous silicon The membrane 160
It is formed to a thickness of 5 μm.

Next, as shown in FIG. 30D, the amorphous silicon film 160 is selectively etched away by the action of hydrogen-based active species during the above-described bias catalyst AHA treatment, and the silicon oxide film 159 is removed. After the etching removal, a gate insulating film (silicon oxide film or the like) 118 is formed by catalytic CVD or the like.

Next, as shown in FIG. 30 (5), the gate electrodes 115 of the MOSTFTs 1 and 2 are formed of a heat-resistant metal such as a Mo—Ta alloy by sputtering.
After a gate line connected to the gate electrode of the FT1 is formed and an overcoat film (silicon oxide film or the like) 137 is formed, ion activation is performed by RTA treatment at 1000 ° C. for 10 to 20 seconds. Thereafter, after opening the window of the source portion of the MOSTFT 2, the source electrode 127 and the ground line of the MOSTFT 2 are formed of a heat-resistant metal such as a Mo-Ta alloy by a sputtering method. Further, an overcoat film (silicon oxide / silicon nitride laminated film) 136 is formed by plasma CVD, catalytic CVD, or the like.

Next, as shown in FIG. 31 (6), M
Source / drain part of OSTFT1 and MOSTFT2
Of the gate of the MOSTFT1 and the gate of the MOSTFT2 are connected to the Al wiring 12 containing 1% Si.
8 and at the same time, a source electrode of the MOSTFT 1 and a source line 127 connected to the source are formed.

Next, as shown in FIG. 31 (7), after forming an overcoat film (silicon oxide / phosphine silicate glass / silicon nitride laminated film) 130, a GND line window is opened and FIG. As shown in (8), the gate extraction electrode 150 and the metal shielding film 151 are formed by etching after Nb deposition, and the field emission cathode portion is opened to expose the emitter 153, and the above-described bias catalyst AHA treatment is performed. At the same time as cleaning with the hydrogen-based active species, fine irregularities are prominent due to the selective etching action of the hydrogen-based active species.

<Structure Example II of FED> FIG.
As shown in (B) and (C), according to this structural example II,
On a substrate 111 made of glass or the like, similar to the above structure example I,
A switching MOS TFT 1 and a current driving MOS TFT 1 are formed by a high crystallinity, large grain size polycrystalline silicon thin film formed in a step by the above-described method according to the present invention.
Two gate channels 117, a source region 120 and a drain region 121 are formed. Then, a gate electrode 115 is formed over the gate insulating film 118, and a source electrode 127 and a drain electrode 128 are formed over the source and drain regions. MOSTFT drain and MOSTF
The gate of T2 is connected via a drain electrode 128, a capacitor C is formed between the source electrode 127 of the MOSTFT2 via an insulating film 136, and the drain region 121 of the MOSTFT2 is directly connected to the gate of T2.
It extends to the FEC (field emission cathode) of the ED element and functions as an emitter region 152.

Each MOSTFT is covered with an insulating film 130,
On this insulating film, an FEC gate extraction electrode 150 is formed.
A metal shielding film 151 for grounding is formed of the same material and in the same step, and covers each MOSTFT. In the FEC, an emitter region 1 made of a polycrystalline silicon thin film is used.
An n-type polycrystalline diamond film 163 serving as a field emission emitter is formed on 52, and insulating films 118, 1 are formed so as to have openings for partitioning into m × n emitters.
37, 136 and 130 are patterned, and a gate extraction electrode 150 is attached on the upper surface thereof.

A substrate 157 such as a glass substrate formed with a phosphor 156 having a back metal 155 as an anode is provided opposite to the FEC, and a high vacuum is maintained between the substrate and the FEC.

In the FEC having this structure, an n-type polycrystalline diamond film 163 grown on a polycrystalline silicon thin film 152 formed according to the present invention is exposed below the opening of the gate extraction electrode 150, and this is exposed. Each electronic 154
Function as a thin-film emitter that emits light. In other words, since the polycrystalline silicon film 152 serving as the base of the emitter is composed of grains having a large grain size (a grain size of 100 nm or more), the n-type polycrystalline diamond film 163 is used as a seed on the catalyst to form a catalyst. When grown by CVD or the like, the polycrystalline diamond film 163 also grows with a large grain size, and the surface is formed so as to generate fine irregularities 168 advantageous for electron emission. At this time, an electron emitter (emitter) having a large number of fine projection structures (for example, carbon nanotubes) on the surface of a nitrogen-containing or non-nitrogen-containing carbon thin film or a nitrogen-containing or non-nitrogen-containing carbon thin film.
It may be.

Therefore, since the emitter is of a surface emission type composed of a thin film, it can be easily formed, the emitter performance is stabilized, and the life can be extended.

A ground potential metal shielding film 151 (this metal shielding film is formed of a gate lead-out electrode 150) is placed on top of all active elements (including a peripheral driving circuit and a MOSTFT and a diode of a pixel display section). The same material (Nb, Ti / Mo, etc.) is formed in the same step, which is convenient for the process.) As described above, the metal shielding film 151 is formed on the insulating layer on the MOSTFT as described above. To ground potential to prevent charge-up, prevent runaway of emitter current, and reduce MOST
Since the metal shielding film 151 is formed on the insulating layer on the FT, light is prevented from being incident on the MOSTFT.
Does not occur.

Next, the manufacturing process of this FED will be described. First, as shown in FIG. 33 (1), after a polycrystalline silicon thin film 117 is formed on the entire surface through the above-described steps, general-purpose photolithography and An island is formed in the MOSTFT1 and MOSTFT2 and the emitter region by an etching technique, and a protective silicon oxide film 159 is formed on the entire surface by plasma CVD, catalytic CVD, or the like.

Next, in order to optimize V _th by controlling the gate channel impurity concentration of the MOSTFTs 1 and 2,
The whole surface is doped with boron ions 83 at a dose of 5 × 10 ¹¹ atoms / cm ² by ion implantation or ion doping to set an acceptor concentration of 1 × 10 ¹⁷ atoms / cc.

Then, as shown in FIG. 33 (2), using the photoresist 82 as a mask, phosphorus ions 79 are implanted into the source / drain portions and the emitter regions of the MOSTFTs 1 and 2 by ion implantation or ion doping at 1 × 10 4. ^Fifteen
doping at a dose of atoms / cm ² , 2 × 1
After setting the donor concentration to 0 ²⁰ atoms / cc and forming the source region 120, the drain region 121, and the emitter region 152, the silicon oxide film for protecting the emitter region is removed by general-purpose photolithography and etching techniques.

Next, as shown in (3) of FIG. 33, monosilane, methane (CH ₄ ), and an appropriate ratio of dopant are used as seeds with the polycrystalline silicon thin film 152 forming the emitter region formed by biased or non-biased catalytic CVD. After mixing, an n-type polycrystalline diamond film 163 having fine irregularities 168 on the surface is formed in the emitter region, and an n-type amorphous diamond film 170 is formed on the other silicon oxide film 159 and the glass substrate 111 at the same time.

Next, as shown in (4) of FIG. 33, the amorphous diamond film 170 is selectively etched away by the action of hydrogen-based active species during the above-described bias catalyst AHA treatment, and the silicon oxide film 159 is removed. After the etching removal, a gate insulating film (silicon oxide film or the like) 118 is formed by catalytic CVD or the like.

Next, as shown in (5) of FIG. 34, the gate electrodes 115 of the MOSTFTs 1 and 2 and the MOST are made of a heat-resistant metal such as a Mo—Ta alloy by a sputtering method.
After a gate line connected to the gate electrode of the FT1 is formed and an overcoat film (silicon oxide film or the like) 137 is formed, ion activation treatment such as RTA at 1000 ° C. for 10 to 20 seconds is performed. Thereafter, after opening the window of the source of the MOSTFT 2, the source electrode 127 and the ground line of the MOSTFT 2 are formed of a heat-resistant metal such as a Mo-Ta alloy by a sputtering method. Further, an overcoat film (silicon oxide / silicon nitride laminated film) 136 is formed by plasma CVD, catalytic CVD, or the like.

Next, as shown in FIG. 34 (6), M
Source / drain part of OSTFT1 and MOSTFT2
Of the gate of the MOSTFT1 and the gate of the MOSTFT2 are connected to the Al wiring 12 containing 1% Si.
8 and at the same time, a source electrode of the MOSTFT 1 and a source line 127 connected to the source are formed.

Next, as shown in (7) of FIG. 34, after forming an overcoat film (silicon oxide / phosphine silicate glass / silicon nitride laminated film) 130, a GND line window is opened, and FIG. As shown in (8), the gate extraction electrode 150 and the metal shielding film 151 are formed by etching after Nb deposition, and the field emission cathode portion is opened to expose the emitter 163, and the above-described bias catalyst AHA treatment is performed. At the same time as the cleaning with the hydrogen-based active species, fine irregularities are made more pronounced by the selective etching action of the hydrogen-based active species.

In the above, when forming the polycrystalline diamond film 163, the carbon-containing compound used as a raw material gas includes, for example, 1) paraffinic hydrocarbons such as methane, ethane, propane, and butane 2) acetylene , Allylene-based acetylene-based hydrocarbons 3) olefin-based hydrocarbons such as ethylene, propylene, butylene 4) di-olefin-based hydrocarbons such as butadiene 5) cyclopropane, cyclobutane, cyclopentane,
Alicyclic hydrocarbons such as cyclohexane 6) Aromatic hydrocarbons such as cyclobutadiene, benzene, toluene, xylene and naphthalene 7) Ketones such as acetone, diethyl ketone and benzophenone 8) Alcohols such as methanol and ethanol 9) Trimethylamine , Amines such as triethylamine, etc. 10) Substances consisting only of carbon atoms, such as graphite, coal, coke, etc., which may be used alone or in combination of two or more.

Further, usable inert gases are, for example, argon, helium, neon, krypton, xenon and radon. As the dopant, for example, a compound containing boron, lithium, nitrogen, phosphorus, sulfur, chlorine, arsenic, selenium, beryllium, or a simple substance can be used, and the doping amount may be 10 ¹⁶ atoms / cc or more.

Fifth Embodiment In this embodiment, the present invention is applied to a solar cell as a photoelectric conversion device. The production example is shown below.

First, as shown in (1) of FIG. 35, a concave portion having a step of a predetermined shape / dimension is formed on a metal substrate 111 of stainless steel or the like, and silicon or / and carbon ultrafine particles are adhered. Silicon or / and / or the like by the bias catalyst AHA treatment, the bias catalyst CVD method, etc.
Then, an n-type polycrystalline silicon film 7 is formed in the concave portion using the ultrafine particle layer of carbon having a diamond structure as a seed. The polycrystalline silicon film 7 is formed by the above-described multi-bias catalyst A
It may be formed by HA treatment, and is formed as a 100-200 nm thick n-type polycrystalline silicon film containing a single crystal or a mixture of tin or other group IV element (Ge, Pb) having a high crystallization rate and a large grain size. . The polycrystalline silicon film 7 is supplied with an n-type impurity such as phosphorus as PH ₃ or the like together with monosilane to contain, for example, 1 × 10 ¹⁷ to 1 × 10 ¹⁸ atoms / cc.

Next, as shown in FIG. 35 (2), tin or another group IV element (Ge, Pb) is formed on the polycrystalline silicon film 7 by using it as a seed by bias catalytic CVD or the like.
I-type polycrystalline silicon film 18 containing a single or a mixture of
Growing a p-type polycrystalline silicon film 181 containing a single or a mixture of 0, tin or other group IV elements (Ge, Pb),
A photoelectric conversion layer is formed.

For example, tin hydride (SnH ₄ ) is mixed with monosilane at an appropriate ratio by bias catalyst CVD to obtain i.
The large-diameter tin-containing polycrystalline silicon film 180 is
It is grown to a thickness of μm, and p-type impurity boron (such as B ₂ H ₆ ) and tin hydride (SnH ₄ ) are mixed in an appropriate ratio to monosilane, for example, 1 × 10 ¹⁷ to 1 × 10 ¹⁸ atoms.
/ Cc-containing p-type tin-containing polycrystalline silicon film 181 having a large grain size is formed to a thickness of 100 to 200 nm. At this time, tin or another group IV element (Ge, Pb) is contained in each film.
Alone or in a mixture, for example, tin with 1 × 10 ¹⁶ atoms /
cc or more, preferably 1 × 10 ¹⁸ to 1 × 10 ²⁰ atom
By containing s / cc, the crystal irregularity and stress existing at the crystal grain boundaries are reduced, so that the carrier mobility can be improved (this is because the n-type or p-type polycrystalline silicon films 7 and 181 are reduced). The same applies to the case of forming.

Further, the above-mentioned multi-bias catalyst AHA
Processing may be performed. For example, an n-type or p-type tin-containing polycrystalline silicon thin film of 20 to 50 n
After growing to a thickness of m, bias catalyst AHA treatment is performed,
An n-type or p-type tin-containing polycrystalline silicon thin film is grown to a thickness of 20 to 50 nm by bias catalyst CVD, and after bias catalyst AHA treatment, furthermore, n-type or p-type by bias catalyst CVD.
After growing a tin-containing polycrystalline silicon thin film of a thickness of 20 to 50 nm, a film may be formed by repeating the respective processes as necessary as a bias catalyst AHA process (this is an i-type polycrystalline The same applies to the case of the silicon film 180).
By this method, a tin-containing polycrystalline silicon film having a higher crystallization rate and a larger grain size can be formed. In addition, a high-speed film formation may be performed by increasing the supply amount of the source gas during the film formation.

Next, as shown in (3) of FIG. 35, the entire surface of the tin-containing polycrystalline silicon film having a high crystallization rate and a large grain size of the nip junction formed by the above-mentioned method is formed on the entire surface. Electrode 18
Form 2 For example, using a general-purpose sputtering technique, a 130 to 150 nm thick ITO
(Indium Tin Oxide) or IZO (Indium Zinc Oxid)
e) Form a transparent electrode 182 such as a film. Then, a comb-shaped electrode 183 of silver or the like is formed on a predetermined region of the metal electrode by a general-purpose sputtering technique using a metal mask in the range of 100 to 1.
It is formed to a thickness of 50 nm.

The above film does not necessarily need to contain tin or another group IV element, but can be manufactured in the same manner as described above. In addition to the above nip junction structure, a pin junction, a pn junction, an np
A structure such as bonding can be similarly manufactured.

The solar cell according to the present embodiment can form a photoelectric conversion thin film having high carrier mobility and high conversion efficiency by using a polycrystalline silicon film having a high crystallization rate and a large grain size according to the present invention. Since the surface texture structure and the back surface texture structure are formed, a photoelectric conversion thin film having a high light confinement effect and a high conversion efficiency can be formed. This is also
The present invention can be advantageously used not only for a solar cell but also for a thin-film photoelectric conversion device such as a photosensitive drum for electrophotography.

On the other hand, in a conventional photoelectric conversion device of this type, an amorphous carbon thin film is formed by RF plasma CVD, VHF plasma CVD, or the like, and ultrafine carbon particles are formed by plasma hydrogen treatment. A large grain polycrystalline silicon film is formed as a nucleus for crystal growth. An n-type polycrystalline silicon layer, an i-type polycrystalline silicon active layer and a p-type polycrystalline silicon layer are continuously formed, and an ITO film is formed on the entire surface. And finally form a comb-shaped electrode,
A thin-film polycrystalline silicon solar cell having a thickness of about 2 μm has been obtained.

However, this conventional method cannot avoid the following disadvantages. 1) Since a crystalline silicon-based thin film formed at a low temperature by RF plasma CVD, VHF plasma CVD, or the like has low energy, the chemical decomposition reaction of the source gas and the plasma hydrogen treatment are likely to be insufficient, and the crystal grain size is small. Because it ’s small
Mobility is small, and excessive current due to local electrical short or leakage is likely to occur due to the large number of grain boundaries or pinholes, and when deposited to a thickness of several μm required as a photoelectric conversion layer. The internal stress and strain of the film increase,
In the worst case, there is a problem that the film is peeled off.
As a result, the production yield and the reliability of the photoelectric conversion layer are significantly reduced, which is a great obstacle to the practical use of a photoelectric conversion device including the same. 2) Since the plasma CVD method such as the RF plasma CVD and the VHF plasma CVD has low energy, the utilization efficiency of the source gas is as low as 5 to 10%. For this reason, productivity is low and cost reduction is difficult.

The above-described embodiment of the present invention can be variously modified based on the technical idea of the present invention.

For example, the number of repetitions and each condition of the above-described bias catalyst CVD method and bias catalyst AHA treatment may be variously changed, and the material of the substrate and the like to be used is not limited to the above.

The present invention is suitable for an internal circuit such as a display unit, a peripheral drive circuit, a video signal processing circuit, and a MOSTFT such as a memory circuit. It is also possible to form passive regions such as resistance, capacitance (capacitance), wiring, inductance and the like with the polycrystalline silicon thin film according to the present invention.

[0307]

As described above, according to the present invention, when forming a polycrystalline semiconductor thin film on a substrate, a concave portion having a step of a predetermined shape / dimension is formed on the substrate, and at least the concave portion is formed in the concave portion. Ultra-fine particles made of silicon and / or carbon are attached, and hydrogen or a hydrogen-containing gas is brought into contact with the heated catalyst, and the hydrogen-based active species generated by the action of an electric field and / or a magnetic field lower than the glow discharge starting voltage. Cleaning is performed by acting on the ultrafine particles below, and the semiconductor material thin film is vapor-phase-grown by bias catalytic CVD or the like using carbon ultrafine particles of silicon or / and diamond structure as seeds. A remarkable function and effect as shown in (7) is obtained.

(1) A concave portion having a step having an appropriate shape and dimensions is formed at an arbitrary designated place on the substrate, and ultrafine particles such as silicon powder are adhered and dispersed therein, and the bias catalyst A
By the action of the hydrogen-based active species in the HA treatment, the amorphous component of the ultrafine particles can be selectively removed by etching, and furthermore, the oxide film and organic dirt on the surface of the ultrafine particles can be removed. As a nucleus (seed), a polycrystalline silicon film or the like having a large grain size with little variation can be formed in a designated region by bias or non-bias catalytic CVD, high-density bias catalytic CVD, or the like. E
Bias catalyst AH compared to hydrogen plasma treatment of CR discharge
The A treatment has a wide effective area of strong energy (can be set freely by the size of the catalyst body) and its variation is small, so that the productivity of large area substrate processing is high, and the versatility is high because it is inexpensive. .

(2) A high-performance and high-quality TFT can be formed at an arbitrary designated place on an insulating substrate, and the integrated circuit substrate can be freely formed. Then, if necessary, the surface in which the large-grain polycrystalline silicon film is embedded in the concave portion having a step having an appropriate size and shape in the TFT forming region on the insulating substrate is polished to obtain a flat large-grain. Since a substrate having a polycrystalline silicon film surface with a diameter can be obtained, high-performance, high-quality polycrystalline silicon semiconductor devices, electro-optical devices, and the like can be manufactured.

(3) This bias catalyst AHA treatment is performed under reduced pressure (for example, a hydrogen-based carrier gas of 10 to 50 Pa).
The hydrogen is converted to a high-temperature catalyst (800 to 2000
C., for example, 1500-2000 ° C. for tungsten), and a large amount of high-temperature hydrogen-based active species (hydrogen-based molecules,
When hydrogen atoms and activated hydrogen ions are generated and sprayed on silicon and / or carbon ultrafine particles formed on the substrate (the substrate temperature is particularly 300 to 400).
° C), sufficient thermal energy of a large amount of high-temperature hydrogen-based active species (hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions, etc.), and sufficient directional kinetic energy in the accelerating electric field or / and magnetic field by the electric field. , The temperature is locally increased, the organic substances and oxide film on the surface of the ultrafine particles are etched and removed by the action of hydrogen-based active species, and the ultrafine particles (cluster) are reliably stabilized. This can be effectively used as a nucleus (seed) for the next crystal growth of polycrystalline silicon or the like.

(4) The ultrafine particles obtained by the bias catalyst AHA treatment are used as seeds, and a semiconductor material thin film is formed thereon by bias catalyst CVD or high density under the action of an electric field and / or magnetic field lower than the glow discharge starting voltage. It is easy to grow (as a polycrystalline semiconductor thin film) in a state where it is easily polycrystallized by the bias catalyst CVD, and in particular, it is vapor-phase grown on the polycrystalline semiconductor thin film by the following bias catalyst AHA treatment and bias catalyst CVD. Since the crystallization of the silicon film or the like is promoted by using the polycrystalline semiconductor thin film as a seed, a polycrystalline semiconductor thin film having a high crystallization rate and high quality can be obtained. As a result, not only top gate type but also bottom gate type and dual gate type MOS
Even with TFTs, a high-crystallinity polycrystalline silicon thin film and the like with a high carrier (electron / hole) mobility and a high crystallization rate can be obtained. In addition, it is possible to manufacture a semiconductor thin film device and an electro-optical device having a high current density, and a highly efficient solar cell and the like.

(5) Conventional RF / VHF plasma CVD
Compared with the bias catalyst CVD, the source gas is efficiently thermally decomposed and catalyzed with high energy, so that the utilization efficiency of the source gas is high and the film forming rate is high, so that the productivity is high and the cost can be reduced.

(6) Since bias catalyst CVD and bias catalyst AHA processing can be performed without generating plasma, there is no damage due to plasma, and a simpler and less expensive apparatus can be realized as compared with plasma AHA processing.

(7) In the bias catalyst AHA treatment, even if the substrate temperature is lowered, the energy of the hydrogen-based active species is large, so that the target ultrafine particles of silicon and / or diamond-structured carbon are reliably and stably formed. Therefore, even when the substrate temperature is lowered to 300 to 400 ° C. in particular, the polycrystalline semiconductor thin film grows efficiently with the ultrafine particles as seeds, and thus is a large and inexpensive low strain point insulating substrate (glass substrate, glass substrate, Heat-resistant resin substrate) can be used, and the cost can be reduced in this respect as well.

[Brief description of the drawings]

FIG. 1 shows a MOSTFT according to a first embodiment of the present invention.
FIG. 4 is a cross-sectional view showing the manufacturing process in order of steps.

FIG. 2 is a cross-sectional view showing a manufacturing process in the order of steps.

FIG. 3 is a sectional view showing the manufacturing process in the order of steps.

FIG. 4 is a sectional view showing the manufacturing process in the order of steps.

FIG. 5 is a schematic cross-sectional view of one state of an apparatus for catalytic CVD and catalytic AHA treatment used in the production.

FIG. 6 is a schematic sectional view of the same device in another state.

FIG. 7 is a schematic sectional view showing the device in more detail.

FIG. 8 is a schematic cross-sectional view of a bias-type device.

FIG. 9 is a schematic cross-sectional view of another device using the bias method.

FIG. 10 is a schematic sectional view of another device according to the bias method.

FIG. 11 is a timing chart of a gas flow rate during processing using this apparatus.

FIG. 12 is a schematic view of a gas supply system of the apparatus.

FIG. 13 is a graph showing a Raman spectrum of a semiconductor film obtained by this process in comparison.

FIG. 14 is a graph showing the crystallization ratios of the semiconductor thin films in comparison.

FIG. 15 is a graph showing a comparison of the heavy metal concentration in the membrane depending on the purity of the catalyst and the support.

FIG. 16 is a sectional view illustrating the manufacturing process of the LCD according to the second embodiment of the present invention in the order of steps.

FIG. 17 is a cross-sectional view showing the manufacturing process in the order of steps.

FIG. 18 is a cross-sectional view showing the manufacturing process in the order of steps.

FIG. 19 is a cross-sectional view showing the manufacturing process in the order of steps.

FIG. 20 is a perspective view showing an overall schematic layout of the LCD.

FIG. 21 is an equivalent circuit diagram of the LCD.

FIG. 22 is a cross-sectional view showing another manufacturing process of the LCD in the order of steps.

FIG. 23 is a cross-sectional view showing the manufacturing process in the order of steps.

FIG. 24 is a sectional view showing various types of MOSTFTs of the LCD.

FIG. 25 is an equivalent circuit diagram (A) of an essential part of an organic EL display device according to a third embodiment of the present invention, an enlarged sectional view (B) of the essential part, and a sectional view (C) of a peripheral part of the pixel. It is.

FIG. 26 is a cross-sectional view showing a manufacturing process of the organic EL display device in the order of steps.

FIG. 27 is an equivalent circuit diagram (A) of a main part of another organic EL display device, an enlarged cross-sectional view (B) of the main part, and a cross-sectional view (C) of the periphery of the pixel.

FIG. 28 is a cross-sectional view showing a manufacturing process of the organic EL display device in the order of steps.

FIG. 29 is an equivalent circuit diagram (A) of an essential part of an FED according to a fourth embodiment of the present invention, an enlarged sectional view (B) of the essential part, and a schematic plan view (C) of the essential part.

FIG. 30 is a cross-sectional view showing a manufacturing process of the FED in the order of steps.

FIG. 31 is a cross-sectional view showing the manufacturing process in the order of steps.

FIG. 32 is an equivalent circuit diagram (A) of a main part of another FED,
It is the expanded sectional view (B) of the principal part, and the top view (C) of the principal part.

FIG. 33 is a cross-sectional view showing a manufacturing process of the FED in the order of steps.

FIG. 34 is a cross-sectional view showing the manufacturing process in the order of steps.

FIG. 35 is a sectional view illustrating the manufacturing process of the solar cell according to the fifth embodiment of the present invention in the order of steps.

[Explanation of symbols]

1, 61, 98, 111, 157: substrate, 7, 67: polycrystalline silicon thin film, 14, 67, 117: channel, 15, 75, 102, 105, 115: gate electrode, 8, 68, 103, 104 , 106, 118 ... gate insulating film, 20, 21, 80, 81, 120, 121 ...
n ⁺ type source or drain regions, 24, 25, 84, 8
5 ... p ⁺ type source or drain region, 27, 28, 8
6, 92, 130, 136, 137 ... insulating films, 29, 3
0, 87, 88, 89, 90, 91, 93, 97, 12
7, 128, 131 ... electrode, 40 ... source gas, 42 ... shower head, 44 ... film forming chamber, 45 ... susceptor, 46 ...
Catalyst, 47 ... Shutter, 48 ... Catalyst power, 49 ...
Bias power supply, 94, 96: alignment film, 95: liquid crystal, 99
... Color filter layer, 100A ... Silicon or carbon fine particles, 100B ... Clean silicon or carbon fine particles, 100 ', 140 ... Black mask layer,
132, 133 ... organic light emitting layer, 134, 135, 144
... Anode, 138, 141, 142, 171 ... Cathode, 15
0 ... Gate extraction electrode (gate line), 151 ... Shielding film, 152 ... Emitter, 153 ... N-type polycrystalline silicon film, 155 ... Back metal, 156 ... Phosphor, 15
8, 168: fine irregularities, 163: n-type polycrystalline diamond film, 180: i-type polycrystalline silicon film, 181 ... p
Type polycrystalline silicon film, 182 transparent electrode, 183 comb electrode, 190 concave portion, 200, 201 electrode, 20
2, 203: magnetic pole (permanent magnet), 204: electromagnet

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09F 9/30 365 G09F 9/30 365Z 5F052 9/35 9/35 5F110 H01J 9/02 H01J 9/02 B 5G435 H01L 21/20 H01L 21/20 21/336 27/08 331E 27/08 331 29/06 601N 29/06 601 29/66 E 29/66 H05B 33/10 29/786 33/12 B H05B 33/10 33/14 A 33/12 33/22 Z 33/14 H01L 29/78 618A 33/22 626C 618B 618G 627A 627G 627F 623Z 612B F-term (reference) 2H092 HA06 JA24 JA25 JA26 JB58 KA04 KA18 KB04 KB22 MA05 MA07 MA07 MA13 MA29 NA25 NA29 QA07 3K007 AB04 AB11 AB18 BA06 BB07 CA01 CB01 DA01 DB03 EB00 FA01 GA04 5C094 AA07 AA08 AA31 AA43 AA44 BA03 BA12 B A27 BA32 BA34 BA43 CA19 CA24 DA09 DA13 DB01 DB04 EA04 EA05 EA06 EA10 EB02 ED03 ED11 ED15 FA01 FA02 FB01 FB02 FB12 FB14 FB15 GB10 JA01 JA02 5F045 AA00 AB03 AB40 BB02 BB08 BB14 DP05 EB02 AC04 5F052 AA11 DA02 DA03 DB01 FA01 JA01 JA06 JA07 JA09 JA10 5F110 AA01 AA08 AA16 AA17 AA21 AA28 BB02 BB04 BB05 BB10 CC02 CC08 DD01 DD02 DD03 DD13 DD14 DD21 DD25 EE06 EE09 EE23 EE30 FF32 FF30 FF23 FF23 FF23 GG25 GG32 GG33 GG34 GG44 GG51 GG52 GG57 GG58 GG60 HJ01 HJ04 HJ12 HJ13 HJ23 HL03 HL06 HL07 HL23 HM15 NN03 NN04 NN23 NN24 NN25 NN35 NN44 NN46 NN54 NN72 NN73 Q12 AQ19 Q19 A19 BB GG12 HH12 HH13 HH14 KK05

Claims (24)

[Claims] When forming a polycrystalline semiconductor thin film on a substrate, a step of forming a concave portion having a step of an appropriate shape / dimension on the substrate, comprising at least silicon and / or carbon in the concave portion. A step of attaching ultrafine particles, and contacting hydrogen or a hydrogen-containing gas with the heated catalyst,
Cleaning by applying the hydrogen-based active species generated thereby to the ultrafine particles under the action of an electric field and / or a magnetic field that is equal to or lower than the glow discharge starting voltage; and removing at least a part of the raw material gas and hydrogen or the hydrogen-containing gas. The catalyst is decomposed catalytically by contact with the heated catalyst, and at least reactive species such as radicals and ions generated by the ultrafine particles are crystallized as a seed under the action of an electric field and / or a magnetic field lower than the glow discharge starting voltage. Growing the polycrystalline semiconductor thin film through a step of growing the semiconductor material thin film in a vapor phase. 2. A method of manufacturing a semiconductor device having a polycrystalline semiconductor thin film on a substrate, comprising: forming a concave portion having a step having an appropriate shape / dimension on the substrate; and forming silicon and / or silicon in at least the concave portion. Or attaching ultrafine particles made of carbon, and contacting hydrogen or a hydrogen-containing gas with the heated catalyst,
Cleaning by applying the hydrogen-based active species generated thereby to the ultrafine particles under the action of an electric field and / or a magnetic field that is equal to or lower than the glow discharge starting voltage; and removing at least a part of the raw material gas and hydrogen or the hydrogen-containing gas. The catalyst is decomposed catalytically by contact with the heated catalyst, and at least reactive species such as radicals and ions generated by the ultrafine particles are crystallized as a seed under the action of an electric field and / or a magnetic field lower than the glow discharge starting voltage. Growing the semiconductor material thin film in a vapor phase to obtain the polycrystalline semiconductor thin film. 3. The ultrafine particles are adhered from a paste state or a dispersion liquid state, and after vapor phase growth of the semiconductor material thin film, if necessary, the semiconductor material thin film is polished to flatten a surface including the thin film surface. The method according to claim 1 or 2, wherein 4. After the vapor-phase growth of the semiconductor material thin film, hydrogen or a hydrogen-containing gas is brought into contact with a heated catalyst to generate high-temperature hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions, etc. Annealing is performed by applying a hydrogen-based active species to the semiconductor material thin film under the action of an electric field and / or a magnetic field equal to or lower than the glow discharge starting voltage, and if necessary, vapor-phase growth of the same semiconductor material thin film as the semiconductor material thin film 3. The method according to claim 1, wherein the step and the annealing are repeated. 4. 5. The heated catalyst body is brought into contact with at least a part of a raw material gas and a hydrogen-based carrier gas to catalytically decompose, and reacting species such as radicals and ions generated by the glow discharge start voltage. After the semiconductor material thin film is deposited on the substrate heated under the action of the following electric field and / or magnetic field and the semiconductor material thin film is vapor-phase grown, the supply of the source gas is stopped, and the hydrogen is added to the heated catalyst. At least a part of the system carrier gas is brought into contact, and hydrogen-based active species such as high-temperature hydrogen-based molecules, hydrogen-based atoms, and activated hydrogen ions generated by the contact are subjected to the action of an electric field and / or a magnetic field equal to or lower than a glow discharge starting voltage. The method according to claim 4, wherein the annealing is performed by acting on the thin film of semiconductor material. 6. The method according to claim 5, wherein a supply amount of hydrogen or a hydrogen-containing gas during the annealing is set to be larger than a supply amount of hydrogen or a hydrogen-containing gas during the vapor phase growth. 7. The catalyst body is made of at least one material selected from the group consisting of tungsten, tria-containing tungsten, molybdenum, platinum, palladium, vanadium, silicon, alumina, a metal-adhered ceramic, and silicon carbide. A method according to claim 1 or 2, wherein the method comprises: 8. The purity of the catalyst and the support supporting the catalyst is 99.99 wt% (4N) or more, preferably 9% or more.
The method according to claim 1 or 2, wherein the content is 9.999 wt% (5N) or more. 9. The polycrystalline semiconductor thin film comprises a polycrystalline silicon thin film, a polycrystalline germanium thin film, a polycrystalline silicon-germanium film, a polycrystalline silicon carbide thin film, and the hydrogen or the hydrogen-containing gas is 3. The method according to claim 1, comprising hydrogen or a mixed gas of hydrogen and an inert gas. 10. The method according to claim 9, wherein said semiconductor material thin film contains at least one kind of Group IV element such as tin in an appropriate amount. 11. The DC voltage, AC voltage (high-frequency voltage and / or low-frequency voltage), or DC voltage and AC voltage (high-frequency voltage and / or
The method according to claim 1, wherein a voltage on which a low-frequency voltage is superimposed is applied. 12. The frequency of the high-frequency voltage is 1 to 100.
12. The method of claim 11, wherein the frequency of the low frequency voltage is less than 1 MHz. 13. A thin film insulated gate field effect transistor according to claim 1, wherein said polycrystalline semiconductor thin film forms a channel, a source and a drain region, a wiring, a resistor, a capacitor or an electron emitter. Way. 14. After forming the channel, source and drain regions, a glow discharge is applied to these regions if necessary using hydrogen-based active species generated by contacting hydrogen or a hydrogen-containing gas with a heated catalyst. The method according to claim 13, wherein the method operates under the action of an electric field and / or a magnetic field that is equal to or lower than the starting voltage. 15. The polycrystalline semiconductor thin film, wherein the crystal grain size is reduced from the gate insulating film side to the outside to increase the density, or the polycrystalline semiconductor thin film or the amorphous semiconductor thin film containing microcrystals is used as the polycrystalline semiconductor thin film. The method according to claim 1, wherein the conductive semiconductor thin film is coated. 16. The method according to claim 15, wherein the amorphous semiconductor thin film or the microcrystalline amorphous semiconductor thin film is removed to form source and drain electrodes in contact with the polycrystalline semiconductor thin film. 17. A silicon semiconductor device, a silicon semiconductor integrated circuit device, a silicon-germanium semiconductor device, a silicon-germanium semiconductor integrated circuit device, a compound semiconductor device, a compound semiconductor integrated circuit device, a silicon carbide semiconductor device, and a silicon carbide semiconductor integrated circuit device. , Liquid crystal display,
Manufacturing thin films for organic or inorganic electroluminescent displays, field emission displays (FED) devices, light emitting polymer displays, light emitting diode displays, CCD area / linear sensor devices, MOS sensor devices, solar cell devices. 3. The method according to 1 or 2. 18. A semiconductor device having an internal circuit and a peripheral circuit, a solid-state imaging device, an electro-optical device, and the like, in which a channel, a source and a drain region of a thin-film insulated gate field effect transistor constituting at least a part thereof are formed. The method according to claim 17, wherein the method is formed by the polycrystalline semiconductor thin film. 19. The method according to claim 18, further comprising a cathode or an anode connected to a drain or a source of the thin film insulated gate field effect transistor, respectively, below the organic or inorganic electroluminescent layer for each color. 20. The cathode also covers the active element including the thin-film insulated gate field effect transistor, or the cathode or anode is provided on each layer of the organic or inorganic electroluminescent layer for each color and on the entire surface between each layer. 20. The method according to claim 19, wherein the method comprises fabricating the device being deposited. 21. forming a black mask layer between the organic or inorganic electroluminescent layers for each color;
The method according to claim 19. 22. An emitter of a field emission display device is connected to the drain of the thin-film insulated gate field effect transistor via the polycrystalline semiconductor thin film and an n-type polycrystalline semiconductor grown on the polycrystalline semiconductor thin film. 19. The method according to claim 18, wherein the semiconductor layer is formed by a crystalline semiconductor film, a polycrystalline diamond film, a carbon thin film containing or not containing nitrogen, or a plurality of fine protrusion structures (for example, carbon nanotubes) formed on the surface of a carbon thin film containing or not containing nitrogen. The method described in. 23. The method according to claim 22, wherein a metal shielding film at a ground potential is formed on the active device including the thin film insulated gate field effect transistor. 24. The method according to claim 23, wherein the metal shielding film is formed of the same material as the gate extraction electrode of the field emission display device by the same process.