JP4644964B2 - Method for forming polycrystalline semiconductor thin film and method for manufacturing semiconductor device - Google Patents

Description

【００９５】
触媒ＡＨＡ処理：
触媒ＡＨＡ処理は、触媒ＣＶＤにおいて原料ガスを供給しない方法であり、具体的には、減圧下で、水素系キャリアガスをガス流量３００〜１０００ＳＣＣＭ、ガス圧１０〜５０Ｐａで供給して触媒体を所定温度（約１６００〜１８００℃、例えば約１７００℃）に加熱し、大量の高温の水素系活性種を発生させ、これらを基板上に形成した例えば多結晶性シリコン薄膜に吹き付ける。これにより、大量の高温の水素系活性種が有する熱エネルギーがそれらの膜に移動して、それらの膜温度を上昇させ、アモルファスシリコンや微結晶シリコンを含有するときには水素系活性種の還元作用によりアモルファス成分が選択的にエッチングされてこれらは多結晶化し、多結晶性シリコン薄膜は高結晶化して、大粒径の錫含有多結晶性シリコン膜化し、錫等のIV族元素の効果によりその結晶粒界に存在する不整及びストレスを低減し、高キャリア移動度及び高品質の錫含有多結晶性シリコン薄膜を形成することができる。
【００９６】
また、上記の水素系活性種は、多結晶性シリコン薄膜上又は膜内にシリコン酸化物が存在したときにこれと還元反応してＳｉＯ等を生成し、蒸発除去させるので、それらの膜上又は膜内のシリコン酸化物を減少／除去させることができ、高キャリア移動度及び高品質の多結晶性シリコン薄膜を形成できる。この触媒ＡＨＡ処理を後述のゲートチャンネル／ソース／ドレイン形成後に行うと、大量の高温の水素系活性種が有する熱エネルギーがそれらの膜に移動して、それらの膜温度を上昇させ、結晶化促進と同時にゲートチャンネル／ソース／ドレインに注入され、キャリア不純物（燐、ひ素、ボロン等）がイオン活性化される。
【００９７】
触媒ＣＶＤにより、窒化シリコン膜、酸化シリコン膜、錫含有多結晶シリコン薄膜を連続成膜する一例を示す。まず、上記の各膜を同一のチャンバで形成する場合は、水素系キャリアガスを常時供給し、触媒体を所定温度に加熱してスタンバイをしておき、次のように処理してよい。
【００９８】
モノシランにアンモニアを適当比率で混合して所定膜厚の窒化シリコン膜を形成し、前の原料ガスを十分に排出した後に、連続してモノシランとＨｅ希釈Ｏ₂を適当比率で混合して所定膜厚の酸化シリコン膜を形成し、前の原料ガス等を十分に排出した後に、モノシランとＳｎＨ₄を適当比率で混合して触媒ＣＶＤにより所定膜厚の錫含有多結晶性シリコン薄膜を形成する。成膜後は原料ガスをカットし、触媒体を問題ない温度まで冷却して水素系キャリアガスをカットする。なお、絶縁膜形成時の原料ガスは傾斜減少又は傾斜増加させて、傾斜接合の絶縁膜としてもよい。
【００９９】
或いは、それぞれ独立したチャンバで形成する場合は、各チャンバ内に水素系キャリアガスを常時供給し、触媒体を所定温度に加熱してスタンバイしておき、次のように処理してよい。Ａチャンバに移し、モノシランにアンモニアを適量比率で混合して所定膜厚の窒化シリコン膜を形成する。次にＢチャンバに移し、モノシランにＨｅ希釈Ｏ₂を適量比率で混合して酸化シリコン膜を形成する。次にＣチャンバに移し、モノシランとＳｎＨ₄を適量比率で混合して、錫含有の多結晶性シリコン薄膜を形成する。必要に応じて次にＢチャンバに移し、モノシランにＨｅ希釈Ｏ₂を適量比率で混合して触媒ＣＶＤにより多結晶性シリコン膜を形成する。成膜後は原料ガスをカットし、触媒体を問題ない温度まで冷却して水素系キャリアガスをカットする。この時に、それぞれのチャンバ内に水素系キャリアガスとそれぞれの原料ガスを常時供給して、スタンバイの状態にしておいてもよい。
【０１００】
ここで、各膜の成膜条件としては（但し、多結晶性シリコン薄膜の成膜条件は上述したので省略）、チャンバ内に水素系キャリアガス（水素、アルゴン＋水素、ヘリウム＋水素、ネオン＋水素等）を常時流し、流量と圧力、サセプタ温度を下記の所定の値に制御する。
チャンバ内圧力：１〜１５Ｐａ程度、例えば１０Ｐａ
サセプタ温度 ：３００〜４００℃
水素系キャリアガス流量（混合ガスの場合、水素は７０〜８０モル％以上）：５０〜１５０ＳＣＣＭ
【０１０１】
また、窒化シリコン膜は、次の条件で５０〜２００ｎｍの厚みに形成する。
水素（Ｈ₂）をキャリアガスとし、原料ガスとしてモノシラン（ＳｉＨ₄）に アンモニア（ＮＨ₃）を適量比率で混合して形成。
水素（Ｈ₂）流量：５０〜１５０ＳＣＣＭ、
ＳｉＨ₄流量：１〜２０ＳＣＣＭ、ＮＨ₃流量：５〜６０ＳＣＣＭ
【０１０２】
また、酸化シリコン膜は、次の条件で１００〜２００ｎｍの厚みに形成する。
水素（Ｈ₂）をキャリアガス、原料ガスとしてモノシラン（ＳｉＨ₄）にＨｅ 希釈Ｏ₂を適量比率で混合して形成。
水素（Ｈ₂）流量：５０〜１５０ＳＣＣＭ、
ＳｉＨ₄流量：１〜２０ＳＣＣＭ、Ｈｅ希釈Ｏ₂流量：１〜２ＳＣＣＭ
【０１０３】
上記のようにして、凹部１９０内において超微粒子１００Ｂをシードに多結晶性シリコン薄膜７を成長させた後、基板表面を光学研磨して、凹部以外の領域の多結晶性シリコン薄膜を除去してもよい。これによって錫含有又は非含有大粒径多結晶性シリコン薄膜が凹部内に埋め込まれた平坦な表面の基板が形成される。但し、この時には、光学研磨された錫含有又は非含有の大粒径多結晶性シリコン薄膜表面には、酸化膜及び有機汚れ被膜が形成されるので、触媒ＡＨＡ処理してクリーニングした後に、以降の処理を行うのがよい。
【０１０４】
そして次に、多結晶性シリコン薄膜７をソース、チャンネル及びドレイン領域とするＭＯＳＴＦＴの作製を行なう。
【０１０５】
即ち、図２の（５）に示すように、汎用フォトリソグラフィ及びエッチングにより多結晶性シリコン薄膜７をアイランド化した後、ｎＭＯＳＴＦＴ用のチャンネル領域の不純物濃度制御によるしきい値（Ｖ_th）の最適化のために、ｐＭＯＳＴＦＴ部をフォトレジスト９でマスクし、イオン注入又はイオンドーピングによりｐ型不純物イオン（例えばボロンイオン）１０を例えば５×１０¹¹ａｔｏｍｓ／ｃｍ²のドーズ量でドーピングし、１×１０¹⁷ａｔｏｍｓ／ｃｃのアクセプタ濃度に設定し、多結晶性シリコン薄膜７の導電型をｐ型化した多結晶性シリコン薄膜１１とする。
【０１０６】
次いで、図２の（６）に示すように、ｐＭＯＳＴＦＴ用のチャンネル領域の不純物濃度制御によるＶ_thの最適化のために、今度はｎＭＯＳＴＦＴ部をフォトレジスト１２でマスクし、イオン注入又はイオンドーピングによりｎ型不純物イオン（例えば燐イオン）１３を例えば１×１０¹²ａｔｏｍｓ／ｃｍ²のドーズ量でドーピングし、２×１０¹⁷ａｔｏｍｓ／ｃｃのドナー濃度に設定し、多結晶性シリコン薄膜７の導電型をｎ型化した多結晶性シリコン薄膜１４とする。尚、多結晶性シリコン薄膜７の上に酸化シリコン膜がある場合は除去して、しきい値（Ｖ_th）の最適化のイオン注入又はイオンドーピングしてもよい。
【０１０７】
次いで、図３の（７）に示すように、必要あれば結晶化促進と膜中の不純物の活性化のために上記の触媒ＡＨＡ処理を行なった後、触媒ＣＶＤ等によりゲート絶縁膜の酸化シリコン膜５０ｎｍ厚８を形成した後、ゲート電極材料としてのリンドープド多結晶シリコン膜１５を例えば２〜２０ＳＣＣＭのＰＨ₃及び２０ＳＣＣＭのモノシランの供給下での上記と同様の触媒ＣＶＤ法によって厚さ例えば４００ｎｍ厚に堆積させる。
【０１０８】
次いで、図３の（８）に示すように、フォトレジスト１６を所定パターンに形成し、これをマスクにしてリンドープド多結晶シリコン膜１５をゲート電極形状にパターニングし、更に、必要に応じてフォトレジスト１６の除去後に図３の（９）に示すように、例えば触媒ＣＶＤ等によりゲート電極用保護膜の酸化シリコン膜１７を２０〜３０ｎｍ厚に形成する。
【０１０９】
次いで、図３の（１０）に示すように、ｐＭＯＳＴＦＴ部をフォトレジスト１８でマスクし、イオン注入又はイオンドーピングによりｎ型不純物である例えば燐イオン１９を例えば１×１０¹⁵ａｔｏｍｓ／ｃｍ²のドーズ量でドーピングし、２×１０²⁰ａｔｏｍｓ／ｃｃのドナー濃度に設定し、ｎＭＯＳＴＦＴのｎ⁺型ソース領域２０及びドレイン領域２１をそれぞれ形成する。
【０１１０】
次いで、図４の（１１）に示すように、ｎＭＯＳＴＦＴ部をフォトレジスト２２でマスクし、イオン注入又はイオンドーピングによりｐ型不純物である例えばボロンイオン２３を例えば１×１０¹⁵ａｔｏｍｓ／ｃｍ²のドーズ量でドーピングし、２×１０²⁰ａｔｏｍｓ／ｃｃのアクセプタ濃度に設定し、ｐＭＯＳＴＦＴのｐ⁺型ソース領域２４及びドレイン領域２５をそれぞれ形成する。
【０１１１】
こうしてゲート、ソース及びドレインを形成するが、これらは上記したプロセス以外の方法で形成することが可能である。
【０１１２】
即ち、図１の（４）の工程後に、多結晶性シリコン薄膜７をｐＭＯＳＴＦＴとｎＭＯＳＴＦＴ領域にアイランド化し、ｐＭＯＳＴＦＴ領域にイオン注入又はイオンドーピングでｎ型不純物、例えば燐イオンを１×１０¹²ａｔｏｍｓ／ｃｍ²のドーズ量でドーピングし、２×１０¹⁷ａｔｏｍｓ／ｃｃのドナー濃度に設定し、ｎＭＯＳＴＦＴ領域にｐ型不純物、例えばボロンイオンを５×１０¹¹ａｔｏｍｓ／ｃｍ²のドーズ量でドーピングし、１×１０¹⁷ａｔｏｍｓ／ｃｃのアクセプタ濃度に設定し、各チャンネル領域の不純物濃度を制御し、Ｖ_thを最適化する。
【０１１３】
そして、次に、汎用フォトリソグラフィ技術により、フォトレジストマスクで各ソース／ドレイン領域を形成する。ｎＭＯＳＴＦＴの場合、イオン注入又はイオンドーピング法によりｎ型不純物、例えばひ素、燐イオンを１×１０¹⁵ａｔｏｍｓ／ｃｍ²のドーズ量でドーピングし、２×１０²⁰ａｔｏｍｓ／ｃｃのドナー濃度に設定し、ｐＭＯＳＴＦＴの場合、イオン注入又はイオンドーピング法によりｐ型不純物、例えばボロンイオンを１×１０¹⁵ａｔｏｍｓ／ｃｍ²のドーズ量でドーピングし、２×１０²⁰ａｔｏｍｓ／ｃｃのアクセプタ濃度に設定する。
【０１１４】
しかる後、必要あれば膜中の不純物の活性化のために触媒ＡＨＡ処理を行った後、ゲート絶縁膜として酸化シリコン膜を形成するが、必要に応じて連続して窒化シリコン膜と酸化シリコン膜を形成する。
【０１１５】
即ち、必要に応じて、触媒ＡＨＡ処理後に連続して触媒ＣＶＤ法により、水素系キャリアガスとモノシランにＨｅ希釈Ｏ₂を適量比率で混合して酸化シリコン膜８を２０〜３０ｎｍ厚に形成し、必要に応じて水素系キャリアガスとモノシランにＮＨ₃を適量比率で混合して窒化シリコン膜を１０〜２０ｎｍ厚に形成し、更に前記の条件で酸化シリコン膜を２０〜３０ｎｍ厚に形成する。この後は、上記と同様の汎用の触媒ＣＶＤ法、フォトリソグラフィ技術によりゲート電極を形成する。
【０１１６】
ゲート、ソース及びドレイン形成後は、図４の（１２）に示すように、全面に上記したと同様の触媒ＣＶＤ法等によって、水素系キャリアガス１５０ＳＣＣＭを共通として、１〜２ＳＣＣＭのヘリウムガス希釈のＯ₂、１５〜２０ＳＣＣＭのモノシラン供給下で酸化シリコン膜２６を例えば１００〜２００ｎｍ厚に、１〜２０ＳＣＣＭのＰＨ₃、１〜２ＳＣＣＭのヘリウム希釈のＯ₂、１５〜２０ＳＣＣＭのモノシラン供給下でフォスフィンシリケートガラス（ＰＳＧ）膜２７を３００〜４００ｎｍ厚に形成し、５０〜６０ＳＣＣＭのＮＨ₃、１５〜２０ＳＣＣＭのモノシラン供給下で窒化シリコン膜２８を例えば１００〜２００ｎｍ厚に形成し、積層絶縁膜を形成する。その後に、例えば約１０００℃で２０〜３０秒のＲＴＡ（Rapid Thermal Anneal）処理でイオン活性化させ、各領域に設定したキャリア不純物濃度とする。
【０１１７】
次いで、図４の（１３）に示すように、上記の絶縁膜の所定位置にコンタクト窓開けを行い、各コンタクトホールを含む全面に１％Ｓｉ入りアルミニウム等の電極材料をスパッタ法等で１μｍの厚みに堆積し、これをパターニングして、ｐＭＯＳＴＦＴ及びｎＭＯＳＴＦＴのそれぞれのソース又はドレイン電極２９（Ｓ又はＤ）とゲート取出し電極又は配線３０（Ｇ）を形成し、トップゲート型の各ＣＭＯＳＴＦＴを形成する。この後に、フォーミングガス中で４００℃、１ｈの水素化及びシンター処理する。
【０１１８】
なお、上記のゲート電極の形成に代えて、全面にＭｏ−Ｔａ合金等の耐熱性金属のスパッタ膜４００〜５００ｎｍ厚を形成し、汎用フォトリソグラフィ及びエッチング技術により、ｎＭＯＳＴＦＴ及びｐＭＯＳＴＦＴのゲート電極を形成してよい。
【０１１９】
上述したように、本実施の形態によれば、下記（ａ）〜（ｋ）の優れた作用効果を得ることができる。
【０１２０】
（ａ）基板の任意の指定場所に適当な形状及び寸法の段差を有する凹部を形成し、そこにシリコンパウダー等の超微粒子を付着分散させ、触媒ＡＨＡ処理での水素系活性種の作用により、この超微粒子のアモルファス成分を選択的にエッチング除去し、更にこの超微粒子の表面の酸化膜及び有機汚れ等を除去できるので、この超微粒子を結晶成長の核（シード）として触媒ＣＶＤ、高密度触媒ＣＶＤ法等により、ばらつきの少ない大きな粒径の多結晶性シリコン薄膜等を指定された領域に形成できる。
【０１２１】
（ｂ）絶縁性基板の任意の指定場所に高性能、高品質のＴＦＴを形成でき、その集積回路基板を自由に形成できる。
【０１２２】
（ｃ）必要に応じて、絶縁性基板上のＴＦＴ形成領域の適当な寸法及び形状の段差を有する凹部内に大粒径多結晶性シリコン薄膜が埋め込まれた面を研磨して、平坦な大粒径多結晶性シリコン薄膜面の基板が得られるので、高性能、高品質の多結晶性シリコン半導体装置、電気光学装置等の製造が可能となる。
【０１２３】
（ｄ）超微粒子を結晶成長のシードとして基板上に形成した多結晶性半導体薄膜に触媒ＡＨＡ処理を行うと、高温の水素系活性種等が有する大量の熱エネルギーがその膜等に移動して、その膜等の温度を局部的に上昇させる。これによって、アモルファス成分がエッチングされるため、アモルファスシリコンや微結晶シリコン薄膜は多結晶化し、多結晶性シリコン薄膜は高結晶率化して、大粒径で高結晶化率の多結晶性シリコン薄膜が形成され、キャリア移動度向上が図れる。また、この薄膜上に更に同様の半導体薄膜を気相成長させ、これらの触媒ＡＨＡ処理と気相成長とを繰り返すと多結晶性シリコン等は高結晶化して、高結晶化率、大粒径の多結晶性シリコン薄膜等を形成することができる。この結果、トップゲート型のみならず、ボトムゲート型、デュアルゲート型ＭＯＳＴＦＴでも、高いキャリア（電子／正孔）移動度の高結晶化率で大粒径の多結晶性シリコン薄膜等が得られるために、この高性能の多結晶性シリコン等の半導体薄膜を使用した高速、高電流密度の半導体装置、電気光学装置、更には高効率の太陽電池等の製造が可能となる。
【０１２４】
（ｅ）更に、多結晶性シリコン薄膜等の膜上又は膜内又は粒界にシリコン酸化物が存在したとき、これと反応してＳｉＯを形成して蒸発させるので、多結晶性シリコン薄膜内のシリコン酸化物を減少、除去させることができ、移動度の向上を図ることができる。
【０１２５】
（ｆ）触媒ＣＶＤ、高密度触媒ＣＶＤ法による成膜を行う場合、触媒体の種類及び温度、基板加熱温度、気相成膜条件、原料ガスの種類、添加するｎ又はｐ型不純物濃度等により、広範囲のｎ又はｐ型不純物濃度の多結晶性シリコン膜が容易に得られ、かつ更に触媒ＡＨＡ処理により大きな粒径で高結晶化率の多結晶性シリコン膜を形成できるので、高キャリア移動度でＶ_th調整が容易で低抵抗での高速動作が可能となる。
【０１２６】
（ｇ）触媒ＣＶＤ、高密度触媒ＣＶＤ法等により、錫又は他のIV族元素（鉛、ゲルマニウムなど）、例えば錫を１０¹⁸〜１０²⁰ａｔｏｍｓ／ｃｃ含有のアモルファス又は微結晶又は多結晶シリコン膜を形成し、その後に触媒ＡＨＡ処理で大きな粒径の多結晶性シリコン膜を形成できるので、錫含有の効果により多結晶性シリコン粒界に存在する結晶不整を減少させて内部応力を減少させ、大きな移動度多結晶性シリコン膜形成が可能となる。
【０１２７】
（ｈ）なお、プラズマＣＶＤによる成膜後に触媒ＡＨＡ処理を行う場合、プラズマＣＶＤでのアモルファスシリコン膜中に１０〜２０％含有する水素を触媒ＡＨＡ処理で減少／除去させ、大きな粒径の多結晶性シリコン膜を形成するので、大きなキャリア移動度の多結晶性シリコン膜の形成が可能となる。
【０１２８】
（ｉ）触媒ＣＶＤ及び触媒ＡＨＡ処理は、プラズマの発生なしに行えるので、プラズマによるダメージがなく、またプラズマＡＨＡ処理に比べ、シンプルで安価な装置を実現できる。
【０１２９】
（ｊ）触媒ＡＨＡ処理は基体温度を低温化しても上記水素系活性種のエネルギーが大きいために、目的とするシリコン及び／又はダイヤモンド構造のカーボンの超微粒子が確実に安定して得られることから、基体温度を特に３００〜４００℃と低温化しても、多結晶性半導体薄膜が超微粒子をシードに効率良く成長し、従って大型で安価な低歪点の絶縁基板（ガラス基板、耐熱性樹脂基板等）を使用でき、この点でもコストダウンが可能となる。
【０１３０】
（ｋ）ゲートチャンネル／ソース／ドレイン領域に添加されたｎ又はｐ型不純物の触媒ＡＨＡ処理でのイオン活性化に、条件によっては触媒ＣＶＤ装置が兼用できるので、設備投資の削減、生産性向上でのコストダウンが可能となる。
【０１３１】
第２の実施の形態
＜ＬＣＤの製造例１＞
本実施の形態は、高温プロセスによる多結晶性シリコンＭＯＳＴＦＴを用いたＬＣＤ（液晶表示装置）に本発明を適用したものであり、以下にその製造例を示す（この製造例は、後述する有機ＥＬやＦＥＤ等の表示装置等にも同様に適用可能である）。
【０１３２】
まず、図１２の（１）に示すように、画素部及び周辺回路部において、石英ガラス、結晶化ガラスなどの耐熱性絶縁基板６１（歪点約８００〜１１００℃、厚さ５０ミクロン〜数ｍｍ）の一主面に、上述した触媒ＣＶＤ法等により下地保護膜（図示せず）の形成後に上述したと同様にして凹部１９０（ここでは図示せず：以下、同様）を形成し、更にシリコン及び／又はカーボン超微粒子１００Ａを付着させる。
【０１３３】
次いで、図１２の（２）に示すように、上述の触媒ＡＨＡ処理により、超微粒子１００Ａをクリーニングし、有機物等が除去されたシリコン又は／及びダイヤモンド構造のカーボン超微粒子層１００Ｂに改質させる。
【０１３４】
次いで、図１２の（３）に示すように、上述した触媒ＣＶＤ法等によって、超微粒子層１００Ｂをシードに多結晶性シリコン薄膜６７を凹部内に例えば５０ｎｍ厚に形成する。この多結晶性シリコン薄膜は、上述のマルチ触媒ＡＨＡ処理により形成してよい。
【０１３５】
次いで、図１３の（４）に示すように、フォトレジストマスクを用いて多結晶性シリコン薄膜６７をパターニング（アイランド化）し、例えば、表示領域のｎＭＯＳＴＦＴ部と周辺駆動回路領域のｎＭＯＳＴＦＴ部及びｐＭＯＳＴＦＴ部などのトランジスタ、ダイオード等の能動素子、抵抗、容量、インダクタンス等の受動素子の活性層を形成する。
【０１３６】
次いで、トランジスタ活性層６７のチャンネル領域の不純物濃度制御によるＶ_thの最適化のために前記と同様のボロン又は燐等の所定の不純物のイオン注入を行なった後、図１３の（５）に示すように、例えば上記と同様の触媒ＣＶＤ法等によって多結晶性シリコン薄膜６７の表面に厚さ例えば５０ｎｍ厚のゲート絶縁膜用の酸化シリコン膜６８を形成する。触媒ＣＶＤ法等でゲート絶縁膜用の酸化シリコン膜６８を形成する場合、基板温度及び触媒体温度は上記したものと同様であるが、酸素ガス流量は１〜２ＳＣＣＭ、モノシランガス流量は１５〜２０ＳＣＣＭ、水素系キャリアガスは１５０ＳＣＣＭとしてよい。尚、チャンネル領域の不純物濃度制御する前又は後に、例えば、約１０００℃、３０分の高温熱酸化により、ゲート絶縁膜用の酸化シリコン膜６８を形成してもよい。
【０１３７】
次いで、図１３の（６）に示すように、ゲート電極及びゲートライン用材料として、例えばＭｏ−Ｔａ合金をスパッタリングで厚さ例えば４００ｎｍ厚に堆積させるか、或いは、リンドープド多結晶性シリコン膜を例えば水素系キャリアガス１５０ＳＣＣＭ、２〜２０ＳＣＣＭのフォスフィン（ＰＨ₃）及び２０ＳＣＣＭのモノシランガスの供給下での上記と同様の触媒ＣＶＤ法等によって厚さ例えば４００ｎｍ厚に堆積させる。そして、汎用フォトリソグラフィー及びエッチング技術により、ゲート電極材料層をゲート電極７５及びゲートラインの形状にパターニングする。尚、リンドープド多結晶性シリコン膜の場合は、触媒ＣＶＤ等により、その表面に保護用酸化シリコン膜（１０〜２０ｎｍ厚）を形成してもよい。
【０１３８】
次いで、図１４の（７）に示すように、ｐＭＯＳＴＦＴ部をフォトレジスト７８でマスクし、イオン注入又はイオンドーピング法によりｎ型不純物である例えばヒ素（又は燐）イオン７９を例えば１×１０¹⁵ａｔｏｍｓ／ｃｍ²のドーズ量でドーピングし、２×１０²⁰ａｔｏｍｓ／ｃｃのドナー濃度に設定し、ｎＭＯＳＴＦＴのｎ⁺型ソース領域８０及びドレイン領域８１をそれぞれ形成する。
【０１３９】
次いで、図１４の（８）に示すように、ｎＭＯＳＴＦＴ部をフォトレジスト８２でマスクし、イオン注入又はイオンドーピング法によりｐ型不純物である例えばボロンイオン８３を例えば１×１０¹⁵ａｔｏｍｓ／ｃｍ²のドーズ量でドーピングし、２×１０²⁰ａｔｏｍｓ／ｃｃのアクセプタ濃度に設定し、ｐＭＯＳＴＦＴのｐ⁺型ソース領域８４及びドレイン領域８５をそれぞれ形成する。
【０１４０】
次いで、図１４の（９）に示すように、全面に上記したと同様のバイアス触媒ＣＶＤ法等によって、水素系キャリアガス１５０〜２００ＳＣＣＭを共通として、１〜２ＳＣＣＭのＨｅ希釈Ｏ₂、１５〜２０ＳＣＣＭのモノシラン供給下で酸化シリコン膜を例えば１００〜２００ｎｍ厚に、更に、１〜２０ＳＣＣＭのフォスフィン（ＰＨ₃）、１〜２ＳＣＣＭのＨｅ希釈Ｏ₂、１５〜２０ＳＣＣＭのモノシラン供給下でフォスフィンシリケートガラス（ＰＳＧ）膜を３００〜４００ｎｍ厚に形成し、５０〜６０ＳＣＣＭのアンモニア（ＮＨ₃）、１５〜２０ＳＣＣＭのモノシラン供給下で窒化シリコン膜を例えば１００〜２００ｎｍ厚に形成する。これらの絶縁膜の積層によって層間絶縁膜８６を形成する。なお、このような層間絶縁膜は、上記とは別の通常の方法で形成してもよい。この後に、例えば９００℃、５分間のＮ₂中のアニール又は１０００℃、２０〜３０秒のＮ₂中のＲＴＡ処理によりイオン活性化し、各領域に設定したキャリア不純物濃度とする。
【０１４１】
次いで、図１５の（１０）に示すように、上記の絶縁膜８６の所定位置にコンタクト窓開けを行い、各コンタクトホールを含む全面にアルミニウムなどの電極材料をスパッタ法等で１μｍの厚みに堆積し、これをパターニングして、画素部のｎＭＯＳＴＦＴのソース電極８７及びデータライン、周辺回路部のｐＭＯＳＴＦＴ及びｎＭＯＳＴＦＴのソース電極８８、９０とドレイン電極８９、９１及び配線をそれぞれ形成する。この後に、例えばフォーミングガス中、４００℃、１ｈの水素化及びシンター処理して界面準位の改善とオーミックコンタクトの改善を図る。
【０１４２】
次いで、表面上に酸化シリコン膜等の層間絶縁膜９２をＣＶＤ法等で形成した後、図１５の（１１）に示すように、画素部のｎＭＯＳＴＦＴドレイン領域において層間絶縁膜９２及び８６にコンタクトホールを開け、例えば１３０〜１５０ｎｍ厚のＩＴＯ（Indium tin oxide：インジウム酸化物にスズをドープした透明電極材料）膜を真空蒸着法等で全面に堆積させ、パターニングしてｎＭＯＳＴＦＴのドレイン領域８１に接続された透明画素電極９３を形成する。この後に、例えばフォーミングガス中、２５０℃、１ｈ、アニールして、ＩＴＯ膜とのオーミックコンタクトを改善し、ＩＴＯの透明度を向上させる。
【０１４３】
こうしてアクティブマトリクス基板（以後、ＴＦＴ基板と称する）を作製し、透過型のＬＣＤを作製することができる。この透過型ＬＣＤは、図１５（１２）に示すように、透明画素電極９３上に配向膜９４、液晶９５、配向膜９６、透明電極９７、対向基板９８が積層された構造からなっている。
【０１４４】
なお、上記した工程は、反射型のＬＣＤの製造にも同様に適用可能である。図２０（Ａ）には、この反射型のＬＣＤの一例が示されているが、図中の１０１は粗面化された絶縁膜９２上に被着された反射膜であり、ＭＯＳＴＦＴのドレインと接続されている。
【０１４５】
このＬＣＤの液晶セルを面面組立で作製する場合（２インチサイズ以上の中／大型液晶パネルに適している。）、まずＴＦＴ基板６１と、全面ベタのＩＴＯ（Indium Tin Oxide）電極９７を設けた対向基板９８の素子形成面に、ポリイミド配向膜９４、９６を形成する。このポリイミド配向膜はロールコート、スピンコート等により５０〜１００ｎｍ厚に形成し、１８０℃／２ｈで硬化キュアする。
【０１４６】
次いで、ＴＦＴ基板６１と対向基板９８をラビング、又は光配向処理する。ラビングバフ材にはコットンやレーヨン等があるが、バフかす（ゴミ）やリタデーション等の面からはコットンの方が安定している。光配向は非接触の線型偏光紫外線照射による液晶分子の配向技術である。なお、配向には、ラビング以外にも、偏光又は非偏光を斜め入射させることによって高分子配向膜を形成することができる（このような高分子化合物は、例えばアゾベンゼンを有するポリメチルメタクリレート系高分子等がある）。
【０１４７】
次いで、洗浄後に、ＴＦＴ基板６１側にはコモン剤塗布、対向基板９８側にはシール剤塗布する。ラビングバフかす除去のために、水、又はＩＰＡ（イソプロピルアルコール）洗浄する。コモン剤は導電性フィラーを含有したアクリル、又はエポキシアクリレート、又はエポキシ系接着剤であってよく、シール剤はアクリル、又はエポキシアクリレート、又はエポキシ系接着剤であってよい。加熱硬化、紫外線照射硬化、紫外線照射硬化＋加熱硬化のいずれも使用できるが、重ね合せの精度と作業性からは紫外線照射硬化＋加熱硬化タイプが良い。
【０１４８】
次いで、対向基板９８側に所定のギャップを得るためのスペーサを散布し、ＴＦＴ基板６１と所定の位置で重ね合せる。対向基板９８側のアライメントマークとＴＦＴ基板６１側のアライメントマークとを精度よく合わせた後に、紫外線照射してシール剤を仮硬化させ、その後に一括して加熱硬化する。
【０１４９】
次いで、スクライブブレークして、ＴＦＴ基板６１と対向基板９８を重ね合せた単個の液晶パネルを作成する。
【０１５０】
次いで、液晶９５を両基板６１−９８間のギャップ内に注入し、注入口を紫外線接着剤で封止後に、ＩＰＡ洗浄する。液晶の種類は何れでも良いが、例えばネマティック液晶を用いる高速応答のＴＮ（ツイストネマティック）モードが一般的である。
【０１５１】
次いで、加熱急冷処理して、液晶９５を配向させる。
【０１５２】
次いで、ＴＦＴ基板６１のパネル電極取り出し部にフレキシブル配線を異方性導電膜の熱圧着で接続し、更に対向基板９８に偏光板を貼合わせる。
【０１５３】
また、液晶パネルの面単組立の場合（２インチサイズ以下の小型液晶パネルに適している。）、上記と同様、ＴＦＴ基板６１と対向基板９８の素子形成面に、ポリイミド配向膜９４、９６を形成し、両基板をラビング、又は非接触の線型偏光紫外線光の配向処理する。
【０１５４】
次いで、ＴＦＴ基板６１と対向基板９８をダイシング又はスクライブブレークで単個に分割し、水又はＩＰＡ洗浄する。ＴＦＴ基板６１にはコモン剤塗布、対向基板９８にはスペーサ含有のシール剤塗布し、両基板を重ね合せる。これ以降のプロセスは上記に準ずる。
【０１５５】
上記したＬＣＤにおいて、対向基板９８はＣＦ（カラーフィルタ）基板であって、カラーフィルタ層（図示せず）をＩＴＯ電極９７下に設けたものである。対向基板９８側からの入射光は例えば反射膜９３で効率良く反射されて対向基板９８側から出射してよい。
【０１５６】
他方、ＴＦＴ基板６１として、ＴＦＴ基板６１にカラーフィルタを設けたオンチップカラーフィルタ（ＯＣＣＦ）構造のＴＦＴ基板とするときには、対向基板９８にはＩＴＯ電極がベタ付け（又はブラックマスク付きのＩＴＯ電極がベタ付け）される。
【０１５７】
透過型ＬＣＤの場合、次のようにしてオンチップカラーフィルタ（ＯＣＣＦ）構造とオンチップブラック（ＯＣＢ）構造を作製することができる。
【０１５８】
即ち、図１５の（１３）に示すように、フォスフィンシリケートガラス／酸化シリコンの絶縁膜８６のドレイン部も窓開けしてドレイン電極用のアルミニウム埋込み層を形成した後、Ｒ、Ｇ、Ｂの各色を各セグメント毎に顔料分散したフォトレジスト９９を所定厚さ（１〜１．５μｍ）で形成した後、汎用フォトリソグラフィ技術で所定位置（各画素部）のみを残すパターニングで各カラーフィルタ層９９（Ｒ）、９９（Ｇ）、９９（Ｂ）を形成する（オンチップカラーフィルタ構造）。この際、ドレイン部の窓開けも行う。なお、不透明なセラミック基板や低透過率のガラス及び耐熱性樹脂基板は使用できない。
【０１５９】
次いで、表示用ＴＦＴのドレインに連通するコンタクトホールに、カラーフィルタ層上にかけてブラックマスク層となる遮光層１００’を金属のパターニングで形成する。例えば、スパッタ法により、モリブデンを２００〜２５０ｎｍ厚で成膜し、表示用ＭＯＳＴＦＴを覆って遮光する所定の形状にパターニングする（オンチップブラック構造）。
【０１６０】
次いで、透明樹脂の平坦化膜９２を形成し、更にこの平坦化膜に設けたスルーホールにＩＴＯ透明電極９３を遮光層１００’に接続するように形成する。
【０１６１】
このように、表示アレイ部上に、カラーフィルタ９９やブラックマスク１００’を作り込むことにより、液晶表示パネルの開口率を改善し、またバックライトも含めたディスプレイモジュールの低消費電力化が実現する。
【０１６２】
図１６は、上述のトップゲート型ＭＯＳＴＦＴを組み込んで駆動回路一体型に構成したアクティブマトリクス液晶表示装置（ＬＣＤ）の全体を概略的に示すものである。このアクティブマトリクスＬＣＤは、主基板６１（これはアクティブマトリクス基板を構成する。）と対向基板９８とをスペーサ（図示せず）を介して貼り合わせたフラットパネル構造からなり、両基板６１−９８間に液晶（ここでは図示せず）が封入されている。主基板６１の表面には、マトリクス状に配列した画素電極９３と、この画素電極を駆動するスイッチング素子とからなる表示部、及びこの表示部に接続される周辺駆動回路部とが設けられている。
【０１６３】
表示部のスイッチング素子は、上記したｎＭＯＳ又はｐＭＯＳ又はＣＭＯＳでＬＤＤ構造のトップゲート型ＭＯＳＴＦＴで構成される。また、周辺駆動回路部にも、回路要素として、上記したトップゲート型ＭＯＳＴＦＴのＣＭＯＳ又はｎＭＯＳ又はｐＭＯＳＴＦＴ又はこれらの混在が形成されている。なお、一方の周辺駆動回路部はデータ信号を供給して各画素のＴＦＴを水平ライン毎に駆動する水平駆動回路であり、また他方の周辺駆動回路部は各画素のＴＦＴのゲートを走査ライン毎に駆動する垂直駆動回路であり、通常は表示部の両辺にそれぞれ設けられる。これらの駆動回路は、点順次アナログ方式、線順次デジタル方式のいずれも構成できる。
【０１６４】
図１７に示すように、直交するゲートバスラインとデータバスラインの交差部に上記のＭＯＳＴＦＴが配置され、このＭＯＳＴＦＴを介して液晶容量（Ｃ_LC）に画像情報を書き込み、次の情報がくるまで電荷を保持する。この場合、ＴＦＴのチャンネル抵抗だけで保持させるには十分ではないので、それを補うため液晶容量と並列に蓄積容量（補助容量）（Ｃ_S）を付加し、リーク電流による液晶電圧の低下を補ってよい。こうしたＬＣＤ用ＭＯＳＴＦＴでは、画素部（表示部）に使用するＴＦＴの特性と周辺駆動回路に使用するＴＦＴの特性とでは要求性能が異なり、特に画素部のＴＦＴではオフ電流の制御、オン電流の確保が重要な問題となる。このため、表示部には、後述の如きＬＤＤ構造のＴＦＴを設けることによって、ゲート−ドレイン間に電界がかかりにくい構造としてチャンネル領域にかかる実効的な電界を低減させ、オフ電流を低減し、特性の変化も小さくできる。しかし、プロセス的には複雑になり、素子サイズも大きくなり、かつオン電流が低下するなどの問題も発生するため、それぞれの使用目的に合わせた最適設計が必要である。
【０１６５】
なお、使用可能な液晶としては、ＴＮ液晶（アクティブマトリクス駆動のＴＮモード用に用いられるネマチック液晶）をはじめ、ＳＴＮ（スーパーツイステッドネマチック）、ＧＨ（ゲスト・ホスト）、ＰＣ（フェーズ・チェンジ）、ＦＬＣ（強誘電性液晶）、ＡＦＬＣ（反強誘電性液晶）、ＰＤＬＣ（ポリマー分散型液晶）等の各種モード用の液晶を採用してよい。
【０１６６】
＜ＬＣＤの製造例２＞
次に、本実施の形態による低温プロセスの多結晶性シリコンＭＯＳＴＦＴを用いたＬＣＤ（液晶表示装置）の製造例を示す（この製造例は後述する有機ＥＬやＦＥＤの表示装置等にも同様に適用可能である）。
【０１６７】
この製造例では、上述の製造例１において、基板６１としてアルミノけい酸ガラス、ホウケイ酸ガラス等を使用し、図１２の（１）、（２）及び（３）の工程を同様に行う。即ち、基板６１上に触媒ＣＶＤと触媒ＡＨＡ処理により錫含有（又は非含有）の多結晶性シリコン薄膜６７を形成してこれをアイランド化し、表示領域のｎＭＯＳＴＦＴ部と周辺駆動回路領域のｎＭＯＳＴＦＴ部及びｐＭＯＳＴＦＴ部を形成する。この場合、同時に、ダイオード、コンデンサ、インダクタンス、抵抗等の領域を形成する。
【０１６８】
次いで、図１８の（１）に示すように（但し、下地保護膜及び凹部１９０は図示省略：以下、同様）、各ＭＯＳＴＦＴゲートチャンネル領域のキャリア不純物濃度を制御してＶ_thを最適化するために、表示領域のｎＭＯＳＴＦＴ部と周辺駆動回路領域のｎＭＯＳＴＦＴ部をフォトレジスト８２でカバーし、周辺駆動回路領域のｐＭＯＳＴＦＴ部に、イオン注入又はイオンドーピング法により例えば燐、ひ素等のｎ型不純物７９を１×１０¹²ａｔｏｍｓ／ｃｍ²のドーズ量でドーピングし、２×１０¹⁷ａｔｏｍｓ／ｃｃのドナー濃度に設定し、更に図１８の（２）に示すように、周辺駆動回路領域のｐＭＯＳＴＦＴ部をフォトレジスト８２でカバーし、表示領域のｎＭＯＳＴＦＴ部と周辺駆動回路領域のｎＭＯＳＴＦＴ部に、イオン注入又はイオンドーピング法により例えばボロン等のｐ型不純物８３を５×１０¹¹ａｔｏｍｓ／ｃｍ²のドーズ量でドーピングし、１×１０¹⁷ａｔｏｍｓ／ｃｃのアクセプタ濃度を設定する。
【０１６９】
次いで、図１８の（３）に示すように、表示領域のｎＭＯＳＴＦＴ部にｎ^-型のＬＤＤ（Lightly Doped Drain）部を形成するために、汎用フォトリソグラフィ技術により、表示領域のｎＭＯＳＴＦＴのゲート部と周辺駆動領域のｐＭＯＳＴＦＴ及びｎＭＯＳＴＦＴ全部をフォトレジスト８２で覆い、露出した表示領域のｎＭＯＳＴＦＴのソース／ドレイン領域に、イオン注入又はイオンドーピング法により例えば燐等のｎ型不純物７９を１×１０¹³ａｔｏｍｓ／ｃｍ²のドーズ量でドーピングし、２×１０¹⁸ａｔｏｍｓ／ｃｃのドナー濃度に設定して、ｎ^-型のＬＤＤ部を形成する。
【０１７０】
次いで、図１９の（４）に示すように、表示領域のｎＭＯＳＴＦＴ部及び周辺駆動回路領域のｎＭＯＳＴＦＴ部の全部をフォトレジスト８２でカバーし、周辺駆動回路領域のｐＭＯＳＴＦＴ部のゲート部をフォトレジスト８２でカバーして露出したソース、ドレイン領域に、イオン注入又はイオンドーピング法により例えばボロン等のｐ型不純物８３を１×１０¹⁵ａｔｏｍｓ／ｃｍ²のドーズ量でドーピングし、２×１０²⁰ａｔｏｍｓ／ｃｃのアクセプタ濃度に設定してｐ⁺型のソース部８４、ドレイン部８５を形成する。
【０１７１】
次いで、図１９の（５）に示すように、周辺駆動回路領域のｐＭＯＳＴＦＴ部をフォトレジスト８２でカバーし、表示領域のｎＭＯＳＴＦＴのゲート及びＬＤＤ部と周辺駆動回路領域のｎＭＯＳＴＦＴ部のゲート部をフォトレジスト８２でカバーし、露出した表示領域及び周辺駆動領域のｎＭＯＳＴＦＴのソース、ドレイン領域に、イオン注入又はイオンドーピング法により例えば燐、ひ素等のｎ型不純物７９を１×１０¹⁵ａｔｏｍｓ／ｃｍ²のドーズ量でイオンドーピングし、２×１０²⁰ａｔｏｍｓ／ｃｃのドナー濃度に設定し、ｎ⁺型のソース部８０、ドレイン部８１を形成する。
【０１７２】
次いで、図１９の（６）に示すように、プラズマＣＶＤ、ＴＥＯＳ系プラズマＣＶＤ、触媒ＣＶＤ法等により、ゲート絶縁膜６８として、酸化シリコン膜４０〜５０ｎｍ厚、窒化シリコン膜１０〜２０ｎｍ厚、酸化シリコン膜４０〜５０ｎｍ厚の積層膜を形成する。そして、ハロゲンランプ等でのＲＴＡ処理を例えば、約１０００℃、１０〜３０秒行い、添加したｎ又はｐ型不純物をイオン活性化することにより、設定した各々のキャリア不純物濃度を得る。
【０１７３】
この後に、全面に４００〜５００ｎｍ厚の１％Ｓｉ入りアルミニウムスパッタ膜を形成し、汎用フォトリソグラフィ及びエッチングにより、全ＴＦＴのゲート電極７５及びゲートラインを形成する。更にこの後に、プラズマＣＶＤ、触媒ＣＶＤ法等により、酸化シリコン膜１００〜２００ｎｍ厚、フォスフィンシリケートガラス（ＰＳＧ）膜２００〜３００ｎｍ厚、窒化シリコン膜１００〜２００ｎｍ厚の積層膜からなる絶縁膜８６を形成する。
【０１７４】
次いで、汎用フォトリソグラフィ及びエッチング技術により、周辺駆動回路の全ＴＦＴ部のソース／ドレイン部及び表示用ｎＭＯＳＴＦＴ部のソース部の窓開けを行う。窒化シリコン膜はＣＦ₄のプラズマエッチング、酸化シリコン膜及びリンシリケートガラス膜はフッ酸系エッチング液でエッチング処理する。
【０１７５】
次いで、図１９の（７）に示すように、全面に４００〜５００ｎｍ厚の１％Ｓｉ入りアルミニウムスパッタ膜を形成し、汎用フォトリソグラフィ及びエッチング技術により、周辺駆動回路の全ＴＦＴのソース、ドレイン電極８８、８９、９０、９１を形成すると同時に、表示用ｎＭＯＳＴＦＴのソース電極８７及びデータラインを形成する。
【０１７６】
次いで、図示は省略したが、プラズマＣＶＤ、触媒ＣＶＤ法等により、酸化シリコン膜１００〜２００ｎｍ厚、フォスフィンシリケートガラス膜（ＰＳＧ膜）２００〜３００ｎｍ厚、窒化シリコン膜１００〜３００ｎｍ厚を層間絶縁膜（上述の９２）として全面に形成し、フォーミングガス中で約４００℃、１時間、水素化及びシンター処理する。その後に、表示用ｎＭＯＳＴＦＴのドレイン部コンタクト用窓開けを行う。
【０１７７】
ここで、ＬＣＤが透過型の場合は、画素開口部の酸化シリコン膜、フォスフィンシリケートガラス膜及び窒化シリコン膜は除去し、また反射型の場合は、画素開口部等の酸化シリコン膜、フォスフィンシリケートガラス膜及び窒化シリコン膜は除去する必要はない（これは上述又は後述のＬＣＤにおいても同様である）。
【０１７８】
透過型の場合、図１５の（１０）と同様に、全面に、スピンコート等で２〜３μｍ厚のアクリル系透明樹脂平坦化膜を形成し、汎用フォトリソグラフィ及びエッチング技術により、表示用ＴＦＴのドレイン側の透明樹脂窓開けを形成した後、全面に１３０〜１５０ｎｍ厚のＩＴＯスパッタ膜を形成し、汎用フォトリソグラフィ及びエッチング技術により、表示用ｎＭＯＳＴＦＴのドレイン部とコンタクトしたＩＴＯ透明電極を形成する。更に熱処理（フォーミングガス中で２００〜２５０℃、１時間）により、コンタクト抵抗の低減化とＩＴＯ透明度向上を図る。
【０１７９】
反射型の場合は、全面に、スピンコート等で２〜３μｍ厚の感光性樹脂膜を形成し、汎用フォトリソグラフィ及びエッチング技術により、少なくとも画素部に凹凸形状パターンを形成し、リフローさせて凹凸反射下部を形成する。同時に、表示用ｎＭＯＳＴＦＴのドレイン部の感光性樹脂窓開けを形成する。しかる後、全面に、３００〜４００ｎｍ厚の１％Ｓｉ入りアルミニウムスパッタ膜を形成し、汎用フォトリソグラフィ及びエッチング技術により、画素部以外のアルミニウム膜を除去し、表示用ｎＭＯＳＴＦＴのドレイン電極と接続した凹凸形状のアルミニウム反射部を形成する。その後に、フォーミングガス中で３００℃、１時間シンター処理する。
【０１８０】
なお、上記において、ｎＭＯＳＴＦＴのソース、ドレインを形成した後に、触媒ＡＨＡ処理すれば、多結晶性シリコン薄膜の膜温度を局部的に上昇させ、結晶化が更に促進され、高移動度及び高品質の多結晶性シリコン薄膜を形成する。同時に、高温の水素分子、水素原子、活性化水素イオン等が有する熱エネルギーが膜に移動して、膜温度を局部的に上昇させるので、ゲートチャンネル／ソース／ドレイン領域に注入された燐、ひ素、ボロンイオン等が活性化される。
【０１８１】
なお、プラズマＣＶＤ法によってアモルファスシリコン含有微結晶シリコン薄膜を形成した場合、膜中に１０〜２０％の水素が含有されるが、触媒ＡＨＡ処理によって減少／除去することができて多結晶性シリコン膜化し、高移動度及び高品質の多結晶性シリコン薄膜を形成する。又、多結晶性シリコン薄膜上又は膜内にシリコン酸化物が存在するときに、これと還元反応してＳｉＯを生成し、蒸発除去させるので、それらの膜上又は膜内のシリコン酸化物を減少／除去させることができ、高移動度及び高品質の多結晶性シリコン薄膜を形成できる。
【０１８２】
＜ボトムゲート型又はデュアルゲート型ＭＯＳＴＦＴ＞
ＭＯＳＴＦＴを組み込んだ例えばＬＣＤにおいて、上述のトップゲート型に代えて、ボトムゲート型、デュアルゲート型のＭＯＳＴＦＴからなる透過型ＬＣＤを製造した例を述べる（但し、反射型ＬＣＤも同様である）。
【０１８３】
図２０（Ｂ）に示すように、表示部及び周辺部にはボトムゲート型のｎＭＯＳＴＦＴが設けられ、或いは図２０（Ｃ）に示すように、表示部及び周辺部にはデュアルゲート型のｎＭＯＳＴＦＴがそれぞれ設けられている。これらのボトムゲート型、デュアルゲート型ＭＯＳＴＦＴのうち、特にデュアルゲート型の場合には上下のゲート部によって駆動能力が向上し、高速スイッチングに適し、また上下のゲート部のいずれかを選択的に用いて場合に応じてトップゲート型又はボトムゲート型として動作させることもできる。
【０１８４】
図２０（Ｂ）のボトムゲート型ＭＯＳＴＦＴにおいて、図中の１０２はＭｏ−Ｔａ合金等のゲート電極であり、１０３は窒化シリコン膜及び１０４は酸化シリコン膜であってゲート絶縁膜を形成し、このゲート絶縁膜上にはトップゲート型ＭＯＳＴＦＴと同様の多結晶性シリコン薄膜６７を用いたチャンネル領域等が形成されている。また、図２０（Ｃ）のデュアルゲート型ＭＯＳＴＦＴにおいて、下部ゲート部はボトムゲート型ＭＯＳＴＦＴと同様であるが、上部ゲート部は、ゲート絶縁膜１０６を酸化シリコン膜と窒化シリコン膜、必要に応じて更に酸化シリコン膜の積層膜で形成し、この上に上部ゲート電極７５を設けている。
【０１８５】
＜ボトムゲート型ＭＯＳＴＦＴの製造＞
まず、ガラス基板６１上の全面に、Ｍｏ−Ｔａ合金のスパッタ膜を３００〜４００ｎｍ厚に形成し、これを汎用フォトリソグラフィ及びエッチング技術により２０〜４５度のテーパーエッチングし、少なくともＴＦＴ形成領域に、ボトムゲート電極１０２を形成すると同時に、ゲートラインを形成する。ガラス材質の使い分けは上述したトップゲート型に準ずる。
【０１８６】
次いで、プラズマＣＶＤ、ＴＥＯＳ系プラズマＣＶＤ、触媒ＣＶＤ、減圧ＣＶＤ等の気相成長法により、ゲート絶縁膜及び保護膜用の窒化シリコン膜１０３及び酸化シリコン膜１０４を形成し、少なくともＴＦＴ形成領域内に適当な形状／寸法の段差を有する凹部を形成し、シリコン又は／及びカーボン超微粒子を付着させ、触媒ＡＨＡ処理によりクリーニングされたシリコン又は／及びダイヤモンド構造のカーボン超微粒子を形成する。これをシードに触媒ＣＶＤ等により錫含有又は非含有の多結晶性シリコン薄膜を凹部内に形成し、更に触媒ＡＨＡ処理を繰り返して高結晶化率の大粒径多結晶性シリコン薄膜６７を形成する。これらの気相成膜条件は上述したトップゲート型に準ずる。なお、ボトムゲート絶縁膜及び保護膜用の窒化シリコン膜はガラス基板からのＮａイオンストッパ作用を期待して設けるものであるが、合成石英ガラスの場合は不要である。
【０１８７】
これ以降のプロセスは上述したものに準ずるが、すでに上記の工程でゲート電極を形成しているので、ここではゲート電極用多結晶シリコン膜形成、ゲート電極形成、ゲート多結晶シリコン酸化工程は不要である。
【０１８８】
そして次に、上述したと同様に、ｐＭＯＳＴＦＴ、ｎＭＯＳＴＦＴ領域をアイランド化し（但し、一方の領域のみを図示：以下、同様）、各チャンネル領域のキャリア不純物濃度を制御してＶ_thを最適化するために、イオン注入又はイオンドーピング法によりｎ型又はｐ型不純物を適当量混入した後、更に、各ＭＯＳＴＦＴのソース、ドレイン領域を形成するためにイオン注入又はイオンドーピング法によりｎ型又はｐ型不純物を適当量混入させる。この後に、不純物活性化のために触媒ＡＨＡ処理又はＲＴＡ処理のアニールをする。
【０１８９】
これ以降のプロセスは、上述したものに準ずる。
【０１９０】
＜デュアルゲート型ＭＯＳＴＦＴの製造＞
上記のボトムゲート型と同様に、ボトムゲート電極１０２、ゲート絶縁膜１０３及び１０４、シリコン又は／及びダイヤモンド構造のカーボン超微粒子をシードとして凹部内に形成した高結晶化率で大粒径の多結晶性シリコン薄膜６７をそれぞれ形成する。但し、ボトムゲート絶縁膜及び保護膜用の窒化シリコン膜１０３はガラス基板からのＮａイオンストッパ作用を期待して設けるものであるが、合成石英ガラスの場合は不要である。
【０１９１】
そして次に、上述したと同様に、ｐＭＯＳＴＦＴ、ｎＭＯＳＴＦＴ領域をアイランド化し、各チャンネル領域のキャリア不純物濃度を制御してＶ_thを最適化するために、イオン注入又はイオンドーピング法によりｎ型又はｐ型不純物を適当量混入した後、更に、各ＭＯＳＴＦＴのソース、ドレイン領域を形成するためにイオン注入又はイオンドーピング法によりｎ型又はｐ型不純物を適当量混入させる。
【０１９２】
次いで、トップゲート絶縁膜１０６用の酸化シリコン膜及び窒化シリコン膜、必要に応じて更に酸化シリコン膜の積層膜を成膜する。気相成長条件は上述したトップゲート型に準ずる。尚、この後に不純物活性化のためにＲＴＡ処理のアニールをする。
【０１９３】
この後に、全面に４００〜５００ｎｍ厚の１％Ｓｉ入りアルミニウムスパッタ膜を形成し、汎用フォトリグラフィ及びエッチング技術により、全ＴＦＴのトップゲート電極７５及びゲートラインを形成する。この後に、プラズマＣＶＤ、触媒ＣＶＤ法等により、酸化シリコン膜１００〜２００ｎｍ厚、フォスフィンシリケートガラス（ＰＳＧ）膜２００〜３００ｎｍ厚等からなる絶縁膜８６を形成する。次に、汎用フォトリソグラフィ及びエッチング技術により、周辺駆動回路の全ＭＯＳＴＦＴのソース、ドレイン電極部、さらに表示部ｎＭＯＳＴＦＴのソース電極部の窓開けを行う。
【０１９４】
次いで、全面に４００〜５００ｎｍ厚の１％Ｓｉ入りアルミニウムスパッタ膜を形成し、汎用フォトリソグラフィ及びエッチング技術により、ソース及びドレインの各アルミニウム電極８７、８８及び８９、ソースライン及び配線等を形成する。次いで、プラズマＣＶＤ、触媒ＣＶＤ法等により、酸化シリコン膜１００〜２００ｎｍ厚、フォスフィンシリケートガラス膜（ＰＳＧ膜）２００〜３００ｎｍ厚、窒化シリコン膜１００〜３００ｎｍ厚を層間絶縁膜９２として全面に形成し、フォーミングガス中で約４００℃、１時間、水素化及びシンター処理する。その後に、表示用ｎＭＯＳＴＦＴのドレイン部コンタクト用窓開けを行い、ＩＴＯ等の画素電極９３を形成する。
【０１９５】
上述したように、本実施の形態によれば、上述の第１の実施の形態と同様に、触媒ＣＶＤと触媒ＡＨＡ処理により、ＬＣＤの表示部及び周辺駆動回路部のＭＯＳＴＦＴのゲートチャンネル、ソース及びドレイン領域となる、高キャリア移動度でＶ_th調整が容易であり、低抵抗での高速動作が可能な高結晶化率で大粒径の多結晶性シリコン薄膜を形成することができる。この多結晶性シリコン薄膜によるトップゲート、ボトムゲート又はデュアルゲート型ＭＯＳＴＦＴを用いた液晶表示装置は、高いスイッチング特性と低リーク電流のＬＤＤ構造を有する表示部と、高い駆動能力のＣＭＯＳ、又はｎＭＯＳ、又はｐＭＯＳ周辺駆動回路、映像信号処理回路、メモリー回路等を一体化した構成が可能となり、高画質、高精細、狭額縁、高効率、安価な液晶パネルの実現が可能である。
【０１９６】
そして、低温（３００〜４００℃）で形成できるので、安価で、大型化が容易な低歪点ガラスを採用でき、コストダウンが可能となる。しかも、アレイ部上にカラーフィルタやブラックマスクを作り込むことにより、液晶表示パネルの開口率、輝度等を改善し、カラーフィルタ基板を不要とし、生産性改善等によるコストダウンが実現する。
【０１９７】
第３の実施の形態
本実施の形態は、本発明を有機又は無機のエレクトロルミネセンス（ＥＬ）表示装置、例えば有機ＥＬ表示装置に適用したものである。以下にその構造例と製造例を示す。
【０１９８】
＜有機ＥＬ素子の構造例Ｉ＞
図２１（Ａ）、（Ｂ）に示すように、この構造例Ｉによれば、ガラス等の基板１１１上に、本発明に基づいて上述した方法で段差１９０内に形成された高結晶化率、大粒径の多結晶性シリコン薄膜によって、スイッチング用ＭＯＳＴＦＴ１と電流駆動用ＭＯＳＴＦＴ２のゲートチャンネル１１７、ソース領域１２０及びドレイン領域１２１が形成されている。そして、ゲート絶縁膜１１８上にゲート電極１１５、ソース及びドレイン領域上にソース電極１２７及びドレイン電極１２８、１３１が形成されている。ＭＯＳＴＦＴ１のドレインとＭＯＳＴＦＴ２のゲートとはドレイン電極１２８を介して接続されていると共に、ＭＯＳＴＦＴ２のソース電極１２７との間に絶縁膜１３６を介してキャパシタＣが形成され、かつ、ＭＯＳＴＦＴ２のドレイン電極１３１は有機ＥＬ素子の陰極１３８にまで延設されている。
【０１９９】
各ＭＯＳＴＦＴは絶縁膜１３０で覆われ、この絶縁膜上には陰極を覆うように有機ＥＬ素子の例えば緑色有機発光層１３２（又は青色有機発光層１３３、更には図示しない赤色有機発光層）が形成され、この有機発光層を覆うように陽極（１層目）１３４が形成され、更に共通の陽極（２層目）１３５が全面に形成されている。なお、ＣＭＯＳＴＦＴからなる周辺駆動回路、映像信号処理回路、メモリー回路等の製法は、上述した液晶表示装置に準ずる（以下、同様）。
【０２００】
この構造の有機ＥＬ表示部は、有機ＥＬ発光層が電流駆動用ＭＯＳＴＦＴ２のドレインに接続され、陰極（Ｌｉ−Ａｌ、Ｍｇ−Ａｇなど）１３８がガラス等の基板１１１の面に被着され、陽極（ＩＴＯ膜など）１３４、１３５がその上部に設けられており、従って、上面発光１３６’となる。また、陰極がＭＯＳＴＦＴ上を覆っている場合は発光面積が大きくなり、このときには陰極が遮光膜となり、発光光等がＭＯＳＴＦＴに入射しないのでリーク電流発生がなく、ＴＦＴ特性の悪化がない。
【０２０１】
また、各画素部周辺に図２１（Ｃ）のようにブラックマスク部（クロム、二酸化クロム等）１４０を形成すれば、光漏れ（クロストーク等）を防止し、コントラストの向上が図れる。
【０２０２】
なお、画素表示部に緑色、青色、赤色の３色発光層を使用する方法、色変換層を使用する方法、白色発光層にカラーフィルターを使用する方法のいずれでも、良好なフルカラーのＥＬ表示装置が実現でき、また、各色発光材料である高分子化合物のスピンコーティング法、又は金属錯体の真空加熱蒸着法においても、長寿命、高精度、高品質、高信頼性のフルカラー有機ＥＬ部を生産性良く作成できるので、コストダウンが可能となる（以下、同様）。
【０２０３】
従来のこの種の有機ＥＬは、アモルファス又は微結晶シリコンＭＯＳＴＦＴを用いているので、Ｖ_thが変動しても電流値が変わり易く、画質に変動が起き易い。しかも、移動度が小さいため、高速応答でドライブできる電流にも限界があり、またｐチャンネルの形成が困難であり、小規模なＣＭＯＳ回路構成さえも困難である。そこで、比較的大面積化が容易であって高信頼性でキャリア移動度も高く、ＣＭＯＳ回路構成も可能な多結晶性シリコンＭＯＳＴＦＴを用いることが望ましいが、従来の多結晶シリコン膜は、１）アモルファスシリコン膜を３００〜４００℃のプラズマＣＶＤ法で成膜し、エキシマレーザーアニールして多結晶シリコン膜化する。２）アモルファスシリコン膜を４３０〜５００℃のＬＰＣＶＤ法で成膜し、窒素ガス中で６００℃／５〜２０ｈｒと８５０℃／０．５〜３ｈｒで固相成長させて多結晶シリコン膜化する。
【０２０４】
しかし、１）は、高価なエキシマレーザー装置の採用、エキシマレーザーの不安定性起因のＴＦＴ特性むらと品質問題、生産性低下等によるコストアップとなる。２）は、６００℃以上、１５〜２０ｈｒｓの長時間の熱処理のために、汎用ガラス基板を使用できず、石英ガラス採用となるので、コストアップとなる。また、フルカラー有機ＥＬ層では、その微細加工プロセスにおいて、電極の酸化や有機ＥＬ材料が酸素、水分にさらされたり、加熱で構造変化（溶解あるいは再結晶化）して劣化しやすいので、各色発光領域を高精度に形成するのが難しい。
【０２０５】
次に、本実施の形態による有機ＥＬ素子の製造プロセスを説明すると、まず、図２２の（１）に示すように、上述した工程を経て多結晶性シリコン薄膜からなるソース領域１２０、チャンネル領域１１７及びドレイン領域１２１を形成した後、ゲート絶縁膜１１８を形成し、この上にＭＯＳＴＦＴ１、２のゲート電極１１５をＭｏ−Ｔａ合金等のスパッタリング成膜とフォトリソグラフィ及びエッチング技術により形成し、またＭＯＳＴＦＴ１のゲート電極に接続されるゲートラインをスパッタリング成膜とフォトリソグラフィ及びエッチング技術により（以下、同様）形成する。そして、オーバーコート膜（酸化シリコン等）１３７を触媒ＣＶＤ等の気相成長法により（以下、同様）形成後、１０００℃、１０〜３０秒等のＲＴＡ処理によりイオン活性化する。そしてＭＯＳＴＦＴ２のソース電極１２７及びアースラインを形成し、更にオーバーコート膜（酸化シリコン／窒化シリコン積層膜など）１３６を形成する。
【０２０６】
次いで、図２２の（２）に示すように、ＭＯＳＴＦＴ１のソース／ドレイン部、ＭＯＳＴＦＴ２のゲート部の窓開けを行った後、図２２の（３）に示すように、１％Ｓｉ入りＡｌのスパッタリングと汎用フォトリソグラフィ及びエッチング技術によりＭＯＳＴＦＴ１のドレイン電極とＭＯＳＴＦＴ２のゲート電極を１％Ｓｉ入りＡｌ配線１２８で接続し、同時にＭＯＳＴＦＴ１のソース電極と、この電極に接続される１％Ｓｉ入りＡｌからなるソースラインを形成する。そして、オーバーコート膜（酸化シリコン／フォスフィンシリケートガラス／窒化シリコン積層膜など）１３０を形成し、ＭＯＳＴＦＴ２のドレイン部の窓開けを行い、ＭＯＳＴＦＴ２のドレイン部と接続した発光部の陰極１３８を形成する。
【０２０７】
次いで、図２２の（４）に示すように、有機発光層１３２等及び陽極１３４、１３５を形成する。
【０２０８】
なお、上記において、緑色（Ｇ）発光有機ＥＬ層、青色（Ｂ）発光有機ＥＬ層、赤色（Ｒ）発光有機ＥＬ層はそれぞれ、１００〜２００ｎｍ厚に形成するが、これらの有機ＥＬ層は、低分子化合物の場合は真空加熱蒸着法で形成され、高分子化合物の場合はディッピングコーティング、スピンコーティングなどの塗布法やインクジェット法によりＲ、Ｇ、Ｂ発光ポリマーを配列する方法が用いられる。金属錯体の場合は、昇華可能な材料を真空加熱蒸着法で形成される。
【０２０９】
有機ＥＬ層には、単層型、二層型、三層型等があるが、ここでは低分子化合物の三層型の例を示す。
単層型；陽極／バイポーラー発光層／陰極、
二層型；陽極／ホール輸送層／電子輸送性発光層／陰極、又は陽極／ホール輸送性発光層／電子輸送層／陰極、
三層型；陽極／ホール輸送層／発光層／電子輸送層／陰極、又は陽極／ホール輸送性発光層／キャリアブロック層／電子輸送性発光層／陰極
【０２１０】
なお、図２１（Ｂ）の素子において、有機発光層の代わりに公知の発光ポリマーを用いれば、パッシブマトリクス又はアクティブマトリクス駆動の発光ポリマー表示装置（ＬＥＰＤ）として構成することができる（以下、同様）。
【０２１１】
＜有機ＥＬ素子の構造例II＞
図２３（Ａ）、（Ｂ）に示すように、この構造例IIによれば、ガラス等の基板１１１上に、上記の構造例Ｉと同様に、本発明に基づいて上述した方法で形成された高結晶化率、大粒径の多結晶性シリコン薄膜によって、スイッチング用ＭＯＳＴＦＴ１と電流駆動用ＭＯＳＴＦＴ２のゲートチャンネル１１７、ソース領域１２０及びドレイン領域１２１が形成されている。そして、ゲート絶縁膜１１８上にゲート電極１１５、ソース及びドレイン領域上にソース電極１２７及びドレイン電極１２８、１３１が形成されている。ＭＯＳＴＦＴ１のドレインとＭＯＳＴＦＴ２のゲートとはドレイン電極１２８を介して接続されていると共に、ＭＯＳＴＦＴ２のドレイン電極１３１との間に絶縁膜１３６を介してキャパシタＣが形成され、かつ、ＭＯＳＴＦＴ２のソース電極１２７は有機ＥＬ素子の陽極１４４にまで延設されている。
【０２１２】
各ＭＯＳＴＦＴは絶縁膜１３０で覆われ、この絶縁膜上には陽極を覆うように有機ＥＬ素子の例えば緑色有機発光層１３２（又は青色有機発光層１３３、更には図示しない赤色有機発光層）が形成され、この有機発光層を覆うように陰極（１層目）１４１が形成され、更に共通の陰極（２層目）１４２が全面に形成されている。
【０２１３】
この構造の有機ＥＬ表示部は、有機ＥＬ発光層が電流駆動用ＭＯＳＴＦＴ２のソースに接続され、ガラス等の基板１１１の面に被着された陽極１４４を覆うように有機ＥＬ発光層を形成し、その有機ＥＬ発光層を覆うように陰極１４１を形成し、全面に陰極１４２を形成しており、従って、下面発光１３６’となる。また、陰極が有機ＥＬ発光層間及びＭＯＳＴＦＴ上を覆っている。即ち、全面に、例えば緑色発光有機ＥＬ層を真空加熱蒸着法等により形成した後に、緑色発光有機ＥＬ部をフォトリソグラフィ及びドライエッチングで形成し、連続して同様に、青色、赤色発光有機ＥＬ部を形成し、最後に全面に陰極（電子注入層）１４１をマグネシウム：銀合金又はアルミニウム：リチウム合金により形成する。この全面に更に形成した陰極（電子注入層）で密封するので、外部から有機ＥＬ層間に湿気が侵入することを特に全面被着の陰極１４２により防止して湿気に弱い有機ＥＬ層の劣化や電極の酸化を防止し、長寿命、高品質、高信頼性が可能となる（これは、図２１の構造例Ｉでも陽極で全面被覆されているため、同様である）。また、陰極１４１及び１４２により放熱効果が高まるので、発熱による薄膜の構造変化（融解又は再結晶化）が低減し、長寿命、高品質、高信頼性が可能となる。しかも、これによって、高精度、高品質のフルカラーの有機ＥＬ層を生産性良く作成できるので、コストダウンが可能となる。
【０２１４】
また、各画素部周辺に図２３（Ｃ）のようにブラックマスク部（クロム、二酸化クロム等）１４０を形成すれば、光漏れ（クロストーク等）を防止し、コントラストの向上が図れる。なお、このブラックマスク部１４０は、酸化シリコン膜１４３（これはゲート絶縁膜１１８と同時に同一材料で形成してよい。）によって覆われている。
【０２１５】
次に、この有機ＥＬ素子の製造プロセスを説明すると、まず、図２４の（１）に示すように、上述した工程を経て高結晶化率で大粒径の多結晶性シリコン薄膜からなるソース領域１２０、チャンネル領域１１７及びドレイン領域１２１を形成した後、バイアス触媒ＣＶＤ等の気相成長法によりゲート絶縁膜１１８を形成し、Ｍｏ−Ｔａ合金等のスパッタリング成膜及び汎用フォトリソグラフィ及びエッチング技術によりこの上にＭＯＳＴＦＴ１、２のゲート電極１１５を形成し、またＭｏ−Ｔａ合金等のスパッタリング成膜及び汎用フォトリソグラフィ及びエッチング技術によりＭＯＳＴＦＴ１のゲート電極に接続されるゲートラインを形成する。そして、バイアス触媒ＣＶＤ等の気相成長法によりオーバーコート膜（酸化シリコン等）１３７を形成後、１０００℃、１０〜３０秒のＲＴＡ処理によりイオン活性化する。そして、１％Ｓｉ入りＡｌのスパッタリング成膜及び汎用フォトリソグラフィ及びエッチング技術によりＭＯＳＴＦＴ２のドレイン電極１３１及びＶ_ddラインを形成し、更に触媒ＣＶＤ等の気相成長法によりオーバーコート膜（酸化シリコン／窒化シリコン積層膜等）１３６を形成する。
【０２１６】
次いで、図２４の（２）に示すように、汎用フォトリソグラフィ及びエッチング技術によりＭＯＳＴＦＴ１のソース／ドレイン部、ＭＯＳＴＦＴ２のゲート部の窓開けを行った後、図２４の（３）に示すように、１％Ｓｉ入りＡｌのスパッタリング成膜及び汎用フォトリソグラフィ及びエッチング技術により、ＭＯＳＴＦＴ１のドレインとＭＯＳＴＦＴ２のゲートを１％Ｓｉ入りＡｌ配線１２８で接続し、同時にＭＯＳＴＦＴ１のソースに接続される１％Ｓｉ入りＡｌからなるソースラインを形成する。そして、オーバーコート膜（酸化シリコン／フォスフィンシリケートガラス／窒化シリコン積層膜など）１３０を形成し、汎用フォトリソグラフィ及びエッチング技術によりＭＯＳＴＦＴ２のソース部の窓開けを行い、ＩＴＯ等のスパッタリング及び汎用フォトリソグラフィ及びエッチング技術によりＭＯＳＴＦＴ２のソース部と接続した発光部の陽極１４４を形成する。
【０２１７】
次いで、図２４の（４）に示すように、上記のように有機発光層１３２等及び陰極１４１、１４２を形成する。
【０２１８】
なお、以下に述べる有機ＥＬの各層の構成材料や形成方法は図２３の例に適用されるが、図２１の例にも同様に適用されてよい。
【０２１９】
緑色発光有機ＥＬ層に低分子化合物を用いる場合は、ガラス基板上の陽極（ホール注入層）である電流駆動用ＭＯＳＴＦＴのソース部とコンタクトしたＩＴＯ透明電極上に、連続した真空加熱蒸着法により形成する。
１）ホール輸送層は、アミン系化合物（例えば、トリアリールアミン誘導体、アリールアミンオリゴマー、芳香族第三アミン等）等
２）発光層は、緑色発光材料であるトリス（８−ヒドロキシキシリノ）Ａｌ錯体（Ａｌｑ）等
３）電子輸送層は、１，３，４−オキサジアゾール誘導体（ＯＸＤ）、１，２，４−トリアゾール誘導体（ＴＡＺ）等
４）陰極である電子注入層は、４ｅＶ以下の仕事関数を有する材料で作られるのが好ましい。
例えば、１０：１（原子比）のマグネシウム：銀合金の１０〜３０ｎｍ厚
アルミニウム：リチウム（濃度は０．５〜１％）合金の１０〜３０ｎｍ厚
ここで、銀は有機界面との接着性を増すためにマグネシウム中に１〜１０原子％添加され、リチウムは安定化のためにアルミニウム中に濃度は０．５〜１％添加される。
【０２２０】
緑色画素部を形成するには、緑色画素部をフォトレジストでマスクし、ＣＣｌ₄ガスのプラズマエッチングにより陰極である電子注入層のアルミニウム：リチウム合金を除去し、連続して電子輸送層、発光層、ホール輸送層の低分子系化合物及びフォトレジストを酸素プラズマエッチングで除去し、緑色画素部を形成する。この時に、フォトレジストの下にはアルミニウム：リチウム合金があるので、フォトレジストがエッチングされても問題ない。又、この時に、電子輸送層、発光層、ホール輸送層の低分子系化合物層は、ホール注入層のＩＴＯ透明電極よりも大きい面積とし、後工程で全面に形成する陰極１４２の電子注入層（マグネシウム：銀合金等）と電気的ショートしないようにする。
【０２２１】
次に、青色発光有機ＥＬ層を低分子化合物で形成する場合は、ガラス基板上の陽極（ホール注入層）である電流駆動用ＴＦＴのソース部とコンタクトしたＩＴＯ透明電極上に、連続して真空加熱蒸着により形成する。
１）ホール輸送層は、アミン系化合物（例えば、トリアリールアミン誘導体、アリールアミンオリゴマー、芳香族第三アミン等）等
２）発光層は、青色発光材料であるＤＴＶＢｉのようなジスチリル誘導体等
３）電子輸送層は、１，３，４−オキサジアゾール誘導体（ＴＡＺ）、１，２，４−トリアゾール誘導体（ＴＡＺ）等
４）陰極である電子注入層は、４ｅＶ以下の仕事関数を有する材料で作られるのが好ましい。
例えば、１０：１（原子比）のマグネシウム：銀合金の１０〜３０ｎｍ厚
アルミニウム：リチウム（濃度は０．５〜１％）合金の１０〜３０ｎｍ厚
ここで、銀は有機界面との接着性を増すためにマグネシウム中に１〜１０原子％添加され、リチウムは安定化のためにアルミニウム中に濃度は０．５〜１％添加される。
【０２２２】
青色画素部を形成するには、青色画素部をフォトレジストでマスクし、ＣＣｌ₄ガスのプラズマエッチングで陰極である電子注入層のアルミニウム：リチウム合金を除去し、連続して電子輸送層、発光層、ホール輸送層の低分子系化合物及びフォトレジストを酸素プラズマエッチングで除去し、青色画素部を形成する。この時に、フォトレジストの下にはアルミニウム：リチウム合金があるので、フォトレジストがエッチングされても問題ない。又、この時に、電子輸送層、発光層、ホール輸送層の低分子系化合物層は、ホール注入層のＩＴＯ透明電極よりも大きい面積とし、後工程で全面に形成する陰極１４２の電子注入層（マグネシウム：銀合金等）と電気的ショートしないようにする。
【０２２３】
また、赤色発光有機ＥＬ層を低分子化合物で形成する場合は、ガラス基板上の陽極（ホール注入層）である電流駆動用ＴＦＴのソース部とコンタクトしたＩＴＯ透明電極上に、連続して真空加熱蒸着により形成する。
１）ホール輸送層は、アミン系化合物（例えば、トリアリールアミン誘導体、アリールアミンオリゴマー、芳香族第三アミン等）等
２）発光層は、赤色発光材料であるＥｕ（Ｅｕ(ＤＢＭ)₃（Ｐｈｅｎ））等
３）電子輸送層は、１，３，４−オキサジアゾール誘導体（ＯＸＤ）、１，２
，４−トリアゾール誘導体（ＴＡＺ）等
４）陰極である電子注入層は、４ｅＶ以下の仕事関数を有する材料で作られるのが好ましい。
例えば、１０：１（原子比）のマグネシウム：銀合金の１０〜３０ｎｍ厚
アルミニウム：リチウム（濃度は０．５〜１％）合金の１０〜３０ｎｍ厚
銀は有機界面との接着性を増すためにマグネシウム中に１〜１０原子％添加され、リチウムは安定化のためにアルミニウム中に濃度は０．５〜１％添加される。
【０２２４】
赤色画素部を形成するには、赤色画素部をフォトレジストでマスクし、ＣＣｌ₄ガスのプラズマエッチングで陰極である電子注入層のアルミニウム：リチウム合金を除去し、連続して電子輸送層、発光層、ホール輸送層の低分子系化合物及びフォトレジストを酸素プラズマエッチングで除去し、赤色画素部を形成する。この時に、フォトレジストの下にはアルミニウム：リチウム合金があるので、フォトレジストがエッチングされても問題ない。又、この時に、電子輸送層、発光層、ホール輸送層の低分子系化合物層は、ホール注入層のＩＴＯ透明電極よりも大きい面積とし、後工程で全面に形成する陰極１４２の電子注入層（マグネシウム：銀合金等）と電気的ショートしないようにする。この後に、共通の陰極１４２の電子注入層（マグネシウム：銀合金等）を全面に形成する。
【０２２５】
陰極である電子注入層は、４ｅＶ以下の仕事関数を有する材料で作られるのが好ましい。例えば、１０：１（原子比）のマグネシウム：銀合金の１０〜３０ｎｍ厚、又はアルミニウム：リチウム（濃度は０．５〜１％）合金の１０〜３０ｎｍ厚とする。ここで、銀は有機界面との接着性を増すためにマグネシウム中に１〜１０原子％添加され、リチウムは安定化のためにアルミニウム中に濃度は０．５〜１％添加される。なお、スパッタリングで成膜してもよい。
【０２２６】
第４の実施の形態
本実施の形態は、本発明を電界放出型（フィールドエミッション）ディスプレイ装置（ＦＥＤ：Field Emission Display）に適用したものである。以下にその構造例と製造例を示す。
【０２２７】
＜ＦＥＤの構造例Ｉ＞
図２５（Ａ）、（Ｂ）、（Ｃ）に示すように、この構造例Ｉによれば、ガラス等の基板１１１上に、本発明に基づいて上述した方法で段差内に形成された高結晶化率、大粒径の多結晶性シリコン薄膜によって、スイッチング用ＭＯＳＴＦＴ１と電流駆動用ＭＯＳＴＦＴ２のゲートチャンネル１１７、ソース領域１２０及びドレイン領域１２１が形成されている。そして、ゲート絶縁膜１１８上にゲート電極１１５、ソース及びドレイン領域上にソース電極１２７及びドレイン電極１２８が形成されている。ＭＯＳＴＦＴ１のドレインとＭＯＳＴＦＴ２のゲートとはドレイン電極１２８を介して接続されていると共に、ＭＯＳＴＦＴ２のソース電極１２７との間に絶縁膜１３６を介してキャパシタＣが形成され、かつ、ＭＯＳＴＦＴ２のドレイン領域１２１はそのままＦＥＤ素子のＦＥＣ（電界放出カソード）にまで延設され、エミッタ領域１５２として機能している。
【０２２８】
各ＭＯＳＴＦＴは絶縁膜１３０で覆われ、この絶縁膜上には、ＦＥＣのゲート引き出し電極１５０と同一材料にて同一工程で接地用の金属遮蔽膜１５１が形成され、各ＭＯＳＴＦＴ上を覆っている。ＦＥＣにおいては、多結晶性シリコン薄膜からなるエミッタ領域１５２上に電界放出エミッタとなるｎ型多結晶性シリコン膜１５３が形成され、更にｍ×ｎ個の各エミッタに区画するための開口を有するように、絶縁膜１１８、１３７、１３６及び１３０がパターニングされ、この上面にはゲート引き出し電極１５０が被着されている。
【０２２９】
また、このＦＥＣに対向して、バックメタル１５５付きの蛍光体１５６をアノードとして形成したガラス基板等の基板１５７が設けられており、ＦＥＣとの間は高真空に保持されている。
【０２３０】
この構造のＦＥＣにおいては、ゲート引き出し電極１５０の開口下には、本発明に基づいて形成された多結晶性シリコン薄膜１５２上に成長されたｎ型多結晶性シリコン膜１５３が露出し、これがそれぞれ電子１５４を放出する薄膜型のエミッタとして機能する。即ち、エミッタの下地となる多結晶性シリコン薄膜１５２は、大粒径（グレインサイズ数１００ｎｍ以上）のグレインからなっているため、これをシードとしてその上にｎ型多結晶性シリコン膜１５３をバイアス触媒ＣＶＤ等によって成長させると、この多結晶性シリコン膜１５３はさらに大きな粒径で成長し、表面が電子放出にとって有利な微細な凹凸１５８を生じるように形成されるのである。尚、この時に、多結晶性ダイヤモンド膜、窒素含有又は非含有の炭素薄膜、窒素含有又は非含有の炭素薄膜表面に多数の微細突起構造（例えばカーボンナノチューブ）を有する電子放出体（エミッタ）としてもよい。
【０２３１】
従って、エミッタが薄膜からなる面放出型であるために、その形成が容易であると共に、エミッタ性能も安定し、長寿命化が可能となる。
【０２３２】
また、すべての能動素子（これには周辺駆動回路及び画素表示部のＭＯＳＴＦＴとダイオードが含まれる。）の上部にアース電位の金属遮蔽膜１５１（この金属遮蔽膜は、ゲート引き出し電極１５０と同じ材料（Ｎｂ、Ｔｉ／Ｍｏ等）、同じ工程で形成すると工程上都合がよい。）が形成されているので、次の（１）、（２）の利点を得ることができる。
【０２３３】
（１）気密容器内にあるガスがエミッタ１５３から放出された電子により正イオン化されて絶縁層上にチャージアップし、この正電荷が絶縁層下にあるＭＯＳＴＦＴに不要な反転層を形成し、この反転層からなる不要な電流経路を介して余分な電流が流れるために、エミッタ電流の暴走が起きる。しかし、ＭＯＳＴＦＴ上の絶縁層に金属遮蔽膜１５１を形成してアース電位に落としているので、チャージアップ防止が可能となり、エミッタ電流の暴走を防止できる。
【０２３４】
（２）エミッタ１５３から放出された電子の衝突により蛍光体１５６が発光するが、この光によりＭＯＳＴＦＴのゲートチャンネル内に電子、正孔が発生し、リーク電流となる。しかし、ＭＯＳＴＦＴ上の絶縁層に金属遮蔽膜１５１が形成されているので、ＭＯＳＴＦＴへの光入射が防止され、ＭＯＳＴＦＴの動作不良は生じない。
【０２３５】
また、バイアス触媒ＣＶＤ等により、少なくとも多結晶性シリコンＭＯＳＴＦＴのドレイン領域に連続してｎ型多結晶性シリコン膜等の電子放出体（エミッタ）が形成されているので、その接合性が良好であり、高効率のエミッタ特性が可能となる。
【０２３６】
また、１つの画素表示部の電子放出体（エミッタ）領域を複数に分割し、それぞれにスイッチング素子のＭＯＳＴＦＴを接続すれば、たとえ１つのＭＯＳＴＦＴが故障しても、他のＭＯＳＴＦＴが動作するので、１つの画素表示部は必ず電子放出する構成となっており、高品質で歩留が高く、コストダウンできる。又、これらのＭＯＳＴＦＴにおいて、電気的オープン不良のＭＯＳＴＦＴは問題ないが、電気的ショートしたＭＯＳＴＦＴはレーザーリペアで分離できるので、高品質で歩留が高く、コストダウンできる。
【０２３７】
これに比べて、従来のＦＥＤでは、シリコン単結晶基板を用いるために、基板コストが高く、ウエーハサイズ以上の大面積化が困難である。そして、カソード電極表面に減圧ＣＶＤ等により導電性の多結晶シリコン膜を形成し、その表面にプラズマＣＶＤ等により結晶性ダイヤモンド膜を形成して電子放出体を構成することが提案されているが、減圧ＣＶＤ時の成膜温度が６３０℃と高く、ガラス基板を採用できないので、コストダウンが難しい。そして、その減圧ＣＶＤによる多結晶シリコン膜は粒径が小さく、その上の結晶性ダイヤモンド膜も粒径が小さく、電子放出体の特性が良くない。更に、プラズマＣＶＤのために、反応エネルギーが不足しているので、良い結晶性ダイヤモンド膜は得にくい。又、透明電極又はＡｌ、Ｔｉ、Ｃｒ等の金属のカソード電極と導電性の多結晶シリコン膜の接合性が悪いので、良好な電子放出特性は得られない。
【０２３８】
次に、本実施の形態によるＦＥＤの製造プロセスを説明すると、まず、図２６の（１）に示すように、上述した工程を経て全面に多結晶性シリコン薄膜１１７を形成した後、汎用フォトリソグラフィ及びエッチング技術によりＭＯＳＴＦＴ１とＭＯＳＴＦＴ２及びエミッタ領域にアイランド化し、プラズマＣＶＤ、触媒ＣＶＤ法等により全面に保護用酸化シリコン膜１５９を形成する。
【０２３９】
次いで、ＭＯＳＴＦＴ１、２のゲートチャンネル不純物濃度の制御によるＶ_thの最適化のために、イオン注入又はイオンドーピング法により全面にボロンイオン８３を５×１０¹¹ａｔｏｍｓ／ｃｍ²のドーズ量でドーピングし、１×１０¹⁷ａｔｏｍｓ／ｃｃのアクセプタ濃度に設定する。
【０２４０】
次いで、図２６の（２）に示すように、フォトレジスト８２をマスクにして、イオン注入又はイオンドーピング法によりＭＯＳＴＦＴ１、２のソース／ドレイン部及びエミッタ領域に燐イオン７９を１×１０¹⁵ａｔｏｍｓ／ｃｍ²のドーズ量でドーピングし、２×１０²⁰ａｔｏｍｓ／ｃｃのドナー濃度に設定し、ソース領域１２０、ドレイン領域１２１、エミッタ領域１５２をそれぞれ形成した後、汎用フォトリソグラフィ及びエッチング技術によりエミッタ領域の保護用酸化シリコン膜を除去する。
【０２４１】
次いで、図２６の（３）に示すように、バイアス又は非バイアス触媒ＣＶＤによりエミッタ領域を形成する多結晶性シリコン薄膜１５２をシードに、モノシランとＰＨ₃等のドーパントを適量比率で混合し、表面に微細凹凸１５８を有し、ドーパントを例えば５×１０²⁰〜１×１０²¹ａｔｏｍｓ／ｃｃ含有するｎ型多結晶性シリコン膜１５３を１〜５μｍ厚にエミッタ領域に形成し、同時に他の酸化シリコン膜１５９及びガラス基板１１１上にはｎ型アモルファスシリコン膜１６０を１〜５μｍ厚に形成する。
【０２４２】
次いで、図２６の（４）に示すように、上述した触媒ＡＨＡ処理時の水素系活性種などの作用により、アモルファスシリコン膜１６０を選択的にエッチング除去し、酸化シリコン膜１５９のエッチング除去後に触媒ＣＶＤ等によりゲート絶縁膜（酸化シリコン膜等）１１８を形成する。
【０２４３】
次いで、図２７の（５）に示すように、スパッタリング法によるＭｏ−Ｔａ合金等の耐熱性金属によりＭＯＳＴＦＴ１、２のゲート電極１１５、ＭＯＳＴＦＴ１のゲート電極に接続されるゲートラインを形成し、オーバーコート膜（酸化シリコン膜等）１３７を形成した後、１０００℃、１０〜２０秒のＲＴＡ処理等でイオン活性化を行い、ＭＯＳＴＦＴ２のソース部窓開け後にスパッタリング法によるＭｏ−Ｔａ合金等の耐熱性金属でＭＯＳＴＦＴ２のソース電極１２７及びアースラインを形成する。更に、プラズマＣＶＤ、触媒ＣＶＤ等によりオーバーコート膜（酸化シリコン／窒化シリコン積層膜など）１３６を形成する。
【０２４４】
次いで、図２７の（６）に示すように、ＭＯＳＴＦＴ１のソース／ドレイン部及びＭＯＳＴＦＴ２のゲート部の窓開けを行い、ＭＯＳＴＦＴ１のドレインとＭＯＳＴＦＴ２のゲートを１％Ｓｉ入りＡｌ配線１２８で接続し、同時にＭＯＳＴＦＴ１のソース電極とそのソースに接続されるソースライン１２７を形成する。
【０２４５】
次いで、図２７の（７）に示すように、オーバーコート膜（酸化シリコン／フォスフィンシリケートガラス／窒化シリコン積層膜など）１３０を形成した後、ＧＮＤラインの窓開けし、図２７の（８）に示すように、ゲート引き出し電極１５０や金属遮蔽膜１５１をＮｂ蒸着後のエッチングで形成し、更に電界放出カソード部を窓開けしてエミッタ１５３を露出させ、上述した触媒ＡＨＡ処理での水素系活性種等でクリーニングすると同時に、水素径活性種等の選択的エッチング作用により微細な凹凸を顕著化させる。
【０２４６】
＜ＦＥＤの構造例II＞
図２８（Ａ）、（Ｂ）、（Ｃ）に示すように、この構造例IIによれば、ガラス等の基板１１１上に、上記の構造例Ｉと同様に、本発明に基づいて上述した方法で段差内に形成された高結晶化率、大粒径の多結晶性シリコン薄膜によって、スイッチング用ＭＯＳＴＦＴ１と電流駆動用ＭＯＳＴＦＴ２のゲートチャンネル１１７、ソース領域１２０及びドレイン領域１２１が形成されている。そして、ゲート絶縁膜１１８上にゲート電極１１５、ソース及びドレイン領域上にソース電極１２７及びドレイン電極１２８が形成されている。ＭＯＳＴＦＴ１のドレインとＭＯＳＴＦＴ２のゲートとはドレイン電極１２８を介して接続されていると共に、ＭＯＳＴＦＴ２のソース電極１２７との間に絶縁膜１３６を介してキャパシタＣが形成され、かつ、ＭＯＳＴＦＴ２のドレイン領域１２１はそのままＦＥＤ素子のＦＥＣ（電界放出カソード）にまで延設され、エミッタ領域１５２として機能している。
【０２４７】
各ＭＯＳＴＦＴは絶縁膜１３０で覆われ、この絶縁膜上には、ＦＥＣのゲート引き出し電極１５０と同一材料にて同一工程で接地用の金属遮蔽膜１５１が形成され、各ＭＯＳＴＦＴ上を覆っている。ＦＥＣにおいては、多結晶性シリコン薄膜からなるエミッタ領域１５２上に電界放出エミッタとなるｎ型多結晶性ダイヤモンド膜１６３が形成され、更にｍ×ｎ個の各エミッタに区画するための開口を有するように、絶縁膜１１８、１３７、１３６及び１３０がパターニングされ、この上面にはゲート引き出し電極１５０が被着されている。
【０２４８】
また、このＦＥＣに対向して、バックメタル１５５付きの蛍光体１５６をアノードとして形成したガラス基板等の基板１５７が設けられており、ＦＥＣとの間は高真空に保持されている。
【０２４９】
この構造のＦＥＣは、ゲート引き出し電極１５０の開口下には、本発明に基づいて形成された多結晶性シリコン薄膜１５２上に成長されたｎ型多結晶ダイヤモンド膜１６３が露出し、これがそれぞれ電子１５４を放出する薄膜型のエミッタとして機能する。即ち、エミッタの下地となる多結晶性シリコン膜１５２は、大粒径（グレインサイズ数１００ｎｍ以上）のグレインからなっているため、これをシードとしてその上にｎ型多結晶性ダイヤモンド膜１６３を触媒ＣＶＤ等によって成長させると、この多結晶性ダイヤモンド膜１６３はやはり大粒径で成長し、表面が電子放出にとって有利な微細な凹凸１６８を生じるように形成されるのである。尚、この時に、窒素含有又は非含有の炭素薄膜、窒素含有又は非含有の炭素薄膜表面に多数の微細突起構造（例えばカーボンナノチューブ）を有する電子放出体（エミッタ）としてもよい。
【０２５０】
従って、エミッタが薄膜からなる面放出型であるために、その形成が容易であると共に、エミッタ性能も安定し、長寿命化が可能となる。
【０２５１】
また、すべての能動素子（これには周辺駆動回路及び画素表示部のＭＯＳＴＦＴとダイオードが含まれる。）の上部にアース電位の金属遮蔽膜１５１（この金属遮蔽膜は、ゲート引き出し電極１５０と同じ材料（Ｎｂ、Ｔｉ／Ｍｏ等）、同じ工程で形成すると工程上都合がよい。）が形成されているので、上述したと同様に、ＭＯＳＴＦＴ上の絶縁層に金属遮蔽膜１５１を形成してアース電位に落とし、チャージアップ防止が可能となり、エミッタ電流の暴走を防止でき、また、ＭＯＳＴＦＴ上の絶縁層に金属遮蔽膜１５１が形成されているので、ＭＯＳＴＦＴへの光入射が防止され、ＭＯＳＴＦＴの動作不良は生じない。
【０２５２】
次に、このＦＥＤの製造プロセスを説明すると、まず、図２９の（１）に示すように、上述した工程を経て全面に多結晶性シリコン薄膜１１７を形成した後、汎用フォトリソグラフィ及びエッチング技術によりＭＯＳＴＦＴ１とＭＯＳＴＦＴ２及びエミッタ領域にアイランド化し、プラズマＣＶＤ、触媒ＣＶＤ法等により全面に保護用酸化シリコン膜１５９を形成する。
【０２５３】
次いで、ＭＯＳＴＦＴ１、２のゲートチャンネル不純物濃度の制御によるＶ_thの最適化のために、イオン注入又はイオンドーピング法により全面にボロンイオン８３を５×１０¹¹ａｔｏｍｓ／ｃｍ²のドーズ量でドーピングし、１×１０¹⁷ａｔｏｍｓ／ｃｃのアクセプタ濃度に設定する。
【０２５４】
次いで、図２９の（２）に示すように、フォトレジスト８２をマスクにして、イオン注入又はイオンドーピング法によりＭＯＳＴＦＴ１、２のソース／ドレイン部及びエミッタ領域に燐イオン７９を１×１０¹⁵ａｔｏｍｓ／ｃｍ²のドーズ量でドーピングし、２×１０²⁰ａｔｏｍｓ／ｃｃのドナー濃度に設定し、ソース領域１２０、ドレイン領域１２１、エミッタ領域１５２をそれぞれ形成した後、汎用フォトリソグラフィ及びエッチング技術によりエミッタ領域の保護用酸化シリコン膜を除去する。
【０２５５】
次いで、図２９の（３）に示すように、バイアス又は非バイアス触媒ＣＶＤによりエミッタ領域を形成する多結晶性シリコン薄膜１５２をシードに、モノシランとメタン（ＣＨ₄）及びドーパントを適量比率混合し、表面に微細凹凸１６８を有するｎ型多結晶性ダイヤモンド膜１６３をエミッタ領域に形成し、同時に他の酸化シリコン膜１５９及びガラス基板１１１上にはｎ型アモルファスダイヤモンド膜１７０を形成する。
【０２５６】
次いで、図２９の（４）に示すように、上述した触媒ＡＨＡ処理時の水素系活性種等などの作用により、アモルファスダイヤモンド膜１７０を選択的にエッチング除去し、酸化シリコン膜１５９のエッチング除去後に触媒ＣＶＤ等によりゲート絶縁膜（酸化シリコン膜等）１１８を形成する。
【０２５７】
次いで、図３０の（５）に示すように、スパッタリング法によるＭｏ−Ｔａ合金等の耐熱性金属によりＭＯＳＴＦＴ１、２のゲート電極１１５、ＭＯＳＴＦＴ１のゲート電極に接続されるゲートラインを形成し、オーバーコート膜（酸化シリコン膜等）１３７を形成した後、ＲＴＡ等の１０００℃、１０〜２０秒のイオン活性化処理を行う。この後にＭＯＳＴＦＴ２のソース部窓開け後にスパッタリング法によるＭｏ−Ｔａ合金等の耐熱性金属でＭＯＳＴＦＴ２のソース電極１２７及びアースラインを形成する。更に、プラズマＣＶＤ、触媒ＣＶＤ等によりオーバーコート膜（酸化シリコン／窒化シリコン積層膜など）１３６を形成する。
【０２５８】
次いで、図３０の（６）に示すように、ＭＯＳＴＦＴ１のソース／ドレイン部及びＭＯＳＴＦＴ２のゲート部の窓開けを行い、ＭＯＳＴＦＴ１のドレインとＭＯＳＴＦＴ２のゲートを１％Ｓｉ入りＡｌ配線１２８で接続し、同時にＭＯＳＴＦＴ１のソース電極とそのソースに接続されるソースライン１２７を形成する。
【０２５９】
次いで、図３０の（７）に示すように、オーバーコート膜（酸化シリコン／フォスフィンシリケートガラス／窒化シリコン積層膜など）１３０を形成した後、ＧＮＤラインの窓開けし、図３０の（８）に示すように、ゲート引き出し電極１５０や金属遮蔽膜１５１をＮｂ蒸着後のエッチングで形成し、更に電界放出カソード部を窓開けしてエミッタ１６３を露出させ、上述した触媒ＡＨＡ処理での水素系活性種でクリーニングすると同時に、水素系活性種等の選択的エッチング作用により微細な凹凸を顕著化させる。
【０２６０】
なお、上記において、多結晶性ダイヤモンド膜１６３を成膜する際、使用する原料ガスとしての炭素含有化合物は、例えば
１）メタン、エタン、プロパン、ブタン等のパラフィン系炭化水素
２）アセチレン、アリレン系のアセチレン系炭化水素
３）エチレン、プロピレン、ブチレン等のオレフィン系炭化水素
４）ブタジエン等のジオレフィン系炭化水素
５）シクロプロパン、シクロブタン、シクロペンタン、シクロヘキサン等の脂環式炭化水素
６）シクロブタジエン、ベンゼン、トルエン、キシレン、ナフタリン等の芳香族炭化水素
７）アセトン、ジエチルケトン、ベンゾフェノン等のケトン類
８）メタノール、エタノール等のアルコール類
９）トリメチルアミン、トリエチルアミン等のアミン類
１０）グラファイト、石炭、コークス等の炭素原子のみからなる物質
であってよく、これらは、１種を単独で用いることもできるし、２種以上を併用することもできる。
【０２６１】
また、使用可能な不活性ガスは、例えばアルゴン、ヘリウム、ネオン、クリプトン、キセノン、ラドンである。ドーパントとしては、例えばホウ素、リチウム、窒素、リン、硫黄、塩素、ひ素、セレン、ベリリウム等を含む化合物又は単体が使用可能であり、そのドーピング量は１０¹⁶ａｔｏｍｓ／ｃｃ以上であってよい。
【０２６２】
第５の実施の形態
本実施の形態は、本発明を光電変換装置としての太陽電池に適用したものである。以下にその製造例を示す。
【０２６３】
まず、図３１の（１）に示すように、ステンレス等の金属基板１１１上に、所定の形状／寸法の段差を有する凹部を形成し、シリコン又は／及びカーボン超微粒子を付着させて、上述した触媒ＡＨＡ処理、触媒ＣＶＤ法等によって、シリコン又は／及びダイヤモンド構造のカーボン超微粒子層をシードにｎ型多結晶性シリコン膜７を凹部内に形成する。この多結晶性シリコン膜７は、上述のマルチ触媒ＡＨＡ処理により形成してよく、高結晶化率、大粒径の錫又は他のIV族元素（Ｇｅ、Ｐｂ）の単独又は混合物含有のｎ型多結晶性シリコン膜として１００〜２００ｎｍ厚に形成する。この多結晶性シリコン膜７には、リン等のｎ型不純物をＰＨ₃等としてモノシランと共に供給して例えば１×１０¹⁷〜１×１０¹⁸ａｔｏｍｓ／ｃｃ含有させる。
【０２６４】
次いで、図３１の（２）に示すように、多結晶性シリコン膜７上に、これをシードにして触媒ＣＶＤ等により錫又は他のIV族元素（Ｇｅ、Ｐｂ）の単独又は混合物含有のｉ型多結晶性シリコン膜１８０、錫又は他のIV族元素（Ｇｅ、Ｐｂ）の単独又は混合物含有のｐ型多結晶性シリコン膜１８１等を成長させ、光電変換層を形成する。
【０２６５】
例えば、触媒ＣＶＤにより、モノシランに水素化錫（ＳｎＨ₄）を適量比率で混合してｉ型の大粒径の錫含有多結晶性シリコン膜１８０を２〜５μｍ厚に成長させ、この上に、モノシランにｐ型不純物ボロン（Ｂ₂Ｈ₆など）と水素化錫（ＳｎＨ₄）を適量比率混合して、例えば１×１０¹⁷〜１×１０¹⁸ａｔｏｍｓ／ｃｃ含有させたｐ型の大粒径の錫含有多結晶性シリコン膜１８１を１００〜２００ｎｍ厚に形成する。この時にそれぞれの膜中に錫又は他のIV族元素（Ｇｅ、Ｐｂ）の単独又は混合物、例えば錫を１×１０¹⁶ａｔｏｍｓ／ｃｃ以上、好ましくは１×１０¹⁸〜１×１０²⁰ａｔｏｍｓ／ｃｃ含有させることにより、結晶粒界に存在する結晶不整及び応力を低減させるので、キャリア移動度向上を図ることができる（これは、ｎ型又はｐ型多結晶性シリコン膜７、１８１を形成する場合も同様である）。
【０２６６】
また、上述したマルチ触媒ＡＨＡ処理を行ってよい。例えば、バイアス触媒ＣＶＤでｎ型又はｐ型の錫含有多結晶性シリコン薄膜を２０〜５０ｎｍ厚に成長させた後、触媒ＡＨＡ処理を行い、触媒ＣＶＤでｎ型又はｐ型の錫含有多結晶性シリコン薄膜を２０〜５０ｎｍ厚に成長させ、触媒ＡＨＡ処理後、更に触媒ＣＶＤでｎ型又はｐ型の錫含有多結晶性シリコン薄膜を２０〜５０ｎｍに成長させた後、触媒ＡＨＡ処理を行うように、各処理を必要回数繰り返す方法で成膜してもよい（これはｉ型多結晶性シリコン膜１８０の場合も同様である）。この方法によって、より高結晶化率であってより大きい粒径の錫含有多結晶性シリコン膜を形成できる。また、成膜途中で原料ガス供給量を増加して、高速成膜とすることもできる。
【０２６７】
次いで、図３１の（３）に示すように、上記の方法で形成したｎ−ｉ−ｐ接合の高結晶化率で大粒径の錫含有多結晶性シリコン膜の全面に、透明電極１８２を形成する。例えば、汎用スパッタリング技術により、無反射コート用の１３０〜１５０ｎｍ厚のＩＴＯ（Indium Tin Oxide）又はＩＺＯ（Indium Zinc Oxide）膜等の透明電極１８２を形成する。そして、この上に、汎用スパッタリング技術により、メタルマスクを用いて、所定領域に銀等のくし型電極１８３を１００〜１５０ｎｍ厚に形成する。
【０２６８】
なお、上記の膜は錫又は他のIV族元素を必ずしも含有していなくてもよいが、この場合も上記と同様に製造することができる。また、上記のｎ−ｉ−ｐ接合構造以外にも、ｐ−ｉ−ｎ接合、ｐ−ｎ接合、ｎ−ｐ接合等の構造も同様に作製することができる。
【０２６９】
本実施の形態による太陽電池は、本発明に基づく高結晶化率で大粒径の多結晶性シリコン膜によって、高キャリア移動度で変換効率の大きい光電変換薄膜を形成でき、良好な表面テクスチャ構造と裏面テクスチャ構造が形成されるので、光封じ込め効果が高く、変換効率の大きい光電変換薄膜を形成できる。これはまた、太陽電池に限らず、電子写真用の感光体ドラム等の薄膜光電変換装置にも有利に利用することができる。
【０２７０】
これに比べて、従来のこの種の光電変換装置では、ＲＦプラズマＣＶＤ、ＶＨＦプラズマＣＶＤ等によりアモルファスカーボン薄膜を形成し、プラズマ水素処理でカーボン超微粒子を形成してこれを多結晶シリコン結晶成長の核として大粒径多結晶シリコン膜を形成しており、ｎ型多結晶シリコン層とｉ型多結晶シリコン活性層及びｐ型多結晶シリコン層を連続成膜し、その全面にＩＴＯ膜を積層し、最後にくし型電極を形成して、２μｍ厚程度の薄膜多結晶性シリコン太陽電池を得ている。
【０２７１】
ところが、この従来法では、次のような欠点を回避できない。
１）ＲＦプラズマＣＶＤ、ＶＨＦプラズマＣＶＤ法等による低温形成の結晶質シリコン系薄膜は、そのエネルギーが低いので、原料ガスの化学的分解反応やプラズマ水素処理が不十分になりやすく、結晶粒径が小さいので、移動度が小さく、しかも粒界の多さやピンホール等のために局部的な電気的ショート又はリークによる過剰電流が発生しやすく、光電変換層として必要な数μｍの膜厚に堆積させたときに膜の内部応力や歪が大きくなって、最悪の場合には膜が剥離してしまうという問題がある。これによって、光電変換層の製造歩留や信頼性を著しく低下させ、それを含む光電変換装置の実用化を目指す上で大きな支障となる。
２）ＲＦプラズマＣＶＤ、ＶＨＦプラズマＣＶＤ等のプラズマＣＶＤ法はエネルギーが低いので、原料ガスの利用効率が５〜１０％と低い。このために、生産性が低く、コストダウンしにくい。
【０２７２】
以上に述べた本発明の実施の形態は、本発明の技術的思想に基づいて種々変形が可能である。
【０２７３】
例えば、上述した触媒ＣＶＤ法と触媒ＡＨＡ処理の繰り返し回数や各条件は種々変更してよく、用いる基板等の材質も上述したものに限定されることはない。
【０２７４】
また、本発明は、表示部等の内部回路や周辺駆動回路及び映像信号処理回路及びメモリー回路等のＭＯＳＴＦＴに好適なものであるが、それ以外にもダイオードなどの素子の能動領域や、抵抗、キャパシタンス（容量）、配線、インダクタンス等の受動領域を本発明による多結晶性シリコン薄膜で形成することも可能である。
【０２７５】
【発明の作用効果】
本発明は上述したように、基体上に多結晶性半導体薄膜を形成するに際し、前記基体上に所定の形状／寸法の段差を有する凹部を形成し、少なくともこの凹部内にシリコン及び／又はカーボンからなる微粒子を付着させ、水素又は水素含有ガスを加熱された触媒体に接触させ、これによって生成した水素系活性種を前記微粒子に作用させてクリーニングを行い、シリコン又は／及びダイヤモンド構造のカーボン超微粒子をシードに触媒ＣＶＤ法等により前記半導体材料薄膜を気相成長させているので、次の（１）〜（４）に示すような顕著な作用効果が得られる。
【０２７６】
（１）基板の任意の指定場所に適当な形状及び寸法の段差を有する凹部を形成し、そこにシリコンパウダー等の超微粒子を付着分散させ、触媒ＡＨＡ処理での水素系活性種の作用により、この超微粒子のアモルファス成分を選択的にエッチング除去し、更にこの超微粒子の表面の酸化膜及び有機汚れ等を除去できるので、この超微粒子を結晶成長の核（シード）として触媒ＣＶＤ、高密度触媒ＣＶＤ法等により、ばらつきの少ない大きな粒径の多結晶性シリコン膜等を指定された領域に形成できる。
【０２７７】
（２）絶縁性基板の任意の指定場所に高性能、高品質のＴＦＴを形成でき、その集積回路基板を自由に形成できる。そして、必要に応じて、絶縁性基板上のＴＦＴ形成領域の適当な寸法及び形状の段差を有する凹部内に大粒径多結晶性シリコン膜が埋め込まれた面を研磨して、平坦な大粒径多結晶性シリコン膜面の基板が得られるので、高性能、高品質の多結晶性シリコン半導体装置、電気光学装置等の製造が可能となる。
【０２７８】
（３）触媒ＣＶＤ及び触媒ＡＨＡ処理は、プラズマの発生なしに行えるので、プラズマによるダメージがなく、またプラズマＡＨＡ処理に比べ、シンプルで安価な装置を実現できる。
【０２７９】
（４）触媒ＡＨＡ処理は基体温度を低温化しても上記水素系活性種のエネルギーが大きいために、目的とするシリコン及び／又はダイヤモンド構造のカーボン超微粒子が確実に安定して得られることから、基体温度を特に３００〜４００℃と低温化しても、多結晶性半導体薄膜が微粒子をシードに効率良く成長し、従って大型で安価な低歪点の絶縁基板（ガラス基板、耐熱性樹脂基板等）を使用でき、この点でもコストダウンが可能となる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態によるＭＯＳＴＦＴの製造プロセスを工程順に示す断面図である。
【図２】同、製造プロセスを工程順に示す断面図である。
【図３】同、製造プロセスを工程順に示す断面図である。
【図４】同、製造プロセスを工程順に示す断面図である。
【図５】同、製造に用いる触媒ＣＶＤ及び触媒ＡＨＡ処理用の装置の一状態での概略断面図である。
【図６】同、この装置の他の状態での概略断面図である。
【図７】同、この装置を用いた処理時のガス流量のタイミングチャートである。
【図８】同、この装置のガス供給系の概略図である。
【図９】同、この処理により得られた半導体膜のラマンスペクトルを比較して示すグラフである。
【図１０】同、半導体薄膜の結晶化率を比較して示すグラフである。
【図１１】同、触媒体及びこの支持体の純度による膜中の重金属濃度を比較して示すグラフである。
【図１２】本発明の第２の実施の形態によるＬＣＤの製造プロセスを工程順に示す断面図である。
【図１３】同、製造プロセスを工程順に示す断面図である。
【図１４】同、製造プロセスを工程順に示す断面図である。
【図１５】同、製造プロセスを工程順に示す断面図である。
【図１６】同、ＬＣＤの全体の概略レイアウトを示す斜視図である。
【図１７】同、ＬＣＤの等価回路図である。
【図１８】同、ＬＣＤの他の製造プロセスを工程順に示す断面図である。
【図１９】同、製造プロセスを工程順に示す断面図である。
【図２０】同、ＬＣＤのＭＯＳＴＦＴを各種示す断面図である。
【図２１】本発明の第３の実施の形態による有機ＥＬ表示装置の要部の等価回路図（Ａ）、同要部の拡大断面図（Ｂ）及び同画素周辺部の断面図（Ｃ）である。
【図２２】同、有機ＥＬ表示装置の製造プロセスを工程順に示す断面図である。
【図２３】同、他の有機ＥＬ表示装置の要部の等価回路図（Ａ）、同要部の拡大断面図（Ｂ）及び同画素周辺部の断面図（Ｃ）である。
【図２４】同、有機ＥＬ表示装置の製造プロセスを工程順に示す断面図である。
【図２５】本発明の第４の実施の形態によるＦＥＤの要部の等価回路図（Ａ）、同要部の拡大断面図（Ｂ）及び同要部の概略平面図（Ｃ）である。
【図２６】同、ＦＥＤの製造プロセスを工程順に示す断面図である。
【図２７】同、製造プロセスを工程順に示す断面図である。
【図２８】同、他のＦＥＤの要部の等価回路図（Ａ）、同要部の拡大断面図（Ｂ）及び同要部の平面図（Ｃ）である。
【図２９】同、ＦＥＤの製造プロセスを工程順に示す断面図である。
【図３０】同、製造プロセスを工程順に示す断面図である。
【図３１】本発明の第５の実施の形態による太陽電池の製造プロセスを工程順に示す断面図である。
【符号の説明】
１、６１、９８、１１１、１５７…基板、７、６７…多結晶性シリコン薄膜、
１４、６７、１１７…チャンネル、
１５、７５、１０２、１０５、１１５…ゲート電極、
８、６８、１０３、１０４、１０６、１１８…ゲート絶縁膜、
２０、２１、８０、８１、１２０、１２１…ｎ⁺型ソース又はドレイン領域、
２４、２５、８４、８５…ｐ⁺型ソース又はドレイン領域、
２７、２８、８６、９２、１３０、１３６、１３７…絶縁膜、
２９、３０、８７、８８、８９、９０、９１、９３、９７、１２７、１２８、１３１…電極、４０…原料ガス、４２…シャワーヘッド、４４…成膜室、
４５…サセプタ、４６…触媒体、４７…シャッター、４８…触媒体電源、
９４、９６…配向膜、９５…液晶、９９…カラーフィルタ層、
１００Ａ…シリコン又はカーボン微粒子、
１００Ｂ…クリーニングされたシリコン又はカーボン微粒子、
１００’、１４０…ブラックマスク層、１３２、１３３…有機発光層、
１３４、１３５、１４４…陽極、１３８、１４１、１４２、１７１…陰極、
１５０…ゲート引き出し電極（ゲートライン）、１５１…遮蔽膜、
１５２…エミッタ、１５３…ｎ型多結晶性シリコン膜、１５５…バックメタル、
１５６…蛍光体、１５８、１６８…微細凹凸、
１６３…ｎ型多結晶性ダイヤモンド膜、１８０…ｉ型多結晶性シリコン膜、
１８１…ｐ型多結晶性シリコン膜、１８２…透明電極、１８３…くし型電極、
１９０…凹部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming a polycrystalline semiconductor thin film such as polycrystalline silicon on a substrate, and a method for manufacturing a semiconductor device having the polycrystalline semiconductor thin film on a substrate.
[0002]
[Prior art]
Conventionally, when a source, drain, and channel region of a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) such as a MOS TFT (Thin Film Transistor = Thin Film Insulated Gate Field Effect Transistor) is formed of a polycrystalline silicon film, plasma CVD ( CVD: Chemical Vapor Deposition = chemical vapor deposition method), PVD (PVD: Physical Vapor Deposition = physical vapor deposition method), low pressure CVD method, or the like is used.
[0003]
For example, according to Japanese Patent Application Laid-Open No. 5-283726, an amorphous silicon film is formed on a substrate polished with silicon powder by using plasma CVD or PVD method with fine particles of silicon powder adhering to the substrate as a nucleus, and then a permanent magnet. There has been proposed a method of forming a polycrystalline silicon film by repeating a process of exposing for a certain period of time with hydrogen plasma of ECR discharge using a plasma.
[0004]
In addition, amorphous or polycrystalline silicon formed by plasma CVD, low pressure CVD or the like is simply subjected to high-temperature annealing or as shown in JP-A-7-131030, JP-A-9-116156, and JP-B-7-118443. Although the excimer laser annealing (ELA) treatment has improved the carrier mobility of the polycrystalline silicon film, this method uses 80 to 120 cm.²It was the limit to obtain carrier mobility of about / V · sec. However, the electron mobility of MOSTFT using a polycrystalline silicon thin film obtained by ELA of an amorphous silicon thin film by plasma CVD is 100 cm.²/ V · sec, which can cope with high definition, recently, LCD (Liquid Crystal Display) using a polycrystalline silicon MOSTFT integrated with a driving circuit has been attracting attention (Japanese Patent Laid-Open No. 6). -24433)).
[0005]
[Problems to be solved by the invention]
However, none of the above methods can avoid the following drawbacks.
[0006]
(1) In the above method using silicon powder, in order to control the particle size, polishing is performed with silicon powder or a paste containing silicon powder, or silicon powder is dispersed in an organic solvent, and an ultrasonic cleaning machine is used. However, it is impossible to control the adhesion to any designated place on the substrate. For this reason, for example, since a TFT formation region on the substrate cannot be designated, it is not possible to freely form a high-performance / high-quality TFT and its integrated circuit substrate.
[0007]
(2) In this method, the control of the silicon grain size is not sufficient, and the film quality of the polycrystalline silicon on the substrate varies, resulting in characteristic variations, and there are problems in yield and quality. Further, during the adhesion and dispersion of the silicon powder, an oxide film, an organic stain film, and the like are easily formed on the surface, so that it is difficult to become a seed for growing a polycrystalline silicon crystal.
[0008]
(3) Hydrogen plasma of ECR discharge using a permanent magnet is strong energy compared to hydrogen plasma of RF / VHF plasma, so the effect is high, but since the effective processing area is narrow, characteristics are likely to vary and large area substrates The productivity of processing is low, and the ECR apparatus is expensive and low in versatility.
[0009]
In addition, when using an excimer laser, there are many problems such as stability of output, productivity, increase in device price due to increase in size, and decrease in yield / quality. Especially in a large glass substrate of 1 m × 1 m. As a result, the above-mentioned problems are enlarged, and it becomes more difficult to improve performance / quality and reduce costs.
[0010]
In addition, in the method of manufacturing a polycrystalline silicon MOSTFT by solid phase growth, a gate SiO that is annealed at 600 ° C. or more for 10 hours and thermally oxidized at about 1000 ° C.₂Therefore, it is necessary to employ a semiconductor manufacturing apparatus. For this reason, the substrate size is limited to a wafer size of 8 to 12 inches φ, and high-heat-resistant and expensive quartz glass has to be adopted, which makes it difficult to reduce costs and is used for EVF and data / AV projectors. Is limited.
[0011]
Recently, a catalytic CVD method, which is excellent thermal CVD capable of producing a polycrystalline silicon film, a silicon nitride film, etc. on an insulating substrate such as a glass substrate at a low temperature has been developed (Japanese Patent Publication No. 63-40314, Japanese Patent Publication No. 63-40314). No. 8-250438), and the practical application is being promoted. In the catalytic CVD method, 30 cm without crystallization annealing.²Although carrier mobility of about / V · sec is obtained, it is still insufficient for producing a high-quality MOSTFT device. When a polycrystalline silicon film is formed on a glass substrate, an initial amorphous silicon transition layer (thickness of 5 to 10 nm) is likely to be formed depending on the film forming conditions. Mobility is difficult to obtain. In general, an LCD using a drive circuit integrated type polycrystalline silicon MOSTFT is easy to manufacture with a bottom gate type MOSTFT in terms of yield and productivity, but this problem becomes a bottleneck.
[0012]
An object of the present invention is to provide a method capable of forming a polycrystalline semiconductor thin film such as polycrystalline silicon having a high crystallization rate and high quality easily, at low cost and in a large area.
[0013]
Another object of the present invention is to provide a method of manufacturing a semiconductor device such as a MOS TFT having such a polycrystalline semiconductor thin film as a constituent part.
[0014]
[Means for Solving the Problems]
That is, the present invention provides a method for forming a polycrystalline semiconductor thin film on a substrate or a semiconductor device having a polycrystalline semiconductor thin film on a substrate.
Forming a recess having a step having an appropriate shape / dimension on the substrate;
Attaching at least ultrafine particles of silicon and / or carbon in the recesses;
Bringing hydrogen or a hydrogen-containing gas into contact with a heated catalyst body, causing the hydrogen-based active species generated thereby to act on the fine particles, and cleaning,
A step of crystal growth using the fine particles as a seed to vapor-deposit a semiconductor material thin film;
This relates to a method for forming a polycrystalline semiconductor thin film, or a method for manufacturing a semiconductor device, wherein the polycrystalline semiconductor thin film is obtained through the steps.
[0015]
According to the present invention, when a polycrystalline semiconductor thin film is formed on a substrate, a recess having a step having an appropriate shape / size is formed on the substrate, and at least the silicon and / or carbon made of silicon and / or carbon is formed in the recess. Fine particles are adhered, hydrogen or a hydrogen-containing gas is brought into contact with the heated catalyst body, and the hydrogen-based active species generated thereby are allowed to act on the ultrafine particles to perform cleaning, and the ultrafine particles are grown as crystals on the seeds. Since the semiconductor material thin film is vapor-phase-grown, remarkable effects as shown in the following (1) to (4) can be obtained.
[0016]
(1) A concave portion having an appropriate shape and size step is formed at an arbitrary designated position of the substrate, and ultrafine particles such as silicon powder are adhered and dispersed therein, and by the action of hydrogen-based active species in the catalyst AHA treatment, The ultrafine particles can be selectively removed by etching, and the oxide film and organic stains on the surface of the ultrafine particles can be removed. By a CVD method or the like, a polycrystalline silicon film having a large particle size with little variation can be formed in a specified region. Here, the treatment with hydrogen-based active species (high-temperature hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions, etc.) generated by bringing hydrogen or a hydrogen-containing gas into contact with the heated catalyst body is a catalyst AHA (Atomic Hydrogen Anneal). The catalyst AHA treatment causes hydrogen-based active species such as high-temperature hydrogen-based molecules, hydrogen-based atoms, and active hydrogen ions to act on the ultrafine particles by spraying or the like. Heating by radiant heat of the medium is also applied to remove organic substances and oxide films on the surface of the fine particles, and it can effectively act as a seed for crystal growth of the polycrystalline semiconductor thin film.
[0017]
(2) A high-performance, high-quality TFT can be formed at any specified location on the insulating substrate, and the integrated circuit substrate can be freely formed. Then, if necessary, the surface where the large-grain polycrystalline silicon thin film is embedded in the concave portion having a step having an appropriate size and shape in the TFT formation region on the insulating substrate is polished to obtain a flat large particle. Since a substrate having a polycrystalline silicon thin film surface can be obtained, high-performance and high-quality polycrystalline silicon semiconductor devices, electro-optical devices and the like can be manufactured.
[0018]
(3) Since the bias catalyst CVD and the catalyst AHA treatment can be performed without generating plasma, the plasma is not damaged, and a simpler and cheaper apparatus can be realized as compared with the plasma AHA treatment.
[0019]
(4) Since the energy of the hydrogen-based active species is large even when the substrate temperature is lowered in the catalyst AHA treatment, the target silicon and / or diamond structure carbon ultrafine particles can be obtained stably and reliably. Even when the substrate temperature is lowered to 300 to 400 ° C. in particular, the polycrystalline semiconductor thin film efficiently grows using ultrafine particles as seeds, and thus a large and inexpensive low strain point insulating substrate (glass substrate, heat resistant resin substrate, etc.) ) Can be used, and this also makes it possible to reduce costs.
[0020]
In the present invention, the ultrafine particles of silicon and / or carbon formed by the catalyst AHA treatment are 1 particle / μm with a particle diameter of 1 nm or more (preferably 10 to 100 nm).²Or more (preferably 1 to 100 / μm)²It is desirable that the area ratio is scattered. The polycrystalline semiconductor thin film is based on a polycrystal having a large particle size (generally several hundred nm or more in grain size) from which an amorphous component has been removed or may be present in a very small amount. Consists of a containing structure. The above-mentioned semiconductor material thin film to be the polycrystalline semiconductor thin film is a low crystalline semiconductor thin film other than polycrystal, and has a structure based on a microcrystal containing an amorphous component, for example, a microcrystalline silicon thin film. A structure based on an amorphous (amorphous) containing microcrystals is called, for example, an amorphous silicon thin film or an amorphous carbon thin film. This is because the ultrafine silicon particles and the like become diamond-structured carbon and the like by the action of hydrogen-based active species in the catalyst AHA treatment, and this serves as a seed for crystal growth to form a polycrystalline silicon thin film. Become.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
In the method of the present invention, in order to form a recess having an appropriate size and step on a substrate such as a glass substrate, general-purpose photolithography and etching techniques are preferably employed. It is preferable to form a recess of ˜500 nm, 10 μm in length × 30 μm in width. In this case, RIE (Reactive Ion Etching), CF_FourGas plasma etching or wet etching with a hydrofluoric acid-based etchant may be performed.
[0022]
In order to adhere and disperse silicon powder or carbon powder or fine particles mixed with these in the recess, the silicon powder or the carbon powder or the silicon powder or carbon powder in the recess is polished by polishing with a paste containing silicon powder or carbon powder. Carbon powder or silicon powder and carbon powder fine particles may be adhered and dispersed. In addition, silicon powder or carbon powder or a mixture of these powders is dispersed in an organic solvent (acetone, ethyl alcohol, ethyl alcohol / acetone, etc.), and silicon powder or carbon is placed in the recess by the power and time management of the ultrasonic cleaner. Powder or fine particles mixed with these may be adhered and dispersed. The particle diameter of these powders is preferably 10 nm to 10 μm, for example 50 to 200 nm, particularly 10 to 50 nm. If not polished, a particle size smaller than the size of the recess step is desirable.
[0023]
The catalyst AHA treatment cleans the surface of silicon powder and / or carbon powder adhering to the inside of the recess and removes foreign films such as oxide film and organic dirt, and at the same time, selectively etches amorphous silicon and carbon. Thus, silicon fine particles and diamond-structured carbon fine particles are formed and used as seeds for polycrystalline growth. This catalytic AHA treatment may be carried out as part of a continuous operation before the formation of the polycrystalline semiconductor thin film by the following catalytic CVD or high-density catalytic CVD method.
[0024]
This polycrystalline semiconductor thin film is preferably formed by a vapor phase growth method (catalytic CVD method, high-density plasma CVD method, high-density catalytic CVD method, etc .; hereinafter the same). In this case, desirably, the catalyst body heated to a temperature lower than the melting point (800 to 2000 ° C., for example, 1600 to 1800 ° C.) is contacted with at least a part of the raw material gas and hydrogen or a hydrogen-containing gas to catalytically decompose. Preferably, reactive species such as radicals and ions generated thereby are deposited on the heated substrate, and the thin film is vapor-phase grown by catalytic CVD. At this time, silicon powder or carbon powder (particularly, diamond-structured carbon fine particles: hereinafter the same) or silicon powder and carbon powder mixed fine particles in the recesses provided in the substrate are used as seeds for crystal growth, for example, tin. 10¹⁸-10²⁰A polycrystalline silicon thin film having a large particle size containing atoms / cc can be formed. Then, if necessary, the semiconductor material thin film is polished to flatten the surface including the thin film surface, and the polycrystalline silicon thin film can be embedded in the recess of the TFT region of the substrate.
[0025]
Further, after the vapor phase growth, the supply of the raw material gas is stopped continuously, and desirably, a catalyst body heated to a temperature lower than the melting point (this may be the same as the catalyst body, And at least a part of the hydrogen or hydrogen-containing gas are contacted with each other, and hydrogen-based active species such as high-temperature hydrogen-based molecules, hydrogen-based atoms, and activated hydrogen ions generated thereby It is preferable to perform annealing by catalytic AHA treatment by acting on the semiconductor material thin film.
[0026]
In this case, the hydrogen or hydrogen-containing gas supply amount at the annealing is made larger than the hydrogen or hydrogen-containing gas supply amount at the vapor phase growth. For example, the hydrogen-based carrier gas used during vapor phase growth is hydrogen or a mixed gas of hydrogen and an inert gas (such as argon, helium, xenon, krypton, radon, etc., which has good thermal conductivity and contributes to improved reactivity). In addition, in the case of a mixed gas, the hydrogen content ratio is 50 mol% or more, so that oxidation deterioration of the catalyst body can be prevented. The hydrogen or hydrogen-containing gas used during the catalyst AHA treatment may be the same as the hydrogen-based carrier gas used during vapor phase growth. For example, the gas flow rate is 300 to 1000 SCCM (Standard cc per minute), and the gas pressure is 10 to 50 Pa. It is preferable to increase the gas pressure (the gas pressure at the time of biased or non-biased catalytic CVD is 0.1 to several Pa) to increase the heat conduction by the gas and increase the generation amount of hydrogen-based active species.
[0027]
In addition, after vapor phase growth of the semiconductor material thin film, hydrogen or a hydrogen-containing gas is continuously brought into contact with a heated catalyst body, and high-temperature hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions, and the like generated thereby It is desirable that annealing is performed by applying a hydrogen-based active species to the semiconductor material thin film, and if necessary, vapor phase growth of the semiconductor material thin film similar to the semiconductor material thin film and the annealing are repeated. For this purpose, it is preferable to have a control means for controlling the source gas supply means and the hydrogen or hydrogen-containing gas supply means.
[0028]
That is, a multi-catalyst of two or more steps is repeated, in which a step of vapor-phase growth of a semiconductor material thin film on the polycrystalline semiconductor thin film obtained by the catalyst AHA treatment and an annealing step are repeated until the desired film thickness is obtained. By the AHA treatment, this semiconductor material thin film is easily grown on the base film already polycrystallized by the catalyst AHA treatment, using this as a seed, in a state where it is easily polycrystallized, and has a desired high crystallization rate and high quality. The polycrystalline semiconductor film can be obtained with a predetermined film thickness. That is, by multi-catalyst AHA treatment in which catalytic CVD and catalyst AHA treatment are repeated, for example, polycrystalline silicon formed on a diamond ultrafine carbon particle layer by catalytic CVD is seeded by catalytic AHA treatment, and then catalytic CVD is performed thereon. A polycrystalline silicon film having a high crystallization ratio and a large grain size can be formed by vapor-phase-growing a semiconductor material thin film and further performing a catalyst AHA treatment.
[0029]
Specifically, in a silicon film, the thermal energy of a large amount of high-temperature hydrogen-based active species is transferred, the temperature of the film is locally increased, and amorphous components are removed by the reduction action of the hydrogen-based active species. The microcrystalline silicon thin film is polycrystallized by etching, and the polycrystalline silicon thin film is highly crystallized to easily form a polycrystalline silicon thin film having a large grain size. The thin film is further crystallized and has a large particle size, and carrier mobility can be improved.
[0030]
In addition, when silicon oxide is present on the polycrystalline silicon thin film or in the film or at the grain boundary, the hydrogen-based active species react with this to generate SiO to be removed by evaporation. Silicon oxide in the film can be reduced / removed, and carrier mobility can be improved.
[0031]
Further, in the case of this catalytic CVD, a wide range of n or p type impurity concentrations can be obtained depending on the type and temperature of the catalyst body, the substrate heating temperature, the gas phase film formation conditions, the type of source gas, the concentration of the n or p type impurity to be added, A polycrystalline silicon thin film can be easily obtained, and a polycrystalline silicon thin film having a large particle diameter can be formed by catalytic AHA treatment._th(Threshold) adjustment is easy, and high-speed operation with low resistance is possible.
[0032]
In the case where a polycrystalline silicon film is formed by plasma CVD and this is subjected to catalytic AHA treatment, hydrogen contained in the polycrystalline silicon film by plasma CVD is reduced / removed by catalytic AHA treatment, Since a polycrystalline silicon film having a large particle size can be formed, a polycrystalline silicon film having a large carrier mobility can be formed. Furthermore, a polycrystalline silicon film having a wide range of n or p-type impurity concentration can be easily obtained depending on the substrate heating temperature, vapor phase film forming conditions, source gas type, catalyst AHA treatment conditions, added n or p-type impurity concentration, etc. So you can get V with high mobility._thAdjustment is easy and high-speed operation with low resistance is possible.
[0033]
Specifically, the above-mentioned vapor phase growth by the catalytic CVD is performed by heating the catalyst body to a temperature in the range of 800 to 2000 ° C. and lower than its melting point (for example, energizing the catalyst body and heating the resistance body itself. The reaction species generated by catalytic reaction or thermal decomposition reaction of at least part of the raw material gas and the hydrogen or hydrogen-containing gas with the heated catalyst body were heated to, for example, 300 to 400 ° C. A thin film can be deposited on the substrate. Such catalyst body temperature and the following catalyst body materials are the same during the catalyst AHA treatment.
[0034]
Here, when the heating temperature of the catalyst body is less than 800 ° C., the catalytic reaction or thermal decomposition reaction of the raw material gas becomes insufficient and the deposition rate tends to decrease. Mixing into the deposited film impairs the electrical characteristics of the film, resulting in film quality degradation, and heating above the melting point of the catalyst body loses its form stability and should be avoided. The heating temperature of the catalyst body is preferably below 1100 ° C. to 1800 ° C. below the melting point of its constituent materials.
[0035]
The catalyst body can be formed of at least one material selected from the group consisting of tungsten, tria-containing tungsten, molybdenum, platinum, palladium, vanadium, silicon, alumina, ceramics with metal attached, and silicon carbide.
[0036]
The purity of the polycrystalline semiconductor thin film formed by setting the purity of the catalyst body and the support body supporting the catalyst body to 99.99 wt% (4N) or more, preferably 99.999 wt% (5N) or more. Heavy metal contamination can be reduced.
[0037]
The substrate temperature is preferably a temperature equal to or lower than the strain point of the substrate, for example, 200 to 800 ° C., more preferably 300 to 400 ° C., so that efficient and high-quality film formation can be performed. When the substrate temperature is high, inexpensive borosilicate glass and aluminosilicate glass cannot be used, and the impurity doping concentration distribution is likely to change due to the influence of heat.
[0038]
When forming a polycrystalline silicon film by a normal thermal CVD method, the substrate temperature needs to be about 600 to 900 ° C., but the film formation according to the present invention does not require plasma or photoexcitation, It is extremely advantageous to be able to perform thermal CVD at a low temperature as described above. Since the substrate temperature at the time of catalytic CVD based on the present invention is low as described above, a glass such as a borosilicate glass or an aluminosilicate glass having a low strain point of 470 to 670 ° C. or a heat resistant resin as a substrate, for example, a glass substrate. A substrate or the like can be used. This is inexpensive and can be easily reduced in thickness, can be increased in size (1 m × 1 m or more), and a long rolled glass plate can be produced. For example, a thin film can be continuously or discontinuously produced on a long rolled glass plate using the above-described method.
[0039]
The source gas used to form the lower crystalline semiconductor thin film by vapor phase growth by biased or non-biased catalytic CVD according to the present invention is silicon hydride or its derivative, silicon hydride or its derivative and hydrogen, germanium, carbon or tin Mixtures of gases containing hydrogen, mixtures of silicon hydride or derivatives thereof with gases containing impurities consisting of Group III or V elements of the periodic table, silicon hydrides or derivatives thereof and hydrogen, germanium, carbon or tin And a mixture of a gas containing impurities and a gas containing impurities composed of Group III or V elements of the periodic table.
[0040]
By using the source gas as described above, a polycrystalline silicon film, a polycrystalline germanium film, a polycrystalline silicon-germanium film, or a polycrystalline silicon carbide film can be formed as a polycrystalline semiconductor thin film. .
[0041]
Then, during or after the growth of the semiconductor material thin film, a total amount of at least one group IV element such as tin, germanium, lead, etc. is appropriate (10¹⁵atoms / cc or more, for example, 10¹⁸-10²⁰atoms / cc) (further, the annealing process by the catalyst AHA treatment is performed in this state), the irregularities existing in the crystal grain boundaries of the polycrystalline semiconductor thin film are reduced, and the film stress is reduced to increase the carrier movement. It is easy to obtain a high-quality polycrystalline semiconductor. This group IV element can be mixed in the source gas as a gas component, or can be contained in the semiconductor material thin film by ion implantation or ion doping. Further, the oxygen, nitrogen and carbon concentrations in the polycrystalline semiconductor film formed according to the present invention are 1 × 10 3 respectively.¹⁹atoms / cc or less, preferably 5 × 10¹⁸atoms / cc or less is preferable, and the hydrogen concentration is preferably 0.01 atomic% or more. The sodium (Na) concentration is 1 × 10 in the SIMS lowest concentration region.¹⁸atoms / cc or less is preferred.
[0042]
In addition, it is desirable to heat-treat the catalyst body in a hydrogen-based gas atmosphere before performing the catalytic CVD (or bias catalytic CVD). This is because, when the heat treatment of the catalyst body is sufficient, the constituent material of the catalyst body may be released and mixed into the film formed. Such contamination can be eliminated by heating in the air. Therefore, after performing the baking for a predetermined time at a temperature higher than that at the time of film formation (for example, 2200 to 2500 ° C. for tungsten) with the hydrogenation gas filled in the film formation chamber, Heating is preferably performed so as to return to a temperature (eg, 1700 ° C. for tungsten), and then a raw material gas (so-called reaction gas) is supplied using a hydrogen-based gas as a carrier gas. Depending on the purity and material of the catalyst body, this empty baking process is performed only at the beginning, and is not necessarily performed before film formation.
[0043]
The catalytic AHA treatment has an action of selectively etching particularly amorphous components in the polycrystalline semiconductor thin film by a high-temperature hydrogen-based active species, and has a high crystallization rate, a large particle size (especially a grain size of several hundred nm or more). ), And a carrier impurity in the film is activated. At this time, the catalyst body temperature is 1600 to 1800 ° C., and the distance between the substrate and the catalyst body is 20 Improved processing effects, such as shortening the processing time by increasing the hydrogen carrier gas flow rate (increasing the gas pressure) and increasing the hydrogen-based active species, etc. Therefore, it may be changed arbitrarily.
[0044]
With the polycrystalline semiconductor thin film obtained by the treatment of the present invention, the channel, source and drain regions of MOSTFT, wiring, resistance, capacitance, electron emitter, or the like can be formed. In this case, if the catalyst AHA treatment is performed on these regions after the channel, source and drain regions are formed, ion activation of the n-type or p-type impurities can be performed.
[0045]
Further, in order to reduce oxygen penetration from the outside into the polycrystalline semiconductor thin film such as polycrystalline silicon, the crystal grain size is increased from the gate insulating film side to the outside in the polycrystalline silicon thin film, for example. The polycrystalline silicon thin film is preferably covered with an amorphous silicon thin film or a microcrystalline silicon-containing amorphous silicon thin film. In this case, by using general-purpose photolithography and etching techniques, the microcrystalline silicon or amorphous silicon thin film can be removed to form source and drain electrodes in contact with the polycrystalline silicon thin film.
[0046]
The present invention relates to a silicon semiconductor device, a silicon semiconductor integrated circuit device, a silicon-germanium semiconductor device, a silicon-germanium semiconductor integrated circuit device, a compound semiconductor device, a compound semiconductor integrated circuit device, a silicon carbide semiconductor device, a silicon carbide semiconductor integrated circuit device, Liquid crystal display device, organic or inorganic electroluminescence (EL) display device, field emission display (FED) device, light emitting polymer display device, light emitting diode display device, CCD area / linear sensor device, MOS sensor device, solar cell device It is suitable for forming a thin film.
[0047]
In this case, when manufacturing a semiconductor device having an internal circuit and a peripheral circuit, a solid-state imaging device, an electro-optical device, etc., the channel, source and drain regions of the MOSTFT constituting at least a part thereof are formed by the polycrystalline semiconductor thin film. Alternatively, a peripheral circuit integrated structure such as a drive circuit, a video signal processing circuit, and a memory circuit may be used.
[0048]
Moreover, it is good to set it as the EL element structure which has the cathode or anode connected to the drain or source of the said MOSTFT in the lower layer of the organic or inorganic electroluminescent layer (EL layer) for each color, respectively.
[0049]
In this case, if the cathode is also covered on the active elements such as the MOSTFT and the diode, the light emitting area is increased in the structure having the anode on the upper side, and the emitted light is incident on the active element due to the light shielding action of the cathode. Therefore, it is possible to prevent a leak current from being generated. Further, if the cathode or anode is deposited on the entire surface of each organic or inorganic EL layer for each color and between the respective layers, the entire surface is covered with the cathode or anode, so that the organic EL is weak against moisture. Prevents layer degradation and electrode oxidation, enabling long life, high quality, and high reliability. Covering with a cathode increases the heat dissipation effect, so the structure of the thin film changes due to heat generation (melting or recrystallization). As a result, a long life, high quality, and high reliability can be achieved. In addition, a high-precision, high-quality full-color organic EL layer can be formed with high productivity, so that the cost can be reduced.
[0050]
Further, when a black mask layer of chromium, chromium dioxide or the like is formed between the organic or inorganic EL layers for each color, light leakage between each color or between pixels is prevented, and the contrast is improved.
[0051]
When the present invention is applied to a field emission display (FED) device, its emitter (field emission cathode) is connected to the drain of the MOSTFT through the polycrystalline semiconductor thin film and on the polycrystalline semiconductor thin film. By the grown n-type polycrystalline semiconductor film, polycrystalline diamond film, nitrogen-containing or non-containing carbon thin film, or a large number of fine protrusion structures (for example, carbon nanotubes) formed on the surface of nitrogen-containing or non-containing carbon thin film It is good to form.
[0052]
In this case, a metal shielding film having a ground potential on the active element such as the MOSTFT or the diode (this is advantageous in terms of simplification of the process and the like if it is formed by the same process using the same material as the gate extraction electrode of the FED device). )), The gas in the hermetic container is positively ionized by the electrons emitted from the emitter and charged up on the insulating layer, and this positive charge forms an unnecessary inversion layer on the active element under the insulating layer. In other words, it is possible to prevent runaway of the emitter current caused by excess current flowing through the inversion layer. Further, when the phosphor emits light due to collision of electrons emitted from the emitter, it is possible to prevent leakage current from being generated due to the generation of electrons and holes in the gate channel of the TFT due to this light.
[0053]
Next, the present invention will be described in more detail with respect to preferred embodiments.
[0054]
First embodiment
A first embodiment of the present invention will be described with reference to FIGS.
[0055]
In this embodiment, the present invention is applied to a top gate type polycrystalline silicon CMOS (Complementary MOS) TFT.
[0056]
<Catalytic CVD method and catalytic AHA treatment and apparatus>
First, the catalytic CVD method and the catalytic AHA treatment used in this embodiment will be described. In the catalytic CVD method, a reaction gas composed of a hydrogen-based carrier gas and a source gas such as silane gas is brought into contact with a heated catalyst body such as tungsten, and radical deposition species or precursors thereof and activated hydrogen ions generated thereby. A high energy is applied to a hydrogen-based active species such as a polycrystalline semiconductor thin film such as polycrystalline silicon on a substrate. Then, after the film formation, the supply of the source gas is stopped or only the hydrogen-based carrier gas is supplied to perform the catalytic AHA treatment of the polycrystalline semiconductor thin film or the silicon ultrafine particles on the substrate (that is, the high temperature Selective reduction etching of amorphous components such as carbon or silicon by hydrogen-based active species such as hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions, or foreign materials such as oxide films on the surface of silicon ultrafine particles, organic stains, etc. The film is removed and diamond ultrafine carbon particles are formed.) These ultrafine silicon particles are used as seeds to form a polycrystalline silicon thin film having a large particle diameter, Heterogeneous films such as oxide films and organic stains on the surface are removed, and ultrafine carbon particles having a diamond structure are formed. These catalytic AHA treatment and catalytic CVD are repeated to obtain a polycrystalline semiconductor thin film such as polycrystalline silicon having a larger particle size and a predetermined film thickness.
[0057]
This catalytic CVD and catalytic AHA treatment is performed using a vacuum apparatus as shown in FIGS.
[0058]
According to this apparatus, a hydrogen-based carrier gas and a source gas 40 such as hydrocarbon (for example, methane) or silicon hydride (for example, monosilane, disilane, trisilane) (and B B as required)₂H₆And PH_ThreeIncluding a doping gas such as ) Is introduced from the supply conduit 41 into the film forming chamber 44 through a supply port (not shown) of the shower head 42. Inside the film forming chamber 44, there are a susceptor 45 for supporting the substrate 1 such as glass, and a shower head 42 with good heat resistance (desirably having a melting point equal to or higher than that of the catalyst 46). Further, for example, a catalyst body 46 such as a coiled tungsten and a shutter 47 that can be opened and closed are arranged. Although not shown, a magnetic seal is provided between the susceptor 45 and the film forming chamber 44. The film forming chamber 44 is followed by a front chamber that performs a pre-process, and is connected to a valve by a turbo molecular pump or the like. Exhausted.
[0059]
The substrate 1 is heated by a heating means such as a heater wire in the susceptor 45, and the catalyst body 46 is heated as a resistance wire to a melting point or lower (particularly 800 to 2000 ° C., in the case of tungsten, about 1600 to 1800 ° C.). Activated. Both terminals of the catalyst body 46 are connected to a DC or AC catalyst body power supply 48 and heated to a predetermined temperature by energization from the power supply.
[0060]
To carry out the catalytic CVD method, the degree of vacuum in the film forming chamber 44 is 1.33 × 10 6 in the state of FIG.^-Four~ 1.33 × 10^-6For example, hydrogen-based carrier gas 50 to 100 SCCM is supplied and the catalyst body is heated to a predetermined temperature and activated, and then silicon hydride (for example, monosilane) gas 1 to 20 SCCM (and B B if necessary)₂H₆And PH_ThreeAn appropriate amount of a doping gas such as is also included. ) Is introduced from the supply conduit 41 through the supply port 43 of the shower head 42 so that the gas pressure is 0.133 to 13.3 Pa, for example, 1.33 Pa. Here, the hydrogen-based carrier gas is any gas in which an appropriate amount of an inert gas is mixed with hydrogen, such as hydrogen, hydrogen + argon, hydrogen + helium, hydrogen + neon, hydrogen + xenon, hydrogen + krypton, etc. Good (hereinafter the same). Depending on the type of raw material gas or the material of the catalyst body, the hydrogen-based carrier gas is not necessarily required.
[0061]
Then, as shown in FIG. 6, the shutter 47 is opened, and at least a part of the hydrogen-based carrier gas and the raw material gas 40 is contacted with the catalyst body 46 to be catalytically decomposed, and high energy is obtained by catalytic decomposition reaction or thermal decomposition reaction. A group of reactive species such as ions such as silicon and radicals (that is, deposited species or precursors thereof and radical hydrogen ions) is formed. Predetermined thin films such as polycrystalline silicon on the substrate 1 where the reactive species 50 such as ions and radicals thus generated are held at a high energy below the strain point of the substrate, for example, 200 to 800 ° C. (especially 300 to 400 ° C.). Vapor phase growth.
[0062]
Thus, without generating plasma, the catalytic action of the catalyst body 46 and energy due to its thermal energy are given to the reactive species without generating plasma, so that the source gas can be efficiently converted into reactive species and uniformly heated on the substrate 1 by thermal CVD. Can be deposited.
[0063]
In addition, since the energy of the deposited species is large even when the substrate temperature is lowered, the desired high-quality film can be obtained. Therefore, the substrate temperature can be further lowered as described above, and a large and inexpensive insulating substrate (method) A glass substrate such as silicate glass or aluminosilicate glass, or a heat-resistant resin substrate such as polyimide) can be used. In this respect, the cost can be reduced.
[0064]
Needless to say, since no plasma is generated, there is no damage caused by plasma, and a low-stress production film can be obtained, and a much simpler and cheaper apparatus can be realized as compared with the plasma CVD method.
[0065]
In this case, the operation can be performed under reduced pressure (for example, 0.133 to 1.33 Pa) or under normal pressure, but the normal pressure type is simpler and less expensive than the reduced pressure type. Even in the normal pressure type, a high quality film with good density, uniformity and adhesion can be obtained as compared with the conventional atmospheric pressure CVD. Also in this case, the normal pressure type has a higher throughput than the reduced pressure type, so that the productivity is high and the cost can be reduced.
[0066]
In the catalytic CVD described above, the substrate temperature rises due to the secondary heat generated by the catalyst body 46. However, as described above, the substrate heating heater 51 may be installed as necessary. Moreover, although the catalyst body 46 is coiled (other than this, a mesh, a wire, and a porous plate shape may also be sufficient), it further increases the contact area with gas by making it into multiple steps (for example, 2 to 3 steps) in the gas flow direction. It is good. In this CVD, since the substrate 1 is disposed above the shower head 42 on the lower surface of the susceptor 45, particles generated in the film forming chamber 44 fall and adhere to the substrate 1 or a film thereon. There is no.
[0067]
<Catalyst AHA treatment and apparatus>
In this embodiment, the above apparatus is used as it is, the supply of the raw material gas is stopped after the vapor phase growth by catalytic CVD, and only the hydrogen-based carrier gas is supplied into the film forming chamber 44 at a flow rate higher than that at the time of catalytic CVD. To the semiconductor material thin film or ultrafine particles with a similar hydrogen carrier gas, and a selective reduction action of a large amount of high temperature hydrogen-based active species to produce amorphous silicon. Etching, annealing for polycrystallization, or cleaning of organic substances, etc., and repeating the process of catalytic CVD and catalyst AHA for the semiconductor material thin film a predetermined number of times to obtain polycrystalline silicon with the desired film thickness A polycrystalline semiconductor thin film such as a thin film is formed.
[0068]
In this catalytic AHA treatment, organic substances and oxides on the surface of the fine particles are cleaned and removed by the hydrogen-based active species decomposed and generated by the heated catalyst body, making it easy to polycrystallize using the semiconductor material thin film as a seed, and a high crystallization rate A thin film based on a polycrystal having a large grain size (especially a grain size of several hundred nm or more) can be formed, or a semiconductor material thin film is more easily crystallized by etching its amorphous component. In this process, a polycrystalline semiconductor thin film can be formed and carrier impurities in the film are activated. At that time, the catalyst body temperature is 1600 to 1800 ° C., the distance between the substrate and the catalyst body is 20 to 50 mm, the substrate temperature is 300 to 400 ° C., and the hydrogen carrier gas is hydrogen or hydrogen and an inert gas (argon) as described above. , Helium, xenon, krypton, radon, etc.), and in the case of a mixed gas, the oxidative deterioration of the catalyst body can be prevented by setting the hydrogen content ratio to 50 mol% or more. The hydrogen or hydrogen-containing gas used during the catalyst AHA treatment may be the same as the hydrogen-based carrier gas used in the vapor phase growth of biased or non-biased catalytic CVD, but the gas flow rate is 300 to 1000 SCCM, the gas pressure is 10 to 50 Pa. It is preferable to increase the temperature (0.1 to several Pa in the case of biased or non-biased catalytic CVD) to increase heat conduction by gas and increase the generation amount of hydrogen-based active species and the like.
[0069]
FIG. 7 shows the introduction time and timing of the hydrogen-based carrier gas and source gas in the catalytic CVD and catalytic AHA processes in the case of forming a polycrystalline silicon thin film, and FIG. 8 shows a flow meter (MFC) and adjustment. A gas introduction system incorporating a valve is shown.
[0070]
First, before film formation, the substrate 1 is loaded into the chamber (film formation chamber) 44 through the gate valve, placed on the susceptor 45, and then the exhaust system is activated to exhaust the chamber 44 to a predetermined pressure. At the same time, the heater built in the susceptor 45 is operated to heat the substrate 1 to a predetermined temperature.
[0071]
Then, first, hydrogen-based carrier gas 300 to 1000 SCCM, for example, 500 SCCM is introduced into the chamber 1 by the gas introduction system. A part of the introduced hydrogen gas becomes hydrogen-based active species such as activated hydrogen ions by the catalytic decomposition reaction by the heating catalyst 46, reaches the substrate surface, and cleans the surface of the substrate 1. Thereafter, the hydrogen carrier gas is set to 150 SCCM.
[0072]
In this way, the gas introduction system is operated in a state where the hydrogen-based carrier gas is supplied into the chamber 44, and the source gas (methane or monosilane 15 SCCM) is introduced into the chamber 44. The introduced source gas generates a deposition species by the thermal catalytic reaction and thermal decomposition reaction of the heating catalyst body 46, and vapor-phase grows on the substrate surface as a polycrystalline silicon thin film or the like.
[0073]
Thereafter, the introduction of the source gas is stopped, the source gas is discharged from the chamber 44, and only the hydrogen-based carrier gas is introduced at a flow rate of 300 to 1000 SCCM, for example, 500 SCCM. Hydrogen-based active species such as activated hydrogen ions generated in the above act on the polycrystalline silicon thin film and the like to etch the amorphous component, thereby forming polycrystalline silicon grains from which the amorphous component has been removed. By using this as a seed, a polycrystalline silicon thin film having a high crystallization rate and a large grain size in which crystallization is promoted is obtained.
[0074]
The polycrystalline silicon thin film thus obtained is further subjected to catalytic AHA treatment, and then the above-described catalytic CVD is performed again to grow a polycrystalline silicon thin film on the polycrystalline silicon thin film as a seed. By repeatedly performing AHA treatment and catalytic CVD, the polycrystalline silicon thin film with high crystallization rate and large grain size is finally formed with the desired film thickness while controlling the thickness of the polycrystalline silicon thin film. can do.
[0075]
As described above, the radical action of the hydrogen-based active species causes thermal energy to move to the film and locally increase the temperature, and the semiconductor thin film has an amorphous component etched to promote crystallization. A polycrystalline semiconductor thin film with high carrier mobility and high quality can be obtained, and when silicon oxide is present on or in the polycrystalline silicon thin film, it undergoes a reduction reaction with this. Since SiO or the like is generated and evaporated, silicon oxide on or in the thin film can be reduced / removed, and a high-carrier mobility, high-quality polycrystalline silicon thin film and the like can be obtained.
[0076]
In addition, microcrystalline silicon-containing amorphous silicon or amorphous silicon-containing microcrystalline silicon thin film is crystallized using seed ultrafine particles as a seed, and polycrystalline silicon thin film is promoted to increase the crystallinity and has a large grain size. Turn into a film. Moreover, since the amorphous silicon contained in the film is etched under the action of the hydrogen-based active species, a polycrystalline silicon thin film having a high crystallization rate and a large grain size is formed.
[0077]
During the catalyst AHA treatment, carrier impurities present in the semiconductor thin film are activated at a high temperature, and an optimum carrier impurity concentration can be obtained in each region, and a large amount of high-temperature hydrogen-based active species (hydrogen molecules) , Hydrogen atoms, activated hydrogen ions, etc.) (reduction and removal of adsorbed gas and organic residue etc. on the substrate, etc.) are possible, and the catalyst body is also difficult to be oxidized and deteriorated. For example, silicon dangling bonds are eliminated and the characteristics are improved.
[0078]
By repeating the annealing by the catalytic AHA treatment and the vapor deposition by bias or non-biased catalytic CVD of the semiconductor thin film until a desired film thickness is obtained, the semiconductor thin film is already polycrystallized by the catalytic AHA treatment. It becomes easy to grow in a state where it is easily polycrystallized, and an intended high crystallization rate and high quality polycrystalline semiconductor thin film can be obtained with a predetermined film thickness. That is, by multi-catalyst AHA treatment in which catalytic CVD and catalyst AHA treatment are repeated, for example, microcrystalline silicon-containing amorphous silicon or amorphous silicon and microcrystalline silicon-containing polycrystalline silicon thin film formed by biased or non-biased catalytic CVD are converted into catalytic AHA. A polycrystalline silicon thin film is formed by the treatment, and the polycrystalline silicon thin film has a high crystallinity. Further, the polycrystalline silicon thin film is vapor-phase grown by catalytic CVD using the polycrystalline silicon thin film as a seed, and further the catalytic AHA treatment. Thus, a polycrystalline silicon thin film having a high crystallization rate and a large grain size can be formed.
[0079]
In addition, since both of the above-described catalytic CVD and catalytic AHA treatment can be performed without generating plasma, there is no damage caused by plasma, a low-stress generated film can be obtained, and a simple and inexpensive apparatus compared to the plasma CVD method can be obtained. realizable.
[0080]
FIG. 9 shows the Raman spectrum of the polycrystalline silicon thin film obtained by the above multi-catalyst AHA treatment (repetition of catalytic CVD and catalyst AHA treatment) according to the present embodiment in accordance with the number of repetitions. According to this result, the gas flow rate during silicon deposition (depo) by catalytic CVD was determined as SiH._Four: H₂= 5: 500 SCCM, catalyst temperature = 1800-2000 ° C., substrate temperature = 400 ° C., various catalyst AHA treatment conditions, and the number of repetitions was changed, the number of repetitions was increased and the processing time was lengthened, When the hydrogen flow rate during processing is increased, amorphous (amorphous) silicon and microcrystalline silicon decrease and polycrystalline silicon increases in the order of sample # 1 → # 2 → # 3 → # 4. It is clear that the grain size is increased and the crystallization is increased. Here, AHA1 may be a cleaning process of silicon and / or carbon fine particles on the substrate surface before film formation, and the original catalyst AHA process is AHA2-4.
[0081]
FIG. 10 shows the crystallization rate of each sample in comparison with the presence or absence of polycrystals in the polycrystalline silicon thin film. According to this, it can be seen that the crystallization rate increases in the order of samples # 1 → # 2 → # 3 → # 4, and increases when the crystallite (Im) is included.
[0082]
These results indicate that the treatment according to the present invention is a very excellent method for forming a polycrystalline semiconductor thin film having a high crystallization ratio and a large grain size.
[0083]
In the present embodiment, in the above-described catalytic CVD, the purity of, for example, a catalyst body of 0.4 mmφ tungsten wire and a support body (not shown) of, for example, 0.8 mmφ molybdenum wire supporting the same becomes a problem. However, the conventional purity: 3N (99.9 wt%) is increased to 4N (99.99 wt%) or more, preferably 5N (99.999 wt%) or more, so that the polycrystalline silicon thin film by catalytic CVD is increased. It has been demonstrated that heavy metal contamination such as iron, nickel, and chromium can be reduced. FIG. 11 (A) shows the concentration of heavy metals such as iron, nickel and chromium in the film with a purity of 3N. By increasing this to 5N, heavy metals such as iron, nickel and chromium are shown in FIG. 11 (B). It has been found that the concentration can be greatly reduced. As a result, the TFT characteristics can be improved.
[0084]
<Manufacture of top gate type CMOS TFT>
Next, an example of manufacturing a top gate type CMOS TFT according to this embodiment will be described.
[0085]
First, a silicon nitride film having a thickness of 100 to 200 nm and a silicon oxide film is formed on the insulating substrate 1 such as quartz glass, crystallized glass, borosilicate glass, and aluminosilicate glass shown in FIG. A base protective film having a thickness of 100 to 200 nm is formed, and a recess 190 having a depth (step) of 50 to 200 nm, 10 μm length × 30 μm width is formed at least in the TFT formation region by general-purpose photolithography and etching techniques. At this time, impurities from the glass substrate (Na⁺For example, a silicon nitride film is preferably formed to prevent intrusion. At this time CF_FourGas plasma etching, RIE (Reactive Ion Etching), or wet etching with a hydrofluoric acid-based etchant may be performed.
[0086]
When a heat-resistant resin substrate is used as the substrate 1, in order to form a recess having a step with a predetermined shape and size in at least a TFT formation region of a heat-resistant resin substrate such as polyimide, a polyimide substrate having a thickness of 100 μm, for example, A die having a predetermined shape and size of 50 to 200 nm, 10 μm in length × 30 μm in width is stamped to form a recess having a step having the same shape and size as the die. Alternatively, a heat-resistant resin film such as polyimide having a thickness of 5 to 10 μm is formed on a metal plate such as stainless steel as a reinforcing material according to the dimensions of coating, screen printing, and the like. A die having a predetermined shape and size of 30 μm may be stamped to form a recess having a step having the same shape and size as the die at least in the TFT formation region. Alternatively, a step having a predetermined shape and dimensions of 1 to 2 μm in depth, 10 μm in length and 30 μm in width is formed by etching in at least a TFT formation region of a metal plate such as stainless steel, and a heat resistant resin film such as polyimide is coated to be predetermined. You may form the recessed part which has a level | step difference of a shape and a dimension.
[0087]
Note that the glass material of the substrate 1 is properly used depending on the process temperature of TFT formation. In the case of a low temperature of 200 to 500 ° C .: A glass substrate (500 × 600 × 0.5 to 1.1 μm thickness) such as borosilicate or aluminosilicate glass, or a heat resistant resin substrate may be used.
In the case of a high temperature of 600 to 1000 ° C .: A heat-resistant glass substrate (6 to 12 inches φ, 700 to 800 μm thickness) such as quartz glass or crystallized glass may be used.
[0088]
Next, as shown in (2) of FIG. 1, silicon powder, carbon powder, or ultrafine particles 100A mixed with these are adhered and dispersed in the recess 190. For example, silicon powder, carbon powder, or ultrafine particles of carbon powder or silicon powder and carbon powder may be adhered and dispersed in the recess by polishing with silicon powder or carbon powder or a paste containing silicon powder and carbon powder. Alternatively, silicon powder or carbon powder or a mixture of these powders is dispersed in an organic solvent (acetone, ethyl alcohol, ethyl alcohol / acetone, etc.), and the silicon powder or carbon powder is placed in the recess by the power and time management of the ultrasonic cleaner. Alternatively, ultrafine particles in which these are mixed may be adhered and dispersed. These powders 100A desirably have a size smaller than the recess 190, for example, 50 to 200 nm.
[0089]
Next, as shown in FIG. 1 (3), the surface of the silicon powder and / or the carbon powder 100A is cleaned by the action of hydrogen-based active species in the catalyst AHA treatment, so that the foreign matter such as an oxide film and organic dirt is removed. The film is removed to obtain cleaned ultrafine carbon particles 100B having a silicon or diamond structure. This catalytic AHA treatment may be carried out as an integral part of continuous work before film formation by the following catalytic CVD or high-density catalytic CVD method or the like.
[0090]
This catalytic AHA treatment is a method in which a raw material gas is not supplied in the catalytic CVD method. Specifically, a hydrogen carrier gas is supplied under reduced pressure to bring the catalyst body to a predetermined temperature (about 1600 to 1800 ° C.). For example, set to about 1700 ° C.), for example, 300 to 1000 SCCM of hydrogen-based carrier gas is supplied to a gas pressure of 10 to 50 Pa, and a large amount of high-temperature hydrogen-based active species (such as activated hydrogen ions) is generated. These are sprayed on the ultrafine particles 100A. As a result, high thermal energy possessed by a large amount of high-temperature hydrogen-based active species (activated hydrogen ions, etc.) is transferred, the temperature is locally increased, organic substances on the surface of ultrafine particles are cleaned by etching, and amorphous. Silicon ultrafine particles or carbon ultrafine particles 100B (with a diamond structure) are formed by selective etching of the components, and are used as the nucleus of polycrystalline silicon growth.
[0091]
Next, as shown in FIG. 1 (4), for example, a periodic table group IV element, for example, 10 tin is added by catalytic CVD (or multi-catalyst AHA treatment).¹⁸-10²⁰Atomized / cc-doped (this may be doped by CVD or ion implantation after film formation). Polycrystalline silicon thin film 7 is vapor-phase grown to a thickness of 50 to 100 nm, for example, 50 nm, using ultrafine particles 100B as seeds. Let However, this tin doping is not necessarily required (hereinafter the same). When performing this catalytic CVD, a hydrogen-based carrier gas is supplied to heat the catalyst body to a predetermined temperature (about 1600 to 1800 ° C., for example, 1700 ° C. setting) in order to prevent oxidative deterioration of the catalyst body. Need to cool the catalyst body to a temperature at which there is no problem and cut the hydrogen-based carrier gas.
[0092]
At this time, if necessary, an appropriate amount of n-type impurities (phosphorus, arsenic, antimony) or p-type impurities (boron, etc.) is added to monosilane, for example, 10¹⁵-10¹⁸An n-type or p-type polycrystalline silicon thin film may be formed by containing atoms / cc. Further, a microcrystalline silicon or polycrystalline silicon thin film is grown to a thickness of 10 to 30 nm by catalytic CVD on the ultrafine particles 100B, and then the catalyst AHA treatment is performed thereon. Further, the polycrystalline silicon thin film is formed thereon by catalytic CVD. The film may be grown to a thickness of 10 to 30 nm, further subjected to catalytic AHA treatment, and a polycrystalline silicon thin film may be further grown to a thickness of 10 to 30 nm by catalytic CVD, and further subjected to catalytic AHA treatment. By this method, a thicker polycrystalline silicon thin film having a larger grain size can be formed.
[0093]
In this case, using the apparatus shown in FIGS. 5 and 6, for example, a tin-doped polycrystalline silicon thin film is vapor-phase grown by the above-described catalytic CVD under the following conditions, and then the catalytic AHA treatment is performed under the following conditions. Then, the polycrystalline silicon thin film may be further polycrystallized, and the catalytic CVD and catalytic AHA treatment may be repeated to form the polycrystalline silicon thin film 7 having a thickness of 50 nm. For example, a film having a thickness of 10 to 30 nm is grown by catalytic CVD, subjected to a catalyst AHA treatment, a film having a thickness of 10 to 30 nm is grown by catalytic CVD, and further subjected to a catalyst AHA treatment, and then a film having a thickness of 10 to 30 nm by catalytic CVD. Is finally obtained to obtain a polycrystalline silicon thin film having a desired film thickness.
[0094]
Film formation of tin-containing polycrystalline silicon by catalytic CVD:
Hydrogen (H₂) As a carrier gas and source gas, monosilane (SiH)_Four), Tin hydride (SnH_Four) Are mixed at an appropriate ratio. H₂Flow rate: 50-150 SCCM, SiH_FourFlow rate: 1-20 SCCM, SnH_FourFlow rate: 1-20 SCCM. At this time, an appropriate amount of n-type phosphorus, arsenic, antimony, or the like is mixed into the silane-based gas (such as silane, disilane, or trisilane), or an appropriate amount of p-type boron is mixed. Alternatively, a tin-containing polycrystalline silicon thin film having a p-type impurity carrier concentration may be formed.

[0095]
Catalyst AHA treatment:
The catalyst AHA treatment is a method in which a source gas is not supplied in catalytic CVD. Specifically, a hydrogen carrier gas is supplied at a gas flow rate of 300 to 1000 SCCM and a gas pressure of 10 to 50 Pa under a reduced pressure so that a catalyst body is predetermined. Heating to a temperature (about 1600 to 1800 ° C., for example, about 1700 ° C.) generates a large amount of high-temperature hydrogen-based active species, and sprays them onto, for example, a polycrystalline silicon thin film formed on the substrate. As a result, the thermal energy of a large amount of high-temperature hydrogen-based active species moves to these films, raising their film temperature, and when containing amorphous silicon or microcrystalline silicon, Amorphous components are selectively etched to crystallize them, and the polycrystalline silicon thin film is highly crystallized to form a large-diameter tin-containing polycrystalline silicon film, which is crystallized by the effect of group IV elements such as tin. Irregularities and stress existing at the grain boundaries can be reduced, and a high-carrier mobility and high-quality tin-containing polycrystalline silicon thin film can be formed.
[0096]
In addition, the above hydrogen-based active species, when silicon oxide is present on the polycrystalline silicon thin film or in the film, is reduced with this to generate SiO and the like, and is removed by evaporation. Silicon oxide in the film can be reduced / removed, and a high-carrier mobility and high-quality polycrystalline silicon thin film can be formed. When this catalyst AHA treatment is performed after the formation of the gate channel / source / drain described later, the thermal energy of a large amount of high-temperature hydrogen-based active species is transferred to these films to increase their film temperature and promote crystallization. At the same time, it is implanted into the gate channel / source / drain, and carrier impurities (phosphorus, arsenic, boron, etc.) are ion activated.
[0097]
An example is shown in which a silicon nitride film, a silicon oxide film, and a tin-containing polycrystalline silicon thin film are continuously formed by catalytic CVD. First, when each film is formed in the same chamber, the hydrogen-based carrier gas is always supplied, and the catalyst body is heated to a predetermined temperature to be in a standby state, and may be processed as follows.
[0098]
Monosilane is mixed with monosilane at an appropriate ratio to form a silicon nitride film having a predetermined film thickness, and after sufficiently discharging the previous source gas, monosilane and He diluted O are continuously added.₂Are mixed at an appropriate ratio to form a silicon oxide film having a predetermined thickness, and after sufficiently discharging the previous source gas, etc., monosilane and SnH_FourAre mixed at an appropriate ratio to form a tin-containing polycrystalline silicon thin film having a predetermined thickness by catalytic CVD. After film formation, the raw material gas is cut, the catalyst body is cooled to a temperature at which there is no problem, and the hydrogen-based carrier gas is cut. Note that the source gas at the time of forming the insulating film may be decreased or increased in inclination to form an insulating film for inclined bonding.
[0099]
Alternatively, when each chamber is formed independently, a hydrogen-based carrier gas is constantly supplied into each chamber, the catalyst body is heated to a predetermined temperature and is put on standby, and processing may be performed as follows. Transfer to the A chamber and mix monosilane with ammonia in an appropriate ratio to form a silicon nitride film having a predetermined thickness. Then move to chamber B and dilute O with monosilane.₂Are mixed at an appropriate ratio to form a silicon oxide film. Next, transfer to C chamber, monosilane and SnH_FourAre mixed at an appropriate ratio to form a tin-containing polycrystalline silicon thin film. If necessary then move to chamber B and dilute monosilane with He₂A polycrystalline silicon film is formed by catalytic CVD after mixing them at an appropriate ratio. After film formation, the raw material gas is cut, the catalyst body is cooled to a temperature at which there is no problem, and the hydrogen-based carrier gas is cut. At this time, the hydrogen-based carrier gas and the respective source gases may be constantly supplied into the respective chambers to be in a standby state.
[0100]
Here, as the film forming conditions of each film (however, the film forming conditions of the polycrystalline silicon thin film are omitted since they are described above), a hydrogen-based carrier gas (hydrogen, argon + hydrogen, helium + hydrogen, neon + Hydrogen, etc.) is constantly supplied, and the flow rate, pressure, and susceptor temperature are controlled to the following predetermined values.
Pressure inside the chamber: about 1 to 15 Pa, for example 10 Pa
Susceptor temperature: 300-400 ° C
Hydrogen carrier gas flow rate (in the case of mixed gas, hydrogen is 70 to 80 mol% or more): 50 to 150 SCCM
[0101]
The silicon nitride film is formed to a thickness of 50 to 200 nm under the following conditions.
Hydrogen (H₂) As carrier gas and monosilane (SiH) as source gas_Four) To ammonia (NH_Three) Are mixed at an appropriate ratio.
Hydrogen (H₂) Flow rate: 50-150 SCCM,
SiH_FourFlow rate: 1-20 SCCM, NH_ThreeFlow rate: 5-60 SCCM
[0102]
The silicon oxide film is formed to a thickness of 100 to 200 nm under the following conditions.
Hydrogen (H₂) As a carrier gas and source gas, monosilane (SiH)_Four) To He dilution O₂Formed by mixing at an appropriate ratio.
Hydrogen (H₂) Flow rate: 50-150 SCCM,
SiH_FourFlow rate: 1-20 SCCM, He dilution O₂Flow rate: 1-2 SCCM
[0103]
As described above, after growing the polycrystalline silicon thin film 7 using the ultrafine particles 100B as a seed in the recess 190, the substrate surface is optically polished to remove the polycrystalline silicon thin film in regions other than the recess. Also good. As a result, a flat surface substrate in which a tin-containing or non-containing large grain polycrystalline silicon thin film is embedded in the recess is formed. However, at this time, since an oxide film and an organic stain film are formed on the surface of the optically polished tin-containing or non-containing large grain polycrystalline silicon thin film, after the cleaning with the catalyst AHA treatment, Processing should be done.
[0104]
Then, a MOSTFT using the polycrystalline silicon thin film 7 as a source, channel and drain region is manufactured.
[0105]
That is, as shown in FIG. 2 (5), after the polycrystalline silicon thin film 7 is made into an island by general-purpose photolithography and etching, the threshold value (V) is controlled by controlling the impurity concentration in the channel region for the nMOS TFT._th) Is masked with a photoresist 9, and p-type impurity ions (for example, boron ions) 10 are, for example, 5 × 10 5 by ion implantation or ion doping.¹¹atoms / cm²Doping with a dose of 1 × 10¹⁷An acceptor concentration of atoms / cc is set, and a polycrystalline silicon thin film 11 is obtained in which the conductivity type of the polycrystalline silicon thin film 7 is changed to p-type.
[0106]
Next, as shown in FIG. 2 (6), V by the impurity concentration control of the channel region for the pMOS TFT._thThis time, the nMOS TFT portion is masked with a photoresist 12, and n-type impurity ions (for example, phosphorus ions) 13 are, for example, 1 × 10 6 by ion implantation or ion doping.¹²atoms / cm²Doping with a dose of 2 × 10¹⁷The polycrystalline silicon thin film 14 is set to a donor concentration of atoms / cc, and the polycrystalline silicon thin film 7 is n-type in conductivity type. If there is a silicon oxide film on the polycrystalline silicon thin film 7, it is removed and the threshold value (V_th) Optimized ion implantation or ion doping.
[0107]
Next, as shown in (7) of FIG. 3, after performing the above catalyst AHA treatment for crystallization promotion and activation of impurities in the film if necessary, silicon oxide of the gate insulating film is formed by catalytic CVD or the like. After forming the film 50 nm thick 8, the phosphorus-doped polycrystalline silicon film 15 as the gate electrode material is replaced with a PH of 2-20 SCCM, for example._ThreeAnd a thickness of, for example, 400 nm by a catalytic CVD method similar to that described above under the supply of 20 SCCM monosilane.
[0108]
Next, as shown in FIG. 3 (8), a photoresist 16 is formed in a predetermined pattern, and using this as a mask, the phosphorus-doped polycrystalline silicon film 15 is patterned into a gate electrode shape. Further, if necessary, a photoresist is formed. After removing 16, as shown in FIG. 3 (9), a silicon oxide film 17 as a gate electrode protective film is formed to a thickness of 20 to 30 nm by, for example, catalytic CVD or the like.
[0109]
Next, as shown in (10) of FIG. 3, the pMOS TFT portion is masked with a photoresist 18, and, for example, phosphorus ions 19 which are n-type impurities are ion-implanted by ion implantation or ion doping, for example, 1 × 10.¹⁵atoms / cm²Doping with a dose of 2 × 10²⁰The donor concentration is set to atoms / cc, and nMOSTFT n⁺A type source region 20 and a drain region 21 are formed.
[0110]
Next, as shown in (11) of FIG. 4, the nMOS TFT portion is masked with a photoresist 22, and, for example, boron ions 23, which are p-type impurities, are ionized by ion implantation or ion doping, for example, 1 × 10.¹⁵atoms / cm²Doping with a dose of 2 × 10²⁰The acceptor concentration is set to atoms / cc and the pMOSTFT p⁺A type source region 24 and a drain region 25 are formed.
[0111]
Thus, a gate, a source, and a drain are formed, but these can be formed by a method other than the above-described process.
[0112]
That is, after the step (4) in FIG. 1, the polycrystalline silicon thin film 7 is islanded in the pMOSTFT and nMOSTFT regions, and n-type impurities such as phosphorous ions, for example, phosphorus ions are implanted into the pMOSTFT region by 1 × 10¹²atoms / cm²Doping with a dose of 2 × 10¹⁷The donor concentration is set to atoms / cc, and a p-type impurity such as boron ion is 5 × 10 5 in the nMOS TFT region.¹¹atoms / cm²Doping with a dose of 1 × 10¹⁷The acceptor concentration of atoms / cc is set, the impurity concentration of each channel region is controlled, and V_thTo optimize.
[0113]
Then, each source / drain region is formed with a photoresist mask by a general-purpose photolithography technique. In the case of an nMOS TFT, an n-type impurity such as arsenic or phosphorus ion is introduced by 1 × 10 5 by ion implantation or ion doping.¹⁵atoms / cm²Doping with a dose of 2 × 10²⁰The donor concentration is set to atoms / cc, and in the case of a pMOS TFT, a p-type impurity such as boron ion is 1 × 10 1 by ion implantation or ion doping.¹⁵atoms / cm²Doping with a dose of 2 × 10²⁰The acceptor concentration is set to atoms / cc.
[0114]
Thereafter, if necessary, a catalyst AHA treatment is performed to activate impurities in the film, and then a silicon oxide film is formed as a gate insulating film. If necessary, a silicon nitride film and a silicon oxide film are continuously formed. Form.
[0115]
That is, if necessary, after the catalyst AHA treatment, the hydrogen-based carrier gas and the monosilane are diluted with He diluted O by continuous catalytic CVD.₂Are mixed at an appropriate ratio to form a silicon oxide film 8 having a thickness of 20 to 30 nm, and if necessary, NH is added to hydrogen carrier gas and monosilane._ThreeAre mixed at an appropriate ratio to form a silicon nitride film having a thickness of 10 to 20 nm, and further a silicon oxide film is formed to have a thickness of 20 to 30 nm under the above conditions. Thereafter, a gate electrode is formed by the same general-purpose catalytic CVD method and photolithography technique as described above.
[0116]
After forming the gate, source, and drain, as shown in FIG. 4 (12), the hydrogen carrier gas 150 SCCM is commonly used on the entire surface by the same catalytic CVD method as described above, and 1-2 SCCM helium gas dilution is performed. O₂The silicon oxide film 26 is formed to a thickness of, for example, 100 to 200 nm under a monosilane supply of 15 to 20 SCCM, and a PH of 1 to 20 SCCM._Three, 1-2 SCCM helium diluted O₂A phosphine silicate glass (PSG) film 27 is formed to a thickness of 300 to 400 nm under a monosilane supply of 15 to 20 SCCM, and NH of 50 to 60 SCCM is formed._ThreeUnder the supply of 15-20 SCCM monosilane, the silicon nitride film 28 is formed to a thickness of, for example, 100-200 nm to form a laminated insulating film. Thereafter, ion activation is performed by, for example, RTA (Rapid Thermal Anneal) treatment at about 1000 ° C. for 20 to 30 seconds to obtain carrier impurity concentrations set in each region.
[0117]
Next, as shown in FIG. 4 (13), a contact window is opened at a predetermined position of the insulating film, and an electrode material such as aluminum containing 1% Si is formed on the entire surface including each contact hole by a sputtering method or the like. It is deposited to a thickness and patterned to form the source or drain electrode 29 (S or D) and the gate extraction electrode or wiring 30 (G) of each of the pMOS TFT and nMOS TFT, thereby forming each top gate type CMOS TFT. . This is followed by hydrogenation and sintering in a forming gas at 400 ° C. for 1 h.
[0118]
Instead of forming the gate electrode described above, a sputtered film of heat-resistant metal such as Mo-Ta alloy is formed on the entire surface with a thickness of 400 to 500 nm, and gate electrodes of nMOS TFT and pMOS TFT are formed by general-purpose photolithography and etching techniques. You can do it.
[0119]
As described above, according to the present embodiment, the following excellent effects (a) to (k) can be obtained.
[0120]
(A) A concave portion having a step having an appropriate shape and size is formed at an arbitrary designated position on the substrate, and ultrafine particles such as silicon powder are adhered and dispersed therein, and by the action of hydrogen-based active species in the catalyst AHA treatment, The ultrafine particles can be selectively removed by etching, and the oxide film and organic stains on the surface of the ultrafine particles can be removed. By a CVD method or the like, a polycrystalline silicon thin film having a large particle size with little variation can be formed in a specified region.
[0121]
(B) A high-performance, high-quality TFT can be formed at any specified location on the insulating substrate, and the integrated circuit substrate can be freely formed.
[0122]
(C) If necessary, the surface where the large-grain polycrystalline silicon thin film is embedded in the concave portion having a step having an appropriate size and shape in the TFT formation region on the insulating substrate is polished to obtain a flat large Since a substrate having a grain size polycrystalline silicon thin film surface can be obtained, high performance, high quality polycrystalline silicon semiconductor devices, electro-optical devices and the like can be manufactured.
[0123]
(D) When catalytic AHA treatment is performed on a polycrystalline semiconductor thin film formed on a substrate using ultrafine particles as seeds for crystal growth, a large amount of thermal energy possessed by high-temperature hydrogen-based active species is transferred to the film. The temperature of the film etc. is increased locally. As a result, the amorphous component is etched, so that the amorphous silicon or microcrystalline silicon thin film becomes polycrystalline, the polycrystalline silicon thin film has a high crystallinity, and a polycrystalline silicon thin film having a large grain size and a high crystallization rate is obtained. Thus, carrier mobility can be improved. Further, when a similar semiconductor thin film is vapor-grown on this thin film, and the catalytic AHA treatment and the vapor phase growth are repeated, polycrystalline silicon and the like are highly crystallized, and have a high crystallization rate and a large particle size. A polycrystalline silicon thin film or the like can be formed. As a result, not only the top gate type, but also the bottom gate type and dual gate type MOS TFT can obtain a polycrystalline silicon thin film having a large grain size with a high crystallization rate of high carrier (electron / hole) mobility. In addition, it is possible to manufacture a high-speed, high-current density semiconductor device, an electro-optical device, and a high-efficiency solar cell using the high-performance semiconductor thin film such as polycrystalline silicon.
[0124]
(E) Furthermore, when silicon oxide exists on a film such as a polycrystalline silicon thin film or in a film or at a grain boundary, it reacts with this to form and evaporate SiO. Silicon oxide can be reduced and removed, and mobility can be improved.
[0125]
(F) When performing film formation by catalytic CVD or high-density catalytic CVD, depending on the type and temperature of the catalyst body, the substrate heating temperature, the gas phase film forming conditions, the type of source gas, the concentration of the n-type or p-type impurity to be added, etc. A polycrystalline silicon film having a wide range of n-type or p-type impurity concentration can be easily obtained, and a polycrystalline silicon film having a large grain size and a high crystallization rate can be formed by catalytic AHA treatment, so that high carrier mobility At V_thAdjustment is easy and high-speed operation with low resistance is possible.
[0126]
(G) 10 or more of tin or other group IV elements (lead, germanium, etc.), for example, tin by catalytic CVD, high-density catalytic CVD, etc.¹⁸-10²⁰An amorphous / microcrystalline or polycrystalline silicon film containing atoms / cc can be formed, and then a polycrystalline silicon film having a large grain size can be formed by catalytic AHA treatment. Existing crystal irregularities are reduced to reduce internal stress, and a large mobility polycrystalline silicon film can be formed.
[0127]
(H) In the case where the catalyst AHA treatment is performed after the film formation by plasma CVD, hydrogen containing 10 to 20% in the amorphous silicon film by plasma CVD is reduced / removed by the catalyst AHA treatment, so that a polycrystalline having a large particle size is obtained. Since the crystalline silicon film is formed, it is possible to form a polycrystalline silicon film having a large carrier mobility.
[0128]
(I) Since the catalytic CVD and the catalytic AHA treatment can be performed without generating plasma, the plasma is not damaged, and a simpler and cheaper apparatus can be realized as compared with the plasma AHA treatment.
[0129]
(J) Since the catalytic AHA treatment has high energy of the hydrogen-based active species even when the substrate temperature is lowered, the ultrafine particles of the target silicon and / or diamond-structured carbon can be reliably and stably obtained. Even when the substrate temperature is lowered to 300-400 ° C. in particular, the polycrystalline semiconductor thin film grows efficiently by using ultrafine particles as a seed, and thus a large and inexpensive low strain point insulating substrate (glass substrate, heat resistant resin substrate) Etc.), and in this respect, the cost can be reduced.
[0130]
(K) A catalyst CVD apparatus can be used for ion activation in the catalyst AHA treatment of n-type or p-type impurities added to the gate channel / source / drain regions depending on conditions, thereby reducing capital investment and improving productivity. Cost reduction.
[0131]
Second embodiment
<LCD production example 1>
In the present embodiment, the present invention is applied to an LCD (liquid crystal display device) using a polycrystalline silicon MOS TFT by a high temperature process, and a manufacturing example thereof will be shown below (this manufacturing example is an organic EL described later). It can be similarly applied to display devices such as FED and FED).
[0132]
First, as shown in (1) of FIG. 12, in the pixel portion and the peripheral circuit portion, a heat-resistant insulating substrate 61 such as quartz glass or crystallized glass (strain point is about 800 to 1100 ° C., thickness is 50 microns to several mm). ), A recess 190 (not shown here: the same applies hereinafter) is formed in the same manner as described above after the formation of the base protective film (not shown) by the above-described catalytic CVD method or the like. And / or the carbon ultrafine particle 100A is made to adhere.
[0133]
Next, as shown in (2) of FIG. 12, the ultrafine particles 100A are cleaned by the above-described catalyst AHA treatment, and modified into a carbon ultrafine particle layer 100B having a silicon or / and diamond structure from which organic substances and the like are removed.
[0134]
Next, as shown in FIG. 12 (3), a polycrystalline silicon thin film 67 is formed in the recess to a thickness of, for example, 50 nm by using the above-described catalytic CVD method or the like, using the ultrafine particle layer 100B as a seed. This polycrystalline silicon thin film may be formed by the above-described multi-catalyst AHA treatment.
[0135]
Next, as shown in FIG. 13 (4), the polycrystalline silicon thin film 67 is patterned (islanded) using a photoresist mask. For example, the nMOS TFT portion in the display region, the nMOS TFT portion in the peripheral drive circuit region, and the pMOS TFT are formed. An active layer of active elements such as transistors, diodes and other passive elements such as resistors, capacitors and inductances is formed.
[0136]
Next, V is controlled by controlling the impurity concentration in the channel region of the transistor active layer 67._thAfter the ion implantation of a predetermined impurity such as boron or phosphorus as described above for the optimization of the above, as shown in (5) of FIG. A silicon oxide film 68 for a gate insulating film having a thickness of, for example, 50 nm is formed on the surface of the silicon thin film 67. When the silicon oxide film 68 for the gate insulating film is formed by a catalytic CVD method or the like, the substrate temperature and the catalyst body temperature are the same as those described above, but the oxygen gas flow rate is 1 to 2 SCCM, the monosilane gas flow rate is 15 to 20 SCCM, The hydrogen-based carrier gas may be 150 SCCM. Note that the silicon oxide film 68 for the gate insulating film may be formed by, for example, high-temperature thermal oxidation at about 1000 ° C. for 30 minutes before or after controlling the impurity concentration in the channel region.
[0137]
Next, as shown in FIG. 13 (6), as the gate electrode and gate line material, for example, a Mo—Ta alloy is deposited by sputtering to a thickness of, for example, 400 nm, or a phosphorus-doped polycrystalline silicon film is formed, for example. Hydrogen carrier gas 150SCCM, 2-20SCCM phosphine (PH_Three) And 20 SCCM monosilane gas, and a thickness of, for example, 400 nm is deposited by the same catalytic CVD method as described above. Then, the gate electrode material layer is patterned into the shape of the gate electrode 75 and the gate line by general-purpose photolithography and etching techniques. In the case of a phosphorus-doped polycrystalline silicon film, a protective silicon oxide film (10 to 20 nm thick) may be formed on the surface by catalytic CVD or the like.
[0138]
Next, as shown in FIG. 14 (7), the pMOS TFT portion is masked with a photoresist 78, and, for example, arsenic (or phosphorus) ions 79, which are n-type impurities, are ionized by ion implantation or ion doping, for example, 1 × 10.¹⁵atoms / cm²Doping with a dose of 2 × 10²⁰The donor concentration is set to atoms / cc, and nMOSTFT n⁺A type source region 80 and a drain region 81 are formed.
[0139]
Next, as shown in FIG. 14 (8), the nMOS TFT portion is masked with a photoresist 82, and, for example, boron ions 83 which are p-type impurities are ionized by ion implantation or ion doping, for example, 1 × 10.¹⁵atoms / cm²Doping with a dose of 2 × 10²⁰The acceptor concentration is set to atoms / cc and the pMOSTFT p⁺A type source region 84 and a drain region 85 are formed.
[0140]
Next, as shown in FIG. 14 (9), by using the same bias catalyst CVD method as described above on the entire surface, a hydrogen carrier gas of 150 to 200 SCCM is used in common, and 1-2 SCCM of He diluted O₂Under the supply of 15-20 SCCM monosilane, the silicon oxide film has a thickness of, for example, 100-200 nm, and further, phosphine (PH_Three), 1-2 SCCM He dilution O₂A phosphine silicate glass (PSG) film is formed to a thickness of 300 to 400 nm under a monosilane supply of 15 to 20 SCCM, and ammonia (NH) of 50 to 60 SCCM is formed._Three) A silicon nitride film is formed to a thickness of, for example, 100 to 200 nm under a monosilane supply of 15 to 20 SCCM. An interlayer insulating film 86 is formed by stacking these insulating films. In addition, you may form such an interlayer insulation film by the normal method different from the above. After this, for example, N at 900 ° C. for 5 minutes₂Annealing at 1000 ° C or N for 20-30 seconds₂The ions are activated by the RTA treatment in the region, and the carrier impurity concentration set in each region is obtained.
[0141]
Next, as shown in FIG. 15 (10), a contact window is opened at a predetermined position of the insulating film 86, and an electrode material such as aluminum is deposited on the entire surface including each contact hole to a thickness of 1 μm by sputtering or the like. Then, this is patterned to form source electrodes 87 and data lines of nMOS TFTs in the pixel portion, source electrodes 88 and 90 and drain electrodes 89 and 91 and wirings of pMOS TFTs and nMOS TFTs in the peripheral circuit portion, respectively. Thereafter, for example, hydrogenation and sintering are performed in forming gas at 400 ° C. for 1 h to improve the interface state and ohmic contact.
[0142]
Next, after an interlayer insulating film 92 such as a silicon oxide film is formed on the surface by a CVD method or the like, contact holes are formed in the interlayer insulating films 92 and 86 in the nMOS TFT drain region of the pixel portion as shown in FIG. For example, an ITO (indium tin oxide: transparent electrode material in which tin is doped with indium oxide) film having a thickness of 130 to 150 nm is deposited on the entire surface by vacuum deposition or the like, and patterned to be connected to the drain region 81 of the nMOS TFT. A transparent pixel electrode 93 is formed. Thereafter, annealing is performed in a forming gas at 250 ° C. for 1 hour, for example, to improve ohmic contact with the ITO film and to improve the transparency of the ITO.
[0143]
Thus, an active matrix substrate (hereinafter referred to as a TFT substrate) can be manufactured, and a transmissive LCD can be manufactured. As shown in FIG. 15 (12), this transmissive LCD has a structure in which an alignment film 94, a liquid crystal 95, an alignment film 96, a transparent electrode 97, and a counter substrate 98 are laminated on a transparent pixel electrode 93.
[0144]
Note that the above-described steps can be similarly applied to the production of a reflective LCD. FIG. 20A shows an example of the reflective LCD. In FIG. 20A, reference numeral 101 in the figure denotes a reflective film deposited on the roughened insulating film 92. It is connected.
[0145]
When the liquid crystal cell of this LCD is manufactured by surface assembly (suitable for medium / large liquid crystal panels of 2 inches or more), first a TFT substrate 61 and a solid ITO (Indium Tin Oxide) electrode 97 are provided. Polyimide alignment films 94 and 96 are formed on the element forming surface of the counter substrate 98. This polyimide alignment film is formed to a thickness of 50 to 100 nm by roll coating, spin coating or the like, and cured and cured at 180 ° C./2 h.
[0146]
Next, the TFT substrate 61 and the counter substrate 98 are rubbed or photo-aligned. The rubbing buff material includes cotton and rayon, but cotton is more stable in terms of buffing (dust) and retardation. Photo-alignment is a technique for aligning liquid crystal molecules by non-contact linearly polarized ultraviolet irradiation. For alignment, in addition to rubbing, a polymer alignment film can be formed by obliquely entering polarized light or non-polarized light (such a polymer compound is, for example, a polymethyl methacrylate polymer having azobenzene). Etc.).
[0147]
Next, after cleaning, a common agent is applied to the TFT substrate 61 side, and a sealing agent is applied to the counter substrate 98 side. Wash with water or IPA (isopropyl alcohol) to remove rubbing buff. The common agent may be an acrylic containing a conductive filler, or an epoxy acrylate, or an epoxy adhesive, and the sealant may be an acrylic, an epoxy acrylate, or an epoxy adhesive. Any of heat curing, ultraviolet radiation curing, ultraviolet radiation curing + heat curing can be used, but the ultraviolet radiation curing + heat curing type is preferable in terms of overlay accuracy and workability.
[0148]
Next, spacers for obtaining a predetermined gap are scattered on the counter substrate 98 side and overlapped with the TFT substrate 61 at a predetermined position. After aligning the alignment mark on the counter substrate 98 side and the alignment mark on the TFT substrate 61 side with high precision, the sealant is temporarily cured by irradiating with ultraviolet rays, and then heated and cured all at once.
[0149]
Next, a scribe break is made to produce a single liquid crystal panel in which the TFT substrate 61 and the counter substrate 98 are overlapped.
[0150]
Next, liquid crystal 95 is injected into the gap between the two substrates 61-98, and the injection port is sealed with an ultraviolet adhesive and then IPA cleaned. Any type of liquid crystal may be used, but for example, a fast response TN (twisted nematic) mode using nematic liquid crystal is common.
[0151]
Next, the liquid crystal 95 is aligned by heating and quenching.
[0152]
Next, a flexible wiring is connected to the panel electrode extraction portion of the TFT substrate 61 by thermocompression bonding of an anisotropic conductive film, and a polarizing plate is further bonded to the counter substrate 98.
[0153]
In the case of a single surface assembly of a liquid crystal panel (suitable for a small liquid crystal panel of 2 inches or less), polyimide alignment films 94 and 96 are formed on the element formation surfaces of the TFT substrate 61 and the counter substrate 98 as described above. Then, both substrates are rubbed or non-contact linearly polarized ultraviolet light is aligned.
[0154]
Next, the TFT substrate 61 and the counter substrate 98 are divided into single pieces by dicing or scribe break, and washed with water or IPA. A common agent is applied to the TFT substrate 61, a sealant containing a spacer is applied to the counter substrate 98, and the two substrates are overlapped. The subsequent processes follow the above.
[0155]
In the LCD described above, the counter substrate 98 is a CF (color filter) substrate, and a color filter layer (not shown) is provided under the ITO electrode 97. Incident light from the counter substrate 98 side may be efficiently reflected by, for example, the reflective film 93 and emitted from the counter substrate 98 side.
[0156]
On the other hand, when the TFT substrate 61 is a TFT substrate having an on-chip color filter (OCCF) structure in which a color filter is provided on the TFT substrate 61, the counter substrate 98 has a solid ITO electrode (or an ITO electrode with a black mask). It is solid).
[0157]
In the case of a transmissive LCD, an on-chip color filter (OCCF) structure and an on-chip black (OCB) structure can be manufactured as follows.
[0158]
That is, as shown in FIG. 15 (13), the drain portion of the phosphine silicate glass / silicon oxide insulating film 86 is also opened to form an aluminum buried layer for the drain electrode. Each color filter layer 99 is patterned by forming a photoresist 99 in which each color is pigment-dispersed in each segment with a predetermined thickness (1 to 1.5 μm) and then leaving only a predetermined position (each pixel portion) by general-purpose photolithography technology. (R), 99 (G), and 99 (B) are formed (on-chip color filter structure). At this time, the window of the drain part is also opened. Note that an opaque ceramic substrate, low-transmittance glass, and a heat-resistant resin substrate cannot be used.
[0159]
Next, a light shielding layer 100 'serving as a black mask layer is formed by metal patterning over the color filter layer in a contact hole communicating with the drain of the display TFT. For example, molybdenum is formed to a thickness of 200 to 250 nm by sputtering, and is patterned into a predetermined shape that covers the display MOS TFT and shields it from light (on-chip black structure).
[0160]
Next, a planarizing film 92 of transparent resin is formed, and further, an ITO transparent electrode 93 is formed in a through hole provided in the planarizing film so as to be connected to the light shielding layer 100 ′.
[0161]
As described above, the color filter 99 and the black mask 100 ′ are formed on the display array portion, thereby improving the aperture ratio of the liquid crystal display panel and realizing low power consumption of the display module including the backlight. .
[0162]
FIG. 16 schematically shows an entire active matrix liquid crystal display (LCD) in which the above-mentioned top gate type MOSTFT is incorporated and configured as an integrated drive circuit. This active matrix LCD has a flat panel structure in which a main substrate 61 (which constitutes an active matrix substrate) and a counter substrate 98 are bonded together via a spacer (not shown). Liquid crystal (not shown here) is enclosed in the. On the surface of the main substrate 61, there are provided a display unit composed of pixel electrodes 93 arranged in a matrix, switching elements for driving the pixel electrodes, and a peripheral drive circuit unit connected to the display unit. .
[0163]
The switching element of the display unit is composed of the above-mentioned nMOS, pMOS, or CMOS, and a top gate type MOSTFT having an LDD structure. Also, in the peripheral drive circuit section, the above-mentioned top gate MOSTFT CMOS, nMOS, pMOSTFT, or a mixture thereof is formed as a circuit element. One peripheral driving circuit unit is a horizontal driving circuit that supplies a data signal to drive the TFT of each pixel for each horizontal line, and the other peripheral driving circuit unit sets the gate of the TFT of each pixel for each scanning line. The vertical driving circuit is normally provided on both sides of the display portion. These drive circuits can be configured in either a dot sequential analog system or a line sequential digital system.
[0164]
As shown in FIG. 17, the MOSTFT is arranged at the intersection of the orthogonal gate bus line and the data bus line, and the liquid crystal capacitance (C_LCThe image information is written in () and the electric charge is held until the next information comes. In this case, since it is not sufficient to hold only the channel resistance of the TFT, a storage capacitor (auxiliary capacitor) (C_S) May be added to compensate for the decrease in the liquid crystal voltage due to the leakage current. Such LCD MOSTFTs have different performance requirements depending on the characteristics of TFTs used in the pixel portion (display portion) and TFTs used in the peripheral drive circuit. In particular, TFTs in the pixel portion control off current and ensure on current. Is an important issue. For this reason, the display portion is provided with a TFT having an LDD structure as will be described later, thereby reducing the effective electric field applied to the channel region as a structure in which an electric field is unlikely to be applied between the gate and the drain, thereby reducing the off-current. The change of can be made small. However, the process is complicated, the element size is increased, and problems such as a decrease in on-current occur. Therefore, an optimum design for each purpose of use is required.
[0165]
Available liquid crystals include TN liquid crystal (nematic liquid crystal used for active matrix drive TN mode), STN (super twisted nematic), GH (guest / host), PC (phase change), FLC. Liquid crystals for various modes such as (ferroelectric liquid crystal), AFLC (antiferroelectric liquid crystal), and PDLC (polymer dispersion type liquid crystal) may be employed.
[0166]
<LCD production example 2>
Next, an example of manufacturing an LCD (Liquid Crystal Display) using a low-temperature process polycrystalline silicon MOSTFT according to the present embodiment will be shown (this example is applied to an organic EL or FED display device to be described later). Is possible).
[0167]
In this manufacturing example, aluminosilicate glass, borosilicate glass, or the like is used as the substrate 61 in the manufacturing example 1 described above, and the steps (1), (2), and (3) in FIG. That is, a polycrystalline silicon thin film 67 containing (or not containing) tin is formed on the substrate 61 by catalytic CVD and catalytic AHA treatment to form an island, and an nMOS TFT portion in the display region and an nMOS TFT portion in the peripheral drive circuit region and A pMOS TFT portion is formed. In this case, regions such as a diode, a capacitor, an inductance, and a resistance are formed at the same time.
[0168]
Next, as shown in FIG. 18A (however, the base protective film and the recess 190 are not shown: the same applies hereinafter), the carrier impurity concentration in each MOSTFT gate channel region is controlled by V_thFor example, the nMOS TFT portion in the display region and the nMOS TFT portion in the peripheral drive circuit region are covered with a photoresist 82, and the pMOS TFT portion in the peripheral drive circuit region is made of, for example, phosphorus or arsenic by ion implantation or ion doping. 1 × 10 of n-type impurity 79¹²atoms / cm²Doping with a dose of 2 × 10¹⁷The donor concentration is set to atoms / cc. Further, as shown in FIG. 18B, the pMOS TFT portion in the peripheral drive circuit region is covered with the photoresist 82, and the nMOS TFT portion in the display region and the nMOS TFT portion in the peripheral drive circuit region. Next, 5 × 10 5 of p-type impurity 83 such as boron is formed by ion implantation or ion doping.¹¹atoms / cm²Doping with a dose of 1 × 10¹⁷An acceptor concentration of atoms / cc is set.
[0169]
Next, as shown in (3) of FIG.^-In order to form an LDD (Lightly Doped Drain) portion of the mold, the gate portion of the nMOS TFT in the display region and the pMOS TFT and nMOS TFT in the peripheral drive region are all covered with a photoresist 82 by a general-purpose photolithography technique, and the nMOS TFT in the exposed display region An n-type impurity 79 such as phosphorus, for example, is implanted into the source / drain regions of 1 × 10 10 by ion implantation or ion doping.¹³atoms / cm²Doping with a dose of 2 × 10¹⁸Set the donor concentration to atoms / cc and n^-The LDD part of the mold is formed.
[0170]
Next, as shown in FIG. 19 (4), the entire nMOS TFT portion in the display region and the nMOS TFT portion in the peripheral drive circuit region are covered with the photoresist 82, and the gate portion of the pMOS TFT portion in the peripheral drive circuit region is covered with the photoresist 82. A p-type impurity 83 such as boron, for example, by ion implantation or ion doping is applied to the exposed source and drain regions covered with¹⁵atoms / cm²Doping with a dose of 2 × 10²⁰Set acceptor concentration at atoms / cc and set p⁺A mold source portion 84 and drain portion 85 are formed.
[0171]
Next, as shown in FIG. 19 (5), the pMOS TFT portion in the peripheral drive circuit region is covered with a photoresist 82, and the gate and LDD portion of the display region and the gate portion of the nMOS TFT portion in the peripheral drive circuit region are exposed to photo. An n-type impurity 79 such as phosphorus or arsenic, for example, by ion implantation or ion doping is applied to the source and drain regions of the nMOS TFT in the exposed display region and the peripheral drive region by covering the resist 82 with 1 × 10 × 10.¹⁵atoms / cm²Ion doping with a dose of 2 × 10²⁰set to donors concentration of atoms / cc, n⁺A mold source 80 and drain 81 are formed.
[0172]
Next, as shown in FIG. 19 (6), the gate insulating film 68 is formed as a silicon oxide film 40-50 nm thick, a silicon nitride film 10-20 nm thick, oxidized by plasma CVD, TEOS plasma CVD, catalytic CVD, or the like. A laminated film having a silicon film thickness of 40 to 50 nm is formed. Then, RTA treatment with a halogen lamp or the like is performed, for example, at about 1000 ° C. for 10 to 30 seconds, and the added n or p type impurities are ion activated to obtain each set carrier impurity concentration.
[0173]
Thereafter, an aluminum sputtered film containing 1% Si having a thickness of 400 to 500 nm is formed on the entire surface, and gate electrodes 75 and gate lines of all TFTs are formed by general-purpose photolithography and etching. Thereafter, an insulating film 86 made of a laminated film having a silicon oxide film thickness of 100 to 200 nm, a phosphine silicate glass (PSG) film of 200 to 300 nm, and a silicon nitride film of 100 to 200 nm is formed by plasma CVD, catalytic CVD, or the like. Form.
[0174]
Next, the windows of the source / drain portions of all TFT portions of the peripheral drive circuit and the source portion of the display nMOS TFT portion are opened by general-purpose photolithography and etching techniques. Silicon nitride film is CF_FourThe plasma etching, the silicon oxide film, and the phosphorous silicate glass film are etched with a hydrofluoric acid-based etchant.
[0175]
Next, as shown in FIG. 19 (7), an aluminum sputtered film containing 1% Si having a thickness of 400 to 500 nm is formed on the entire surface, and the source and drain electrodes of all TFTs of the peripheral drive circuit are formed by general-purpose photolithography and etching techniques. At the same time as forming 88, 89, 90, 91, the source electrode 87 and the data line of the display nMOS TFT are formed.
[0176]
Next, although not shown in the drawing, the silicon oxide film 100 to 200 nm thickness, the phosphine silicate glass film (PSG film) 200 to 300 nm thickness, and the silicon nitride film 100 to 300 nm thickness are formed by plasma CVD, catalytic CVD method, etc. (The above-mentioned 92) is formed on the entire surface, and hydrogenated and sintered in a forming gas at about 400 ° C. for 1 hour. Thereafter, a window for drain contact of the display nMOS TFT is opened.
[0177]
Here, when the LCD is a transmission type, the silicon oxide film, phosphine silicate glass film, and silicon nitride film in the pixel opening are removed, and when the LCD is a reflection type, the silicon oxide film such as the pixel opening and the phosphine are removed. It is not necessary to remove the silicate glass film and the silicon nitride film (the same applies to the LCD described above or later).
[0178]
In the case of the transmissive type, an acrylic transparent resin flattening film having a thickness of 2 to 3 μm is formed on the entire surface by spin coating or the like as in (10) of FIG. After forming the transparent resin window on the drain side, an ITO sputtered film having a thickness of 130 to 150 nm is formed on the entire surface, and an ITO transparent electrode in contact with the drain portion of the display nMOS TFT is formed by general-purpose photolithography and etching techniques. Further, the contact resistance is reduced and the ITO transparency is improved by heat treatment (200 to 250 ° C., 1 hour in forming gas).
[0179]
In the case of the reflective type, a photosensitive resin film having a thickness of 2 to 3 μm is formed on the entire surface by spin coating, etc., and a concavo-convex pattern is formed at least on the pixel portion by general-purpose photolithography and etching technology, and reflow is performed to reflect the concavo-convex Form the bottom. At the same time, a photosensitive resin window opening in the drain portion of the display nMOS TFT is formed. Thereafter, an aluminum sputtered film containing 1% Si having a thickness of 300 to 400 nm is formed on the entire surface, the aluminum film other than the pixel portion is removed by general-purpose photolithography and etching techniques, and the unevenness connected to the drain electrode of the display nMOS TFT. A shaped aluminum reflecting portion is formed. Thereafter, sintering is performed in a forming gas at 300 ° C. for 1 hour.
[0180]
In the above, if the catalyst AHA treatment is performed after forming the source and drain of the nMOS TFT, the film temperature of the polycrystalline silicon thin film is locally increased, crystallization is further promoted, and high mobility and high quality are achieved. A polycrystalline silicon thin film is formed. At the same time, the thermal energy of high-temperature hydrogen molecules, hydrogen atoms, activated hydrogen ions, etc., moves to the film and locally raises the film temperature, so that phosphorus and arsenic implanted into the gate channel / source / drain region Boron ions and the like are activated.
[0181]
When an amorphous silicon-containing microcrystalline silicon thin film is formed by the plasma CVD method, 10-20% hydrogen is contained in the film, but it can be reduced / removed by the catalyst AHA treatment, so that the polycrystalline silicon film And a high mobility and high quality polycrystalline silicon thin film is formed. In addition, when silicon oxide is present on or in the polycrystalline silicon thin film, it reacts with this to produce SiO and evaporate and remove, reducing the silicon oxide on or in the film. A high mobility and high quality polycrystalline silicon thin film can be formed.
[0182]
<Bottom gate type or dual gate type MOSTFT>
An example of manufacturing a transmissive LCD including a bottom gate type and a dual gate type MOS TFT instead of the above-described top gate type in an LCD incorporating a MOS TFT will be described (however, the same applies to a reflective LCD).
[0183]
As shown in FIG. 20B, a bottom gate type nMOS TFT is provided in the display portion and the peripheral portion, or as shown in FIG. 20C, a dual gate type nMOS TFT is provided in the display portion and the peripheral portion. Each is provided. Among these bottom gate type and dual gate type MOSTFTs, especially in the case of the dual gate type, the driving capability is improved by the upper and lower gate portions, suitable for high-speed switching, and either of the upper and lower gate portions is selectively used. Depending on the case, it can be operated as a top gate type or a bottom gate type.
[0184]
In the bottom gate type MOSTFT of FIG. 20B, reference numeral 102 in the figure denotes a gate electrode such as a Mo—Ta alloy, 103 denotes a silicon nitride film, and 104 denotes a silicon oxide film, which forms a gate insulating film. On the gate insulating film, a channel region using a polycrystalline silicon thin film 67 similar to the top gate type MOS TFT is formed. In the dual gate type MOSTFT of FIG. 20C, the lower gate part is the same as the bottom gate type MOSTFT, but the upper gate part has a gate insulating film 106 made of a silicon oxide film and a silicon nitride film, and if necessary. Further, it is formed of a laminated film of a silicon oxide film, and an upper gate electrode 75 is provided thereon.
[0185]
<Manufacture of bottom gate type MOSTFT>
First, a sputtered film of Mo-Ta alloy is formed on the entire surface of the glass substrate 61 to a thickness of 300 to 400 nm, and this is taper-etched by 20 to 45 degrees by general-purpose photolithography and etching techniques, at least in the TFT formation region. At the same time as the bottom gate electrode 102 is formed, a gate line is formed. Glass materials are used according to the top gate type described above.
[0186]
Next, a silicon nitride film 103 and a silicon oxide film 104 for a gate insulating film and a protective film are formed by vapor phase growth methods such as plasma CVD, TEOS plasma CVD, catalytic CVD, and low pressure CVD, and at least in the TFT formation region. A concave portion having a step having an appropriate shape / size is formed, and silicon or / and carbon ultrafine particles are adhered, and carbon or fine particles of silicon or / and diamond structure cleaned by the catalyst AHA treatment are formed. Using this as a seed, a polycrystalline silicon thin film containing or not containing tin is formed in the recess by catalytic CVD or the like, and the catalytic AHA treatment is repeated to form a large grain polycrystalline silicon thin film 67 with a high crystallization rate. . These vapor deposition conditions conform to the top gate type described above. The bottom gate insulating film and the silicon nitride film for the protective film are provided in anticipation of a Na ion stopper action from the glass substrate, but are not necessary in the case of synthetic quartz glass.
[0187]
The subsequent processes are the same as those described above, but since the gate electrode has already been formed in the above steps, the steps of forming the polysilicon film for the gate electrode, forming the gate electrode, and oxidizing the gate polysilicon are unnecessary. is there.
[0188]
Then, as described above, the pMOSTFT and nMOSTFT regions are islanded (however, only one region is shown: the same applies hereinafter), and the carrier impurity concentration in each channel region is controlled to V_thIn order to optimize the n-type or p-type impurity by ion implantation or ion doping, an n-type or p-type impurity is formed by ion implantation or ion doping to form the source and drain regions of each MOS TFT. Alternatively, an appropriate amount of p-type impurity is mixed. Thereafter, annealing for catalytic AHA treatment or RTA treatment is performed for impurity activation.
[0189]
The subsequent processes are the same as those described above.
[0190]
<Manufacture of dual gate type MOS TFT>
Similar to the above-mentioned bottom gate type, the bottom gate electrode 102, the gate insulating films 103 and 104, the silicon or / and diamond ultrafine carbon particles are used as seeds in the recesses, and the polycrystalline has a high crystallization ratio and a large grain size. Each of the functional silicon thin films 67 is formed. However, the silicon nitride film 103 for the bottom gate insulating film and the protective film is provided in anticipation of the Na ion stopper action from the glass substrate, but is unnecessary in the case of synthetic quartz glass.
[0191]
Then, as described above, the pMOSTFT and nMOSTFT regions are islanded, and the carrier impurity concentration in each channel region is controlled to V_thIn order to optimize the n-type or p-type impurity by ion implantation or ion doping, an n-type or p-type impurity is formed by ion implantation or ion doping to form the source and drain regions of each MOS TFT. Alternatively, an appropriate amount of p-type impurity is mixed.
[0192]
Next, a stacked film of a silicon oxide film and a silicon nitride film for the top gate insulating film 106 and, if necessary, a silicon oxide film are formed. Vapor phase growth conditions conform to the top gate type described above. After this, annealing for RTA treatment is performed for impurity activation.
[0193]
Thereafter, an aluminum sputtered film containing 1% Si having a thickness of 400 to 500 nm is formed on the entire surface, and top gate electrodes 75 and gate lines of all TFTs are formed by general-purpose photolithography and etching techniques. Thereafter, an insulating film 86 made of a silicon oxide film having a thickness of 100 to 200 nm, a phosphine silicate glass (PSG) film having a thickness of 200 to 300 nm, or the like is formed by plasma CVD, catalytic CVD, or the like. Next, the windows of the source and drain electrode portions of all the MOSTFTs in the peripheral drive circuit and the source electrode portion of the display nMOSTFT are opened by general-purpose photolithography and etching techniques.
[0194]
Next, an aluminum sputtered film containing 1% Si having a thickness of 400 to 500 nm is formed on the entire surface, and source and drain aluminum electrodes 87, 88 and 89, source lines, wirings, and the like are formed by general-purpose photolithography and etching techniques. Next, a silicon oxide film 100 to 200 nm thick, a phosphine silicate glass film (PSG film) 200 to 300 nm thick, and a silicon nitride film 100 to 300 nm thick are formed as an interlayer insulating film 92 on the entire surface by plasma CVD, catalytic CVD, or the like. Hydrogenation and sintering in forming gas at about 400 ° C. for 1 hour. Thereafter, a drain contact window for the display nMOS TFT is opened to form a pixel electrode 93 such as ITO.
[0195]
As described above, according to the present embodiment, as in the first embodiment described above, the gate channel, source, and source of the MOS TFT in the LCD display portion and the peripheral drive circuit portion are performed by catalytic CVD and catalytic AHA treatment. V with high carrier mobility, which becomes the drain region_thA polycrystalline silicon thin film having a large grain size and a high crystallization ratio that can be adjusted easily and can be operated at high speed with low resistance can be formed. A liquid crystal display device using a top gate, bottom gate or dual gate type MOS TFT with this polycrystalline silicon thin film has a display portion having an LDD structure with high switching characteristics and low leakage current, and a CMOS or nMOS with high driving capability, Alternatively, a configuration in which a pMOS peripheral drive circuit, a video signal processing circuit, a memory circuit, and the like are integrated can be realized, and a liquid crystal panel with high image quality, high definition, a narrow frame, high efficiency, and low cost can be realized.
[0196]
And since it can form at low temperature (300-400 degreeC), it can employ | adopt the low strain point glass which is cheap and easy to enlarge, and a cost reduction is attained. In addition, by forming a color filter or a black mask on the array portion, the aperture ratio, luminance, etc. of the liquid crystal display panel are improved, a color filter substrate is not required, and cost reduction is realized by improving productivity.
[0197]
Third embodiment
In the present embodiment, the present invention is applied to an organic or inorganic electroluminescence (EL) display device, for example, an organic EL display device. The structural examples and production examples are shown below.
[0198]
<Structural example I of organic EL element>
As shown in FIGS. 21A and 21B, according to this structural example I, the high crystallization rate formed in the step 190 on the substrate 111 such as glass by the method described above according to the present invention. The gate channel 117, the source region 120, and the drain region 121 of the switching MOSTFT 1 and the current driving MOSTFT 2 are formed by a polycrystalline silicon thin film having a large grain size. A gate electrode 115 is formed on the gate insulating film 118, and a source electrode 127 and drain electrodes 128 and 131 are formed on the source and drain regions. The drain of MOSTFT 1 and the gate of MOSTFT 2 are connected via a drain electrode 128, a capacitor C is formed between the source electrode 127 of MOSTFT 2 via an insulating film 136, and the drain electrode 131 of MOSTFT 2 is It extends to the cathode 138 of the organic EL element.
[0199]
Each MOSTFT is covered with an insulating film 130, and on this insulating film, for example, a green organic light emitting layer 132 (or a blue organic light emitting layer 133 or a red organic light emitting layer not shown) of an organic EL element is formed so as to cover the cathode. An anode (first layer) 134 is formed so as to cover the organic light emitting layer, and a common anode (second layer) 135 is further formed on the entire surface. In addition, the manufacturing method of the peripheral drive circuit, the video signal processing circuit, the memory circuit, and the like made of CMOS TFT is in accordance with the above-described liquid crystal display device (the same applies hereinafter).
[0200]
In the organic EL display unit having this structure, the organic EL light emitting layer is connected to the drain of the current driving MOS TFT 2, the cathode (Li—Al, Mg—Ag, etc.) 138 is deposited on the surface of the substrate 111 such as glass, and the anode (ITO film etc.) 134, 135 are provided on the upper part thereof, and therefore, the top emission 136 ′ is obtained. Further, when the cathode covers the MOSTFT, the light emission area becomes large. At this time, the cathode serves as a light shielding film, and light emission or the like does not enter the MOSTFT so that no leak current is generated and the TFT characteristics are not deteriorated.
[0201]
Further, if a black mask portion (chromium, chromium dioxide, etc.) 140 is formed around each pixel portion as shown in FIG. 21C, light leakage (crosstalk, etc.) can be prevented and contrast can be improved.
[0202]
In addition, a good full-color EL display device can be obtained by any of a method using a three-color light emitting layer of green, blue, and red for a pixel display portion, a method using a color conversion layer, and a method using a color filter for a white light emitting layer. In addition, it is possible to produce a long-life, high-accuracy, high-quality, high-reliability full-color organic EL unit in the spin coating method of polymer compounds, which are light emitting materials for each color, or the vacuum heating deposition method of metal complexes. Since it can be created well, the cost can be reduced (hereinafter the same).
[0203]
Since this type of conventional organic EL uses amorphous or microcrystalline silicon MOSTFT, V_thEven if fluctuates, the current value is likely to change, and the image quality is likely to fluctuate. Moreover, since the mobility is small, there is a limit to the current that can be driven with a high-speed response, it is difficult to form a p-channel, and even a small-scale CMOS circuit configuration is difficult. Therefore, it is desirable to use a polycrystalline silicon MOSTFT that is relatively easy to increase in area, has high reliability, has high carrier mobility, and can be configured as a CMOS circuit. An amorphous silicon film is formed by a plasma CVD method at 300 to 400 ° C., and excimer laser annealing is performed to form a polycrystalline silicon film. 2) An amorphous silicon film is formed by LPCVD at 430 to 500 ° C., and is solid phase grown in nitrogen gas at 600 ° C./5 to 20 hr and 850 ° C./0.5 to 3 hr to form a polycrystalline silicon film.
[0204]
However, 1) increases the cost due to the use of an expensive excimer laser device, uneven TFT characteristics due to the instability of the excimer laser, quality problems, and productivity reduction. In 2), since a general-purpose glass substrate cannot be used for a long-time heat treatment at 600 ° C. or more and 15 to 20 hours, quartz glass is used, which increases costs. Also, in the full-color organic EL layer, in the microfabrication process, the electrode is oxidized and the organic EL material is easily deteriorated by exposure to oxygen and moisture, or structural change (dissolution or recrystallization) by heating. It is difficult to form the region with high accuracy.
[0205]
Next, the manufacturing process of the organic EL element according to the present embodiment will be described. First, as shown in FIG. 22A, the source region 120 and the channel region 117 made of a polycrystalline silicon thin film are obtained through the above-described steps. After forming the gate region 115 and the drain region 121, the gate insulating film 118 is formed. On the gate insulating film 118, the gate electrode 115 of the MOS TFTs 1 and 2 is formed by sputtering film formation of Mo-Ta alloy or the like and photolithography and etching techniques. A gate line connected to the gate electrode is formed by sputtering film formation, photolithography, and etching techniques (hereinafter the same). Then, after an overcoat film (silicon oxide or the like) 137 is formed by a vapor phase growth method such as catalytic CVD (hereinafter the same), ion activation is performed by RTA treatment such as 1000 ° C. for 10 to 30 seconds. Then, the source electrode 127 and the ground line of the MOS TFT 2 are formed, and an overcoat film (silicon oxide / silicon nitride laminated film or the like) 136 is further formed.
[0206]
Next, as shown in (2) of FIG. 22, after opening the source / drain part of MOSTFT1 and the gate part of MOSTFT2, sputtering of Al containing 1% Si as shown in (3) of FIG. The drain electrode of MOSTFT1 and the gate electrode of MOSTFT2 are connected by Al wiring 128 containing 1% Si by general photolithography and etching techniques, and at the same time, the source electrode of MOSTFT1 and the source made of Al containing 1% Si connected to this electrode Form a line. Then, an overcoat film (silicon oxide / phosphine silicate glass / silicon nitride laminated film, etc.) 130 is formed, the window of the drain part of the MOSTFT 2 is opened, and the cathode 138 of the light emitting part connected to the drain part of the MOSTFT 2 is formed. .
[0207]
Next, as shown in FIG. 22 (4), the organic light emitting layer 132 and the like and the anodes 134 and 135 are formed.
[0208]
In the above, the green (G) light-emitting organic EL layer, the blue (B) light-emitting organic EL layer, and the red (R) light-emitting organic EL layer are each formed to a thickness of 100 to 200 nm. In the case of a low molecular compound, it is formed by a vacuum heating vapor deposition method. In the case of a high molecular compound, a method of arranging R, G, B light emitting polymers by a coating method such as dipping coating or spin coating or an ink jet method is used. In the case of a metal complex, a sublimable material is formed by a vacuum heating vapor deposition method.
[0209]
Examples of the organic EL layer include a single-layer type, a two-layer type, and a three-layer type. Here, an example of a three-layer type of a low-molecular compound is shown.
Single layer type; anode / bipolar light emitting layer / cathode,
Two-layer type; anode / hole transport layer / electron transport light-emitting layer / cathode, or anode / hole transport light-emitting layer / electron transport layer / cathode,
Three layer type; anode / hole transport layer / light emitting layer / electron transport layer / cathode, or anode / hole transport light emitting layer / carrier block layer / electron transport light emitting layer / cathode
[0210]
Note that in the element of FIG. 21B, when a known light emitting polymer is used instead of the organic light emitting layer, a light emitting polymer display device (LEPD) driven by a passive matrix or an active matrix can be configured (hereinafter the same). .
[0211]
<Structural example II of organic EL element>
As shown in FIGS. 23 (A) and 23 (B), according to this structural example II, it is formed on the substrate 111 such as glass by the method described above based on the present invention, similar to the structural example I described above. The gate channel 117, the source region 120, and the drain region 121 of the switching MOSTFT 1 and the current driving MOSTFT 2 are formed by a polycrystalline silicon thin film having a high crystallization rate and a large grain size. A gate electrode 115 is formed on the gate insulating film 118, and a source electrode 127 and drain electrodes 128 and 131 are formed on the source and drain regions. The drain of the MOSTFT 1 and the gate of the MOSTFT 2 are connected via a drain electrode 128, a capacitor C is formed between the drain electrode 131 of the MOSTFT 2 via an insulating film 136, and the source electrode 127 of the MOSTFT 2 is It extends to the anode 144 of the organic EL element.
[0212]
Each MOSTFT is covered with an insulating film 130, and on this insulating film, for example, a green organic light emitting layer 132 (or a blue organic light emitting layer 133 or a red organic light emitting layer (not shown)) of an organic EL element is formed so as to cover the anode. A cathode (first layer) 141 is formed so as to cover the organic light emitting layer, and a common cathode (second layer) 142 is further formed on the entire surface.
[0213]
In the organic EL display unit having this structure, the organic EL light emitting layer is connected to the source of the current driving MOS TFT 2 and the organic EL light emitting layer is formed so as to cover the anode 144 deposited on the surface of the substrate 111 such as glass. The cathode 141 is formed so as to cover the organic EL light emitting layer, and the cathode 142 is formed on the entire surface. Therefore, the bottom emission 136 ′ is obtained. A cathode covers the organic EL light emitting layer and the MOS TFT. That is, after a green light emitting organic EL layer is formed on the entire surface by, for example, vacuum heating vapor deposition or the like, a green light emitting organic EL part is formed by photolithography and dry etching. Finally, a cathode (electron injection layer) 141 is formed on the entire surface with magnesium: silver alloy or aluminum: lithium alloy. Since the cathode (electron injection layer) formed on the entire surface is sealed, moisture can be prevented from entering the organic EL layer from the outside, particularly by the cathode 142 deposited on the entire surface. Thus, a long life, high quality, and high reliability are possible (this is the same because the whole surface of the structure example I in FIG. 21 is covered with the anode). Moreover, since the heat radiation effect is enhanced by the cathodes 141 and 142, the structural change (melting or recrystallization) of the thin film due to heat generation is reduced, and a long life, high quality, and high reliability are possible. In addition, this makes it possible to produce a high-precision, high-quality full-color organic EL layer with high productivity, thereby reducing costs.
[0214]
Further, if a black mask portion (chromium, chromium dioxide, etc.) 140 is formed around each pixel portion as shown in FIG. 23C, light leakage (crosstalk, etc.) can be prevented and contrast can be improved. The black mask portion 140 is covered with a silicon oxide film 143 (which may be formed of the same material as the gate insulating film 118).
[0215]
Next, the manufacturing process of this organic EL element will be described. First, as shown in FIG. 24 (1), a source region made of a polycrystalline silicon thin film having a high crystallization rate and a large grain size through the above-described steps. 120, after forming the channel region 117 and the drain region 121, a gate insulating film 118 is formed by a vapor phase growth method such as bias catalytic CVD, and this is performed by sputtering film formation of Mo-Ta alloy or the like and general-purpose photolithography and etching techniques. The gate electrodes 115 of the MOS TFTs 1 and 2 are formed thereon, and a gate line connected to the gate electrode of the MOS TFT 1 is formed by sputtering film formation of Mo—Ta alloy or the like and general-purpose photolithography and etching techniques. Then, after an overcoat film (silicon oxide or the like) 137 is formed by a vapor phase growth method such as bias catalyst CVD, ion activation is performed by RTA treatment at 1000 ° C. for 10 to 30 seconds. Then, the drain electrode 131 and V of the MOS TFT 2 are formed by sputtering film formation of Al containing 1% Si, general-purpose photolithography and etching techniques._ddA line is formed, and an overcoat film (silicon oxide / silicon nitride laminated film or the like) 136 is formed by a vapor phase growth method such as catalytic CVD.
[0216]
Next, as shown in (2) of FIG. 24, after opening the source / drain portion of MOSTFT1 and the gate portion of MOSTFT2 by general-purpose photolithography and etching techniques, as shown in (3) of FIG. With 1% Si-containing Al sputtering film formation and general-purpose photolithography and etching techniques, the drain of MOSTFT 1 and the gate of MOSTFT 2 are connected by Al wiring 128 containing 1% Si, and at the same time, Al containing 1% Si is connected to the source of MOSTFT 1. A source line is formed. Then, an overcoat film (silicon oxide / phosphine silicate glass / silicon nitride laminated film, etc.) 130 is formed, a window of the source portion of the MOSTFT 2 is opened by general-purpose photolithography and etching techniques, sputtering of ITO and general-purpose photolithography Then, the anode 144 of the light emitting part connected to the source part of the MOSTFT 2 is formed by an etching technique.
[0217]
Next, as shown in FIG. 24 (4), the organic light emitting layer 132 and the cathodes 141 and 142 are formed as described above.
[0218]
In addition, although the constituent material and formation method of each layer of organic EL described below are applied to the example of FIG. 23, they may be similarly applied to the example of FIG.
[0219]
When a low molecular weight compound is used for the green light-emitting organic EL layer, it is formed by continuous vacuum heating vapor deposition on the ITO transparent electrode in contact with the source part of the MOST TFT for current drive, which is the anode (hole injection layer) on the glass substrate. To do.
1) The hole transport layer is an amine compound (for example, a triarylamine derivative, an arylamine oligomer, an aromatic tertiary amine, etc.), etc.
2) The light emitting layer is a green light emitting material such as tris (8-hydroxyxylino) Al complex (Alq)
3) The electron transport layer includes 1,3,4-oxadiazole derivative (OXD), 1,2,4-triazole derivative (TAZ), etc.
4) The electron injection layer as the cathode is preferably made of a material having a work function of 4 eV or less.
For example, 10-30 nm thickness of 10: 1 (atomic ratio) magnesium: silver alloy
Aluminum: 10-30 nm thickness of lithium (concentration 0.5-1%) alloy
Here, silver is added in an amount of 1 to 10 atomic% in magnesium in order to increase adhesion to the organic interface, and lithium is added in an amount of 0.5 to 1% in aluminum for stabilization.
[0220]
In order to form the green pixel portion, the green pixel portion is masked with a photoresist, and CCl_FourThe cathode: electron injection layer, aluminum: lithium alloy, is removed by plasma etching of the gas, and the low molecular weight compounds and photoresist in the electron transport layer, light-emitting layer, hole transport layer, and photoresist are successively removed by oxygen plasma etching. A pixel portion is formed. At this time, since there is an aluminum: lithium alloy under the photoresist, there is no problem even if the photoresist is etched. At this time, the electron transport layer, the light emitting layer, and the low molecular compound layer of the hole transport layer have a larger area than the ITO transparent electrode of the hole injection layer, and the electron injection layer of the cathode 142 (which is formed on the entire surface in a later step) Magnesium: Silver alloy, etc.)
[0221]
Next, when the blue light-emitting organic EL layer is formed of a low molecular compound, a vacuum is continuously formed on the ITO transparent electrode in contact with the source part of the current driving TFT which is an anode (hole injection layer) on the glass substrate. It is formed by heat evaporation.
1) The hole transport layer is an amine compound (for example, a triarylamine derivative, an arylamine oligomer, an aromatic tertiary amine, etc.), etc.
2) The light emitting layer is a distyryl derivative such as DTVBi which is a blue light emitting material.
3) The electron transport layer is composed of 1,3,4-oxadiazole derivative (TAZ), 1,2,4-triazole derivative (TAZ), etc.
4) The electron injection layer as the cathode is preferably made of a material having a work function of 4 eV or less.
For example, 10-30 nm thickness of 10: 1 (atomic ratio) magnesium: silver alloy
Aluminum: 10-30 nm thickness of lithium (concentration 0.5-1%) alloy
Here, silver is added in an amount of 1 to 10 atomic% in magnesium in order to increase adhesion with an organic interface, and lithium is added in an amount of 0.5 to 1% in aluminum for stabilization.
[0222]
To form the blue pixel portion, the blue pixel portion is masked with a photoresist, and CCl_FourGas plasma etching removes the aluminum: lithium alloy in the electron injection layer, which is the cathode, and continuously removes low molecular weight compounds and photoresists in the electron transport layer, light emitting layer, and hole transport layer by oxygen plasma etching. A pixel portion is formed. At this time, since there is an aluminum: lithium alloy under the photoresist, there is no problem even if the photoresist is etched. At this time, the electron transport layer, the light emitting layer, and the low molecular weight compound layer of the hole transport layer have a larger area than the ITO transparent electrode of the hole injection layer, and the electron injection layer of the cathode 142 (which is formed on the entire surface in a later step) Magnesium: Silver alloy, etc.)
[0223]
When the red light-emitting organic EL layer is formed of a low-molecular compound, vacuum heating is continuously performed on the ITO transparent electrode that is in contact with the source part of the current driving TFT which is the anode (hole injection layer) on the glass substrate. It is formed by vapor deposition.
1) The hole transport layer is an amine compound (for example, a triarylamine derivative, an arylamine oligomer, an aromatic tertiary amine, etc.), etc.
2) The light emitting layer is made of Eu (Eu (DBM)) which is a red light emitting material._Three(Phen)) etc.
3) The electron transport layer is composed of 1,3,4-oxadiazole derivative (OXD), 1,2
, 4-Triazole derivative (TAZ), etc.
4) The electron injection layer as the cathode is preferably made of a material having a work function of 4 eV or less.
For example, 10-30 nm thickness of 10: 1 (atomic ratio) magnesium: silver alloy
Aluminum: 10-30 nm thickness of lithium (concentration 0.5-1%) alloy
Silver is added in an amount of 1 to 10 atomic% in magnesium to increase adhesion to the organic interface, and lithium is added in an amount of 0.5 to 1% in aluminum for stabilization.
[0224]
To form the red pixel portion, the red pixel portion is masked with a photoresist, and CCl_FourGas plasma etching removes the aluminum: lithium alloy in the electron injection layer, which is the cathode, and continuously removes low molecular weight compounds and photoresist in the electron transport layer, light emitting layer, and hole transport layer by oxygen plasma etching, and red A pixel portion is formed. At this time, since there is an aluminum: lithium alloy under the photoresist, there is no problem even if the photoresist is etched. At this time, the electron transport layer, the light emitting layer, and the low molecular compound layer of the hole transport layer have a larger area than the ITO transparent electrode of the hole injection layer, and the electron injection layer of the cathode 142 (which is formed on the entire surface in a later step) Magnesium: Silver alloy, etc.) Thereafter, an electron injection layer (magnesium: silver alloy or the like) of the common cathode 142 is formed on the entire surface.
[0225]
The electron injection layer as the cathode is preferably made of a material having a work function of 4 eV or less. For example, the thickness is 10 to 30 nm of a 10: 1 (atomic ratio) magnesium: silver alloy, or 10 to 30 nm of an aluminum: lithium (concentration is 0.5 to 1%) alloy. Here, silver is added in an amount of 1 to 10 atomic% in magnesium in order to increase adhesion to the organic interface, and lithium is added in an amount of 0.5 to 1% in aluminum for stabilization. Note that the film may be formed by sputtering.
[0226]
Fourth embodiment
In the present embodiment, the present invention is applied to a field emission display (FED). The structural examples and production examples are shown below.
[0227]
<Structure example I of FED>
As shown in FIGS. 25 (A), (B), and (C), according to this structural example I, the height formed on the substrate 111 made of glass or the like in the step by the method described above based on the present invention. The gate channel 117, the source region 120, and the drain region 121 of the switching MOSTFT 1 and the current driving MOSTFT 2 are formed by a polycrystalline silicon thin film having a crystallization rate and a large grain size. A gate electrode 115 is formed on the gate insulating film 118, and a source electrode 127 and a drain electrode 128 are formed on the source and drain regions. The drain of the MOSTFT 1 and the gate of the MOSTFT 2 are connected via a drain electrode 128, a capacitor C is formed between the source electrode 127 of the MOSTFT 2 via an insulating film 136, and the drain region 121 of the MOSTFT 2 is It extends as it is to the FEC (field emission cathode) of the FED element, and functions as the emitter region 152.
[0228]
Each MOSTFT is covered with an insulating film 130. On this insulating film, a metal shielding film 151 for grounding is formed in the same process with the same material as that of the FEC gate lead electrode 150 to cover each MOSTFT. In the FEC, an n-type polycrystalline silicon film 153 to be a field emission emitter is formed on an emitter region 152 made of a polycrystalline silicon thin film, and further has openings for partitioning into m × n emitters. Further, the insulating films 118, 137, 136 and 130 are patterned, and a gate extraction electrode 150 is deposited on the upper surface.
[0229]
Further, a substrate 157 such as a glass substrate formed with a phosphor 156 with a back metal 155 as an anode is provided opposite to the FEC, and a high vacuum is maintained between the FEC and the FEC.
[0230]
In the FEC having this structure, the n-type polycrystalline silicon film 153 grown on the polycrystalline silicon thin film 152 formed according to the present invention is exposed under the opening of the gate lead electrode 150, which is respectively It functions as a thin film type emitter that emits electrons 154. That is, since the polycrystalline silicon thin film 152 serving as the base of the emitter is composed of grains having a large grain size (grain size of several hundred nm or more), the n-type polycrystalline silicon film 153 is biased thereon using this as a seed. When grown by catalytic CVD or the like, the polycrystalline silicon film 153 grows with a larger grain size and is formed so that the surface has fine irregularities 158 that are advantageous for electron emission. At this time, a polycrystalline diamond film, a carbon thin film containing or not containing nitrogen, and an electron emitter (emitter) having a number of fine protrusion structures (for example, carbon nanotubes) on the surface of the carbon thin film containing or not containing nitrogen. Good.
[0231]
Therefore, since the emitter is a surface emission type made of a thin film, its formation is easy, the emitter performance is stable, and the life can be extended.
[0232]
In addition, a metal shielding film 151 having a ground potential is formed on the upper part of all active elements (this includes the MOSTFT and the diode of the peripheral drive circuit and the pixel display portion) (this metal shielding film is made of the same material as the gate lead electrode 150). (Nb, Ti / Mo, etc.) are formed in the same process, which is convenient in terms of process.) Therefore, the following advantages (1) and (2) can be obtained.
[0233]
(1) The gas in the hermetic container is positively ionized by electrons emitted from the emitter 153 and is charged on the insulating layer, and this positive charge forms an unnecessary inversion layer in the MOSTFT under the insulating layer. Since an excess current flows through an unnecessary current path made of an inversion layer, the emitter current runs away. However, since the metal shielding film 151 is formed on the insulating layer on the MOSTFT and dropped to the ground potential, it is possible to prevent the charge-up and to prevent the emitter current from running away.
[0234]
(2) The phosphor 156 emits light due to the collision of electrons emitted from the emitter 153. This light generates electrons and holes in the gate channel of the MOSTFT, resulting in a leakage current. However, since the metal shielding film 151 is formed on the insulating layer on the MOSTFT, light incidence to the MOSTFT is prevented and the MOSTFT does not malfunction.
[0235]
In addition, since an electron emitter (emitter) such as an n-type polycrystalline silicon film is continuously formed at least in the drain region of the polycrystalline silicon MOS TFT by bias catalyst CVD or the like, its bonding property is good. Highly efficient emitter characteristics are possible.
[0236]
In addition, if the electron emitter (emitter) region of one pixel display part is divided into a plurality of parts and the MOSTFT of the switching element is connected to each of them, even if one MOSTFT fails, the other MOSTFT operates. One pixel display unit is always configured to emit electrons, so that the quality is high, the yield is high, and the cost can be reduced. Further, in these MOSTFTs, there is no problem with MOSTFTs with poor electrical openness, but since MOSTFTs that are electrically short-circuited can be separated by laser repair, high quality, high yield, and cost reduction can be achieved.
[0237]
In contrast, in the conventional FED, since a silicon single crystal substrate is used, the substrate cost is high, and it is difficult to increase the area larger than the wafer size. And, it has been proposed to form an electron emitter by forming a conductive polycrystalline silicon film on the cathode electrode surface by low pressure CVD or the like and forming a crystalline diamond film on the surface by plasma CVD or the like. The film formation temperature during the low pressure CVD is as high as 630 ° C., and a glass substrate cannot be adopted, so that it is difficult to reduce the cost. The polycrystalline silicon film formed by the low pressure CVD has a small particle size, and the crystalline diamond film thereon also has a small particle size, and the characteristics of the electron emitter are not good. Furthermore, since the reaction energy is insufficient due to plasma CVD, it is difficult to obtain a good crystalline diamond film. Further, since the bonding property between the transparent electrode or the cathode electrode made of metal such as Al, Ti, and Cr and the conductive polycrystalline silicon film is poor, good electron emission characteristics cannot be obtained.
[0238]
Next, the manufacturing process of the FED according to the present embodiment will be described. First, as shown in FIG. 26 (1), after the polycrystalline silicon thin film 117 is formed on the entire surface through the above-described steps, general-purpose photolithography is performed. Then, MOSTFT1, MOSTFT2, and the emitter region are formed into islands by an etching technique, and a protective silicon oxide film 159 is formed on the entire surface by plasma CVD, catalytic CVD, or the like.
[0239]
Next, V V is controlled by controlling the gate channel impurity concentration of the MOS TFTs 1 and 2._thIn order to optimize this, boron ions 83 are 5 × 10 5 on the entire surface by ion implantation or ion doping.¹¹atoms / cm²Doping with a dose of 1 × 10¹⁷The acceptor concentration is set to atoms / cc.
[0240]
Next, as shown in (2) of FIG. 26, phosphorus ions 79 are introduced into the source / drain portions and the emitter regions of the MOS TFTs 1 and 2 by 1 × 10 × by ion implantation or ion doping using the photoresist 82 as a mask.¹⁵atoms / cm²Doping with a dose of 2 × 10²⁰After setting the donor concentration to atoms / cc and forming the source region 120, the drain region 121, and the emitter region 152, the protective silicon oxide film in the emitter region is removed by general-purpose photolithography and etching techniques.
[0241]
Next, as shown in (3) of FIG. 26, monosilane and PH are formed using a polycrystalline silicon thin film 152 that forms an emitter region by biased or non-biased catalytic CVD as a seed._ThreeEtc. are mixed at an appropriate ratio, and the surface has fine irregularities 158, and the dopant is, for example, 5 × 10²⁰~ 1x10^{twenty one}An n-type polycrystalline silicon film 153 containing atoms / cc is formed in the emitter region to a thickness of 1 to 5 μm. At the same time, an n-type amorphous silicon film 160 is formed on the other silicon oxide film 159 and the glass substrate 111 to a thickness of 1 to 5 μm. To form.
[0242]
Next, as shown in FIG. 26 (4), the amorphous silicon film 160 is selectively removed by the action of the hydrogen-based active species during the above-described catalyst AHA treatment, and the catalyst is removed after the silicon oxide film 159 is removed by etching. A gate insulating film (silicon oxide film or the like) 118 is formed by CVD or the like.
[0243]
Next, as shown in FIG. 27 (5), gate lines connected to the gate electrodes 115 of the MOSTFT 1 and 2 and the gate electrode of the MOSTFT 1 are formed by a heat-resistant metal such as a Mo—Ta alloy by sputtering, and the overcoat is formed. After forming a film (silicon oxide film or the like) 137, ion activation is performed by RTA treatment at 1000 ° C. for 10 to 20 seconds, and after opening the source window of the MOSTFT 2, a heat-resistant metal such as a Mo—Ta alloy by sputtering Thus, the source electrode 127 and the ground line of the MOSTFT 2 are formed. Further, an overcoat film (silicon oxide / silicon nitride laminated film or the like) 136 is formed by plasma CVD, catalytic CVD, or the like.
[0244]
Next, as shown in FIG. 27 (6), the source / drain portion of MOSTFT1 and the gate portion of MOSTFT2 are opened, and the drain of MOSTFT1 and the gate of MOSTFT2 are connected by Al wiring 128 containing 1% Si, A source electrode of the MOSTFT 1 and a source line 127 connected to the source are formed.
[0245]
Next, as shown in (7) of FIG. 27, after forming an overcoat film (silicon oxide / phosphine silicate glass / silicon nitride laminated film, etc.) 130, a window of the GND line is opened, and (8) of FIG. As shown in FIG. 5, the gate lead electrode 150 and the metal shielding film 151 are formed by etching after Nb deposition, and further, the field emission cathode part is opened to expose the emitter 153, and the hydrogen-based activity in the catalyst AHA treatment described above. At the same time as cleaning with seeds or the like, fine irregularities are made noticeable by selective etching action of hydrogen diameter active species or the like.
[0246]
<FED Structure Example II>
As shown in FIGS. 28 (A), (B), and (C), according to the structure example II, on the substrate 111 made of glass or the like, as described in the structure example I, it has been described above based on the present invention. The gate channel 117, the source region 120, and the drain region 121 of the switching MOSTFT 1 and the current driving MOSTFT 2 are formed by a polycrystalline silicon thin film having a high crystallization rate and a large grain size formed in the step by the method. A gate electrode 115 is formed on the gate insulating film 118, and a source electrode 127 and a drain electrode 128 are formed on the source and drain regions. The drain of the MOSTFT 1 and the gate of the MOSTFT 2 are connected via a drain electrode 128, a capacitor C is formed between the source electrode 127 of the MOSTFT 2 via an insulating film 136, and the drain region 121 of the MOSTFT 2 is It extends as it is to the FEC (field emission cathode) of the FED element, and functions as the emitter region 152.
[0247]
Each MOSTFT is covered with an insulating film 130. On this insulating film, a metal shielding film 151 for grounding is formed in the same process with the same material as that of the FEC gate lead electrode 150 to cover each MOSTFT. In FEC, an n-type polycrystalline diamond film 163 to be a field emission emitter is formed on an emitter region 152 made of a polycrystalline silicon thin film, and further has openings for partitioning into m × n emitters. Further, the insulating films 118, 137, 136 and 130 are patterned, and a gate extraction electrode 150 is deposited on the upper surface.
[0248]
Further, a substrate 157 such as a glass substrate formed with a phosphor 156 with a back metal 155 as an anode is provided opposite to the FEC, and a high vacuum is maintained between the FEC and the FEC.
[0249]
In the FEC having this structure, an n-type polycrystalline diamond film 163 grown on the polycrystalline silicon thin film 152 formed in accordance with the present invention is exposed under the opening of the gate extraction electrode 150, and each of them is an electron 154. It functions as a thin film type emitter that emits. That is, since the polycrystalline silicon film 152 serving as the base of the emitter is composed of grains having a large grain size (grain size of several hundred nm or more), the n-type polycrystalline diamond film 163 is used as a catalyst on this as a seed. When grown by CVD or the like, the polycrystalline diamond film 163 also grows with a large grain size, and is formed so that the surface has fine irregularities 168 that are advantageous for electron emission. At this time, a carbon thin film containing or not containing nitrogen, or an electron emitter (emitter) having a number of fine protrusion structures (for example, carbon nanotubes) on the surface of the carbon thin film containing or not containing nitrogen may be used.
[0250]
Therefore, since the emitter is a surface emission type made of a thin film, its formation is easy, the emitter performance is stable, and the life can be extended.
[0251]
In addition, a metal shielding film 151 having a ground potential is formed on the upper part of all active elements (this includes the MOSTFT and the diode of the peripheral drive circuit and the pixel display portion) (this metal shielding film is made of the same material as the gate lead electrode 150). (Nb, Ti / Mo, etc.) are formed in the same process, which is convenient in terms of process.) As described above, the metal shielding film 151 is formed on the insulating layer on the MOSTFT to form the ground potential. Therefore, it is possible to prevent charge-up and prevent runaway of the emitter current. Also, since the metal shielding film 151 is formed on the insulating layer on the MOSTFT, light incidence on the MOSTFT is prevented and the MOSTFT malfunctions. Does not occur.
[0252]
Next, the manufacturing process of the FED will be described. First, as shown in FIG. 29 (1), after the polycrystalline silicon thin film 117 is formed on the entire surface through the above-described steps, the general photolithography and etching techniques are used. An island is formed in the MOSTFT1, MOSTFT2, and the emitter region, and a protective silicon oxide film 159 is formed on the entire surface by plasma CVD, catalytic CVD, or the like.
[0253]
Next, V V is controlled by controlling the gate channel impurity concentration of the MOS TFTs 1 and 2._thIn order to optimize this, boron ions 83 are 5 × 10 5 on the entire surface by ion implantation or ion doping.¹¹atoms / cm²Doping with a dose of 1 × 10¹⁷The acceptor concentration is set to atoms / cc.
[0254]
Next, as shown in (2) of FIG. 29, phosphorus ions 79 are introduced into the source / drain portions and the emitter regions of the MOS TFTs 1 and 2 by 1 × 10 × by ion implantation or ion doping using the photoresist 82 as a mask.¹⁵atoms / cm²Doping with a dose of 2 × 10²⁰After setting the donor concentration to atoms / cc and forming the source region 120, the drain region 121, and the emitter region 152, the protective silicon oxide film in the emitter region is removed by general-purpose photolithography and etching techniques.
[0255]
Next, as shown in (3) of FIG. 29, monosilane and methane (CH) are seeded with a polycrystalline silicon thin film 152 that forms an emitter region by biased or non-biased catalytic CVD._Four) And a dopant in an appropriate ratio, and an n-type polycrystalline diamond film 163 having fine irregularities 168 on the surface is formed in the emitter region. At the same time, an n-type amorphous diamond film is formed on the other silicon oxide film 159 and the glass substrate 111. 170 is formed.
[0256]
Next, as shown in FIG. 29 (4), the amorphous diamond film 170 is selectively etched away by the action of the hydrogen-based active species and the like during the above-described catalyst AHA treatment, and after the silicon oxide film 159 is removed by etching. A gate insulating film (silicon oxide film or the like) 118 is formed by catalytic CVD or the like.
[0257]
Next, as shown in FIG. 30 (5), gate lines connected to the gate electrodes 115 of the MOSTFT 1 and 2 and the gate electrode of the MOSTFT 1 are formed by a heat-resistant metal such as a Mo—Ta alloy by sputtering, and an overcoat is formed. After the film (silicon oxide film or the like) 137 is formed, ion activation treatment is performed at 1000 ° C. for 10 to 20 seconds such as RTA. Thereafter, after the source window of the MOSTFT 2 is opened, the source electrode 127 and the ground line of the MOSTFT 2 are formed of a heat-resistant metal such as a Mo—Ta alloy by sputtering. Further, an overcoat film (silicon oxide / silicon nitride laminated film or the like) 136 is formed by plasma CVD, catalytic CVD, or the like.
[0258]
Next, as shown in FIG. 30 (6), the source / drain portion of MOSTFT1 and the gate portion of MOSTFT2 are opened, and the drain of MOSTFT1 and the gate of MOSTFT2 are connected by Al wiring 128 containing 1% Si. A source electrode of the MOSTFT 1 and a source line 127 connected to the source are formed.
[0259]
Next, as shown in FIG. 30 (7), after an overcoat film (silicon oxide / phosphine silicate glass / silicon nitride laminated film, etc.) 130 is formed, the GND line window is opened, and FIG. As shown in FIG. 5, the gate lead electrode 150 and the metal shielding film 151 are formed by etching after Nb deposition, and the field emission cathode part is opened to expose the emitter 163, and the hydrogen-based activity in the catalyst AHA treatment described above. At the same time as cleaning with seeds, fine unevenness is made noticeable by selective etching action such as hydrogen-based active seeds.
[0260]
In the above, when forming the polycrystalline diamond film 163, the carbon-containing compound as the source gas used is, for example,
1) Paraffinic hydrocarbons such as methane, ethane, propane and butane
2) Acetylene and arylene acetylene hydrocarbons
3) Olefin hydrocarbons such as ethylene, propylene, butylene
4) Diolefin hydrocarbons such as butadiene
5) Cyclopropane, cyclobutane, cyclopentane, cyclohexane and other alicyclic hydrocarbons
6) Aromatic hydrocarbons such as cyclobutadiene, benzene, toluene, xylene, naphthalene
7) Ketones such as acetone, diethyl ketone, and benzophenone
8) Alcohols such as methanol and ethanol
9) Amines such as trimethylamine and triethylamine
10) Substances consisting only of carbon atoms, such as graphite, coal, coke, etc.
These may be used alone or in combination of two or more.
[0261]
Further, usable inert gases are, for example, argon, helium, neon, krypton, xenon, and radon. As the dopant, for example, a compound containing boron, lithium, nitrogen, phosphorus, sulfur, chlorine, arsenic, selenium, beryllium, or the like or a simple substance can be used.¹⁶atoms / cc or more.
[0262]
Fifth embodiment
In this embodiment, the present invention is applied to a solar cell as a photoelectric conversion device. The production example is shown below.
[0263]
First, as shown in (1) of FIG. 31, a recess having a predetermined shape / size step is formed on a metal substrate 111 such as stainless steel, and silicon or / and carbon ultrafine particles are adhered thereto, as described above. An n-type polycrystalline silicon film 7 is formed in the recess by using a catalyst ultra-fine particle layer of silicon or / and diamond structure as a seed by catalytic AHA treatment, catalytic CVD method or the like. This polycrystalline silicon film 7 may be formed by the above-described multi-catalyst AHA treatment, and has a high crystallization rate, a large grain size of tin or other group IV element (Ge, Pb) alone or in a mixture containing n-type. A polycrystalline silicon film is formed to a thickness of 100 to 200 nm. The polycrystalline silicon film 7 is doped with n-type impurities such as phosphorus._ThreeFor example, 1 × 10¹⁷~ 1x10¹⁸atoms / cc.
[0264]
Next, as shown in (2) of FIG. 31, on the polycrystalline silicon film 7, i or a mixture containing tin or other group IV elements (Ge, Pb) alone or in a mixture by catalytic CVD or the like is seeded. A type polycrystalline silicon film 180, a p-type polycrystalline silicon film 181 containing tin or another group IV element (Ge, Pb) alone or in a mixture, and the like are grown to form a photoelectric conversion layer.
[0265]
For example, by catalytic CVD, tin hydride (SnH_Four) Are mixed at an appropriate ratio to grow an i-type large grain tin-containing polycrystalline silicon film 180 to a thickness of 2 to 5 μm. On top of this, p-type impurity boron (B₂H₆Etc.) and tin hydride (SnH)_Four) In an appropriate ratio, for example, 1 × 10¹⁷~ 1x10¹⁸A p-type large-grain-size tin-containing polycrystalline silicon film 181 containing atoms / cc is formed to a thickness of 100 to 200 nm. At this time, tin or another group IV element (Ge, Pb) alone or a mixture such as tin, for example, 1 × 10 6 is contained in each film.¹⁶atoms / cc or more, preferably 1 × 10¹⁸~ 1x10²⁰By containing atoms / cc, crystal irregularities and stress existing in the crystal grain boundaries are reduced, so that carrier mobility can be improved (this is because the n-type or p-type polycrystalline silicon films 7 and 181 are formed). The same applies when forming).
[0266]
Moreover, you may perform the multi catalyst AHA process mentioned above. For example, after an n-type or p-type tin-containing polycrystalline silicon thin film is grown to a thickness of 20 to 50 nm by bias catalytic CVD, a catalytic AHA treatment is performed, and an n-type or p-type tin-containing polycrystalline property is obtained by catalytic CVD. A silicon thin film is grown to a thickness of 20 to 50 nm, and after catalytic AHA treatment, an n-type or p-type tin-containing polycrystalline silicon thin film is further grown to 20 to 50 nm by catalytic CVD, and then catalytic AHA treatment is performed. The film may be formed by a method in which each treatment is repeated as many times as necessary (this is also the case with the i-type polycrystalline silicon film 180). By this method, a tin-containing polycrystalline silicon film having a higher crystallization rate and a larger particle size can be formed. In addition, a high-speed film formation can be performed by increasing the supply amount of the source gas during the film formation.
[0267]
Next, as shown in FIG. 31 (3), a transparent electrode 182 is formed on the entire surface of the tin-containing polycrystalline silicon film having a high crystallization ratio and a large grain size formed by the above method. Form. For example, a transparent electrode 182 such as an ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) film having a thickness of 130 to 150 nm for non-reflective coating is formed by a general-purpose sputtering technique. Then, a comb-shaped electrode 183 made of silver or the like is formed to a thickness of 100 to 150 nm in a predetermined region by a general-purpose sputtering technique using a metal mask.
[0268]
The above film does not necessarily contain tin or other group IV elements, but in this case, it can be produced in the same manner as described above. In addition to the n-i-p junction structure described above, structures such as a p-i-n junction, a p-n junction, and an n-p junction can be similarly produced.
[0269]
The solar cell according to the present embodiment can form a photoelectric conversion thin film with high carrier mobility and high conversion efficiency by a polycrystalline silicon film having a high crystallization rate and a large particle size based on the present invention, and has a good surface texture structure Since the back surface texture structure is formed, a photoelectric conversion thin film having a high light containment effect and a high conversion efficiency can be formed. This is not limited to the solar battery, and can be advantageously used for a thin film photoelectric conversion device such as a photosensitive drum for electrophotography.
[0270]
In contrast, in this type of conventional photoelectric conversion device, an amorphous carbon thin film is formed by RF plasma CVD, VHF plasma CVD, etc., and ultrafine carbon particles are formed by plasma hydrogen treatment, which is used to grow polycrystalline silicon crystals. A large grain polycrystalline silicon film is formed as a nucleus, and an n-type polycrystalline silicon layer, an i-type polycrystalline silicon active layer, and a p-type polycrystalline silicon layer are continuously formed, and an ITO film is laminated on the entire surface. Finally, a comb electrode is formed to obtain a thin-film polycrystalline silicon solar cell having a thickness of about 2 μm.
[0271]
However, this conventional method cannot avoid the following drawbacks.
1) A crystalline silicon thin film formed at a low temperature by RF plasma CVD, VHF plasma CVD or the like has low energy, so that chemical decomposition reaction of raw material gas or plasma hydrogen treatment tends to be insufficient, and the crystal grain size is small. Because it is small, mobility is low, and excessive current due to local electrical shorts or leaks is likely to occur due to the large number of grain boundaries and pinholes, and it is deposited in the film thickness of several μm required as a photoelectric conversion layer. In such a case, the internal stress or strain of the film increases, and in the worst case, the film peels off. As a result, the production yield and reliability of the photoelectric conversion layer are remarkably lowered, which is a major obstacle to aiming at practical use of a photoelectric conversion device including the photoelectric conversion layer.
2) Since plasma CVD methods such as RF plasma CVD and VHF plasma CVD have low energy, the utilization efficiency of the raw material gas is as low as 5 to 10%. For this reason, productivity is low and it is difficult to reduce costs.
[0272]
The embodiment of the present invention described above can be variously modified based on the technical idea of the present invention.
[0273]
For example, the number of repetitions of the above-described catalytic CVD method and catalytic AHA treatment and various conditions may be variously changed, and the material of the substrate or the like to be used is not limited to the above.
[0274]
Further, the present invention is suitable for an internal circuit such as a display unit, a peripheral driving circuit, a video signal processing circuit, a memory circuit, and other MOSTFTs, but besides that, an active region of a device such as a diode, a resistor, It is also possible to form passive regions such as capacitance (capacitance), wiring, and inductance with the polycrystalline silicon thin film according to the present invention.
[0275]
[Effects of the invention]
As described above, in the present invention, when forming a polycrystalline semiconductor thin film on a substrate, a recess having a step having a predetermined shape / dimension is formed on the substrate, and at least the recess is made of silicon and / or carbon. Ultrafine carbon particles having a silicon or / and diamond structure are made by adhering fine particles to be contacted with each other, contacting hydrogen or a hydrogen-containing gas with a heated catalyst body, and causing the hydrogen-based active species generated thereby to act on the fine particles to perform cleaning. Since the semiconductor material thin film is vapor-phase grown by the catalytic CVD method or the like using as a seed, the following remarkable effects (1) to (4) can be obtained.
[0276]
(1) A concave portion having an appropriate shape and size step is formed at an arbitrary designated position of the substrate, and ultrafine particles such as silicon powder are adhered and dispersed therein, and by the action of hydrogen-based active species in the catalyst AHA treatment, The ultrafine particles can be selectively removed by etching, and the oxide film and organic stains on the surface of the ultrafine particles can be removed. By a CVD method or the like, a polycrystalline silicon film having a large particle size with little variation can be formed in a specified region.
[0277]
(2) A high-performance, high-quality TFT can be formed at any specified location on the insulating substrate, and the integrated circuit substrate can be freely formed. Then, if necessary, the surface where the large grain polycrystalline silicon film is embedded in the recess having a step having an appropriate size and shape in the TFT formation region on the insulating substrate is polished to obtain a flat large grain. Since a substrate having a diameter polycrystalline silicon film surface can be obtained, high-performance, high-quality polycrystalline silicon semiconductor devices, electro-optical devices and the like can be manufactured.
[0278]
(3) Since the catalytic CVD and the catalytic AHA treatment can be performed without generating plasma, the plasma is not damaged, and a simpler and cheaper apparatus can be realized as compared with the plasma AHA treatment.
[0279]
(4) Since the energy of the hydrogen-based active species is large even when the substrate temperature is lowered in the catalyst AHA treatment, the target silicon and / or diamond structure carbon ultrafine particles can be obtained stably and reliably. Even when the substrate temperature is lowered to 300 to 400 ° C. in particular, the polycrystalline semiconductor thin film efficiently grows using the fine particles as seeds, and thus a large and inexpensive low strain point insulating substrate (glass substrate, heat resistant resin substrate, etc.) In this respect, the cost can be reduced.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a manufacturing process of a MOS TFT according to a first embodiment of the present invention in order of steps.
FIG. 2 is a sectional view showing the manufacturing process in the order of steps.
FIG. 3 is a cross-sectional view showing the manufacturing process in the order of steps.
FIG. 4 is a cross-sectional view showing the manufacturing process in the order of steps.
FIG. 5 is a schematic cross-sectional view in one state of an apparatus for catalytic CVD and catalytic AHA treatment used for production.
FIG. 6 is a schematic sectional view of the device in another state.
FIG. 7 is a timing chart of the gas flow rate during processing using this apparatus.
FIG. 8 is a schematic view of a gas supply system of the apparatus.
FIG. 9 is a graph showing a comparison of Raman spectra of semiconductor films obtained by this treatment.
FIG. 10 is a graph showing comparison of crystallization ratios of semiconductor thin films.
FIG. 11 is a graph showing a comparison of the concentration of heavy metals in the membrane according to the purity of the catalyst body and the support body.
FIG. 12 is a cross-sectional view showing an LCD manufacturing process according to the second embodiment of the present invention in the order of steps.
FIG. 13 is a sectional view showing the manufacturing process in the order of steps.
FIG. 14 is a sectional view showing the manufacturing process in the order of steps.
FIG. 15 is a sectional view showing the manufacturing process in the order of steps.
FIG. 16 is a perspective view showing a schematic layout of the entire LCD.
FIG. 17 is an equivalent circuit diagram of the LCD.
FIG. 18 is a cross-sectional view showing another manufacturing process of the LCD in the order of steps.
FIG. 19 is a sectional view showing the manufacturing process in the order of steps.
FIG. 20 is a cross-sectional view showing various types of MOS TFTs of the LCD.
FIG. 21 is an equivalent circuit diagram (A) of an essential part of an organic EL display device according to a third embodiment of the present invention, an enlarged sectional view of the essential part (B), and a sectional view of the periphery of the pixel (C). It is.
FIG. 22 is a cross-sectional view showing the manufacturing process of the organic EL display device in the order of steps.
FIG. 23 is an equivalent circuit diagram (A) of a main part of another organic EL display device, an enlarged cross-sectional view (B) of the main part, and a cross-sectional view (C) of the periphery of the pixel.
FIG. 24 is a cross-sectional view showing the manufacturing process of the organic EL display device in the order of steps.
FIG. 25 is an equivalent circuit diagram (A) of an essential part of an FED according to a fourth embodiment of the present invention, an enlarged sectional view (B) of the essential part, and a schematic plan view (C) of the essential part.
FIG. 26 is a cross-sectional view showing the FED manufacturing process in the order of steps.
FIG. 27 is a sectional view showing the manufacturing process in the order of steps.
FIG. 28 is an equivalent circuit diagram (A) of the main part of another FED, an enlarged sectional view (B) of the main part, and a plan view (C) of the main part.
FIG. 29 is a cross-sectional view showing the FED manufacturing process in the order of steps.
FIG. 30 is a sectional view showing the manufacturing process in the order of steps.
FIG. 31 is a cross-sectional view showing the manufacturing process of the solar cell according to the fifth embodiment of the present invention in the order of steps.
[Explanation of symbols]
1, 61, 98, 111, 157 ... substrate, 7, 67 ... polycrystalline silicon thin film,
14, 67, 117 ... channels,
15, 75, 102, 105, 115 ... gate electrodes,
8, 68, 103, 104, 106, 118 ... gate insulating film,
20, 21, 80, 81, 120, 121 ... n⁺Type source or drain region,
24, 25, 84, 85 ... p⁺Type source or drain region,
27, 28, 86, 92, 130, 136, 137 ... insulating film,
29, 30, 87, 88, 89, 90, 91, 93, 97, 127, 128, 131 ... electrodes, 40 ... source gas, 42 ... shower head, 44 ... film formation chamber,
45 ... susceptor, 46 ... catalyst, 47 ... shutter, 48 ... catalyst power supply,
94, 96 ... alignment film, 95 ... liquid crystal, 99 ... color filter layer,
100A ... Silicon or carbon fine particles,
100B: cleaned silicon or carbon fine particles,
100 ', 140 ... black mask layer, 132, 133 ... organic light emitting layer,
134, 135, 144 ... anode, 138, 141, 142, 171 ... cathode,
150... Gate extraction electrode (gate line), 151... Shielding film,
152 ... Emitter, 153 ... n-type polycrystalline silicon film, 155 ... Back metal,
156 ... phosphor, 158, 168 ... fine irregularities,
163 ... n-type polycrystalline diamond film, 180 ... i-type polycrystalline silicon film,
181 ... p-type polycrystalline silicon film, 182 ... transparent electrode, 183 ... comb electrode,
190 ... concave

Claims (22)

When forming a polycrystalline semiconductor thin film on a substrate,
Forming a recess having a step of a predetermined shape / dimension on the substrate;
Attaching at least ultrafine particles of silicon and / or carbon from the paste or dispersion state in the recesses;
A step of bringing hydrogen or a hydrogen-containing gas into contact with a heated catalyst body and causing the hydrogen-based active species generated thereby to act on the ultrafine particles to perform cleaning; and
A step of crystal growth using the ultrafine particles as a seed to vapor-deposit a semiconductor material thin film ;
A method for forming a polycrystalline semiconductor thin film, comprising: polishing the semiconductor material thin film to planarize a surface including the thin film surface; and obtaining the polycrystalline semiconductor thin film. When manufacturing a semiconductor device having a polycrystalline semiconductor thin film on a substrate,
Forming a recess having a step of a predetermined shape / dimension on the substrate;
Attaching at least the ultrafine particles of silicon and / or carbon from the paste or dispersion state in the recesses;
A step of bringing hydrogen or a hydrogen-containing gas into contact with a heated catalyst body and causing the hydrogen-based active species generated thereby to act on the ultrafine particles for cleaning;
A process of vapor-phase growth of a semiconductor material thin film by crystal growth of the ultrafine particles as a seed ; and
A method for manufacturing a semiconductor device, comprising: polishing the semiconductor material thin film to planarize a surface including the thin film surface, and obtaining the polycrystalline semiconductor thin film.   The source material gas and at least a part of hydrogen or a hydrogen-containing gas are contacted with a heated catalyst body to be catalytically decomposed, and reactive species including radicals and ions generated thereby are deposited on the substrate, and the semiconductor material The method according to claim 1 or 2, wherein the thin film is vapor-phase grown. After the vapor phase growth of the semiconductor material thin film, hydrogen or a hydrogen-containing gas is brought into contact with a heated catalyst body, and a hydrogen-based active species composed of high-temperature hydrogen-based molecules, hydrogen-based atoms, and activated hydrogen ions generated thereby. The method according to claim 3 , wherein annealing is performed on the semiconductor material thin film. The method according to claim 4 , wherein the vapor phase growth of the semiconductor material thin film similar to the semiconductor material thin film and the annealing are repeated.   The heated catalyst body is brought into contact with at least a part of the hydrogen or hydrogen-containing gas, and a hydrogen-based active species composed of high-temperature hydrogen-based molecules, hydrogen-based atoms, and activated hydrogen ions generated thereby is converted into the semiconductor material thin film. The method according to claim 1, wherein annealing is performed by acting on the substrate. The heated catalyst body is contacted with at least a part of the raw material gas and the hydrogen-based carrier gas to catalytically decompose, and reactive species formed by the radicals and ions are deposited on the heated substrate. After the vapor deposition of the semiconductor material thin film, the supply of the source gas is stopped, and at least a part of the hydrogen carrier gas is brought into contact with the heated catalyst body, thereby generating high-temperature hydrogen molecules. The method according to claim 1, 2, 4, or 5 , wherein annealing is performed by applying a hydrogen-based active species composed of hydrogen atoms and activated hydrogen ions to the semiconductor material thin film. The method according to claim 7 , wherein a supply amount of hydrogen or a hydrogen-containing gas at the time of annealing is made larger than a supply amount of hydrogen or a hydrogen-containing gas at the time of vapor phase growth.   The catalyst body is formed of at least one material selected from the group consisting of tungsten, tria-containing tungsten, molybdenum, platinum, palladium, vanadium, silicon, alumina, metal-attached ceramics, and silicon carbide. The method described in 1 or 2.   The method according to claim 1 or 2, wherein the purity of the catalyst body and the support body supporting the catalyst body is 99.99 wt% or more.   The polycrystalline semiconductor thin film is composed of a polycrystalline silicon thin film, a polycrystalline germanium thin film, a polycrystalline silicon-germanium thin film, a polycrystalline silicon carbide thin film, and the hydrogen or hydrogen-containing gas is hydrogen or non-hydrogen. The method according to claim 1, comprising a mixed gas with an active gas. The method according to claim 1 or 2 , wherein the semiconductor material thin film contains at least one group IV element.   The method according to claim 1, wherein the polycrystalline semiconductor thin film forms a channel, a source and a drain region, or a wiring, a resistor, a capacitor, or an electron emitter of a thin film insulated gate field effect transistor. The method according to claim 13 , wherein after the channel, source and drain regions are formed, hydrogen-based active species generated by contacting hydrogen or a hydrogen-containing gas with a heated catalyst body are allowed to act on these regions. .   Silicon semiconductor device, silicon semiconductor integrated circuit device, silicon-germanium semiconductor device, silicon-germanium semiconductor integrated circuit device, compound semiconductor device, compound semiconductor integrated circuit device, silicon carbide semiconductor device, silicon carbide semiconductor integrated circuit device, liquid crystal display device, Manufacturing thin films for organic or inorganic electroluminescent display devices, field emission display (FED) devices, light emitting polymer display devices, light emitting diode display devices, CCD area / linear sensor devices, MOS sensor devices, solar cell devices. The method described in 1 or 2. When manufacturing a semiconductor device, a solid-state imaging device, and an electro-optical device having an internal circuit and a peripheral circuit, the polycrystalline semiconductor thin film has a channel, a source, and a drain region of a thin film insulated gate field effect transistor constituting at least a part thereof. The method according to claim 1 , wherein the method is formed by: The method according to claim 16 , further comprising a cathode or an anode connected to a drain or a source of the thin film insulated gate field effect transistor, respectively, under the organic or inorganic electroluminescent layer for each color. The cathode is also covered on the active element including the thin-film insulated gate field effect transistor, or the cathode or anode is deposited on each layer of the organic or inorganic electroluminescent layer for each color and on the entire surface of each layer. The method of claim 17 , wherein the device is manufactured. The method according to claim 17 , wherein a black mask layer is formed between the organic or inorganic electroluminescent layers for each color. An emitter of a field emission display device is connected to the drain of the thin-film insulated gate field effect transistor through the polycrystalline semiconductor thin film, and an n-type polycrystalline semiconductor film grown on the polycrystalline semiconductor thin film or The method according to claim 16 , which is formed by a multi-projection structure formed on the surface of a polycrystalline diamond film, a carbon thin film containing or not containing nitrogen, or a carbon thin film containing or not containing nitrogen. 21. The method according to claim 20 , wherein a metal shielding film having a ground potential is formed on an active element including the thin film insulated gate field effect transistor. The method according to claim 21 , wherein the metal shielding film is formed of the same material and in the same process as the gate extraction electrode of the field emission display device.

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