JP2002050762A - Display element, its manufacturing method, and display unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display element which has resuming function, while reducing the manufacture cost and the manufacture time, and to provide its manufacturing method and a display unit. SOLUTION: In a display element which is equipped with a driver (transistor) and a display (liquid crystal panel), the driver is constituted of a memory transistor 20, which has an accumulation region 16 capable of charge accumulation. In the memory transistor 20, image data are recorded by accumulating charge within the accumulation region 16. As a result, since the display element itself can be given image data recording function, the manufacture cost and the manufacturing time at manufacturing of the display element having a resuming function can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display element for recording image data by accumulating charges transferred from a conduction area in an accumulation area, a method for manufacturing the same, and a display constituted by a plurality of display elements. Related to the device.

[0002]

2. Description of the Related Art In recent years, as a next-generation display device following a CRT (Cathode Ray Tube), for example, a liquid crystal display (Li) for displaying an image by utilizing the change in the alignment of liquid crystal molecules has been proposed.
quid Crystal Display; hereinafter, simply referred to as “LCD”. ) Are widely used. This LC
As the driving method of D, for example, the “active matrix method” is predominant. Here, the “active matrix type” refers to a display unit including a liquid crystal and an electrode (transparent electrode) for changing the molecular orientation thereof,
A TFT (Thin Film Tran) for driving this display unit
A plurality of display elements (pixels) composed of a driving unit (switching element) composed of a sistor (thin film transistor)
Are arranged in a matrix on one substrate (for example, glass). With the spread of flat display devices such as LCDs, demands for higher performance are increasing.

Recently, while improving the image quality (higher definition, higher brightness, etc.) of LCDs has been demanded, it is also required to provide new functions to LCDs. The “new function” includes, for example, an image recording function, that is, a resume function. L with this resume function
In a CD, for example, when the power is turned off, an image displayed immediately before that power is recorded as image data. Then, when the power is turned on again, the recorded image data is read, and the image displayed immediately before the power is turned off is reproduced. Such a resume function of the LCD is, for example, to interrupt the data processing operation using the image data displayed on the LCD, and then to start again, when turning on the power and simultaneously processing the image being processed. Since the data is displayed, it contributes to improvement of work efficiency and the like.

[0004]

However, the conventional LCD does not have a function of recording image data (hereinafter, also simply referred to as a "memory function"). When the resume function is provided to the LCD, a memory device for recording image data and a connection circuit for connecting the memory device to the display body are newly added to the LCD.
There is a problem that the manufacturing cost is increased because the CD must be attached to the CD. Also, in the manufacturing process of LCD,
Since a complicated wiring connection process or the like for connecting the memory device and the display main body is required, the number of manufacturing steps is increased, and there is also a problem that the manufacturing time is lengthened.

The above-mentioned problem is not limited to LCDs, and various flat-panel display devices which do not originally have a memory function, such as an organic electroluminescent (hereinafter, referred to as a display), are also used as display units. Simply "EL"
Also called. ) Element, light emitting diode (Light Emitting D)
iode; hereinafter, also simply referred to as “LED”. ) Or a laser diode (hereinafter, also simply referred to as “LD”).

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a display element having a resume function, a method of manufacturing the same, and a display device while reducing manufacturing cost and manufacturing time. is there.

[0007]

A display device according to the present invention has a display unit for displaying an image and a drive unit for driving the display unit, and the display unit and the drive unit are one in one.
A display element disposed on a base portion of
A conductive region made of a semiconductor, a first impurity region provided adjacent to the memory conductive region, and a second impurity region provided adjacent to the conductive region and separated from the first impurity region. An impurity region, a control electrode provided in a region opposite to the base region with the conductive region interposed, a control electrode provided in a region between the control electrode and the conductive region, and a transition from the conductive region. A storage region for storing the generated charge, a tunnel insulating film disposed in a region between the storage region and the conduction region,
A control insulating film provided in a region between the control electrode and the storage region.

In the display element according to the present invention, when a potential is applied to the control electrode, charges are transferred from the conduction region to the accumulation region and accumulated. Thereby, the image data is recorded.

A method of manufacturing a display element according to the present invention has a display section for displaying an image and a drive section for driving the display section, and the display section and the drive section are provided on one base portion. In the method for manufacturing a display element disposed, a step of forming a driving unit includes a step of forming a conductive region made of a semiconductor in a region above an underlayer, and a step of forming a first impurity adjacent to the conductive region. Forming a region, forming a second impurity region so as to be separated from the first impurity region and adjacent to the conduction region, and forming a tunnel insulating film on the conduction region. Forming a storage region composed of a plurality of fine particles dispersed on the tunnel insulating film, forming a control insulating film on the storage region, and forming a control electrode on the control insulating film; Is like

In the method of manufacturing a display element according to the present invention, first, a conductive region made of a semiconductor is formed in a region above a base portion. Subsequently, after a tunnel insulating film is formed on the conduction region, an accumulation region including a plurality of fine particles dispersed on the tunnel insulating film is formed. Subsequently, after a control insulating film is formed on the storage region, a control electrode is formed on the control insulating film. Subsequently, a first impurity region is formed so as to be adjacent to the conduction region, and a second impurity region is formed so as to be separated from the first impurity region and to be adjacent to the conduction region.

A display device according to the present invention is a display device in which a plurality of display elements having a display section for displaying an image and a drive section for driving the display section are arranged on one base portion. The driving unit in each display element includes a conductive region made of a semiconductor, a first impurity region disposed adjacent to the conductive region, and a conductive region separated from the first impurity region and connected to the conductive region. A second impurity region provided adjacently, a control electrode provided in a region opposite to the provided region of the underlying portion across the conductive region, and a region between the control electrode and the conductive region A storage region for storing charges transitioned from the conduction region, a tunnel insulating film disposed in a region between the storage region and the conduction region, and a region between the control electrode and the storage region. And a control insulating film disposed in the That.

A display device according to the present invention uses the display element of the present invention, and image data is recorded by transferring and accumulating charges from a conduction region to a storage region.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

[First Embodiment] <Structure of Display Element> First, a display element according to a first embodiment of the present invention will be described with reference to FIG. In the following, for example, a description will be given of a display element constituting a transmissive LCD equipped with a liquid crystal as a display unit.

The display element according to the present embodiment is, for example,
In a display element constituting an active matrix type LCD, a transistor (for example, a TFT) functioning as a driver is replaced with a memory transistor having a memory function. In this display element, for example, the state of transmission (transmission / non-transmission) of light generated from a light source (backlight) disposed in a region below the base portion to the counter electrode side in accordance with a change in the alignment of liquid crystal molecules. Control, whereby the contrast (image) is reproduced.

The display element includes a base 10 and a memory transistor 20 disposed on one surface of the base 10.
(Drive unit) and a liquid crystal panel 30 (display unit).

The underlayer 10 includes, for example, a substrate 1 made of a material having transparency and relatively low heat resistance, for example, quartz, quartz glass, silicate glass, or the like, and one surface of the substrate 1 sequentially. The formed silicon nitride (Si
₃ N ₄₎ than consisting insulating film 2 and the silicon dioxide (Si
O ₂ ). Each of the insulating films 2 and 3 has a thickness of about 100 nm. These insulating films 2 and 3 function as buffer layers. The substrate 1 may be made of, for example, a material (eg, plastic) containing a resin having transparency, in addition to the above-described silicate glass. The use of the substrate 1 made of silicate glass or the like having relatively low heat resistance can be achieved, for example, by forming the storage region 16 in a predetermined configuration. Details of the configuration of the accumulation region 16 relating to the material of the substrate 1 will be described later. Here, the insulating films 2 and 3 correspond to a specific example of the “base insulating film” in the present invention.

<< Configuration of Driving Unit >> Memory Transistor 20
A source electrode 11 and a memory conductive region 12 which are arranged on the base portion 10 so as to be separated from each other; a first impurity region 13 which is arranged adjacent to the memory conductive region 12; A second impurity region disposed at a distance from the first impurity region and adjacent to the memory conductive region; a tunnel insulating film disposed over the memory conductive region; A plurality of fine particles (semiconductor fine particles 16) provided on the tunnel insulating film 15.
(B), a control insulating film 17 disposed on the storage region 16, and a memory control electrode 18 disposed on the control insulating film 17.

Here, the memory conductive region 12 corresponds to a specific example of the “conductive region” in the present invention, and the memory control electrode 18 corresponds to a specific example of the “control electrode” in the present invention.

The memory control electrode 18 functions as a “gate electrode” in the memory transistor 20 and controls the conductivity of the memory conductive region 12 and the amount of charge stored in the storage region 16. It is. The memory control electrode 18 is made of, for example, a non-single-crystal semiconductor such as polycrystalline silicon (Si) whose resistance has been reduced by adding an impurity, and has a thickness of about 1 mm.
00 nm. The impurities are, for example, Group V elements such as phosphorus (P) as n-type impurities and Group III elements such as boron (B) as p-type impurities. In addition,
The memory control electrode 18 may be made of, for example, tantalum (Ta), molybdenum (Mo),
It may be made of a metal having low resistance such as aluminum (Al), copper (Cu) or tungsten (W).

The memory conductive region 12 functions as a current flow path, that is, a charge transfer path between the first impurity region 13 and the second impurity region 14, and is, for example, a non-conductive material such as polycrystalline silicon. It is made of a single crystal semiconductor. The thickness of the memory conductive region 12 is, for example,
It is designed to be in the range of 0.01 μm or more and 0.1 μm or less, specifically, about several tens nm.

The first impurity region 13 functions as a “source region” in the memory transistor 20, and the second impurity region 14
0 functions as a “drain region”. First impurity region 13 and second impurity region 14
Are made of a non-single-crystal semiconductor (n-type semiconductor) such as polycrystalline silicon to which a group V element such as phosphorus (P) is added as an n-type impurity, and both have a thickness of about several tens. nm. The first impurity region 13 is provided, for example, such that one end thereof partially runs over part of the source electrode 11.

The memory transistor 20 is, for example,
It has an n-type channel structure. Note that each of the memory conductive region 12, the first impurity region 13, and the second impurity region 13b may be made of, for example, amorphous silicon in addition to the above-described polycrystalline silicon.

The accumulation region 16 is for accumulating charges (here, electrons) transitioned by the quantum mechanical tunnel effect. The accumulation region 16 is composed of a plurality of dispersed semiconductor fine particles 16B. For example, silicon and germanium (G
e) a material containing at least one of the above. The fine particles constituting the accumulation region 16 are, in addition to the above-described semiconductor fine particles 16B, metal fine particles such as tungsten, copper, aluminum or gold (Au), or silicon nitride (SiN _x ) or silicon oxide (SiO _x ). It may be composed of inorganic fine particles.

The tunnel insulating film 15 is for electrically separating the memory conduction region 12 and the storage region 16 from, for example, silicon dioxide, silicon nitride, or a compound of nitrogen, oxygen and silicon (oxynitride). (Silicon). The thickness of the tunnel insulating film 15 is, for example,
It is 2 nm to 20 nm.

The source electrode 11 is made of a metal having low resistance such as aluminum or copper, for example, and is in ohmic contact with the first impurity region 13.

The control insulating film 17 is for electrically separating the storage region 16 from the memory control electrode 18 and is made of, for example, substantially the same material as the tunnel insulating film 15. The thickness of the control insulating film 17 is, for example, 5
It is about 0 nm.

<< Structure of Display Unit >> The liquid crystal panel 30 covers the drive electrode 21 provided on the base portion 10 and the base having a concavo-convex structure constituted by the memory transistor 20, the drive electrode 21 and the like. Protective film 22 provided
And a counter electrode 23 disposed so as to secure a space between the protective film 22 and the liquid crystal 24 sealed in the space between the protective film 22 and the counter electrode 23.

Both the drive electrode 21 and the counter electrode 23 are made of, for example, indium tin oxide (Indium Tin Oxid).
e; hereinafter, simply referred to as “ITO”. )). When a bias is supplied between the two electrodes, the alignment state of the liquid crystal molecules (liquid crystal 24) in the region R corresponding to the region where the drive electrode 21 is provided changes. The drive electrode 21 is arranged, for example, such that one end thereof partially runs over part of the third impurity region 14.

The protective film 22 is for separating the liquid crystal 24 from the circuit portion such as the memory transistor 20 and is made of, for example, silicon nitride or silicon dioxide. As the liquid crystal 24, various alignment characteristics (for example, S
TN (Super Twisted Nematic)
Etc.) can be selected and used at any time.

Although not shown in FIG. 1, the liquid crystal panel 30 includes, for example,
A sealing material for sealing the liquid crystal 24 from the left and right directions in the drawing, a spacer for ensuring a constant area between the protective film 22 and the counter electrode 23, an alignment film for aligning the liquid crystal 24, a light source (backlight) ) Includes a polarizing plate and the like for controlling the optical rotation of the light generated from the above. Of course, if the display element constitutes an LCD for displaying a color image, a color filter is also provided.

This display element is used, for example, as a part of an LCD in which a display element including a plurality of memory transistors 20 and a liquid crystal panel 30 is integrated on one base portion 10 to display an image to be displayed. It functions as one of the pixels. Of course, this display element may be used alone. The integration of the display element (the structure of the display device) will be described in detail in the following embodiments (see fourth to seventh embodiments).

<Operation of Display Element> Next, the operation of the display element (mainly, recording, reading and erasing of image data) will be described with reference to FIG. In the following, for example, it is assumed that the liquid crystal panel 30 has normally black characteristics (light can pass between the driving electrode 21 to the counter electrode 23 when a potential is applied).

<< Display of Image and Recording of Image Data >> In the case of displaying an image and recording image data in this display element, for example, the image data is stored from the memory conductive region 12 to the memory control electrode 18. Positive potential (for example, +15 V) that can cause a charge to transition to the region 16
And a positive potential (for example, +10 V) capable of driving the liquid crystal panel 30 (changing the orientation of liquid crystal molecules) with respect to the source electrode 11. As a result, the liquid crystal panel 30 is driven to display an image (light from the light source is transmitted), and the memory transistor 2
At 0, charges (here, electrons) transition from the memory conduction region 12 to the accumulation region 16 due to the quantum mechanical tunnel effect, and the "recording of image data" is performed by changing the threshold value of the gate potential in the positive direction. . At this time, the recorded image data is stored even if the power of the display element is turned off.

<< Reading of Image Data and Display of Recorded Image >> When reading out recorded image data and displaying a recorded image, for example, the memory control electrode 18 is placed inside the storage region 16. A potential (for example, 5 V) between a gate potential threshold when electric charge is stored and a gate potential threshold when electric charge is not stored is applied, and the liquid crystal panel 3 is applied to the source electrode 11.
0 (eg, +10
V). At this time, when charge is accumulated in the accumulation region 16, the memory conduction region 12 does not conduct, but when no charge is accumulated in the accumulation region 16, the memory conduction region 12 conducts. . That is,
A recorded image is displayed on the liquid crystal panel 30 according to the presence or absence of conduction of the memory conductive region 12.

<< Erase of Image Data >> When erasing the recorded image data, for example, the electric charge accumulated inside the accumulation region 16 is applied to the memory control electrode 18 by the memory conduction region 12. To a negative potential (for example, −15 V). As a result, the threshold value of the gate potential in the memory transistor 20 changes in the negative direction, and the charge transitions from the accumulation region 16 to the memory conduction region 12 due to the quantum mechanical tunnel effect, thereby performing “erasing of image data”.

<Method of Manufacturing Display Element> Next, FIGS.
The method for manufacturing the display element will be described with reference to FIG.

In manufacturing a display element, first, as shown in FIG. 2, a chemical vapor deposition (Chemical Vapor Depositio) is formed on a transparent substrate 1 made of, for example, quartz glass.
n; hereinafter simply referred to as “CVD”. ) Method or sputtering method, the insulating film 2 made of silicon nitride is
It is formed with a thickness of nm. Subsequently, an insulating film 3 made of silicon dioxide is formed on the insulating film 2 with a thickness of about 100 nm by a method substantially similar to the case where the insulating film 2 is formed. Thereby, the base portion 10 is formed.

Subsequently, for example, a high-melting point metal layer such as tantalum or molybdenum is formed by a sputtering method, and the metal layer is patterned by photolithography and etching, thereby forming the underlying portion 10 (insulating film). 3) The source electrode 11 is selectively formed at a predetermined upper position.

Subsequently, for example, about 60
Under a substrate temperature condition in a range of 0 to 700 ° C., a non-single-crystal silicon (for example, amorphous silicon) layer is formed by a CVD method or a sputtering method. Subsequently, the semiconductor layer 100 is selectively formed with a thickness of several tens nm by patterning the non-single-crystal silicon layer using photolithography and etching to separate elements. When performing the above element isolation, for example,
One end of the semiconductor layer 100 to be formed partially overlaps a part of the source electrode 11 so that the semiconductor layer 100 and the source electrode 11 are electrically connected. The semiconductor layer 100 is a preparation layer that becomes the memory conductive region 12, the first impurity region 13, and the second impurity region 14 through an ion implantation process in a later step.

Subsequently, the semiconductor layer 100 made of, for example, amorphous silicon is irradiated with an excimer laser to heat the semiconductor layer 100. This excimer laser heating treatment (Exeimer Laser Annealing; hereinafter simply referred to as “EL
A ". As a result, the amorphous silicon constituting the semiconductor layer 100 is crystallized into polycrystalline silicon.

Subsequently, as shown in FIG. 3, the semiconductor layer 100 is placed in an ionized gas atmosphere containing oxygen atoms (O) under a substrate temperature condition of, for example, about 150 ° C. so as to cover the whole. The exposure oxidizes the surface portion of the semiconductor 100. The generation of the ionized gas is performed, for example, as described in 13.
This is performed by introducing an oxygen gas of 80 Pa into an alternating current electromagnetic field of 6 MHz and 350 W. By this oxidation treatment, the surface portion of the semiconductor layer 100 is oxidized, and the tunnel insulating film 15 made of silicon dioxide is formed. When performing the above oxidation treatment, for example, the oxidation conditions are adjusted so that the thickness of the tunnel insulating film 15 to be formed is about 10 nm. Many structural defects exist at the tunnel insulating film 15 and at the interface between the tunnel insulating film 15 and the semiconductor layer 100. As a method of forming the tunnel insulating film 15, in addition to the above-described method, for example, silicon dioxide may be deposited by a CVD method.

Subsequently, for example, ELA is performed on the tunnel insulating film 15 to heat both the tunnel insulating film 15 and the semiconductor layer 100. At this time, the irradiation time of the excimer laser beam is about 100 nsec, and the semiconductor layer 10
0 is set to be higher than the surface temperature when the tunnel insulating film 15 is formed. During the heat treatment,
Only the temperature of both the tunnel insulating film 15 and the semiconductor layer 100 increases instantaneously, and the temperature of the underlying portion 10 does not increase as much as the temperature of the tunnel insulating film 15 or the like. By this heat treatment, the film quality of the tunnel insulating film 15 is modified, and the tunnel insulating film 15 and the tunnel insulating film 15 and the semiconductor layer 100 are modified.
Structural defects at the interface between are reduced. The energy beam used to heat the tunnel insulating film 15 and the like may be, for example, an electron beam in addition to the above-described excimer laser beam.

Subsequently, for example, a plurality of semiconductor fine particles 16B made of a material containing at least one of silicon and germanium are grown on the tunnel insulating film 15 by the CVD method. A storage region 16 is formed. The growth of the semiconductor fine particles 16B by the above-described CVD method is performed, for example, by using silane (SiH ₄ ) or disilane (Si ₂ H ₆ ).
Such as gas containing silicon atoms (Si) and germane (G
The process is performed in a mixed gas with a gas containing germanium atoms (Ge) such as eH ₄ ). When forming the accumulation region 16, for example, the semiconductor fine particles 16 </ b> B are formed so that the coverage of the tunnel insulating film 15 is smaller than 1.
Grow. In addition, as a method of forming the accumulation region 16, at least one of silicon and germanium may be deposited by a sputtering method, for example, in addition to the above-described method. Also, tungsten,
In the case where the accumulation region 16 is formed of metal fine particles such as copper, aluminum or gold, or inorganic fine particles such as silicon nitride,
For example, the accumulation region 16 can be formed by growing each fine particle using a sputtering method.

Subsequently, as shown in FIG. 4, for example, a gas containing a silicon atom such as silane or disilane and a gas such as oxygen (O ₂ ) or dinitrogen monoxide (N ₂ O) are covered so as to cover the whole. CV in a mixed gas with a gas containing oxygen atoms
By the method D, the control insulating film 17 made of silicon dioxide, silicon nitride or silicon oxynitride is formed with a thickness of about 50 to 100 nm. The method for forming the control insulating film 17 is as follows.
In addition to the above method, for example, silicon may be deposited by sputtering in a gas atmosphere containing oxygen atoms such as oxygen and nitrous oxide.

Subsequently, for example, non-single-crystal silicon doped with impurities by a CVD method or a sputtering method at a predetermined position on the control insulating film 17 under a substrate temperature condition in a range of about 600 to 700 ° C. The memory control electrode 18 made of (polycrystalline silicon or amorphous silicon) is selectively formed. The above-mentioned “predetermined position” when the memory control electrode 18 is formed is, for example, a position corresponding to an arrangement position of the memory conductive region 12 to be formed in a later step. As a method of forming the memory control electrode 18, in addition to the above-described method, for example, after forming a metal layer such as tantalum, molybdenum, aluminum, copper, or tungsten by sputtering, this metal layer is etched and patterned. You may make it.

Subsequently, as shown in FIG. 5, for example, the impurity I is implanted into the semiconductor layer 100 by ion implantation using the memory control electrode 18 as a mask. As the impurity I, for example, phosphorus, which is a group V element, is used. Thereby, each of first impurity region 13 and second impurity region 14 is selectively formed. In the semiconductor layer 100, the impurity I
Are not implanted become the memory conductive regions 12.

Subsequently, the whole is heated by, for example, ELA, and the first impurity region 13 and the second impurity region 14 are heated.
Activate the impurities added to both.

Subsequently, as shown in FIG. 6, for example, using the memory control electrode 18 as a mask, an etching process is entirely performed by reactive ion etching (hereinafter, also simply referred to as “RIE”). Subject to
The first impurity region 13 and the second impurity region 14 are exposed. Thereby, the memory transistor 20 is formed.

Subsequently, as shown in FIG. 1, a drive electrode 21 made of a substrate on which a transparent electrode such as ITO is mounted on the underlying portion 10 around the second impurity region 14 by, for example, a sputtering method. Are formed selectively. When the drive electrode 21 is formed, for example, a part thereof
In such a manner that the drive electrode 21 and the second impurity region 14 are electrically connected to each other.

Subsequently, a protective film 22 made of silicon nitride or silicon dioxide is formed so as to cover the whole by, for example, a sputtering method or a CVD method. Subsequently, a counter electrode 23 made of a substrate on which a transparent electrode such as ITO is mounted is provided above the protective film 22. Subsequently, the protective film 2
The liquid crystal 24 is sealed in a space between the second electrode 2 and the counter electrode 23.
Thereby, the liquid crystal panel 30 is formed, and the display element is completed.

When the liquid crystal panel 30 is formed,
In addition to the protective film 22, the counter electrode 23, and the like, the above-described steps of forming the alignment film, the polarizing plate, the color filter, and the like are required. However, here, only the schematic steps related to the formation of the liquid crystal panel 30 will be described. A description of the formation of a series of members (such as an alignment film) is omitted.

<Effect on Display Element Structure> As described above, in the display element according to the present embodiment, the accumulation region 16
, The image data is recorded by the action of the display element alone (accumulation of charges in the accumulation region 16). Therefore, a function of recording image data can be given to the display element itself.

In this embodiment, since the memory transistor 20 having a memory function also functions as a switching element (drive unit) for driving the liquid crystal panel 30, both functions (memory function and drive function) are performed. There is no need to provide two transistors to ensure this. Therefore, the structure of the display element can be simplified.

In this embodiment, since the accumulation region 16 is constituted by the plurality of dispersed semiconductor fine particles 16B, unintended “erasure of image data” is suppressed by the following operation. be able to. That is, for example, when the accumulation region is formed of a continuous film having a two-dimensional spread, if a structural defect occurs in the tunnel insulating film due to a manufacturing factor (such as a forming temperature), the accumulation region Some of the charges stored in the semiconductor device leak through the defective area. In such a case, unintended “erase of image data” occurs due to the charge leakage phenomenon. On the other hand, in the present embodiment, the electric charge moved to the accumulation region 16 is
The data is distributed and accumulated every 6B. For this reason, even if a structural defect occurs in the tunnel insulating film 15 and the electric charge stored in some of the semiconductor particles 16B leaks through the defect region in the tunnel insulating film 15, the above-mentioned "some semiconductor particles" The electric charge accumulated in the semiconductor particles 16B other than “16B” remains accumulated inside the accumulation region 16. Therefore, the tunnel insulating film 15
The charge leakage phenomenon caused by the defect structure therein, that is, unintended “erase of image data” is suppressed, and written information can be stably stored for a long period of time.

In the present embodiment, the thickness of the memory conduction region 12 is in the range of 0.01 μm or more and 0.1 μm or less. A high-performance memory transistor 30 including the conduction region 13 made of single-crystal silicon can be configured.

<Effects Regarding Display Element Manufacturing Method> In the display element manufacturing method according to the present embodiment, a plurality of semiconductor fine particles 16B are formed by a CVD method so that the coverage of tunnel insulating film 15 is smaller than 1. Since the growth is performed in a dispersed manner, the formation of the accumulation region 16 is easier than in the case where the plurality of semiconductor fine particles 16B are grown so that the coverage is 1. Therefore, the display element can be easily manufactured.

In this embodiment, the tunnel insulating film 15 is formed by exposing the memory conductive region 13 to an ionized gas containing oxygen atoms, so that the tunnel insulating film 15 is formed under a relatively low temperature condition. 15 can be formed, and manufacturing conditions (temperature conditions) can be simplified. Specifically, when forming the tunnel insulating film 15 using a thermal oxidation method or the like, for example, 800 to 10
Although a relatively high temperature condition in the range of 00 ° C. is required, in this embodiment, a relatively low temperature condition of, for example, 150 ° C. may be used.

In this embodiment, after the semiconductor layer 100 made of amorphous silicon is formed, the amorphous silicon is subjected to ELA to be crystallized, and the semiconductor layer 100 made of polycrystalline silicon is formed. Since the semiconductor layer 100 is formed, the semiconductor layer 100 made of polycrystalline silicon can be formed under a relatively low temperature condition, and manufacturing conditions (temperature conditions) can be simplified. Specifically, when the semiconductor layer 100 made of polycrystalline silicon is directly formed, a relatively high temperature condition (for example, 1000 °
C) is required, but in this embodiment, a relatively low temperature condition (for example, 600 to 700 ° C.) may be used.

The present embodiment also has the following advantages due to the lowering of the formation temperatures of the tunnel insulating film 15 and the semiconductor layer 100 described above. That is, for example, relatively high temperature conditions (for example, 800 to 10
When the above-described portions are formed under the temperature of 00 ° C., the material of the substrate 1 is limited to a material having relatively high heat resistance (for example, silicon). On the contrary,
In the present embodiment, it is possible to select a material having relatively low heat resistance according to a decrease in the temperature for forming the tunnel insulating film 15 and the like, and the selectivity regarding the material of the substrate 1 is expanded. Specifically, as the substrate 1, it is possible to use a substrate made of silicate glass or quartz glass, which is cheaper than silicon or the like.

In the present embodiment, after the tunnel insulating film 15 is formed, ELA is applied to the tunnel insulating film 15. Therefore, the tunnel insulating film 15 can be formed without increasing the temperature of the underlying portion 10. Is improved, and structural defects at the tunnel insulating film 15 and at the interface between the tunnel insulating film 15 and the memory conductive region 12 can be reduced. For this reason, the charge leakage phenomenon in the tunnel insulating film 15 is suppressed, and this also contributes to the stabilization of “storage of image data”.

In this embodiment, the memory transistor 20 has an n-type channel structure. However, the present invention is not limited to this. For example, the memory transistor 20 may have a p-type channel structure. The memory transistor 20 having a p-type channel structure can be formed by using a group III element such as boron (B) as the impurity I in the above-described ion implantation step (see FIG. 5). In the display element having such a configuration, a series of functions (recording of image data, etc.) can be achieved by reversing the positive and negative of the potential applied to each electrode in the description of the <function of the display element> described above.
Can be executed.

In this embodiment, all of the memory conductive region 12, the first impurity region 13 and the second impurity region 14 are made of polycrystalline silicon or amorphous silicon. The material is not necessarily limited to this, and the material (polycrystalline silicon, amorphous silicon) of each of the above portions can be freely changed. Specifically, for example, a part (for example, only the memory conductive region 12) of each of the above-mentioned parts is made of amorphous silicon, and the other part (for example, the first impurity region 13 and the second impurity The region 14) may be made of polycrystalline silicon.

In the present embodiment, a transparent material is used as the material of the substrate 1 and the display element is a transmissive L.
Although it is configured to constitute a CD, it is not necessarily limited to this. For example, a non-transparent substrate or the like may be used as the substrate 1 and the display element may constitute a reflective LCD. In this reflection type LCD, the ambient light incident on the liquid crystal panel 30 from the counter electrode 23 side can be used as a light source.
Unlike the case D, there is no need to provide a light source (backlight).

Further, in the present embodiment, as shown in FIGS. 4 to 6, the memory control electrode 18 (see FIG. 4) formed on the control insulating film 17 is used as a mask to form the semiconductor layer 100.
Is subjected to ion implantation (see FIG. 5), and then the whole is subjected to etching by RIE (see FIG. 6), but is not necessarily limited to this. For example, after the memory control electrode 18 is formed, as shown in FIG. 7, the entire surface is etched by RIE using the memory control electrode 18 as a mask, and then, as shown in FIG. The ion implantation process may be applied to the exposed portion of the 100. In such a case, for example, the exposed portion of the semiconductor layer 100 is exposed to an ionized gas atmosphere containing a predetermined metal atom as an impurity. As the ionized gas, for example, when the memory transistor 20 to be formed has an n-type channel structure, a gas containing a group V element such as a phosphorus atom such as phosphine (PH ₃ ) is used. When the memory transistor 20 has a p-type channel structure, a transistor including a group III element such as boron such as diborane (B ₂ H ₆ ) is used. Thereby, similar to the case of the above-described embodiment (see FIG. 5),
Each of the memory conductive region 12, the first impurity region 13, and the second impurity region 14 is selectively formed (see FIG. 8). After the formation of the memory conductive region 12 and the like, the steps of activating the impurities introduced into each of the first impurity region 13 and the second impurity region 14 by ELA are the same as those in the above-described embodiment. Is the same as

In this embodiment, the liquid crystal is used as the display section. However, the present invention is not limited to this. For example, an organic EL element, an LED, an LD, or the like may be used in addition to the liquid crystal. Is also good. In such a case, as in the case of the above-described embodiment, the image data is recorded in the memory transistor 20, and the image data is read as needed.

Here, FIG. 9 shows a schematic configuration of a display element using an organic EL element as a display section, for example, and corresponds to FIG. 1 in the above embodiment. In FIG. 9, the same components as those shown in FIG. 1 are denoted by the same reference numerals. This display element includes a drive unit (memory transistor 20) and a display unit (light emitting panel 40). Light emitting panel 40
Is a drive electrode 41 composed of a substrate on which a transparent electrode such as ITO is mounted, and an aluminum quinolium complex (Alq
₃ ) A light-emitting layer 42 made of, a charge transport layer 43 made of a diamine-based compound, and magnesium silver (MgAg) disposed so as to face the drive electrode 41 with the light-emitting layer 42 and the charge transport layer 43 interposed therebetween. The counter electrode 44 is included. In the light emitting panel 40, for example, when a bias is applied between both electrodes (the drive electrode 41 and the counter electrode 44), charges (for example, holes) are injected from the charge transport layer 43 into the light emitting layer 42, and the light emitting layer 42 , Green light is produced. This light is recognized as an image from the substrate 1 side, for example. Each part constituting the light emitting panel 40 can be formed by, for example, a vacuum evaporation method or a sputtering method. The structural features and the like of the other parts in FIG. 9 are the same as those shown in FIG.

FIG. 10 shows a schematic configuration of a display element using an LED as a display section, for example, and corresponds to FIG. 9 described above. In FIG. 10, the same components as those shown in FIG. 9 are denoted by the same reference numerals. In this display element, for example, two semiconductors having a pn junction, that is, a p-type semiconductor 45 and an n-type semiconductor 46 are provided instead of the light emitting layer 42 and the charge transport layer 43 shown in FIG. Will be done. For example, group II zinc (Z
When gallium arsenide (GaAs) doped with n) is used and gallium arsenide doped with group VI tellurium (Te) is used as the n-type semiconductor 46, a bias is applied between both electrodes, so that The carriers (holes and electrons) in the semiconductor recombine with each other to generate red light, which is recognized as an image. Although not shown, a display element using an LD as a display unit has a structure shown in FIG.
It has almost the same structure as the display element equipped with the ED. In a display element equipped with an LD, light (laser) having high intensity is generated by stimulated emission, and this light is recognized as an image. The structural features and the like of the other parts in FIG. 10 are the same as those shown in FIG.

Other functions, effects, modifications, and the like in the display element using an organic EL element, LED, LD, or the like as the display section are the same as those in the above embodiment.

[Second Embodiment] Next, FIGS.
A display device according to a second embodiment of the present invention will be described with reference to FIG.

The display element according to the second embodiment of the present invention differs from the first embodiment in that one memory transistor 20 has both a memory function and a drive function, and has a drive function. The selection transistor 50a (drive unit) provided is provided separately from the memory transistor 50b. 11 to 15, the same components as those in the first embodiment are denoted by the same reference numerals, and a detailed description of those components will be omitted as appropriate.

This display element includes a base portion 10, a selection transistor 50a and a memory transistor 50b provided on one surface side of the base portion 10, an isolation insulating film 58 provided on both transistors, Isolation insulating film 58
And a liquid crystal panel 60 disposed thereon.

The selection transistor 50a has a source electrode 51 and a selection conduction region 52 disposed on the base portion 10 so as to be separated from each other, and is disposed adjacent to the selection conduction region 52 and separated from each other. The third impurity region 53 and the fourth impurity region 54 provided, the control insulating film 56 provided on the selection conductive region, and the selection conductive region 52 are opposed to each other with the control insulating film 56 interposed therebetween. And the selection control electrode 57 arranged as described above.
On the other hand, the memory transistor 50b has the same structure and function as the memory transistor 20 in the first embodiment. Memory transistor 50
b, fourth impurity region 54 and fifth impurity region 5
5 and the control insulating film 56 correspond to the first impurity region 13, the second impurity region 14, and the control insulating film 17 in the first embodiment, respectively. Both the fourth impurity region 54 and the control insulating film 56 include the selection transistor 50a and the memory transistor 50b.
Is shared as a part of each. Here, the fourth impurity region 54 corresponds to a specific example of “first impurity region” in the present invention, and the fifth impurity region 5
5 corresponds to a specific example of the “second impurity region” in the present invention.

Each of third impurity region 53, fourth impurity region 54, and selection control electrode 57 functions as a "source region", a "drain region", and a "gate electrode" in selection transistor 50a. .
Forming material and structure of each part (the source electrode 51, the selection conductive region 52, the third impurity region 53, the fourth impurity region 54, the control insulating film 56, the selection control electrode 57, and the like) constituting the selection transistor 50a The characteristic features and the like are the same as those of the respective portions corresponding to the respective portions in the memory transistor 20 according to the first embodiment.

The liquid crystal panel 60 has the same structure, function, and the like as the liquid crystal panel 30 in the first embodiment, and includes a drive electrode 61, a protective film 62, a counter electrode 63, a liquid crystal 64, and the like. I have. The drive electrode 61
It is provided on the isolation insulating film 58, and one end thereof extends through both the isolation insulating film 58 and the control insulating film 56 and is electrically connected to the fifth impurity region 55. .

Next, the operation of this display element will be described with reference to FIG. Hereinafter, for example, it is assumed that both the selection transistor 50a and the memory transistor 50b have an n-type channel structure. When both transistors have a p-type channel structure, the same effect is obtained by reversing the polarity of the potential applied to each electrode.

In this display element, when displaying an image and recording image data, for example, a positive potential (for example, +15 V) is applied to the memory control electrode 18 and the selection control electrode 57 is applied. A positive potential (for example, +1) that can drive the selection transistor 50a.
0V), and a positive potential (for example, +10 V) is applied to the source electrode 51. Thereby, the liquid crystal panel 6
When 0 is driven, an image is displayed, and "recording of image data" is performed in the memory transistor 50b.

When reading recorded image data and displaying a recorded image, for example, a positive potential (for example, +5 V) is applied to the memory control electrode 18 and the selection control electrode 57 is applied. Positive potential (for example, +1
0V), and a positive potential (for example, +10 V) is applied to the source electrode 51. As a result, “reading of image data” is performed in the memory transistor 50 b, and a recorded image is displayed on the liquid crystal panel 60.

When erasing the recorded image data, for example, a negative potential (eg, −15 V) is applied to the memory control electrode 18 and a positive potential (eg, −15 V) is applied to the selection control electrode 57. For example, a positive potential (for example, +10 V) is applied to the source electrode 51.
Thus, “erasing of image data” is performed in the memory transistor 50b.

Next, a method for manufacturing this display element will be described with reference to FIGS. In the manufacturing method of the display element, the storage region 1 is formed on the tunnel insulating film 15.
6 (the semiconductor fine particles 16B) are the same as the steps up to the step shown in FIG. 3 in the first embodiment, and the description thereof will be omitted.

When the display element is manufactured, the storage region 16
Then, as shown in FIG. 12, for example, an etching process is performed by RIE in a mixed gas of carbon tetrafluoride and hydrogen, and the tunnel insulating film 15 and the accumulation region 16 (semiconductor fine particles 16B) are removed. A region other than the portion corresponding to the region where the memory conductive region 12 (see FIG. 14) to be formed in a later step is removed is selectively removed.

Subsequently, as shown in FIG. 13, for example,
In a mixed gas of a gas containing silicon atoms such as silane and disilane and a gas containing oxygen atoms such as oxygen and dinitrogen monoxide, silicon dioxide, silicon nitride or silicon oxynitride is formed so as to cover the whole by a CVD method. The control insulating film 56 is formed with a thickness of about 50 to 100 nm.

Subsequently, non-single-crystal silicon (polycrystalline silicon) doped with impurities is formed on the control insulating film 56 by a CVD method or a sputtering method under a substrate temperature condition in a range of about 600 to 700 ° C. Alternatively, each of the selection control electrode 57 and the memory control electrode 18 made of (or amorphous silicon) is selectively formed.

Subsequently, as shown in FIG. 14, for example,
Using both the selection control electrode 57 and the memory control electrode 18 as a mask, an impurity I is implanted into the semiconductor layer 100 by ion implantation, and the third impurity region 53, the fourth impurity region 54, and the fifth Each of the impurity regions 55 is selectively formed. As the impurity I, for example, when both the select transistor 50a and the memory transistor 20 have an n-type channel structure, phosphorus or the like which is a Group V element is used, while the p-type channel structure is used. In this case, a group III element such as boron is used.
Portions of the semiconductor layer 100 where the impurity I is not implanted become the selection conductive regions 52 and the memory conductive regions 12.

Subsequently, the whole is heated by, for example, ELA to activate the impurities added to the third impurity region 53, the fourth impurity region 54, and the fifth impurity region 55, respectively. Thereby, the selection transistor 50a
And a memory transistor 50b are formed.

Subsequently, as shown in FIG. 15, for example,
Using the same forming material and forming method as when the control insulating film 56 is formed, the isolation insulating film 58 is formed so as to cover both the selection control electrode 57 and the memory control electrode 18.

Subsequently, for example, by an etching process using RIE, a part of each of the isolation insulating film 58 and the control insulating film 56 above the fifth impurity region 55 is selectively removed to form an opening 58k. Then, a part of the fifth impurity region 55 is exposed. Subsequently, a drive electrode 61 formed of a substrate on which a transparent electrode such as ITO is mounted is formed on the isolation insulating film 58 by, for example, a sputtering method. When the drive electrode 61 is formed, one end thereof extends through the opening 58k so as to be electrically connected to the exposed portion of the fifth impurity region 55.

The steps after the formation of the protective film 62 (the step of forming the liquid crystal panel 60) shown in FIG. 11 are the steps after the formation of the protective film 22 in the first embodiment (see FIG. 1). ), And the description thereof is omitted. When the formation of the liquid crystal panel 60 is completed, the display element is completed.

In the display element according to the present embodiment, two transistors having different functions, that is, the selection transistor 50a having the driving function and the memory transistor 20 having the memory function are provided. Unlike the first embodiment, which has both functions, the gate potential applied for image display and the gate potential applied for image recording can be independently controlled.

The functions, effects, modifications, and the like other than those described above relating to the structure and the manufacturing method of the display element of the present embodiment are the same as those of the first embodiment.

In this embodiment, as shown in FIG. 11, the selection transistor 50a, the memory transistor 50b, and the liquid crystal panel 60 are arranged in this order, but the present invention is not limited to this. The arrangement order of each of the above-described parts can be freely changed according to the circuit design or the like. For example, as shown in FIG. 16, the memory transistor 50b, the selection transistor 50a, and the liquid crystal panel 60 may be arranged in this order.
In such a case, the third impurity region 53 and the fourth
Each of impurity regions 54 of memory transistor 50
b functions as a “source region” and a “drain region”, and each of the fourth impurity region 54 and the fifth impurity region 55 functions as a “source region” and a “drain region” in the select transistor 50a. Become. In the display element having such a configuration, the same operation and effect as in the above embodiment can be obtained. The structural features and the like of the other parts in FIG. 16 are the same as those shown in FIG.

[Third Embodiment] Next, a display device according to a third embodiment of the present invention will be described with reference to FIG.

The display element according to the third embodiment of the present invention is different from the above-described second embodiment in which the memory transistor 50b has one memory control electrode 18.
The memory transistor 50d has the same structure as the display element in the second embodiment, except that the memory transistor 50d has two control electrodes (the memory control electrode 18 and the memory auxiliary electrode 71). Note that, in FIG. 17, the same components as those in the second embodiment are denoted by the same reference numerals, and detailed description of these components will be omitted as appropriate.

This display element includes a base portion 10, a selection transistor 50c and a memory transistor 50d provided on the base portion 10, an isolation insulating film 58 provided on both transistors, and a liquid crystal panel 60. And

The memory transistor 50d includes, in addition to the components constituting the memory transistor 50b in the second embodiment, a memory auxiliary electrode 71 provided on the base portion 10, and a memory auxiliary electrode 71 An auxiliary insulating film 72 for electrically isolating the memory conductive region 12 and the like is provided. The memory auxiliary electrode 71 is disposed, for example, so as to face the memory control electrode 18 with the memory conduction region 12 interposed therebetween. It is for suppressing. The thickness of the auxiliary insulating film 72 in a region between the memory auxiliary electrode 71 and the memory conductive region 12 is, for example, the memory control electrode 18.
The thickness of the control insulating film 56 in the region between the control insulating film 56 and the storage region 16 is smaller. Specifically, for example, the former thickness (for example, 25 nm) is different from the latter thickness (for example, 5 nm).
0 nm). Here, the memory auxiliary electrode 71 corresponds to a specific example of “auxiliary electrode” in the present invention.

The selection transistor 50c is an auxiliary insulating film provided in the region between the base portion 10 and the selection conduction region 52 and the like, in addition to the parts constituting the selection transistor 50a in the second embodiment. 72 are included.

Next, the operation of this display element will be described with reference to FIG. In the following, it is assumed that, for example, both the selection transistor 50c and the memory transistor 50d have an n-type channel structure. When both transistors have a p-type channel structure, the same effect is obtained by reversing the polarity of the potential applied to each electrode.

In this display element, when displaying an image and recording image data, for example, when the potential of the memory auxiliary electrode 71 is set to 0 V, a positive potential ( For example, +15 V) is applied, a positive potential (for example, +10 V) is applied to the selection control electrode 57, and a positive potential (for example, +10 V) is applied to the source electrode 51. As a result, the liquid crystal panel 60 is driven to display an image, and "recording of image data" is performed in the memory transistor 50d.

When the recorded image data is read out and the recorded image is displayed, for example, with the potential of the memory control electrode 18 set to 0 V, a positive potential ( For example, 10 V) is applied, and a positive potential (for example, +1) is applied to the selection control electrode 57.
0V), and a positive potential (for example, +10 V) is applied to the source electrode 51. Thus, “reading of image data” is performed in the memory transistor 50 d, and a recorded image is displayed on the liquid crystal panel 60.

In this display element, as described above, when reading the recorded image data, the memory auxiliary electrode 7
1 is applied with a potential. Therefore, unlike the above-described embodiments in which a potential is applied to the memory control electrode 18, a potential change between the memory conductive region 12 and the storage region 16 when the potential is applied is suppressed.

When erasing recorded image data, for example, a negative potential (for example, -15 V) is applied to the memory control electrode 18 with the potential of the memory auxiliary electrode 71 set to 0 V. Then, a positive potential (for example, +10 V) is applied to the selection control electrode 57, and a positive potential (for example, +10 V) is applied to the source electrode 51. Thus, “erasing of image data” is performed in the memory transistor 50d.

This display element can be manufactured through the same manufacturing steps as in the case of the second embodiment. The memory auxiliary electrode 71 and the auxiliary insulating film 72
Are formed in the same manner as the memory control electrode 18 and the control insulating film 56 in the second embodiment.

In the display element according to the present embodiment, when performing “reading of image data”, the memory auxiliary electrode 71 is used.
Is applied to both of them, a potential change between the memory conductive region 12 and the storage region 16 is suppressed, and a transition of charges due to this potential change is suppressed. For this reason,
Unintended recording or erasing of image data at the time of "reading out image data" is suppressed, and the recorded image data can be read out accurately.

In this embodiment, the auxiliary insulating film 72 is used.
Is made smaller than the thickness of the control insulating film 56, the distance between the memory auxiliary electrode 71 and the storage region 16 is larger than the distance between the memory control electrode 18 and the storage region 16. Become smaller. In such a case, at the time of “reading of image data”, the memory control electrode 18
By applying a potential lower than the potential required when applying a potential to the memory auxiliary electrode 71,
It is possible to drive the memory transistor 50d. Therefore, power consumption required to drive the memory transistor 50d can be reduced.

The functions, effects, modifications, and the like other than those described above relating to the structure and the manufacturing method of the display element of this embodiment are the same as those of the above embodiments.

[Fourth Embodiment] Next, FIGS.
A display device according to a fourth embodiment of the present invention will be described with reference to FIG. In the following, for example, it is assumed that a display device is configured by integrating a plurality of display elements in the first embodiment.

FIG. 18 shows a planar structure of a display device (LCD) in which display elements are integrated, and FIG. 19 shows a sectional structure taken along line AA in FIG. FIG. 20 illustrates a circuit configuration of the display device illustrated in FIG. In FIG. 18, for example, among the plurality of display elements shown in FIG.
112, 121 and 122 are shown. In the following, in FIGS. 18 to 20, among the arrangement directions of the display elements, the X-axis direction in the drawings is described as “row (or row direction)”, and the Y direction in the drawings is described as “column ( Or column direction) ". In each drawing, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description of these components will be omitted as appropriate.

In the display element 111 where the source electrode 11 is provided in the first embodiment, a data line D1 having the same function as the source electrode 11 is provided.
Are arranged. The data line D1 extends in, for example, the “column direction”, and a plurality of display elements (for example, the display element 121 and the like) other than the display element 111 arranged in the same “column” are also provided. It is arranged via the data line D1.

In the display element 111, the gate line G1 having the same function as that of the memory control electrode 18 is provided in the area where the memory control electrode 18 is provided in the first embodiment. ing. A part of the gate line G1 extends, for example, in the “row” direction, and
A plurality of display elements other than the display element 111 (for example, the display element 112) are also disposed via the gate line G1.

It should be noted that a plurality of other display elements (for example, display element 12) are arranged in the same “column” as display element 112.
2) are arranged via the data line D2 as in the case of the display element 111 and the like described above. Also, the display element 1
The other display elements (for example, the display element 122 or the like) arranged in the same “row” as the display element 1
As in the case of No. 11, it is arranged via the gate line G2. Of course, the other plurality of display elements constituting the display device also have the above-described four display elements (111, 112, 1).
21 and 122), they are arranged via a plurality of data lines, gate lines and word lines, respectively. The other structure of each display element is the same as that of the first embodiment (see FIG. 1).

In this display device, as shown in FIG. 18, for example, gate lines and data lines are arranged so as to be orthogonal. One display element including the memory transistor 20 and the liquid crystal panel 30 corresponds to “one pixel” forming an image.

In the display device having such a configuration, for example, when only the display element 111 is driven, one of the “operations of the display element” described in the first embodiment is referred to as the “control electrode for memory”. "18" is replaced with "gate line G1" and "source electrode 11" is replaced with "data line D1", so that a potential is applied to each wiring. This makes it possible to execute a series of functions (recording of image data, etc.) on the display element 111 as in the case of the first embodiment. In addition,
When the display element 111 is driven, another wiring (gate line G) other than the above-described wiring (gate line G1 and data line D1) is used.
2, the data line D2, etc.) is, for example, 0V.

This display device repeats, for example, the method of manufacturing the display element described in the first embodiment,
It can be manufactured by arranging a plurality of memory transistors 20 and a liquid crystal panel 30 on one base 10 in a matrix. The forming materials and forming methods of the data lines and the gate lines are the same as those of the source electrode 11 and the memory control electrode 18 in the first embodiment, for example.

In the display device according to the present embodiment, a plurality of display elements having the memory function shown in the first embodiment are used, so that peripheral devices such as a memory device are separately provided. Without having the resume function. Therefore, the manufacturing cost of the display device can be reduced. In addition, since a complicated wiring connection step or the like for connecting the peripheral device and the display device described above is not required, the number of manufacturing steps involved in manufacturing the display device can be reduced, and the manufacturing time can be reduced.

[Fifth Embodiment] Next, FIGS.
The display device according to the fifth embodiment of the present invention will be described with reference to FIG. In the following, for example, it is assumed that a display device is configured by integrating a plurality of display elements in the second embodiment.

FIG. 21 shows a planar structure of a display device in which display elements are integrated, and FIG. 22 shows a sectional structure taken along line BB in FIG. FIG. 23 illustrates a circuit configuration of the display device illustrated in FIG. FIG. 21 shows, for example, four display elements 211, 212, 221, 222 among a plurality of display elements arranged in a matrix (see FIG. 23). 21 to 23, the same components as those in the second embodiment are denoted by the same reference numerals, and detailed description of these components will be described.
Omitted as appropriate.

In the selection transistor 50a of the display element 211, a data line D11 is provided in a region where the source electrode 51 is provided in the second embodiment. This data line D11 is, for example, a “column”
And a plurality of display elements other than the display elements 211 arranged in the same “column” (display elements 22).
1) are also arranged via the data line D11.

A gate line G11 having the same function as the selection control electrode 57 is provided in the area where the selection control electrode 57 is provided in the second embodiment. A part of the gate line G11 extends, for example, in the “row” direction, and includes a plurality of display elements other than the display elements 211 (display elements 212) arranged in the same “row”.
) Are also arranged via the gate line G11.

In the memory transistor 50b of the display element 211, in the area where the memory control electrode 18 is provided in the second embodiment, the word line W11 having the same function as the memory control electrode 18 is provided. Are arranged. A part of the word line W11 is, for example,
A plurality of display elements (such as the display element 212) other than the display element 211 disposed in the same “row” and extending in the “row” direction are also disposed via the word line W11. ing.

Note that a plurality of display elements (212, 221 and 222, etc.) other than the display element 212 also have a plurality of various wirings (data lines D1 and D2) as in the case of the display element 212.
1, D12, gate lines G11, G12, word line W1
1, W12). The other structure of each display element is the same as that of the second embodiment (see FIG. 11).

In this display device, as shown in FIG. 21, for example, each wiring is arranged so that a data line is orthogonal to each of a gate line and a word line. One display element including the selection transistor 50a, the memory transistor 50b, and the liquid crystal panel 60 includes:
This corresponds to “one pixel” that constitutes an image.

In the display device having such a configuration, for example, when only the display element 211 is driven, one of the functions of the display element described in the second embodiment is the “selection control electrode 57”. To “Gate line G1
1 "," memory control electrode 18 "is replaced with" word line W11 "," third impurity region 53 "is replaced with" data line D11 ", and a potential is applied to each wiring. . This makes it possible to execute a series of functions (recording of image data and the like) on the display element 211 as in the case of the second embodiment.
Note that when driving the display element 211, the above-described wiring (gate line G11, word line W11, data line D11)
The potentials of the other wirings (gate line G12, word line W12, data line D12, etc.) are, for example, 0V.

This display device repeats, for example, the method of manufacturing the display element described in the second embodiment,
It can be manufactured by arranging a plurality of select transistors 50a, memory transistors 50b, and liquid crystal panels 60 on one base 10 in a matrix. The forming materials and forming methods of the data lines, gate lines, and word lines are the same as those of the source electrode 51, the selection control electrode 57, and the memory control electrode 18 in the second embodiment, for example. It is.

In the display device according to this embodiment, the selection transistor 50a shown in the second embodiment is used.
And a plurality of display elements having the memory transistor 50b, the gate potential applied for image display and the gate potential applied for image recording can be independently controlled.

[Sixth Embodiment] Next, FIGS.
A display device according to a sixth embodiment of the present invention will be described with reference to FIG.

The display device according to the present embodiment is obtained by, for example, changing the arrangement position of the gate lines and the extending direction of the word lines shown in the fifth embodiment.

FIG. 24 shows a planar structure of a display device in which display elements are integrated, and FIG. 25 shows a sectional structure taken along line CC in FIG. FIG. 26 illustrates a circuit configuration of the display device illustrated in FIG. FIG. 24 shows, for example, four display elements 311, 312, 321, and 322 among a plurality of display elements arranged in a matrix (see FIG. 26). 24 to 26, the same components as those in the fifth embodiment are denoted by the same reference numerals, and detailed description of these components will be omitted as appropriate.

In this display device, as shown in FIG. 25, an interlayer insulating film 80 is provided in a region between the isolation insulating film 58 and the liquid crystal panel 60. In the display element 311,
A word line W21 is provided on the isolation insulating film 58,
A part thereof penetrates the isolation insulating film 58 and is electrically connected to the memory control electrode 18. This word line W21
Corresponds to the word line W11 in the fifth embodiment, and is arranged, for example, so as to be parallel to the data line D11, that is, to extend in the “column” direction. I have. As shown in FIG.
Other display elements (such as the display element 321) arranged in the same “column” as 11 are arranged via the word line W21. Note that other display elements (such as the display element 322) arranged in the same “column” as the display element 312
Also, as in the case of the display element 311 and the like, the word line W2
2 are provided. The material and method of forming the word line W21 and the interlayer insulating film 80 are the same as those of the data line D11 and the isolation insulating film 58, for example.

Gate lines G21 and G22 correspond to gate lines G11 and G12 in the fifth embodiment. As shown in FIG. 24, the gate lines G21, G
22 is different from, for example, the fifth embodiment in which the gate lines G11 and G12 are arranged in the lower region of the select transistor 50a in FIG. It is arranged.

As described above, even when the disposition position and the extending direction of the various wirings (for example, the word line W21, the gate line G21, etc.) constituting the display device are changed, the fifth embodiment can be used. The same effect as in the case can be obtained. Note that the arrangement positions and extending directions of the various wirings are not necessarily limited to the above-described cases, and can be freely changed according to the circuit design and the like.

[Seventh Embodiment] Next, FIGS.
With reference to FIG. 9, a display device according to a seventh embodiment of the present invention will be described. In the following, for example, it is assumed that a display device is configured by integrating a plurality of display elements having the same structure as the display element in the third embodiment.

FIG. 27 shows a plan structure of a display device in which display elements are integrated, and FIG. 28 shows a cross-sectional structure taken along line DD in FIG. FIG. 29 illustrates a circuit configuration of the display device illustrated in FIG. FIG. 27 illustrates, for example, four display elements 411, 412, 421, and 422 among a plurality of display elements (see FIG. 29) arranged in a matrix. 27 to 29, the same components as those in the third embodiment are denoted by the same reference numerals, and detailed description of these components will be described.
Omitted as appropriate.

In the memory transistor 50d of the display element 411, the lower word having the same function as the memory auxiliary electrode 71 is provided in the area where the memory auxiliary electrode 71 is provided in the third embodiment. Line WL31
Are arranged. The lower word line WL31 extends, for example, in the “column” direction, and includes a plurality of display elements (such as the display element 421) other than the display element 411 arranged in the same “column”. Also, they are arranged via a lower word line WL31. The material and method for forming the lower word line WL31 are the same as, for example, those of the memory auxiliary electrode 71. It should be noted that other display elements (such as the display element 422) arranged in the same “column” as the display element 412 are also configured via the lower word line WL32 as in the case of the display element 411. ing.

Of the display element 411, the upper word line WU31 in the memory transistor 50d, the data line D31 and the gate line G3 in the select transistor 50c.
1 are, for example, the data line D11, the gate line G11, and the word line 11 in the fifth embodiment.
Have the same structural features and functions as those of the above. That is, a plurality of display elements other than the display element 411 (display elements 412, 421, 422, etc.) are connected to various wirings (upper word lines WU31, WU32, etc., data lines D31, D32) in the same manner as the display element 411. , Etc.), and gate lines G31, G32, etc.).

The other structure of each display element is the same as that of the third embodiment (see FIG. 17).

In the display device having such a configuration, for example, when only the display element 411 is driven, one of the functions of the display element described in the third embodiment is “selection control electrode 57”. To "Gate line G3
1 ", the" memory control electrode 18 "is replaced with the" upper word line WU31 ", and the" memory auxiliary electrode 7 "is replaced.
"1" is replaced with "lower word line WL31", "third impurity region 53" is replaced with "data line D31", and a potential is applied to each wiring. This allows
As in the case of the third embodiment, the display element 411
Can execute a series of functions (recording of image data, etc.). When the display element 411 is driven, all the wirings (gate lines G) other than the above-described wirings are used.
32, etc., upper word line WU32, etc., lower word line WL3
2 and the data line D32) are set to, for example, 0V.

This display device repeats, for example, the method of manufacturing the display element described in the third embodiment,
It can be manufactured by arranging a plurality of select transistors 50c, memory transistors 50d, and liquid crystal panels 60 on one base portion 10 in a matrix.

The display device according to this embodiment is constituted by the plurality of display elements shown in the third embodiment, and at the time of “reading image data”, the lower word line (for example, , Lower word line WL
31), an unintended recording or erasing of image data is suppressed, and a recorded image can be accurately reproduced.

As described above, the present invention has been described with reference to the respective embodiments. However, the present invention is not limited to the above embodiments, and can be variously modified. For example, in each of the above-described embodiments, the insulating film 2 and the insulating film 3 are sequentially laminated on the substrate 1 to form the base portion 10.
Only one of (silicon nitride) and the insulating film 3 (silicon dioxide) may be formed to form the underlayer 10. Alternatively, for example, an insulating film made of silicon oxynitride may be formed on the substrate 1 to form the base portion 10. The base portion 10 may be any material that can serve as a base when forming a memory transistor or the like. For example, an insulating film formed on an appropriate substrate via an arbitrary semiconductor element may be used. May be used as a base portion.

In each of the above embodiments, the memory conduction region 12, the first impurity region 13, the second impurity region 14, the selection conduction region 52, the third impurity region 53, and the fourth impurity region Although each of the 54 and the fifth impurity region 55 is made of polycrystalline silicon or amorphous silicon, it is not necessarily limited to this. For example, each of the above portions may be made of a composite of polycrystalline silicon and amorphous silicon or the like, may be made of a material other than silicon (for example, germanium or the like), or Compound semiconductors (eg, silicon germanium and gallium arsenide (Ga
As) etc.).

In each of the above embodiments, the tunnel insulating film 15 is made of an oxide film. However, the present invention is not limited to this. For example, the tunnel insulating film 15 may be made of a nitride film or an oxynitride film. Is also good. The tunnel insulating film 15 made of a nitride film is made of, for example, ammonia (N
H ₃ ) or nitrogen (N ₂ ) is introduced into an AC electromagnetic field to generate an ionized gas containing nitrogen atoms (N), and then the semiconductor layer 100 can be formed by exposing the semiconductor layer 100 to the ionized gas. On the other hand, the tunnel insulating film 15 made of an oxynitride film
For example, it can be formed by introducing dinitrogen monoxide (N ₂ O) into an AC electromagnetic field to generate an ionized gas containing oxygen atoms and nitrogen atoms, and then exposing the semiconductor layer 100 to the ionized gas. .

Further, in each of the above-described embodiments, the structural defects in the tunnel insulating film 15 are reduced by irradiating the energy beam and heating the tunnel insulating film 15, but the present invention is not limited to this. is not. As a method of heating the tunnel insulating film 15, in addition to the above-described irradiation of the energy beam, for example, a heating device such as a lamp or a heater may be used. However, when heating the tunnel insulating film, it is preferable to select a temperature region where the substrate 1 does not deform so as to perform the overheating.

In the third embodiment (see FIG. 17), the memory conduction region 12 and the memory control electrode 1
8, the storage region 16 is disposed in the region between the memory conduction region 12 and the memory auxiliary electrode 71. However, the storage region 16 is not limited to this. 16 may be provided. In the display element having such a configuration, the same operation and effect as in the third embodiment can be obtained. Of course, a display device may be configured using a plurality of display elements in which the arrangement position of the accumulation region 16 is changed.

[0144]

As described above, the method for manufacturing a display element according to any one of claims 1 to 23 or the method for manufacturing a display element according to any one of claims 24 to 29 is described. According to this configuration, since the driving unit includes the accumulation region that accumulates the electric charge that has transitioned from the conduction region, the image data is recorded in the display element itself by accumulating the electric charge inside the accumulation region. . This eliminates the need for a peripheral device such as a memory device, so that the manufacturing cost of the display element can be reduced and the manufacturing time can be shortened.

In particular, according to the display element of the fifth aspect or the method of manufacturing the display element of the twenty-ninth aspect, the auxiliary electrode provided in the region between the base portion and the conduction region is provided. , By applying a potential to the auxiliary electrode at the time of “reading image data”,
The change in potential between the accumulation regions is suppressed, and the movement of charges due to the change in potential is suppressed. For this reason, unintended writing and erasing of image data can be suppressed, and the recorded image data can be accurately read.

According to the display device of the seventh aspect,
Since the thickness of the auxiliary insulating film is made smaller than the thickness of the control insulating film, the potential applied to the auxiliary electrode can be made smaller than the potential applied to the control electrode. Thus, power consumption for driving the memory element can be reduced.

Further, according to the display element of the present invention, since the accumulation region is configured to include a plurality of dispersed fine particles, unintended “erasure of image data” caused by charge leakage. And stored image data can be stably stored for a long period of time.

According to the display element of the present invention, the thickness of the conduction region is in the range of 0.01 μm or more and 0.1 μm or less. A high-performance memory device having such a conductive region can be constructed.

Further, according to the method of manufacturing a display element according to any one of claims 25 to 27, the semiconductor layer is exposed to an ionized gas containing at least one of oxygen atoms and nitrogen atoms. Since the tunnel insulating film is formed, the tunnel insulating film can be formed under a relatively low temperature condition. Therefore, the formation of the tunnel insulating film can be facilitated, and
An inexpensive material having relatively low heat resistance can be used as a material for forming the base.

According to the method of manufacturing a display element of the present invention, the tunnel insulating film is formed, and then the tunnel insulating film is irradiated with an energy beam. Structural defects at the tunnel insulating film and at the interface between the tunnel insulating film and the memory conductive region can be reduced without increasing the temperature of the portion. For this reason, even when the tunnel insulating film is formed under a relatively low temperature condition, it is necessary to prevent charge leakage due to the above structural defect and to stably store recorded image data for a long period of time. Can be.

According to the display device of the present invention, since the display device is constituted by a plurality of display elements of the present invention, it is possible to record image data without requiring a peripheral device such as a memory device. Becomes Thus, the manufacturing cost of the display device can be reduced, and the manufacturing time can be shortened.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a configuration of a display element according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining one step in the method of manufacturing the display element according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining a step following the step shown in FIG. 2;

FIG. 4 is a cross-sectional view for explaining a step following the step shown in FIG. 3;

FIG. 5 is a cross-sectional view for explaining a step following the step shown in FIG. 4;

FIG. 6 is a cross-sectional view for explaining a step following the step shown in FIG. 5;

FIG. 7 is a cross-sectional view for explaining a modification example of the method for manufacturing the display element according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view for explaining a step following the step shown in FIG. 7;

FIG. 9 is a cross-sectional view illustrating a modification example of the structure of the display element according to the first embodiment of the present invention.

FIG. 10 is a cross-sectional view for explaining another modification example of the structure of the display element according to the first embodiment of the present invention.

FIG. 11 is a cross-sectional view for explaining a configuration of a display element according to a second embodiment of the present invention.

FIG. 12 is a cross-sectional view for explaining one step in a method for manufacturing a display element according to the second embodiment of the present invention.

FIG. 13 is a cross-sectional view for explaining a step following the step shown in FIG. 12;

FIG. 14 is a sectional view for illustrating a step following the step shown in FIG. 13;

FIG. 15 is a sectional view for illustrating a step following the step shown in FIG. 14;

FIG. 16 is a cross-sectional view illustrating a modification example of the structure of the display element according to the second embodiment of the present invention.

FIG. 17 is a cross-sectional view for explaining a configuration of a display element according to a third embodiment of the present invention.

FIG. 18 is a plan view illustrating a configuration of a display device according to a fourth embodiment of the present invention.

19 is a cross-sectional view of the display device shown in FIG. 18, taken along line AA.

20 is a circuit diagram for explaining a circuit configuration of the display device shown in FIG.

FIG. 21 is a plan view illustrating a configuration of a display device according to a fifth embodiment of the present invention.

22 is a cross-sectional view of the display device shown in FIG. 21, taken along line BB.

FIG. 23 is a circuit diagram illustrating a circuit configuration of the display device illustrated in FIG. 21.

FIG. 24 is a plan view illustrating a configuration of a display device according to a sixth embodiment of the present invention.

25 is a cross-sectional view of the display device shown in FIG. 24, taken along line AA.

26 is a circuit diagram for describing a circuit configuration of the display device illustrated in FIG.

FIG. 27 is a plan view illustrating a configuration of a display device according to a seventh embodiment of the present invention.

28 is a cross-sectional view of the display device shown in FIG. 27, taken along line AA.

FIG. 29 is a circuit diagram illustrating a circuit configuration of the display device illustrated in FIG. 27.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate, 2, 3 ... Insulating film, 10 ... Base part, 11, 51
... Source electrode, 12 ... Memory conductive electrode, 13 ... First control insulating film, 14 ... Second impurity region, 15 ... Tunnel insulating film, 16 ... Storage region, 16B ... Semiconductor fine particles, 1
7, 56: control insulating film, 18: control electrode for memory, 2
0, 50b, 50d ... memory transistors, 21, 4
1, 61: drive electrode, 22, 62: protective film, 23, 4
4, 63 ... counter electrode, 24, 64 ... liquid crystal, 30, 60 ...
Liquid crystal panel, 40 ... Light emitting panel, 42 ... Light emitting layer, 43 ...
Charge transport layer, 45: p-type semiconductor, 46: n-type semiconductor, 5
0a, 50c: selection transistor, 52: selection control electrode, 53: third impurity region, 54: fourth impurity region, 55: fifth impurity region, 57: selection control electrode,
58: isolation insulating film, 71: auxiliary electrode for memory, 72: auxiliary insulating film, 80: interlayer insulating film, 100: semiconductor layer, 11
1,112,121,122,211,212,22
1,222, 311,312,321,322,41
1,412,421,422 ... display element, D1, D2
D11, D12, D21, D22, D31, D32 ... data lines, G1, G2, G11, G12, G21, G2
2, G31, G32: gate line, I: impurity, W11,
W12, W21, W22 ... word lines, WU31, WU3
2: Upper word line, WL31, WL32: Lower word line.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) H01L 21/8247 H01L 27/10 434 5F110 27/115 29/78 371 29/788 612B 29/792 F term (reference) 2H090 JB02 JB03 2H092 JA21 JA24 JA33 JA36 JA40 JA41 JB13 JB21 JB69 KA04 KA05 KA08 KA10 KA18 KB11 KB25 MA05 MA08 MA18 MA23 MA27 MA30 5C094 AA22 AA33 AA43 AA44 AA54 BA03 BA09 BA23 BA27 BA43 CA19 AEFB1A14 EA14 DA14 AD12 AD41 AD70 AG12 AG21 5F083 EP17 EP22 EP42 ER03 ER14 PR21 PR36 5F110 AA04 AA16 AA17 BB02 BB08 CC10 DD01 DD02 DD03 DD13 DD14 EE02 EE03 EE04 EE09 EE44 EE45 FF02 FF03 FF04 FF23 GG23 FF23 GG23 FF23 GG23 FF23 GG23 FF28 HK04 HK07 HK33 NN02 NN23 NN24 NN34 NN35 NN62 NN71 PP03 PP29 QQ11

Claims (30)

[Claims] 1. A display element having a display unit for displaying an image and a drive unit for driving the display unit, wherein the display unit and the drive unit are disposed on one base unit. Wherein the driving unit comprises: a conductive region made of a semiconductor; a first impurity region disposed adjacent to the conductive region; and a distance from the first impurity region. A second impurity region disposed adjacently, a control electrode disposed in a region opposite to the disposed region of the base portion with the conductive region interposed, and a control electrode disposed between the control electrode and the conductive region. Located in the area between
An accumulation region for accumulating the charge transferred from the conduction region; a tunnel insulating film disposed in an area between the accumulation region and the conduction region; and a region between the control electrode and the accumulation region. A display element, comprising: a control insulating film provided. 2. The semiconductor device according to claim 1, wherein the base portion includes a substrate made of a predetermined material, and a base insulating film disposed to cover a surface of the substrate. 2. The display element according to 1. 3. The display element according to claim 2, wherein said substrate is made of a material containing any of quartz, glass, and resin. 4. The display element according to claim 2, wherein said base insulating film is made of a material containing at least one of silicon nitride and silicon dioxide. 5. An auxiliary electrode provided in a region between the base portion and the conductive region, and an auxiliary insulating film provided in a region between the auxiliary electrode and the conductive region. The display device according to claim 1, further comprising: 6. The storage device according to claim 1, wherein at least one of the control electrode and the auxiliary electrode controls an amount of charge stored in the storage region and a conductivity of the conductive region. 5. The display element according to 5. 7. The display device according to claim 5, wherein a thickness of the auxiliary insulating film is smaller than a thickness of the control insulating film. 8. The display device according to claim 5, wherein both the control electrode and the auxiliary electrode are made of a material containing any of metal, polycrystalline silicon, and amorphous silicon. 9. The method according to claim 1, wherein each of the tunnel insulating film, the control insulating film, and the auxiliary insulating film is made of a material containing any of silicon dioxide, silicon nitride, or a compound of silicon, oxygen, and nitrogen. The display device according to claim 5, wherein 10. The display device according to claim 1, wherein the accumulation region includes a plurality of dispersed fine particles. 11. The display element according to claim 10, wherein the fine particles are made of a semiconductor containing any of silicon or germanium, and a material containing any of metal or silicon nitride. 12. The display device according to claim 1, wherein each of the conduction region, the first impurity region, and the second impurity region is made of a material containing a non-single-crystal semiconductor. 13. The display according to claim 12, wherein at least one of the conductive region, the first impurity region, and the second impurity region is made of a material containing polycrystalline silicon. element. 14. The semiconductor device according to claim 12, wherein at least one of said conductive region, said first impurity region and said second impurity region is made of a material containing amorphous silicon. Display element. 15. The conductive region has a thickness of 0.01 μm.
2. The display device according to claim 1, wherein the thickness is in the range of 0.1 to 0.1 [mu] m. 16. When a positive potential is applied to both the control electrode and the first impurity region,
The amount of charge in the accumulation region increases, and image data is recorded. A positive potential is applied to the control electrode, and when charge is accumulated in the accumulation region, the conduction region becomes conductive. However, when no charge is accumulated in the accumulation region, the conduction region conducts, and image data is displayed in accordance with the presence or absence of conduction of the conduction region. When a negative potential is applied and a positive potential is applied to the second impurity region, the amount of charges in the accumulation region is reduced and image data is erased. The display device according to claim 1. 17. When a negative potential is applied to both the control electrode and the first impurity region, the amount of charge in the accumulation region increases, and image data is recorded. When a negative voltage is applied to the control electrode and the charge is accumulated in the accumulation region, the conduction region does not conduct.However, when the charge is not accumulated in the accumulation region, the conduction region is turned off. By conducting, display of image data is performed according to the presence or absence of conduction of the conduction region, a positive potential is applied to the control electrode, and a negative potential is applied to the second impurity region. 2. The display device according to claim 1, wherein the application of the voltage reduces the amount of charge in the accumulation region and erases image data. 18. When a positive potential is applied to both the control electrode and the first impurity region,
Image data is recorded by increasing the amount of charge in the accumulation region, a positive potential is applied to the auxiliary electrode, and when the charge is accumulated in the accumulation region, the conduction region becomes conductive. However, when no charge is accumulated in the accumulation region, the conduction region conducts, and image data is displayed in accordance with the presence or absence of conduction of the conduction region. When a negative potential is applied and a positive potential is applied to the second impurity region, the amount of charges in the accumulation region is reduced and image data is erased. The display element according to claim 5. 19. When a negative potential is applied to both the control electrode and the first impurity region,
Image data is recorded by increasing the amount of charge in the accumulation region, a negative potential is applied to the auxiliary electrode, and when charge is accumulated in the accumulation region, the conduction region becomes conductive. However, when no charge is accumulated in the accumulation region, the conduction region conducts, and image data is displayed in accordance with the presence or absence of conduction of the conduction region. When a positive potential is applied and a negative potential is applied to the second impurity region, the amount of charges in the accumulation region is reduced and image data is erased. The display element according to claim 5. 20. The display device according to claim 1, wherein the display unit displays an image by utilizing a change in alignment of liquid crystal molecules. 21. The display device according to claim 1, wherein the display unit displays an image using a light emitting diode. 22. The display device according to claim 1, wherein the display unit displays an image using organic electroluminescence. 23. The display device according to claim 1, wherein the display unit displays an image using a laser diode. 24. A display element having a display unit for displaying an image and a drive unit for driving the display unit, wherein the display unit and the drive unit are arranged on one base unit. Wherein the step of forming the drive section includes the steps of: forming a conductive region made of a semiconductor in an upper region of the base portion; and forming a first impurity region adjacent to the conductive region. Forming a second impurity region so as to be separated from the first impurity region and adjacent to the conductive region, and forming a tunnel insulating film on the conductive region; Forming a storage region composed of a plurality of fine particles dispersed thereon, forming a control insulating film on the storage region, and forming a control electrode on the control insulating film. Characteristic display element The method of production. 25. Forming the tunnel insulating film by exposing a semiconductor layer, which is a preparation layer of the conduction region, to an ionized gas containing at least one of oxygen atoms (O) and nitrogen atoms (N). The method for manufacturing a display element according to claim 24, wherein: 26. The method according to claim 25, further comprising a step of heating the surface of the semiconductor layer after forming the tunnel insulating film. 27. The method according to claim 26, wherein the surface of the semiconductor layer is heated by irradiating an energy beam. 28. The storage region is formed by using any one of a vapor deposition method, a sputtering method, and a vacuum deposition method so that a coverage of the tunnel insulating film is smaller than 1. Item 25. The method for manufacturing a display element according to item 24. 29. The method according to claim 29, further comprising the steps of: forming an auxiliary electrode in a concave portion provided on the base portion or a part thereof; and forming an auxiliary insulating film on the auxiliary electrode. Item 25. The method for manufacturing a display element according to item 24. 30. A display device in which a plurality of display elements each having a display unit for displaying an image and a drive unit for driving the display unit are arranged on one base unit, The driving unit of the device includes: a conductive region formed of a semiconductor; a first impurity region disposed adjacent to the conductive region; and a first impurity region separated from the first impurity region and adjacent to the conductive region. A second impurity region, a control electrode provided in a region on the opposite side of the base region with the conductive region interposed therebetween, and a control electrode between the control electrode and the conductive region. Located in the area,
An accumulation region for accumulating the charge transferred from the conduction region; a tunnel insulating film disposed in an area between the accumulation region and the conduction region; and a region between the control electrode and the accumulation region. A display device comprising: a control insulating film provided.