JP2000089250A - Production of electro-optic device and production of drive substrate for exectro-optic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To permit the production of an electro-optic device, such as thin-film semiconductor device for display containing a high-performance driver by forming differences in level of a prescribed shape/size on a substrate and causing graphoepitaxy with the angles at the bases of these differences in level as seeds. SOLUTION: The differences 4 in level of the prescribed shape/size are formed on the substrate 1 and the high-temperature graphoepitaxy is caused with the angles of the bases of the differences 4 in level as the seeds. As a result, a single crystal silicon thin film 7 of high electron mobility above 540 cm2/v/sec may be obtained and, therefore, the production of the reflection type liquid crystal device for display contg. a high-performance driver is made possible. In such a case, the differences 4 in level as such recessed parts as to have an inclined shape are preferably recommended to be formed in such a manner that the flanks with respect to the base surfaces have a rectangular shape or the base angle of preferably <=90 deg. to the bottom end side at the cross section.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an electro-optical device and a method for manufacturing a driving substrate for an electro-optical device, and more particularly, to a method using a monocrystalline silicon layer grown by grapho-epitaxial growth on an insulating substrate for an active region. A method suitable for a gate type thin film insulated gate field effect transistor (hereinafter referred to as a top gate type MOSTFT; a top gate type includes a staggered type or a coplanar type) and a liquid crystal display device having a passive region. It is about.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device has a display portion using amorphous silicon for a TFT and an external driving circuit IC, and a display using a polycrystalline silicon for a TFT by a solid phase growth method. Unit and driving circuit integrated (Japanese Patent Laid-Open No. 6-242433), excimer laser-annealed polycrystalline silicon TFT
(Japanese Patent Laid-Open No. 7-13)
No. 1030).

[0003]

However, the above-mentioned conventional amorphous silicon TFT has good productivity, but has a low electron mobility of about 0.5 to 1.0 cm ² / v · sec. MOSTFT (hereinafter pMO
Called STFT. ) Can not be made. Therefore, p
Since the peripheral driver using the MOSTFT cannot be formed on the same glass substrate as the display, the driver IC is externally mounted and mounted by the TAB method or the like, so that cost reduction is difficult. For this reason, there is a limit to high definition. Further, the electron mobility is 0.5 to 1.0 cm ² / v · s
Since it is as low as around ec, sufficient on-current cannot be obtained, and when used in a display portion, the transistor size is inevitably increased, which is disadvantageous for a high aperture ratio of a pixel.

In addition, the above-described conventional polycrystalline silicon TF
Since the electron mobility of T is 70 to 100 cm ² / v · sec, which can cope with high definition, an LCD (liquid crystal display) using a polycrystalline silicon TFT integrated with a driving circuit has recently attracted attention. However, a large LCD of 15 inches or more
, The electron mobility of polycrystalline silicon is 70-100.
Because of cm ² / v · sec, the driving ability is insufficient, and eventually, an external driving circuit IC is required.

In a TFT using polycrystalline silicon formed by a solid phase growth method, annealing is performed at a temperature of 600 ° C. or more for more than 10 hours, and a gate Si is formed by thermal oxidation at about 1000 ° C.
Since the formation of O ₂ is necessary, a semiconductor manufacturing apparatus has to be adopted. For this reason, a wafer size of 8 to 12 inches φ is a limit, and it is inevitable to use expensive quartz glass having high heat resistance, and it is difficult to reduce the cost. Therefore, EV
F and data / AV projector applications.

Further, in the above-described conventional polycrystalline silicon TFT by excimer laser annealing, there are many problems such as stability of excimer laser output, productivity, increase in apparatus price due to increase in size, reduction in yield / quality, and the like. .

[0007] In particular, when a large glass substrate of 1 m square or the like is used, the above-mentioned problems are magnified, and it becomes more difficult to improve performance / quality and reduce costs.

An object of the present invention is to provide an active matrix substrate with a built-in high-performance driver by forming a single-crystal silicon thin film having a high electron / hole mobility at a relatively low temperature and uniformly, particularly in a peripheral driving circuit portion. Enables the manufacture of electro-optical devices such as display thin film semiconductor devices using the same, and has an LDD structure (Li
ghtly doped drain structure) n-channel MOSTF
T (hereinafter referred to as nMOSTFT) or pMOSTF
T or a display portion of a complementary thin film insulated gate field effect transistor (hereinafter referred to as cMOSTFT) having a high driving capability, and a cMOSTFT, nMOSTFT or pMOST.
It is possible to integrate FT or a peripheral drive circuit consisting of a mixture of them, and realize a high-quality, high-definition, narrow-frame, high-efficiency, large-screen display panel. It can be used even for large glass substrates with low cost, high productivity, no expensive manufacturing equipment is required, cost can be reduced, and threshold adjustment is easy and high speed operation due to low resistance And to enable a large screen.

[0009]

That is, the present invention relates to a pixel electrode (for example, a plurality of pixel electrodes arranged in a matrix):
The same applies to the following. A display unit provided with the same) and a peripheral drive circuit unit provided around the display unit are provided on a first substrate (that is, a driving substrate: the same applies hereinafter). 1st substrate and 2nd
An electro-optical device in which a predetermined optical material such as a liquid crystal is interposed between the substrate and the substrate (that is, a counter substrate; the same applies hereinafter), and a method of manufacturing a driving substrate for the electro-optical device. Forming a step on one surface of one substrate, forming a molten liquid layer of a low melting point metal containing a semiconductor material such as silicon on the first substrate including the step, A step of subjecting the semiconductor material of the melt layer to grapho-epitaxial growth by a cooling process (preferably a slow cooling process) using the step as a seed to deposit a single-crystal semiconductor layer such as a single-crystal silicon layer; A predetermined process to form at least an active element of an active element and a passive element (for example, the single crystal silicon layer is formed in a channel region,
A top gate type thin film transistor (particularly, MOSTFT; hereinafter the same) having a gate portion formed of a gate insulating film and a gate electrode above the channel region as a source region and a drain region, and further having a source and drain electrode is activated. An electro-optical device, and a method of manufacturing a driving substrate for the electro-optical device.
Note that, in the present invention, the single crystal semiconductor layer includes not only a single crystal silicon layer but also a single crystal compound semiconductor layer (the same applies hereinafter). Further, the active element is a concept including an element such as a thin film transistor and other diodes,
The passive element is a concept including a resistor and the like (hereinafter, the same applies). Typical examples of the thin film transistor include a field effect transistor (FET) (there is a MOS type and a junction type, whichever may be used) and a bipolar transistor. The present invention is applicable to any of the transistors. (The same applies hereinafter). The active element is a resistor,
This is a concept that includes inductance, capacitance, etc.
For example, silicon nitride (hereinafter referred to as SiN)
There is a capacitance formed by sandwiching a high-dielectric film such as described above with the above-mentioned single-crystal silicon layer or the like (electrode) having reduced resistance.

According to the present invention, a single-crystal semiconductor thin film such as a single-crystal silicon thin film is formed from a melt of a low-melting-point metal in which silicon is dissolved, by grapho-epitaxial growth using the step formed on the substrate as a seed. Active elements such as top-gate type MOSTFTs in peripheral drive circuits of drive substrates such as active matrix substrates and top-gate type MOSTFTs in peripheral drive circuits of electro-optical devices such as LCDs integrated with a display unit and peripheral drive circuit; Since it is used for at least an active element among passive elements such as an inductance and a capacitance, the following remarkable functions and effects shown in (A) to (F) can be obtained.

(A) A step having a predetermined shape / dimension is formed on a substrate, and the corner of the bottom of the step (base angle) is used as a seed to perform grapho-epitaxial growth to 540 cm.
^Since a single-crystal semiconductor layer such as a single-crystal silicon thin film having a high electron mobility of ² / v · sec or more can be obtained, an electro-optical device such as a display thin-film semiconductor device with a built-in high-performance driver can be manufactured. In this case, the step is preferably formed as a concave portion such that the side surface is perpendicular to the bottom surface in the cross section or inclined so as to form a bottom angle of preferably 90 ° or less toward the lower end side.

(B) In particular, the single-crystal silicon thin film exhibits high electron and hole mobilities comparable to those of a single-crystal silicon substrate as compared with conventional amorphous silicon thin films and polycrystalline silicon thin films. The top gate type MOSTFT has a high switching characteristic [preferably, an LDD (L
nMOS or pM having a (ightly doped drain) structure]
A display unit composed of an OSTFT or a cMOSTFT and a peripheral driving circuit unit composed of a cMOS having a high driving capability, or an nMOS, a pMOSTFT, or a mixture of these can be integrated, thereby achieving high image quality, high definition, a narrow frame, and high efficiency. ,
A large-screen display panel is realized. In particular, polycrystalline silicon has a high hole mobility pMOS as a TFT for LCD.
Although it is difficult to form a TFT, the single crystal silicon thin film according to the present invention exhibits sufficiently high mobility even with holes, so that a peripheral drive circuit that drives electrons and holes alone or in combination of both can be manufactured. This is nMOS or pMOS
Alternatively, a panel integrated with a TFT for a display portion having a cMOS LDD structure can be realized. In the case of a small to medium-sized panel, there is a possibility that one of a pair of peripheral vertical drive circuits can be omitted.

(C) The low-melting-point metal melt can be prepared at a low temperature (for example, 350 ° C.) and formed on a substrate heated to a temperature slightly higher than that by a method such as coating. A silicon single crystal film can be formed uniformly at a relatively low temperature (for example, 350 to 400 ° C.). Therefore, a glass substrate having a relatively low strain point, a heat-resistant organic substrate, or the like can be easily obtained, a low-cost substrate having good physical properties can be used, and the substrate can be enlarged.

(D) Since annealing at medium temperature for a long time (about 600 ° C., ten and several hours) and excimer laser annealing as in the case of the solid phase growth method are not required, high productivity and expensive manufacturing equipment are required. Is unnecessary and cost can be reduced.

(E) In this grapho-epitaxial growth, a wide range of P-type impurity concentration and a high mobility single crystal silicon thin film can be obtained by adjusting the heating temperature of the substrate, the composition ratio of the melt, the melt temperature, the cooling rate, and the like. Since it is easily obtained, Vt
Adjustment of h (threshold) is easy, and high-speed operation and a large screen can be realized by lowering the resistance.

(F) Further, at the time of forming the silicon-containing low-melting-point metal melt layer, an impurity element belonging to Group 3 or Group 5 (boron,
Phosphorus, antimony, arsenic, bismuth, aluminum, etc.) can be doped separately in an appropriate amount to provide an impurity species and / or its concentration of the grown single crystal silicon epitaxial growth layer, that is, a P-type / N-type conductivity type and / or a carrier concentration. Can be arbitrarily controlled.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, the step is
In a cross section, the side surface with respect to the bottom surface is perpendicular to the bottom surface or desirably inclined to form a bottom angle of 90 ° or less toward the lower end side, as an insulating substrate or a diffusion barrier thereon,
For example, the single-crystal silicon layer is formed on a film of SiN or the like (or both of them), and the step is preferably used as a seed at the time of grapho-epitaxial growth of the single crystal silicon layer. The step is preferably formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the active element, for example, a thin film transistor. It is preferable that the passive element is formed along at least one side of an element region in which a resistor is formed.

In this case, the first thin film transistor such as the MOSTFT may be provided in the concave portion of the substrate due to the step, but may be provided on the substrate outside the concave portion or in both of them.

The step is formed by dry etching such as reactive ion etching, and silicon is added in an amount of, for example, 2.0 to 0.005% by weight, for example, 1% by weight.
It is preferable to apply the molten liquid of the low-melting-point metal to the heated insulating substrate and hold it for a predetermined time (several minutes to several tens of minutes) before performing the cooling treatment. With this, a thickness of several μm
A single crystal silicon film of 0.005 μm, for example, 1 μm can be obtained.

Further, an insulating substrate such as a glass substrate or a heat-resistant organic substrate is used as the substrate, and the low melting point metal is selected from the group consisting of indium, gallium, tin, bismuth, lead, zinc, antimony and aluminum. At least one can be used.

In this case, when indium is used as the low melting point metal, the molten liquid is 850 to 1100
C., preferably 900 to 950.degree. C., applied to the insulating substrate, and when using indium gallium or gallium as the low melting metal, the molten liquid is heated to 30.degree.
0-1100 ° C, preferably 350-600 ° C or 40
It can be applied to the insulating substrate heated to 0 to 1100 ° C, preferably 420 to 600 ° C. The substrate can be heated by a method of uniformly heating the entire substrate using an electric furnace, a lamp, or the like, or a method of locally heating only a predetermined location by an optical laser, an electron beam, or the like.

As is clear from the state diagram shown in FIG. 10, the melting point of the low melting point metal containing silicon decreases in accordance with the ratio of the low melting point metal. When indium is used, forming an indium melt layer containing silicon (for example, containing 1% by weight) at a substrate temperature of 850 to 1100 ° C. can use a quartz plate glass as a substrate up to about 1100 ° C. Up to 850 ° C., glass having lower heat resistance, for example, crystallized glass can be used. When gallium is used, a gallium melt layer containing silicon (for example, containing 1% by weight) can be formed at a substrate temperature of 400 to 1100 ° C. for the same reason as described above.

In the latter case (in the case of indium gallium silicon or gallium silicon), a glass substrate having a relatively low strain point or a heat-resistant organic substrate can be used as the substrate, so that a large glass substrate (for example, 1 m ² or more) is used. Although a semiconductor crystal layer can be formed thereon, such a substrate is inexpensive, easily thinned, and a long rolled glass plate or a heat-resistant organic substrate can be manufactured. Using this, a single-crystal silicon thin film formed by grapho-epitaxial growth can be continuously or discontinuously formed on a long rolled glass plate or a heat-resistant organic substrate by the above method.

In the above-mentioned melt coating method, a certain time (several minutes to
After holding for several tens of minutes, the substrate is gradually cooled. In addition, a dipping method in which a glass substrate is immersed in the above solution, held for a certain period of time (several minutes to several tens of minutes), and then gradually pulled up, Alternatively, a floating method in which the surface is moved at an appropriate speed and gradually cooled may be used. The thickness of the epitaxially grown layer and the carrier impurity concentration can be controlled by the composition, temperature, and pulling rate of the melt. The coating method, the dipping method, the floating method, and the like can process the substrate continuously or intermittently, so that mass productivity is also improved.

As described above, since the constituent elements are easily diffused from the inside of the glass into the upper layer of the glass having a low strain point, the thin film of the diffusion barrier layer (for example, silicon nitride: About 50-200 nm)
Should be formed.

After the above-mentioned single crystal silicon layer is deposited from the above-mentioned low melting point metal in which silicon is dissolved by slow cooling, the single crystal silicon layer is deposited by grapho-epitaxial growth using the above-mentioned steps as a seed. Then, a predetermined process is performed on the single crystal silicon layer to produce an active element and a passive element.

As described above, the low melting point metal thin film such as indium deposited on the single crystal silicon layer after cooling is dissolved and removed using hydrochloric acid or the like, but a small amount (10 ¹⁶ atoms / cc) of indium or the like is contained in the silicon layer. ), A P-type single-crystal silicon thin film semiconductor is formed immediately after the formation. Therefore, this is nMOST
It is convenient for FT fabrication. However, by ion-implanting an appropriate amount of N-type impurities such as phosphorus atoms over the entire surface or selectively, an N-type single-crystal silicon thin film can be entirely or selectively formed, so that a pMOSTFT can also be formed. . For this reason, a cMOSTFT can also be produced. When forming a molten layer of a silicon-containing low-melting-point metal, an appropriate amount of an impurity element belonging to Group 3 or Group 5 having high solubility (boron, phosphorus, antimony, arsenic, gallium, bismuth, etc.) may be separately doped to grow silicon. It is possible to arbitrarily control the impurity species and / or the concentration of the epitaxial growth layer, that is, the P type / N type and / or the carrier concentration.

As described above, the single crystal silicon layer grown by the grapho-epitaxial growth on the substrate is applied to the channel region, the source region and the drain region of the top gate type MOSTFT constituting at least a part of the peripheral driving circuit. And / or its concentration can be controlled.

The peripheral driver circuit section and the thin film transistor of the display section constitute an n-channel, p-channel or complementary insulated gate field-effect transistor, for example, a set of complementary and n-channel transistors and a complementary and p-channel transistor. It may be composed of a set of a channel type or a set of a complementary type, an n-channel type and a p-channel type. Further, it is preferable that at least a part of the thin film transistor of the peripheral drive circuit section and / or the display section has an LDD (Lightly doped drain) structure. Note that the LDD structure may be provided not only between the gate and the drain, but also between the gate and the source, or between the gate and the source and between the gate and the drain (this is called a double LDD).

In particular, the MOSTFT has n
A MOS or pMOS or cMOS LDD type TFT is formed, and a cMOS or nMOS
Alternatively, a pMOS TFT or a mixture of these may be formed.

Further, the MOSTFT may be provided in the concave portion of the substrate due to the step and / or in the vicinity of the concave portion outside the concave portion of the substrate.

In this case, a step is formed on one surface of the first substrate, and a single crystal is formed on the substrate including the step.
A polycrystalline or amorphous silicon layer is formed, and the second thin film transistor uses the single crystal, polycrystalline or amorphous silicon layer as a channel region, a source region and a drain region, and a gate portion above and / or below the channel region. , A bottom gate type or a dual gate type. Again,
In the cross section, the step similar to the above is formed as a concave portion in which the side surface is perpendicular to the bottom surface or inclined so as to form a bottom angle of preferably 90 ° or less toward the lower end side, and the step is formed by the single crystal silicon. It serves as a seed during grapho-epitaxial growth of the layer.

The second thin film transistor is provided with the first thin film transistor.
A single crystal silicon layer, which is provided inside and / or outside the substrate recess due to the step formed on the substrate and / or the film formed thereon and is formed by grapho-epitaxial growth similarly to the first thin film transistor, and has its source, drain,
Each region of the channel may be formed.

Also in this second thin film transistor, as in the above, the impurity species of Group 3 or Group 5 of the single crystal, polycrystalline or amorphous silicon layer and / or the concentration thereof are controlled, and The second thin film transistor may be formed along at least one side of an element region formed by the channel region, the source region, and the drain region. Further, the gate electrode under the single crystal, polycrystal or amorphous silicon layer is preferably trapezoidal at its side end. A diffusion barrier layer may be provided between the first substrate and the single crystal, polycrystalline or amorphous silicon layer.

It is preferable that a source or drain electrode of the first and / or second thin film transistor is formed on a region including the step.

The first thin film transistor is at least a top gate type selected from a top gate type, a bottom gate type and a dual gate type having a gate portion above and / or below a channel region; and
The switching element that switches the pixel electrode in the display unit may be the top gate type, the bottom gate type, or the dual gate type second thin film transistor.

In this case, the gate electrode provided below the channel region is made of a heat-resistant material, or the upper gate electrode of the second thin film transistor and the gate electrode of the first thin film transistor are made of a common material. It may be formed.

In the peripheral driver circuit section, in addition to the first thin film transistor, a top gate type having a polycrystalline or amorphous silicon layer as a channel region and having a gate portion above and / or below the channel region;
A bottom-gate or dual-gate thin film transistor, or a diode, a resistor, a capacitor, an inductance element, or the like using the single-crystal silicon layer, the polycrystalline silicon layer, or the amorphous silicon layer may be provided.

The peripheral drive circuit section and / or the thin film transistor of the display section may be configured as a single gate or a multi-gate.

When the n-type or p-channel type thin film transistor of the peripheral driver circuit portion and / or the display portion is a dual gate type, the upper or lower gate electrode is electrically open or an arbitrary negative voltage ( n-channel type) or positive voltage (p-channel type)
Is applied to operate as a bottom gate type or top gate type thin film transistor.

The thin film transistor of the peripheral drive circuit section is an n-channel type, a p-channel type or a complementary type.
Wherein the thin film transistor of the display portion is an n-channel type, a p-channel type, or a complementary type when a single crystal silicon layer is used as a channel region;
When the polycrystalline silicon layer is used as a channel region, the channel region may be an n-channel type, a p-channel type, or a complementary type. When the amorphous silicon layer is used as a channel region, the channel region may be an n-channel type, a p-channel type, or a complementary type.

In the present invention, after the deposition of the single-crystal silicon layer, an upper gate portion including a gate insulating film and a gate electrode is formed on the single-crystal silicon layer, and the upper gate portion is used as a mask to form the single-crystal silicon layer. Group 3 or 5 in layer
The channel region, the source region, and the drain region may be formed by introducing a group III impurity element.

When the second thin film transistor is a bottom gate type or a dual gate type, a lower gate electrode made of a heat-resistant material is provided below the channel region, and a gate insulating film is formed on the gate electrode. After forming the lower gate portion, the second thin film transistor can be formed through a process common to the first thin film transistor including the step of forming the step. In this case, the upper gate electrode of the second thin film transistor and the gate electrode of the first thin film transistor can be formed of a common material.

After forming the single-crystal silicon layer on the lower gate portion, an impurity element of group 3 or 5 is introduced into the single-crystal silicon layer to form source and drain regions, and then activated. Processing can be performed.

After the formation of the single crystal silicon layer, the source and drain regions of the first and second thin film transistors are formed by ion implantation of the impurity element using a resist as a mask. After forming the gate insulating film, the gate electrode of the first thin film transistor and, if necessary, the upper gate electrode of the second thin film transistor may be formed.

When the thin film transistor is a top gate type, after forming the single crystal silicon layer, each source and drain region of the first and second thin film transistors is formed by ion implantation of the impurity element using a resist as a mask. After the ion implantation, an activation process is performed, and thereafter, each gate portion including the gate insulating film and the gate electrode of the first and second thin film transistors can be formed.

Alternatively, when the thin film transistor is a top gate type, after forming the single crystal silicon layer, each gate insulating film of the first and second thin film transistors and each gate electrode made of a heat-resistant material are formed. Forming a gate portion, forming each source and drain region by ion implantation of the impurity element using these gate portions as a mask,
An activation process may be performed after the ion implantation.

In addition, ion implantation for forming a source region and a drain region can be performed using a resist mask that covers the resist mask used in forming the LDD structure.

The substrate may be optically opaque or transparent, and may be provided with a reflective or transmissive pixel electrode for display.

When the display section has a laminated structure of the pixel electrode and the color filter layer, the color filter is formed on the display array section to improve the aperture ratio and brightness of the display panel. In addition, the cost can be reduced by omitting the color filter substrate and improving the productivity.

In this case, when the pixel electrode is a reflective electrode, irregularities are formed on the resin film so as to obtain optimum reflection characteristics and viewing angle characteristics, and the pixel electrode is provided thereon. Is a transparent electrode, the surface is flattened by a transparent flattening film, and the pixel electrode is preferably provided on the flattened surface.

The display section is configured to emit light or modulate light by being driven by the MOSTFT. For example, a liquid crystal display (LCD), an electroluminescence display (EL), a field emission display (FED), Light Emitting Polymer Display (LEPD), Light Emitting Diode Display (L
ED) and the like. In this case, a plurality of the pixel electrodes may be arranged in a matrix on the display unit, and the switching element may be connected to each of the pixel electrodes.

Next, the present invention will be described in more detail with reference to preferred embodiments.

<First Embodiment> FIGS. 1 to 13 show a first embodiment of the present invention.

In this embodiment, a single-crystal silicon layer is grown at high temperature by grapho-epitaxial growth from an indium-silicon melt using the above-mentioned step (concave) provided on a heat-resistant substrate as a seed.
The present invention relates to an active matrix reflection type liquid crystal display (LCD) having a T configuration. First, this reflection type LC
The overall layout of D will be described with reference to FIGS.

As shown in FIG. 11, in this active matrix reflective LCD, a main substrate 1 (which constitutes an active matrix substrate) and a counter substrate 32 are bonded together via a spacer (not shown). It has a flat panel structure, and liquid crystal (not shown here) is sealed between both substrates 1-32. On the surface of the main substrate 1, a display unit including pixel electrodes 29 (or 41) arranged in a matrix, a switching element for driving the pixel electrodes, and a peripheral drive circuit unit connected to the display unit are provided. Is provided.

The switching element of the display unit is formed of an nMOS, pMOS, or cMOS according to the present invention and a top gate type MOSTFT having an LDD structure. In the peripheral drive circuit section, cMOS or nMOS or pMOS of a top gate type MOSTFT according to the present invention is also used as a circuit element.
MOSTFTs or a mixture thereof are formed. Note that one of the peripheral drive circuit units is a horizontal drive circuit that supplies a data signal to drive the TFT of each pixel for each horizontal line, and the other peripheral drive circuit unit connects the gate of the TFT of each pixel for each scan line. , And are usually provided on both sides of the display unit. These drive circuits can be configured in either a dot-sequential analog system or a line-sequential digital system.

As shown in FIG. 12, the above-mentioned TFT is arranged at the intersection of the orthogonal gate bus line and data bus line, and image information is written into the liquid crystal capacitor (C _LC ) via this TFT, and the next information is written. Holds electric charge until comes. In this case, it is not enough to hold the TFT channel resistance alone. To compensate for this, a storage capacitor (auxiliary capacitor) (C _S ) is added in parallel with the liquid crystal capacitor to compensate for a decrease in the liquid crystal voltage due to leak current. May be. Such TF for LCD
In T, the required performance differs between the characteristics of the TFT used for the pixel portion (display portion) and the characteristics of the TFT used for the peripheral drive circuit. In the TFT of the pixel portion, it is important to control the off current and secure the on current. It becomes a problem. For this reason, the display unit
By providing a TFT having an LDD structure as described below,
As a structure in which an electric field is hardly applied between the gate and the drain, an effective electric field applied to the channel region can be reduced, an off current can be reduced, and a change in characteristics can be reduced. However, the process becomes complicated, the element size becomes large, and problems such as a decrease in on-current occur. Therefore, an optimum design is required for each purpose of use.

Usable liquid crystals include TN liquid crystal (nematic liquid crystal used in the TN mode of active matrix driving), STN (super twisted nematic), GH (guest host), PC (phase change). , FLC (ferroelectric liquid crystal), AFL
Liquid crystals for various modes such as C (antiferroelectric liquid crystal) and PDLC (polymer dispersed liquid crystal) may be employed.

The outline of the circuit system of the peripheral drive circuit and its driving method will be described with reference to FIG. The driving circuit is divided into a gate side driving circuit and a data side driving circuit.
It is necessary to configure a shift register on both the data side.
Shift registers are generally pMOSTFT and nMOS
Using both TFTs (so-called CMOS circuit)
Some use only one of the MOSTFTs. However, in terms of operating speed, reliability, and low power consumption, cMOST
FT or CMOS circuits are common.

The scanning drive circuit is composed of a shift register and a buffer, and sends a pulse synchronized with the horizontal scanning period to each line from the shift register. On the other hand, there are two driving methods for the data side driving circuit, a dot sequential method and a line sequential method. In the dot sequential method shown in the figure, the circuit configuration is relatively simple, and the display signal is controlled by a shift register through an analog switch. While writing to each pixel directly. Write sequentially to each pixel within one horizontal scanning time (R, G,
B schematically shows a pixel for each color).

Next, an active matrix reflective LCD according to the present embodiment will be described with reference to FIGS. However, in FIGS. 1 to 6, the left side of each drawing shows the manufacturing process of the display unit, and the right side shows the manufacturing process of the peripheral drive circuit unit.

First, as shown in FIG. 1A, a photoresist 2 is formed in a predetermined pattern on at least a TFT formation region on one main surface of an insulating substrate 1 such as quartz glass or crystallized glass. Is used as a mask, for example, CF
_A plurality of steps 4 are formed on the substrate 1 by applying general-purpose photolithography such as reactive ion etching (RIE) and etching (photoetching) by irradiating F ⁺ ions 3 of ₄ plasma. In this case, as the insulating substrate 1, a high heat-resistant substrate (8 to 8) made of quartz glass, crystallized glass, ceramic, or the like (however, an opaque ceramic substrate cannot be used in a transmission type LCD described later).
12 inch φ, 700 to 800 μm thick) can be used. The step 4 serves as a seed during the later-described monocrystalline silicon grapho-epitaxial growth, and may have a depth d of 0.1 μm, a width w of 5 to 10 μm, and a length (perpendicular to the paper surface) of 10 to 20 μm. The angle between the base and the side (base angle) is a right angle.

Next, as shown in FIG. 1 (2), after removing the photoresist 2, a silicon-indium melt 6 containing about 1% by weight of silicon is heated to 900 to 930 ° C.
Is applied to the entire surface including the step 4 of the substrate 1 which has been heated. Alternatively, a method in which the substrate 1 is dipped in the melt, or the surface of the melt is gradually moved to float, or a jet method or a contact method under the action of an ultrasonic wave is also possible.

Then, after holding the substrate 1 for several minutes to several tens of minutes, the substrate 1 is gradually cooled (in the case of dipping, gradually pulled up), so that the silicon dissolved in the indium is reduced to the corners at the bottom of the step 4. Is used as a seed (seed) for grapho-epitaxial growth as shown in FIG. 2C, and is deposited as a P-type single crystal silicon layer 7 having a thickness of, for example, about 0.1 μm. In the dipping method and the floating method, the composition of the melt, the temperature, the pulling rate, and the like can be easily controlled, and the thickness of the epitaxial growth layer and the P-type carrier impurity concentration can be easily controlled.

In this case, the single crystal silicon layer 7
The 0) plane is epitaxially grown on the substrate, which is due to a known phenomenon called grapho-epitaxial growth. As shown in FIG. 8, when a vertical wall such as the above-described step 4 is formed on the amorphous substrate (glass) 1 and an epitaxial growth layer is formed thereon, as shown in FIG. 8B, the (100) plane grows along the plane of the step 4 as shown in FIG. The size of the single crystal grain increases in proportion to the temperature and time. However, when the temperature and time are reduced or shortened, the interval between the steps must be shortened. The crystal orientation of the growth layer can be controlled by variously changing the shape of the step as shown in FIGS. 9A to 9F. When fabricating MOS transistors, the (100) plane is most often employed. In short, the cross-sectional shape of the step 4 may be such that the angle of the base corner (base angle) is a right angle, or may be inclined inward or outward from the upper end to the lower end. You only need to have it. The base angle of step 4 is usually a right angle or 9
It is desirable that the angle is equal to or less than 0 °, and the corner of the bottom surface has a slight curvature.

After the single-crystal silicon layer 7 is deposited on the substrate 1 by grapho-epitaxial growth,
As shown in FIG. 2 (4), the indium film 6A deposited on the surface side is dissolved and removed with hydrochloric acid, sulfuric acid or the like (at this time, post-treatment so as not to form a lower silicon oxide film), and the single crystal silicon layer 7 is formed. Top gate type M as channel area
An OSTFT is manufactured.

First, the single-crystal silicon thin film 7 formed by the above-mentioned grapho-epitaxial growth is made P-type by containing indium. However, since the P-type impurity concentration varies, the p-channel MOSTFT portion is formed of a photoresist (not shown). ), And p-type impurity ions (for example, B ⁺ ) at 10 kV and 2.7 × 10 ¹¹ atoms / cm ^2.
To adjust the specific resistance. Also,
As shown in FIG. 2 (5), in order to control the impurity concentration in the pMOSTFT formation region, the nMOSTFT portion is masked with a photoresist 60, and N-type impurity ions (for example, P ⁺ ) are used.
65 is doped at 10 kV at a dose of 1 × 10 ¹¹ atoms / cm ² to form an N-type well 7A.

Next, as shown in FIG. 3 (6), a silicon oxide film (hereinafter referred to as SiO ₂ film) is formed on the entire surface of the single crystal silicon thin film layer 7 by plasma CVD, high density plasma CVD, catalytic CVD or the like. .) (About 200 nm thick) and Si
An N film (about 100 nm thick) is continuously formed in this order to form a gate insulating film 8, and further, molybdenum-tantalum (Mo)
-Ta) alloy sputtered film 9 (500-600 nm thick)
To form

Next, as shown in FIG. 3 (7), a photoresist pattern is formed in each step region (in the concave portion) between the TFT portion in the display region and the TFT portion in the peripheral drive region by a general-purpose photolithography technique. Then, a gate electrode 11 of (Mo.Ta) alloy and a gate insulating film (SiN / SiO ₂ ) 12 are formed by continuous etching to expose the single crystal silicon thin film layer 7. (Mo
・ Ta) alloy film 9 is an acid-based etching solution, SiN is CF ₄
Gas plasma etching and SiO ₂ are treated with a hydrofluoric acid-based etchant.

Next, as shown in (8) of FIG. 3, the entire nMOS and pMOSTFT in the peripheral drive region and the gate portion of the nMOSTFT in the display region are covered with the photoresist 13, and the source / drain regions of the exposed nMOSTFT are covered. Phosphorus ions 14 are converted to 5 × 10 ¹³ a at 20 kV, for example.
By doping (ion implantation) at a dose of toms / cm ^2, the LDD portion 15 made of an N ⁻ -type layer is formed in a self-aligned (self-aligned) manner.

Next, as shown in FIG. 4 (9), all of the pMOS TFTs in the peripheral drive region and nM
The gate portion of the OSTFT and the gate and the LDD portion of the nMOSTFT in the display area are covered with a photoresist 16, and phosphorus or arsenic ions 17 are added to the exposed area, for example, for 2 hours.
By doping (ion implantation) at 0 kV and a dose of 5 × 10 ¹⁵ atoms / cm ² , the source 18 and the drain 19 and the LDD 15 made of the N ⁺ type layer of the nMOS TFT are formed.

Next, as shown in (10) of FIG. 4, the nMOSTFT in the peripheral driving region and the nMOST in the display region are formed.
The entire FT and the gate portion of the pMOSTFT are covered with a photoresist 20, and the exposed region is doped with boron ions 21 at, for example, 10 kV at a dose of 5 × 10 ¹⁵ atoms / cm ² , thereby ion-implanting the P ^{+ of the} pMOSTFT. The source part 22 and the drain part 23 of the layer are formed.
Note that this operation is performed in pM
This is unnecessary work because there is no OSTFT.

Next, as shown in FIG.
A photoresist 24 is provided to make an active element portion such as an FT or a diode or a passive element portion such as a resistor or an inductance into an island, and a single crystal other than the active element portion and the passive element portion in the peripheral driving region and the display region is provided. The silicon thin film layer is removed by general-purpose photolithography and etching techniques. The etching solution is hydrofluoric acid.

Then, as shown in FIG. 5 (12), an SiO ₂ film (about 200 nm thick) and a phosphosilicate glass (PSG) film (about 300 nm thick) are formed by plasma CVD, high-density plasma CVD, catalytic CVD, or the like. ) Are continuously formed on the entire surface in this order to form the protective film 25.

Then, in this state, the single crystal silicon layer is activated. In this activation, lamp annealing conditions such as halogen are about 1000 ° C. and about 10 seconds, and a gate electrode material that can withstand this is required.
-Ta alloy is suitable. This gate electrode material therefore
The wiring can be provided not only as a gate portion but also as a wiring over a wide range. Here, expensive excimer laser annealing is not used, but if it is used, the condition is that XeCl (308 nm wavelength) is used for the entire surface, or the selective overlap of 90% or more of only the active element portion and the passive element portion. Scanning is preferred.

Next, as shown in FIG. 5 (13), contact windows for the source / drain portions of all the TFTs of the peripheral drive circuit and the source portions of the display TFTs are opened by general-purpose photolithography and etching techniques. .

Then, a sputtered film of aluminum or aluminum alloy having a thickness of 500 to 600 nm, for example, aluminum or copper containing 1% Si or aluminum or copper containing 1 to 2% copper is formed on the entire surface, and a peripheral film is formed by general-purpose photolithography and etching techniques. The data lines and the gate lines are formed simultaneously with the formation of the source electrodes 26 of all the TFTs in the driving circuit and the display section and the drain electrodes 27 of the peripheral driving circuit section. Then, forming gas (N ₂ +
Sinter treatment in H ₂ ) at about 400 ° C./1 h.

Next, as shown in FIG. 5 (14), an insulating film 36 made of a PSG film (about 300 nm thick) and a SiN film (about 300 nm thick) is formed by plasma CVD, high-density plasma CVD, catalytic CVD, or the like. Is formed on the entire surface.
Next, a contact window is opened in the drain portion of the display TFT. Note that SiO ₂ , PSG and SiN in the pixel portion are used.
The film does not need to be removed.

As a basic requirement of the reflection type liquid crystal display device, the function of reflecting incident light and the function of scattering incident light must be provided inside the liquid crystal panel. This is because the direction of the observer with respect to the display is substantially determined, but the direction of the incident light cannot be uniquely determined.
For this reason, it is necessary to design a reflector assuming that a point light source exists in an arbitrary direction. Therefore, (1) in FIG.
5) As shown in 5), the whole surface is spin-coated or the like with a thickness of 2 to 3 μm.
A photosensitive resin film 28 having a thickness of m is formed, and as shown in (16) of FIG. 6, a concavo-convex pattern for obtaining optimal reflection characteristics and viewing angle characteristics at least in a pixel portion by general-purpose photolithography and etching techniques. Is formed and reflowed to form a lower reflective surface made of the roughened uneven surface 28A.
At the same time, a resin window for contact of the drain portion of the display TFT is opened.

Next, as shown in FIG. 6 (17), aluminum or 1% Si having a thickness of 400 to 500 nm is formed on the entire surface.
An aluminum film or the like other than the pixel portion is removed by a general-purpose photolithography and etching technique to form a sputtered film made of aluminum or the like, and a reflective portion 29 made of uneven aluminum or the like connected to the drain portion 19 of the display TFT is formed.
To form This is used as a pixel electrode for display. Then, about 300 ° C / 1h in forming gas
Sintering to make the contacts sufficient. Note that silver or a silver alloy may be used in place of the aluminum-based material in order to increase the reflectance.

As described above, the step 4 is used as a seed for high-temperature grapho-epitaxial growth,
Are formed in the display section and the peripheral drive circuit section using the single crystal silicon layer 7, respectively.
The display-peripheral drive circuit unit-integrated active matrix substrate 30 incorporating a CMOS circuit composed of an LDD-TFT, a pMOSTFT, and an nMOSTFT can be manufactured.

Next, using this active matrix substrate (drive substrate) 30, a reflective liquid crystal display (LCD)
The method for manufacturing the semiconductor device will be described with reference to FIG. Hereinafter, this active matrix substrate is referred to as a TFT substrate.

When the liquid crystal cell of this LCD is manufactured by surface assembly (suitable for medium / large liquid crystal panels of 2 inch size or more), first, a TFT substrate 30 and a solid IT
A polyimide alignment film 3 is formed on an element forming surface of a counter substrate 32 provided with an O (Indium tin oxide) electrode 31.
3 and 34 are formed. This polyimide alignment film is formed to a thickness of 50 to 100 nm by roll coating, spin coating, or the like, and cured at 180 ° C. for 2 hours.

Next, the TFT substrate 30 and the counter substrate 32 are subjected to rubbing or photo-alignment treatment of polarized ultraviolet rays. Rubbing buff materials include cotton and rayon, but cotton is more stable in terms of buff residue (garbage) and retardation. Photoalignment is a technique for aligning liquid crystal molecules by non-contact linearly polarized ultraviolet irradiation. In addition, in addition to rubbing, a polymer alignment film can be formed by obliquely incident polarized or non-polarized light (such a polymer compound is, for example, a polymethyl methacrylate-based polymer having azobenzene). Etc.).

Next, after cleaning, a common agent is applied to the TFT substrate 30 side, and a sealing agent is applied to the counter substrate 32 side.
Wash with water or IPA (isopropyl alcohol) to remove rubbing buff debris. Common agent is acrylic or epoxy acrylate containing conductive filler,
Alternatively, the sealant may be an acrylic adhesive, an epoxy acrylate, or an epoxy adhesive. Any of heat curing, ultraviolet irradiation curing, ultraviolet irradiation curing and heat curing can be used, but from the viewpoint of overlay accuracy and workability, the ultraviolet irradiation curing and heat curing type is preferable.

Next, spacers for obtaining a predetermined gap are sprayed on the counter substrate 32 side, and are superposed on the TFT substrate 30 at a predetermined position. After the alignment marks on the counter substrate 32 and the alignment marks on the TFT substrate 30 are accurately aligned, the sealant is temporarily cured by irradiating with ultraviolet light, and then heat-cured collectively.

Next, a scribe break is performed to
A single liquid crystal panel in which the substrate 30 and the counter substrate 32 are overlapped is created.

Next, the liquid crystal 35 is injected into the gap between the two substrates 30-32, and the injection port is sealed with an ultraviolet adhesive, followed by IPA cleaning. Any type of liquid crystal may be used. For example, a high-speed TN (twisted nematic) mode using a nematic liquid crystal is generally used.

Next, the liquid crystal 35 is oriented by heating and quenching.

Next, a flexible wiring is connected to the panel electrode take-out portion of the TFT substrate 30 by thermocompression bonding of an anisotropic conductive film, and a polarizing plate is bonded to the counter substrate 32.

Also, in the case of a single liquid crystal panel surface assembly (suitable for a small liquid crystal panel having a size of 2 inches or less), similarly to the above, the polyimide alignment 33, 34 are formed, and both substrates are subjected to rubbing or non-contact linear polarization ultraviolet light alignment treatment.

Next, the TFT substrate 30 and the opposing substrate 32 are divided into single pieces by dicing or scribe break, and washed with water or IPA. A common agent is applied to the TFT substrate 30, a sealing agent containing a spacer is applied to the counter substrate 32,
Lay both substrates together. Subsequent processes follow the above.

In the reflection type LCD described above, the opposing substrate 32 is a CF (color filter) substrate, and the color filter layer 46 is provided below the ITO electrode 31.
The incident light from the counter substrate 32 side is efficiently reflected by the reflection film 29 and emitted from the counter substrate 32 side.

On the other hand, in addition to the above-described substrate structure as shown in FIG. 7, an on-chip color filter (OCCF) in which a color filter is provided on the TFT substrate 30 is used as the TFT substrate 30.
When a TFT substrate having a structure is used, the counter substrate 32 has I
Solid TO electrode (or ITO with black mask)
The electrodes are solid).

[0096] In the case of incorporating an auxiliary capacitance C _S shown in FIG. 12 in the pixel unit, by connecting the dielectric layer provided on the substrate 1 described above (not shown) and the drain region 19 of monocrystalline silicon Good.

As described above, according to the present embodiment, the following remarkable effects can be obtained.

(A) A step 4 having a predetermined shape / dimension is formed on the substrate 1 and high-temperature grapho-epitaxial growth is performed by using the bottom corner of the step as a seed (however, the heating temperature during the growth is 90 ° C.).
0-930 ° C.).
Since a single-crystal silicon thin film 7 having a high electron mobility of at least cm ² / v · sec can be obtained, an LC with a built-in high-performance driver can be obtained.
D can be manufactured.

(B) Since the single-crystal silicon thin film exhibits high electron and hole mobilities comparable to those of a single-crystal silicon substrate as compared with a conventional amorphous silicon thin film or polycrystalline silicon thin film, Gate type T
FT is an LDD with high switching characteristics and low leakage current
NMOS or pMOS or cMOS TFT having structure
And a high drive capability cMOS, nMOS or pMOS
A configuration in which a MOST or a peripheral driving circuit portion composed of a mixture thereof is integrated becomes possible, and a display panel with high image quality, high definition, a narrow frame, a large screen, and high efficiency is realized. Since this single crystal silicon thin film 7 has a sufficiently high hole mobility, a peripheral drive circuit for driving electrons and holes alone or in combination of both can be manufactured.
TF for display of LDD structure of S or pMOS or cMOS
A panel integrated with T can be realized. In the case of a small to medium-sized panel, there is a possibility that one of a pair of peripheral vertical drive circuits can be omitted.

(C) Since the heat treatment temperature during the above-mentioned grapho-epitaxial growth can be 930 ° C. or less, a relatively low temperature (for example, 900 to 93
(0 ° C. or less), the single crystal silicon film 7 can be formed uniformly. In addition, quartz glass, crystallized glass, a ceramic substrate, or the like can be used as the substrate.

(D) Since long-time annealing at an intermediate temperature and excimer laser annealing as in the case of the solid-phase growth method are not required, productivity is high, and expensive manufacturing equipment is not required and cost can be reduced. .

(E) In this high-temperature grapho-epitaxial growth, the indium-silicon composition ratio, the substrate heating temperature,
By adjusting the melt temperature, cooling rate, etc., a wide range of P-type impurity concentration and high mobility single crystal silicon thin film can be easily obtained, so that Vth (threshold) adjustment is easy, and high speed due to low resistance is achieved. Operation is possible.

(F) If a color filter is formed on the display array section, cost reduction can be realized by improving the aperture ratio and luminance of the display panel, omitting the color filter substrate, improving productivity, and the like.

<Second Embodiment> A second embodiment of the present invention will be described with reference to FIGS.

In this embodiment, a top gate type TFT similar to that of the above-described first embodiment is provided in the display portion and the peripheral drive circuit portion. It concerns a type LCD. That is, although the steps from (1) in FIG. 1 to the step shown in (14) in FIG. 5 are the same, after that step, as shown in (15) in FIG. At the same time as opening the window 19 for contacting the drain portion, unnecessary portions of the SiO ₂ , PSG and SiN films in the pixel opening are removed to improve the transmittance. An opaque ceramic substrate cannot be used.

Next, as shown in FIG. 14 (16),
A flat film 28B of a photosensitive acrylic transparent resin having a thickness of 2 to 3 μm is formed on the entire surface by spin coating or the like, and a window of the transparent resin 28B on the drain side of the display TFT is opened by general-purpose photolithography. Let it cure.

Next, as shown in FIG. 14 (17),
An ITO sputtered film having a thickness of 130 to 150 nm is formed on the entire surface, and is contacted with the drain portion 19 of the display TFT by general-purpose photolithography and etching technology.
The TO transparent electrode 41 is formed. Then, by heat treatment (200 to 250 ° C./1 h in a forming gas), the contact resistance between the drain of the display TFT and the ITO is reduced and the transparency of the ITO is improved.

Then, as shown in FIG.
2, and a transmissive LCD is assembled in the same manner as in the first embodiment. However, a polarizing plate is also attached to the TFT substrate side. In this transmissive LCD, transmitted light can be obtained as shown by the solid line, but the opposing substrate 3 can be obtained as shown by the dashed line.
It is also possible to obtain transmitted light from two sides.

In the case of this transmissive LCD, an on-chip color filter (OCCF) structure and an on-chip black (OCB) structure can be manufactured as follows.

[0110] That is, steps up in FIG. 1 (1) of the to 5 (13) is carried out according to the above process, but then, as shown in (14) in FIG. 16, insulating the PSG / SiO ₂ Membrane 25
The drain portion is also opened as a window to form an aluminum buried layer 41A for a drain electrode, and then an insulating film 36 of SiN / PSG is formed.

Next, as shown in (15) of FIG.
After forming a photoresist 61 in which each color of R, G, and B is dispersed in a pigment for each segment with a predetermined thickness (1 to 1.5 μm), as shown in (16) of FIG. Each of the color filter layers 61 (R), 61 (G), is patterned by leaving only predetermined positions (each pixel portion).
61 (B) is formed (on-chip color filter structure). At this time, the window of the drain part is also opened. In addition, an opaque ceramic substrate, glass with low transmittance, and a heat-resistant resin substrate cannot be used.

Next, as shown in (16) of FIG.
In a contact hole communicating with the drain of the display TFT, a light shielding layer 43 serving as a black mask layer is formed by metal patterning over the color filter layer. For example, molybdenum is sputtered by 200 to 250 n.
An m-thick film is formed and patterned into a predetermined shape that covers the display TFT and shields light (on-chip black structure).

Next, as shown in (17) of FIG.
A flattening film 28B made of a transparent resin is formed, and an ITO transparent electrode 41 is further formed in a through hole provided in the flattening film by a light shielding layer 4.
3 is formed.

As described above, by forming the color filter 61 and the black mask 43 on the display array section, the aperture ratio of the liquid crystal display panel can be improved, and the power consumption of the display module including the backlight can be reduced. Realize.

<Third Embodiment> A third embodiment of the present invention will be described.

In this embodiment, the above-described steps (concave portions) are formed on a glass substrate having a low strain point, and a single-crystal silicon layer is formed from indium-gallium-silicon or a gallium-silicon melt using a low-temperature graphene as a seed. Epitaxial growth and top gate type MOSTF
The present invention relates to an active matrix reflection type liquid crystal display (LCD) having a T configuration.

That is, in the present embodiment, as compared with the above-described first embodiment, in the step shown in FIG.
For example, a glass substrate such as borosilicate glass or aluminosilicate glass having a strain point or a maximum use temperature as low as about 600 ° C. is used. This is inexpensive and easy to increase in size, and to increase the thickness of a thin plate (for example, 500 × 60).
If it is 0 × 0.1 to 1.1 mm thick), it can be rolled / lengthened. Of course, a quartz substrate or a crystallized glass substrate can also be employed.

After the step 4 is formed in the same manner as described above, in the step shown in FIG. 1B, a silicon-indium-gallium melt containing 1% by weight of silicon or a silicon-gallium melt is added to the step 4. Is applied to the entire surface including.
At this time, the substrate 1 is heated to about 300 to 600 ° C. or 420 to 60 ° C.
Heat to 0 ° C.

Next, after holding the substrate 1 for several minutes to several tens of minutes, it is gradually cooled (in the case of dipping, it is gradually pulled up, but in the case of floating, it is gradually moved along the melt surface). The silicon dissolved in indium gallium or gallium is grown by grapho-epitaxial growth as shown in (3) of FIG. 2 using the corner at the bottom of the step 4 as a seed, and has a thickness of, for example, 0.1.
It is deposited as a P-type single crystal silicon layer 7 of about μm. In the dipping method or the floating method, the composition of the solution, the temperature, the pulling rate, and the like can be easily controlled, and the thickness of the epitaxial growth layer and the P-type impurity concentration can be easily controlled.

In this case, the single crystal silicon layer 7 has the (100) plane epitaxially grown on the substrate in the same manner as described above, but the shape of the step is changed as shown in FIGS. 9 (a) to 9 (f).
The crystal orientation of the growth layer can be controlled by various changes as described above.

After the single-crystal silicon layer 7 is deposited on the substrate 1 by low-temperature grapho-epitaxial growth, indium / gallium (or gallium) on the surface side is replaced with hydrochloric acid, sulfuric acid or the like as shown in FIG. To dissolve away.

Thereafter, using the single-crystal silicon layer 7, a top gate type MOSTFT is manufactured in the display section and the peripheral drive circuit section in the same manner as in the first embodiment.
The structure shown in FIG. 7 may be similarly applied to the present embodiment.

According to the present embodiment, the following remarkable functions and effects can be obtained in addition to the functions and effects described in the first embodiment.

(A) On the glass substrate 1, about 300 to 60
The silicon single crystal thin film 7 can be formed uniformly by grapho-epitaxial growth at a low temperature of 0 ° C. or 420 to 600 ° C.

(B) Therefore, since a silicon single crystal thin film can be formed not only on a glass substrate but also on an insulating substrate such as an organic substrate, a substrate material having a low strain point, low cost and good physical properties can be arbitrarily selected. In addition, the size of the substrate can be increased. Glass substrates and organic substrates can be manufactured at a lower cost than quartz substrates and ceramic substrates, and can be made thinner / longer / rolled. It is possible to manufacture a large-sized glass substrate or the like having a length / roll, with good productivity and at low cost. When a glass having a low glass strain point (or a maximum operating temperature) (for example, 500 ° C.) is used as the glass substrate, if the constituent elements diffuse from the inside of the glass to the upper layer and affect the transistor characteristics, this is used. For the purpose of suppressing, a barrier layer thin film (for example, silicon nitride:
(About 0 nm).

(C) In this low-temperature grapho-epitaxial growth, by adjusting the indium / gallium composition ratio of the indium / gallium film, the substrate heating temperature, the melt temperature, the cooling rate, etc., a wide range of P-type impurity concentration and high mobility can be obtained. Since a single-crystal silicon thin film can be easily obtained, Vth adjustment is easy and high-speed operation with low resistance is possible.

<Fourth Embodiment> A fourth embodiment of the present invention will be described.

The present embodiment relates to a transmissive LCD as compared with the above-described third embodiment, and its manufacturing process is similar to that of the above-described third embodiment, and is similar to that of the indium-gallium melt. A single crystal silicon thin film can be formed by low-temperature grapho-epitaxial growth using GaN.

Then, using this single crystal silicon thin film,
As described in the fourth embodiment, a transmission type LCD can be manufactured by the steps shown in FIGS. However, an opaque ceramic substrate or an opaque or low transmittance organic substrate is not suitable.

Therefore, in the present embodiment, the first
It is possible to have both excellent functions and effects of the third embodiment and the third embodiment. That is, in addition to the functions and effects of the above-described first embodiment, it is possible to use a low-cost substrate 1 that can be made thin and long, such as an organic substrate such as borosilicate glass or heat-resistant polyimide. The composition ratio of gallium / gallium makes it easy to adjust the conductivity type and Vth of the single-crystal silicon thin film 7, and the color filter 42 and the black mask 43 are formed on the display array to improve the aperture ratio of the liquid crystal display panel. Another object is to realize low power consumption of a display module including a backlight.

<Fifth Embodiment> FIGS. 17 to 25 show
13 shows a fifth embodiment of the present invention.

In this embodiment, the peripheral drive circuit section is a top gate type pMO similar to that of the above-described first embodiment.
It is composed of a cMOS drive circuit composed of an STFT and an nMOSTFT. The display section is of a reflection type, but has various combinations of TFTs having various gate structures.

FIG. 17A shows a top gate type nMOS LDD-T similar to that of the first embodiment.
Although an FT is provided in the display portion, a bottom gate type nMOS LDD-TFT shown in FIG.
The display section shown in FIG. 7C has a dual gate type nMOS.
LDD-TFTs are provided. Both of these bottom gate type and dual gate type MOS TFTs
As will be described later, the top gate type MOS of the peripheral drive circuit section
Although it can be manufactured in the same process as the TFT, especially in the case of the dual gate type, the driving capability is improved by the upper and lower gate portions, suitable for high-speed switching, and by selectively using either the upper or lower gate portion. Depending on the case, it can be operated as a top gate type or a bottom gate type.

The bottom gate type MO shown in FIG.
In the STFT, reference numeral 71 in the figure denotes a gate electrode of Mo / Ta, etc., reference numeral 72 denotes a SiN film and reference numeral 73 denotes a SiO ₂ film, which forms a gate insulating film. On this gate insulating film, a top gate type MOS TFT is formed. A channel region and the like using a similar single crystal silicon layer are formed. FIG.
7C, the lower gate portion is the same as that of the bottom gate type MOSTFT, but the upper gate portion has a gate insulating film 73 formed of a SiO ₂ film and a SiN film, and the upper gate portion is formed thereon. An electrode 74 is provided. However, in each case, each gate portion is formed outside the step 4 serving as a seed for grapho-epitaxial growth.

Next, the above bottom gate type MOSTFT
18 to 22 and a method of manufacturing the above dual gate type MOSTFT will be described with reference to FIGS. 23 to 25, respectively. In addition, the top gate type MO of the peripheral drive circuit section
Since the method of manufacturing the STFT is the same as that described with reference to FIGS. 1 to 6, illustration is omitted here.

In the display section, a bottom gate type MOST
To manufacture the FT, first, as shown in FIG. 18A, a molybdenum / tantalum (Mo.Ta)
An alloy sputtered film 71 (500 to 600 nm thick) is formed.

Next, as shown in FIG. 18B, a photoresist 70 is formed in a predetermined pattern, and using this as a mask, the Mo.Ta film 9 is taper-etched to form a side end portion 7.
1a forms a trapezoidal gate electrode 71 that is gently inclined at 20 to 45 degrees.

Next, as shown in FIG. 18C, after removing the photoresist 71, the substrate 1 including the molybdenum-tantalum alloy film 71 is formed on the substrate 1 by a plasma CVD method or the like.
SiN film (about 100 nm thick) 72 and SiO ₂ film (about 20 nm thick)
(Thickness of 0 nm) 73 is formed in this order to form a gate insulating film.

Next, as shown in (4) of FIG. 18, in the same step as (1) of FIG. 1, a photoresist 2 is formed in a predetermined pattern at least in a TFT formation region, and this is used as a mask. Similarly, a plurality of steps 4 are formed in the gate insulating film on the substrate 1 (and also on the substrate 1) in appropriate shapes and dimensions. The step 4 serves as a seed during the later-described monocrystalline silicon grapho-epitaxial growth, and has a depth d = 0.3 to 0.4 μm and a width w = 2 to 2.
The length may be 3 μm and the length (perpendicular to the paper surface) may be 10 to 20 μm, and the angle (base angle) between the base and the side surface is a right angle.

Next, as shown in FIG. 19 (5), after removing the photoresist 2, in the same step as in FIG. 1 (2), in the same manner as described above, indium containing silicon (or indium gallium or Gallium) melt 6
Is applied on the substrate 1 at the same substrate temperature as described above. Hereinafter, indium will be described as an example.

Next, as shown in FIG. 19 (6), in the same step as in FIG. 2 (3), by gradually cooling, silicon dissolved in indium was seeded at the bottom corner of the step 4. As a (seed), it is subjected to grapho-epitaxial growth and deposited as a P-type single-crystal silicon layer 7 having a thickness of, for example, about 0.1 μm. At this time, the underlying gate electrode 7
Since the side end 71a of 1 has a gentle slope, the single-crystal silicon layer 7 grows on this surface without any interruption of the epitaxial growth due to the step 4.

Next, as shown in FIG. 19 (7), after dissolving and removing indium 6A adhering to the surface side with hydrochloric acid, sulfuric acid or the like, the specific resistance may be adjusted by doping an appropriate amount of impurity ions.

Next, as shown in FIG. 19 (8), in the same step as FIG. 3 (8), the nMOSTF
The gate portion of T is covered with a photoresist 13 and the exposed source / drain regions of the nMOS TFT are doped (ion-implanted) with phosphorus ions 14 to form an LDD portion 15 made of an N ⁻ -type layer in a self-aligned manner. At this time, the surface height difference (or pattern) can be easily recognized by the presence of the bottom gate electrode 71, the position of the photoresist 13 can be easily aligned (mask alignment), and alignment misalignment does not easily occur.

Next, as shown in FIG.
In the same step as (9), the gate portion and the LDD portion of the nMOSTFT are covered with the photoresist 16, and the exposed region is doped (ion-implanted) with phosphorus or arsenic ions 17 to form an n ⁺ type layer of the nMOSTFT. A source part 18 and a drain part 19 are formed.

Next, as shown in (10) of FIG.
In the same step as (10) in FIG. 4, the entire nMOS TFT is covered with the photoresist 20 and the boron ion 2 is removed.
Doping (ion implantation) into the peripheral drive circuit
A source portion and a drain portion of the P ⁺ layer of the MOSTFT are formed.

Next, as shown in FIG. 20 (11),
In the same step as (11) in FIG. 4, a photoresist 24 is provided to make the active element part and the passive element part islands, and the single crystal silicon thin film layer is selectively removed by general-purpose photolithography and etching techniques.

Next, as shown in FIG. 20 (12),
In the same step as (12) in FIG.
SiO by high-density plasma CVD, catalytic CVD, etc.
_{A second} film 53 (about 300 nm thick) and a phosphosilicate glass (PSG) film 54 (about 300 nm thick) are formed on the entire surface in this order. The SiO ₂ film 53 and the PSG film 54 correspond to the above-described protective film 25. Then, in this state, the single crystal silicon film is activated in the same manner as described above.

Next, as shown in FIG. 21 (13),
In the same step as (13) in FIG. 5, a contact window is opened in the source portion by general-purpose photolithography and etching technology. And 400 to 500 nm on the entire surface
A thick sputtered film of aluminum or the like is formed, and a data line and a gate line are formed simultaneously with the source electrode 26 of the TFT by general-purpose photolithography and etching techniques. Then, during forming gas,
Sintering is performed at about 400 ° C. for 1 hour.

Next, as shown in (14) of FIG.
In the same step as (14) in FIG.
PSD film (about 300 nm) by VD, catalytic CVD, etc.
Thickness) and an insulating film 3 composed of a SiN film (about 300 nm thick)
6 is formed on the entire surface, and a contact window is opened in the drain of the display TFT.

Next, as shown in FIG. 21 (15),
In the same step as (15) in FIG. 6, a photosensitive resin film 28 having a thickness of 2 to 3 μm is formed by spin coating or the like, and as shown in (16) in FIG. A concave / convex pattern that obtains optimum reflection characteristics and viewing angle characteristics is formed in the portion, and reflow is performed to form a lower reflective surface composed of the concave / convex rough surface 28A. At the same time, a resin window for contact of the drain portion of the display TFT is opened.

Next, as shown in (16) of FIG.
In the same step as (16) in FIG.
A sputtered film made of aluminum or the like having a thickness of 00 nm is formed, and a reflective portion 29 made of aluminum or the like connected to the drain portion 19 of the display TFT is formed by general-purpose photolithography and etching technology.

As described above, the bottom gate type nMOS is formed on the display portion using the single crystal silicon layer 7 formed with the step 4 as a seed for high-temperature grapho-epitaxial growth.
LDD-TFT (pMOSTFT and n in peripheral circuit section)
A display-peripheral drive circuit unit-integrated active matrix substrate 30 in which a CMOS drive circuit composed of MOSTFTs is built can be manufactured.

FIG. 22 shows an example in which the gate insulating film of the above-mentioned bottom gate type MOSTFT provided in the display portion is formed by an anodic oxidation method of Mo · Ta.

That is, after the step (2) in FIG.
As shown in (3), the molybdenum-tantalum alloy film 71
Is subjected to a known anodic oxidation treatment so that T
a ₂ O ₅ gate insulating film 74 of 100 to 200 n
m thickness.

In the subsequent steps, as shown in FIG. 22D, a step 4 is formed in the same manner as in the step of FIG. 18D, and the silicon-containing indium melt 6 is applied. The active matrix substrate 30 is manufactured as shown in FIG. 22 (5) in the same manner as in the steps of FIG. 19 (5) to FIG. 21 (16).

Next, in order to manufacture a dual-gate type MOSTFT in the display section, first, FIG.
The steps up to (7) in FIG. 19 are performed in the same manner as described above.

That is, as shown in FIG. 23 (8), a step 4 is formed on the insulating films 72 and 73 and the substrate 1, and the single crystal silicon layer 7 is grown by grapho-epitaxial growth using the step 4 as a seed. Next, in the same step as (6) in FIG. 3, an SiO ₂ film (about 200 nm) is formed on the entire surface of the single crystal silicon thin film 7 by plasma CVD, catalytic CVD, or the like.
) And a SiN film (about 100 nm thick) are sequentially formed in this order to form an insulating film 80 (which corresponds to the above-described insulating film 8), and further, a Mo.Ta alloy sputtered film 81 (500 to 6).
(Thickness: 00 nm) (this corresponds to the above-described sputtered film 9).

Then, as shown in FIG. 23 (9), in the same step as FIG. 3 (7), a photoresist pattern 10 is formed, and Mo · Ta is continuously etched.
An alloy top gate electrode 82 (which corresponds to the above-described gate electrode 12) and a gate insulating film 83 (which corresponds to the above-described gate insulating film 11) are formed to expose the single crystal silicon thin film layer 7.

Next, as shown in (10) of FIG.
In the same step as (8) in FIG. 3, the top gate portion of the nMOSTFT is covered with a photoresist 13, and the source / drain regions of the exposed display nMOSTFT are doped (ion-implanted) with phosphorus ions 14 to form an N ⁻ -type. The LDD part 15 of the layer is formed.

Next, as shown in FIG. 23 (11), in the same step as FIG. 4 (9), the gate portion and the LDD portion of the nMOS TFT are covered with the photoresist 16 and the exposed region is doped with phosphorus or arsenic ions 17. (Ion implantation) to form a source portion 18 and a drain portion 19 made of an N ⁺ -type layer of the nMOS TFT.

Next, as shown in FIG. 24 (12),
In the same step as (10) in FIG. 4, the gate portion of the pMOSTFT is covered with the photoresist 20, and the exposed region is doped (ion-implanted) with boron ions 21 so that the source of the P ⁺ layer of the pMOSTFT in the peripheral driving circuit portion is formed. And a drain part are formed.

Next, as shown in (13) of FIG.
In the same step as (11) in FIG. 4, a photoresist 24 is provided to make the active element section and the passive element section into islands, and the single crystal silicon thin film layer other than the active element section and the passive element section is subjected to general-purpose photolithography and etching. Selective removal with technology.

Next, as shown in (14) of FIG.
In the same step as (12) in FIG.
SiO by high-density plasma CVD, catalytic CVD, etc.
_{A 2} film 53 (about 200 nm thick) and a phosphosilicate glass (PSG) film 54 (about 300 nm thick) are formed on the entire surface. These films 53 and 54 correspond to the protective film 25 described above. Then, the single crystal silicon layer 7 is activated.

Next, as shown in (15) of FIG.
In the same step as (13) in FIG. 5, a contact window is opened in the source section. And 400-500n on the whole surface
A m-thick aluminum sputtered film is formed, and the source electrode 2 is formed by general-purpose photolithography and etching techniques.
At the same time as forming 6, a data line and a gate line are formed.

Next, as shown in FIG. 25 (16),
In the same step as (14) in FIG.
Thickness) and an insulating film 3 composed of a SiN film (about 300 nm thick)
6 is formed on the entire surface, and a contact window is opened in the drain of the display TFT.

Next, as shown in (17) of FIG.
A photosensitive resin film 28 having a thickness of 2 to 3 μm is formed on the entire surface by spin coating or the like, and as shown in FIG.
Similarly to the steps (17) and (18), the lower part of the reflection surface composed of the rough surface 28A is formed at least in the pixel part, and at the same time, a resin window for contact of the drain part of the display TFT is opened to further display. An aluminum reflective portion 29 having a concave and convex shape for obtaining optimum reflection characteristics and viewing angle characteristics, which is connected to the drain portion 19 of the TFT for use, is formed.

As described above, using the single crystal silicon layer 7 formed with the step 4 as a seed for high-temperature grapho-epitaxial growth, the dual gate type nMO
SLDD TFT is replaced with pMOSTFT and nMO
Active matrix substrate 3 with integrated display section and peripheral drive circuit section incorporating CMOS drive circuit composed of STFT
0 can be produced.

<Sixth Embodiment> FIGS. 26 to 31 show
14 shows a sixth embodiment of the present invention.

In the present embodiment, unlike the above-described embodiment, the gate electrode of the top gate portion is made of aluminum, aluminum alloy, for example, 1% Si-containing aluminum, 1-2% copper-containing aluminum, copper or the like. It is made of a material with low heat resistance.

First, when a top gate type MOSTFT is provided for both the display section and the peripheral drive circuit section, the above-described first embodiment shown in FIGS.
26, the N-type well 7 is formed in the pMOSTFT portion of the peripheral drive circuit portion as shown in (5) of FIG.
Form A.

Next, as shown in FIG. 26 (6), all of the nMOS and pMOSTFTs in the peripheral drive region and the gate portion of the nMOSTFT in the display region are connected to the photoresist 13
And cover the exposed source / drain regions of the nMOS TFT with phosphorus ions 14 at 5 × 10 ¹³ at, for example, 20 kV.
By doping (ion implantation) at a dose of atoms / cm ^2, the LDD portion 15 made of an N ⁻ -type layer is formed in a self-aligned manner.

Next, as shown in FIG. 27 (7), all of the pMOS TFTs in the peripheral drive region and n in the peripheral drive region
Gate portion of MOSTFT and nMOSTFT in display area
Is covered with a photoresist 16 and phosphorus or arsenic ions 17 are exposed to the
By doping (ion implantation) at 0 kV and a dose of 5 × 10 ¹⁵ atoms / cm ² , the source 18 and the drain 19 and the LDD 15 made of the N ⁺ type layer of the nMOS TFT are formed. In this case, if the resist 13 is left like an imaginary line, and the resist 16 is provided so as to cover the resist 13, the mask 13 can be used as a guide for the mask alignment at the time of forming the resist 16, the mask alignment can be facilitated, and the misalignment can be achieved. Is also reduced.

Then, as shown in FIG. 27 (8), the nMOSTFT in the peripheral drive region and the nMOST in the display region are used.
The entire FT and the gate portion of the pMOSTFT are covered with a photoresist 20, and the exposed region is doped with boron ions 21 at, for example, 10 kV at a dose of 5 × 10 ¹⁵ atoms / cm ² , thereby ion-implanting the P ^{+ of the} pMOSTFT. The source part 22 and the drain part 23 of the layer are formed.

Next, after removing the resist 20, FIG.
As shown in (9), the single crystal silicon layers 7 and 7A are activated in the same manner as described above, and a gate insulating film 12 and a gate electrode material (aluminum or aluminum containing 1% Si or the like) 11 are further provided on the surface. Form. Gate electrode material layer 1
1 can be formed by a vacuum evaporation method or a sputtering method.

Next, after patterning each gate portion in the same manner as described above, the active element portion and the passive element portion are made into islands, and as shown in FIG.
₂ film (about 200 nm thick) and phosphorus silicate glass (P
An SG) film (about 300 nm thick) is continuously formed on the entire surface in this order to form the protective film 25.

Next, as shown in FIG. 28 (11),
By general-purpose photolithography and etching technology, contact windows are opened in the source / drain portions of all the TFTs of the peripheral drive circuit and the source portions of the display TFT.

Then, a sputtered film of aluminum or aluminum containing 1% Si having a thickness of 500 to 600 nm is formed on the entire surface, and the peripheral drive circuit and the source electrodes 26 of all TFTs in the display section are formed by general-purpose photolithography and etching technology. A data line and a gate line are formed at the same time as the formation of the drain electrode 27 of the peripheral driving circuit. After that, forming gas (N ₂ + H ₂ )
Sintering is performed at about 400 ° C. for 1 hour.

Next, (14) in FIG. 5 to (17) in FIG.
A top gate type nMOS LDD-TFT, pMOSTFT, and nMOS having a gate electrode of aluminum or aluminum containing 1% Si, respectively, for a display unit using a single crystal silicon layer 7 and a peripheral driving circuit unit in the same manner as described above.
Active matrix substrate 3 with integrated display section-peripheral drive circuit section incorporating CMOS drive circuit composed of TFTs
0 can be produced.

In the present embodiment, the gate electrode 11 made of aluminum or aluminum containing 1% Si is formed after the activation process of the single crystal silicon layer 7. Since it has no relation to the heat resistance of the material, the heat resistance of the gate electrode material is relatively low, and low-cost aluminum or aluminum containing 1% Si can be used. This is the same when the display section is a bottom gate type MOSTFT.

Next, a dual gate type MOST is provided in the display section.
In the case where the FT and the peripheral driving circuit are provided with a top gate type MOSTFT, FIG.
The steps from (1) to (7) in FIG. 8 are performed in the same manner, and as shown in (7) in FIG.
An N-type well 7A is formed in the MOSTFT portion.

Next, as shown in FIG. 29 (8), the LDD section 15 is formed by doping the TFT section of the display section with phosphorus ions 14 in the same manner as in FIG. 26 (6).

Next, as shown in FIG. 30 (9), the n ⁺ TFT source region 18 is doped by doping phosphorus ions 17 into the nMOSTFT portion of the display section and the peripheral drive circuit section in the same manner as (7) of FIG. Drain regions 19 are respectively formed.

Next, as shown in (10) of FIG.
In the same manner as (8) in FIG.
The TFT portion is doped with boron ions 21 to form P ⁺ type source region 22 and drain region 23, respectively.

Next, after removing the resist 20, FIG.
After patterning the single crystal silicon layer 7 to make the active element portion and the passive element portion into islands as shown in (11), the single crystal silicon layers 7 and 7A are formed as shown in (12) in FIG. An activation process is performed in the same manner as described above. Further, a gate insulating film 80 is formed on the surface of the display unit, and a gate insulating film 12 is formed on the surface of the peripheral driver circuit unit.

Next, as shown in (13) of FIG.
By patterning aluminum formed on the entire surface by a sputtering method, each upper gate electrode 83 of the display section and each gate electrode 11 of the peripheral drive circuit section are formed.

Next, as shown in (14) of FIG.
An SiO ₂ film (about 200 nm thick) and a phosphosilicate glass (PSG) film (about 300 nm thick) are successively formed on the entire surface in this order to form a protective film 25.

Next, in the same manner as described above, the source electrodes 26 of all the TFTs of the peripheral drive circuit and the display section and the drain electrode 27 of the peripheral drive circuit section are formed, and the display section and the single crystal silicon layer 7 are formed. A dual gate type nMOS LDD-TFT, pMOSTFT, and nMOT using aluminum as a gate electrode are respectively provided in the peripheral drive circuit unit.
A display section-peripheral drive circuit section integrated type active matrix substrate 30 incorporating a CMOS drive circuit composed of STFTs can be manufactured.

Also in the present embodiment, after the activation treatment of single crystal silicon layer 7, gate electrodes 11, 83 of aluminum or the like are formed.
Since the influence of heat during the activation process is independent of the heat resistance of the gate electrode material, the heat resistance of the gate electrode material is relatively low, and low-cost aluminum, aluminum alloy, copper Etc. can be used, and the range of choice of the electrode material is expanded. The source electrode 26 (and also the drain electrode) can be formed at the same time in the step (13) of FIG. 31. However, in this case, there is an advantage in the manufacturing method.

In any of the above embodiments, for example, a bottom gate type or a top gate type MOS
When a TFT is manufactured, as shown in FIG. 32A, when a step 4 is provided, the single crystal silicon film 7 grown thereon is thin, so that the step is disconnected (poor connection) or thinned (increased resistance). 3) may occur, so that the connection with the source electrode 26 (or the drain electrode) must be performed in order to ensure the connection with the source electrode 26 (or the drain electrode).
As shown in FIGS. 2 (B) and 2 (C), it is desirable that the electrode be deposited on a region including the step 4.

In the step (6) of FIG. 26 or the step (8) of FIG. 29, after forming the top gate insulating film on the single crystal silicon layer 7, ion implantation and activation are performed.
Thereafter, the top gate electrode, the source, and the drain electrode may be simultaneously formed of aluminum.

In addition, as shown in FIG. 33A, the above-described step 4 is formed on the substrate 1 (and further on the substrate 1) in the above-described example.
For example, as shown in FIG. 33B, it is formed on the SiN film 51 on the substrate 1 (which has a function of stopping diffusion of ions from the glass substrate 1). Can also. Instead of this SiN film 51, or on this SiN film, the above-mentioned gate insulating films 72 and 73
, And the step 4 may be formed thereon.

<Seventh Embodiment> FIGS. 34 and 36 show the seventh embodiment.
14 shows a seventh embodiment of the present invention.

In this embodiment, various examples in which each TFT is formed outside the above-described step 4 (that is, on the substrate 1 other than the step) will be described. The single crystal silicon layer 7 and the gate /
The source / drain electrodes 26 and 27 are schematically illustrated.

First, FIG. 34 shows a top gate type MOSTF.
3A, a recess 4 due to a step is formed along one side of the source along the source region, and the gate insulating film 1 is formed on the single crystal silicon layer 7 on the flat surface of the substrate other than the recess.
2 and a gate electrode 11 are formed. Similarly, (b)
Is an example in which a concave portion 4 due to a step is formed in an L-shaped pattern over two sides not only in the source region but also in the channel length direction up to the end of the drain region.
An example is shown in which a rectangular shape is formed over four sides so as to surround an active area. (D) is an example in which the same concave portion 4 is formed over three sides, and (e) is an example in which the same concave portion 4 is formed in an L-shaped pattern over two sides. The recesses 4-4 are not continuous.

As described above, since the recesses 4 of various patterns can be formed and the TFT is provided on the flat surface other than the recesses 4, the TFT can be easily manufactured.

FIG. 35 shows the case of a bottom gate type MOSTFT, but the steps (or recesses) 4 of various patterns shown in FIG. 34 can be formed in the same manner. That is, FIG.
FIG. 5A is an example corresponding to FIG. 34A, in which a bottom gate type MOSTFT is formed on a flat surface other than the recess 4 due to a step. Similarly, FIG. 35B shows FIG.
FIG. 4C shows an example corresponding to FIGS. 34C and 34D.

FIG. 36 shows a dual gate type MOSTFT.
In this case, the steps (or recesses) 4 of the various patterns shown in FIG. 34 can be formed in the same manner. For example, on the flat surface in the area inside the steps 4 shown in FIG. A dual-gate MOSTFT can be manufactured.

<Eighth Embodiment> FIGS. 37 to 39 show
14 shows an eighth embodiment of the present invention.

FIG. 37 shows an example in which the self-aligned LDD structure has a T
The present invention relates to an FT, for example, a double-gate MOSTFT in which a plurality of top-gate MOSLDD-TFTs are connected.

According to this, the gate electrode 11 is branched into two, one of which is used as the first gate and the first LDD-TF.
A second LDD-TF for T and the other as a second gate
Used for T (however, an N ⁺ -type region 100 is provided between gate electrodes at the center of the single crystal silicon layer to reduce resistance). In this case, a different voltage may be applied to each gate, and even if one gate becomes inoperable for some reason, carriers can be moved between the source and the drain by using the remaining gates. Thus, a highly reliable device can be provided. Further, since the first LDD-TFT and the second LDD-TFT are connected in series to form a thin film transistor for driving each pixel, the source of each thin film transistor is turned off when it is off. The voltage applied between the drains can be greatly reduced. Therefore, the leakage current flowing during the off state can be reduced, and the contrast and the image quality of the liquid crystal display can be improved satisfactorily. In addition, since the two LDD transistors are connected using only the same semiconductor layer as the low-concentration drain region in the LDD transistor, the connection distance between the transistors can be shortened. Even if two pieces are connected, the required area can be prevented from increasing. The first and second gates can be completely separated from each other and operated independently.

FIG. 38 shows a bottom gate type MOSTF.
T has a double-gate structure (A) and dual-gate MOSTFT has a double-gate structure (B).

[0202] These double-gate MOSTFTs also
It has the same advantages as the above-mentioned top gate type. Among them, the dual gate type has the further advantage that one of the upper and lower gate portions can be used even if one of the upper and lower gate portions becomes inoperable.

FIG. 39 shows each of the above-mentioned double gate type MOs.
FIG. 2 shows an equivalent circuit diagram of an STFT. In the above description, the gate is branched into two, but the gate may be branched or divided into three or more. In these double-gate or multi-gate structures, two
The gate electrode may have the above-mentioned branched gate electrode of the same potential, or may have a divided gate electrode of a different potential or the same potential.

<Ninth Embodiment> FIG. 40 shows a ninth embodiment of the present invention.
In the dual gate type TFT described above, one of the upper and lower gates operates as a transistor, while the other gate operates as follows.

That is, FIG. 40A shows that in the nMOS TFT, an arbitrary negative voltage is always applied to the gate electrode on the top gate side to reduce the leakage current in the back channel. The case where the top gate electrode is opened is when the device is used as a bottom gate type. Also,
In FIG. 40B, an arbitrary negative voltage is always applied to the gate electrode on the bottom gate side to reduce the leakage current of the back channel. Also in this case, when the bottom gate electrode is opened, it can be used as a top gate type. In the case of a pMOSTFT, if an arbitrary positive voltage is always applied to the gate electrode, the leakage current of the back channel can be reduced.

In any case, the interface between the single crystal silicon layer 7 and the insulating film has poor crystallinity and a leak current easily flows. However, the leak current can be cut off by applying a negative voltage to the electrode as described above. This is advantageous in combination with the effect of the LDD structure. In addition, a leak current may flow due to light incident from the glass substrate 1 side. However, since the light is blocked by the bottom gate electrode, the leak current can be reduced.

<Tenth Embodiment> FIGS. 41 to 49
Shows a tenth embodiment of the present invention.

As described above, the top gate type, bottom gate type, and dual gate type TFTs each have a difference in structure or function or a feature, and therefore these are employed in the display portion and the peripheral drive circuit portion. At this time, it may be advantageous to provide various combinations of TFTs between these units.

For example, as shown in FIG. 41, when any of a top gate type, a bottom gate type, and a dual gate type MOSTFT is adopted for the display portion, the top gate type MOSTFT and the bottom gate type MOSTFT are used for the peripheral driving circuit.
Of the TFT and the dual gate type MOSTFT, at least a top gate type can be adopted, or they can be mixed. There are 12 combinations (N
o.1 to No.12). Especially, MOS of peripheral drive circuit
When a dual gate structure is used for a TFT, such a dual gate structure can be easily changed to a top gate type or a bottom gate type by selecting upper and lower gate portions. When a TFT having a large driving capacity is required, a dual gate type may be required. For example, it is considered necessary when the present invention is applied to an organic EL or FED as an electro-optical device other than an LCD.

FIGS. 42 and 43 show the MOSTFT of the display section.
44 and FIG. 45 show the case where the MOSTFT of the display section has the LDD structure when FIG.
Reference numeral 7 denotes a TF having an LDD structure in which a MOSTFT in a peripheral drive circuit section has an LDD structure.
48, FIG. 48 and FIG. 49 show respective MOSTs of the peripheral drive circuit unit and the display unit when both the peripheral drive circuit unit and the display unit include the MOSD with the LDD structure.
Various examples (No. 1 to No. 216) showing combinations of FTs by channel conductivity type are shown.

As described above, the combinations for the respective gate structures shown in FIG. 41 are specifically as shown in FIGS. 42 to 49. The same combination is possible even when the peripheral drive circuit section is composed of a mixed-type MOSTFT of a top gate type and another gate type. Note that FIG.
The various combinations of the TFTs shown in FIGS. 49 to 49 are not limited to the case where the channel region and the like of the TFT are formed of single crystal silicon, but may be polycrystalline silicon or amorphous silicon (however,
The same applies to the case of forming the display portion only).

<Eleventh Embodiment> FIGS. 50 to 51
Shows an eleventh embodiment of the present invention.

In the present embodiment, in an active matrix drive LCD, a TFT using the above-described single crystal silicon layer is provided in the peripheral drive circuit section based on the present invention from the viewpoint of improvement in drive capability. However, this is not limited to the top gate type, other gate types may be mixed, the channel conductivity type may be various, and a MOSTFT using a polycrystalline silicon layer other than a single crystal silicon layer is included. It may be. On the other hand, the MOSTFT of the display portion preferably uses a single-crystal silicon layer, but is not limited to this, and may use a polycrystalline silicon or amorphous silicon layer, or at least three types of silicon layers. A mixture of two types may be used. However, when the display section is formed of an nMOS TFT, a practical switching speed can be obtained by using an amorphous silicon layer.
The area can be reduced, and it is more advantageous than amorphous silicon in reducing pixel defects. In addition, not only single-crystal silicon but also polycrystalline silicon is generated at the same time as the above-mentioned grapho-epitaxial growth, so-called CGS (Continuo).
Us grain silicon) structures may also be included, but can also be used to form active and passive devices.

FIG. 50 shows examples (A), (B) and (C) of various combinations of MOSTFTs between the respective parts.
Shows a specific example. When single crystal silicon is used, the current driving capability is improved, so that the element can be made smaller.
The screen can be enlarged, and the aperture ratio in the display section is improved.

In the peripheral drive circuit section, the above MOS
Of course, not only the TFT but also an electronic circuit in which a diode, a capacitance, a resistance, an inductance and the like are integrated may be formed integrally on an insulating substrate (a glass substrate or the like).

<Twelfth Embodiment> FIG. 52 shows a twelfth embodiment of the present invention.

In this embodiment, each of the above-described embodiments is directed to an example of active matrix driving, but the present invention is applied to passive matrix driving.

That is, the display section is provided with no switching element such as the MOSTFT described above, and the incident light or the reflected light of the display section is dimmed only by a potential difference caused by a voltage applied between a pair of electrodes formed on the opposing substrate. You. Such dimming devices include reflective and transmissive LCDs, organic ELs (electroluminescent display devices), FEDs (field emission display devices), LEPDs (light emitting polymer display devices), LE
D (light emitting diode display element) and the like are also included.

<Thirteenth Embodiment> FIG. 53 shows a thirteenth embodiment of the present invention.

In this embodiment, the present invention is applied to an electro-optical device other than an LCD, such as an organic or inorganic EL (electroluminescent display element), an FED (field emission display element),
It is applied to an EPD (generated polymer display element), an LED (light emitting diode display element) and the like.

That is, FIG. 53A shows an EL element driven by an active matrix. For example, an organic EL layer using an amorphous organic compound (or an inorganic EL layer using ZnS: Mn) 90 is formed on the substrate 1. The transparent electrode (ITO) 41 described above is formed at the lower part, and the cathode 91 is formed at the upper part. Light emission of a predetermined color can be obtained through the filter 61 by applying a voltage between these two electrodes.

At this time, in order to apply a data voltage to the transparent electrode 41 by active matrix driving, a single-crystal silicon MOSTFT according to the present invention using a single-crystal silicon layer grown by grapho-epitaxial growth using the step 4 on the substrate 1 as a seed. (That is, nMOSLDD-TFT) is formed on the substrate 1. A similar TFT is provided in a peripheral driving circuit. Since this EL element is driven by a MOSLDD-TFT using a single crystal silicon layer,
High switching speed and low leakage current. The filter 61 can be omitted if the EL layer 90 emits a specific color.

In the case of the EL element, since the driving voltage is high, the peripheral driving circuit section includes, in addition to the above MOSTFT,
It is advantageous to provide a high breakdown voltage driver element (such as a high breakdown voltage cMOS TFT and a bipolar element).

FIG. 53B shows an FED driven by passive matrix. Electrons emitted from the cold cathode 94 by a voltage applied between the electrodes 92 and 93 in a vacuum section between the opposing glass substrates 1-32. Is incident on the opposing phosphor layer 96 by selecting the gate line 95, thereby obtaining light emission of a predetermined color.

Here, the emitter line 92 is guided to a peripheral driving circuit and driven by a data voltage. The peripheral driving circuit is provided with a MOSTFT using a single crystal silicon layer according to the present invention. This contributes to high-speed driving of the emitter line 92. The FED can be driven in an active matrix by connecting the above-mentioned MOSTFT to each pixel.

In the element shown in FIG.
If a known light emitting polymer is used instead of the layer 90, a passive matrix or active matrix driven light emitting polymer display device (LEPD) can be formed. In addition, a device similar to the FED using the diamond thin film on the cathode side in the element of FIG. 53B can also be configured. Further, in a light emitting diode, for example, a gallium-based (gallium.
It can drive a light-emitting portion made of a film of aluminum, arsenic, or the like. Alternatively, it is conceivable that the film of the light emitting portion is grown by single crystal by the epitaxial growth method of the present invention.

The embodiments of the present invention described above can be variously modified based on the technical idea of the present invention.

For example, when the above-mentioned low melting point metal melt 6 is applied, a trivalent or pentavalent element having high solubility, such as boron, phosphorus, antimony, arsenic, aluminum, gallium, indium, bismuth, etc. If the melt 6 is appropriately doped, the P-type or N-type channel conductivity of the silicon epitaxial growth layer 7 to be grown,
The carrier concentration can be arbitrarily controlled.

In order to prevent diffusion of ions from the glass substrate, a SiN film (for example, 50 to 200 nm) is formed on the substrate surface.
Thickness) and, if necessary, a SiO ₂ film (for example, 100 n
m thickness), and the step 4 as described above may be formed on these films. The above-described steps can be formed by an ion milling method or the like in addition to RIE.

The present invention is suitable for a TFT of a peripheral drive circuit. In addition, the active region of an element such as a diode and the passive region such as a resistor, a capacitance and an inductance can be formed by a single crystal silicon according to the present invention. It is also possible to form them in layers.

[0231]

According to the present invention, a single-crystal silicon thin film layer formed by silicon epitaxial growth by depositing single-crystal silicon from a melt of a low-melting-point metal layer in which silicon is dissolved, using the above-described step formed on a substrate as a seed. A single-crystal semiconductor layer as shown in FIG. 1 is used as at least an active element such as a top gate type MOSTFT and a passive element in a peripheral drive circuit section of an electro-optical device such as an LCD integrated with a display section and a peripheral drive circuit. Therefore, the following remarkable functions and effects shown in (A) to (F) can be obtained.

(A) A step having a predetermined shape / dimension is formed on a substrate, and 540 cm ² / v · s
Since a single-crystal semiconductor layer such as a single-crystal silicon thin film having a high electron mobility of ec or more can be obtained, an electro-optical device such as a display thin-film semiconductor device with a built-in high-performance driver can be manufactured.

(B) In particular, the single-crystal silicon top-gate MOSTFT made of the single-crystal silicon thin film has a high switching characteristic, a display section of an nMOS, pMOS or cMOSTFT having an LDD structure, and a cMOS or a high driving capability. A configuration in which an nMOS or pMOSTFT or a peripheral drive circuit comprising a mixture of these is integrated becomes possible, and a display panel with high image quality, high definition, a narrow frame, high efficiency, and a large screen is realized.

(C) The low-melting-point metal melt layer described above can be prepared at a low temperature and formed on a substrate heated to a temperature slightly higher than this by coating or the like, so that a silicon single crystal film can be formed at a relatively low temperature. It can be formed uniformly.

(D) Since long-time annealing at an intermediate temperature and excimer laser annealing as in the case of the solid phase growth method are not required, productivity is high, and expensive manufacturing equipment is not required, and cost can be reduced. .

(E) In this grapho-epitaxial growth, adjustment of the composition ratio of the low melting point metal melt (particularly, the silicon / indium / gallium composition ratio, silicon / indium composition ratio), the substrate heating temperature, the melt temperature, the cooling rate, etc. As a result, a single-crystal silicon thin film having a wide range of P-type impurity concentration and high mobility can be easily obtained, so that Vth adjustment is easy and high-speed operation with low resistance is possible.

(F) In addition, at the time of forming the silicon-containing low melting point metal layer, an appropriate amount of an impurity element of Group 3 or Group 5 having high solubility (boron, phosphorus, antimony, arsenic, bismuth, aluminum, etc.) is separately doped. In this case, the impurity species and / or the concentration of the single crystal silicon thin film formed by the grapho-epitaxial growth, that is, the P-type / N-type conductivity type and / or the carrier concentration can be arbitrarily controlled.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of an LCD (Liquid Crystal Display) according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 3 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 4 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 5 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 6 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 7 is a sectional view of a main part of the LCD.

FIG. 8 is a schematic perspective view for explaining the state of silicon crystal growth on an amorphous substrate.

FIG. 9 is a schematic sectional view showing various step shapes and a silicon growth crystal orientation in the grapho-epitaxial growth technique.

10A and 10B are a Si-In phase diagram (A) and a Si-Ga phase diagram (B).

FIG. 11 is a perspective view showing an overall schematic layout of the LCD according to the first embodiment of the present invention.

FIG. 12 is an equivalent circuit diagram of the LCD.

FIG. 13 is a schematic configuration diagram of the same LCD.

FIG. 14 is a cross-sectional view showing a manufacturing process of the LCD according to the second embodiment of the present invention in the order of steps.

FIG. 15 is a sectional view of a main part of the LCD.

FIG. 16 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 17 is a sectional view of a main part of an LCD according to a fifth embodiment of the present invention.

FIG. 18 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 19 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 20 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 21 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 22 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 23 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 24 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 25 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 26 is a sectional view illustrating the manufacturing process of the LCD according to the sixth embodiment of the present invention in the order of steps.

FIG. 27 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 28 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 29 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 30 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 31 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 32 is a fragmentary cross-sectional view of the same at the time of manufacturing the LCD;

FIG. 33 is a fragmentary cross-sectional view of the same at the time of manufacturing the LCD;

FIG. 34 is a plan view or a sectional view showing various TFTs of an LCD according to a seventh embodiment of the present invention.

FIG. 35 is a cross-sectional view showing various TFTs of the LCD.

FIG. 36 is a cross-sectional view of a principal part of the LCD.

FIG. 37 is a sectional view or a plan view of main parts of an LCD according to an eighth embodiment of the present invention.

FIG. 38 is a cross-sectional view of a principal part of various TFTs of the LCD.

FIG. 39 is an equivalent circuit diagram of a TFT of the LCD.

FIG. 40 shows T of the LCD according to the ninth embodiment of the present invention.
It is principal part sectional drawing of FT.

FIG. 41 is a diagram showing a combination of TFTs of each part of the LCD according to the tenth embodiment of the present invention.

FIG. 42 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 43 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 44 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 45 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 46 is a view showing a combination of TFTs of each part of the LCD.

FIG. 47 is a view showing a combination of TFTs in each part of the LCD.

FIG. 48 is a view showing a combination of TFTs in each part of the LCD.

FIG. 49 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 50 is a schematic layout diagram of an LCD according to an eleventh embodiment of the present invention.

FIG. 51 is a diagram showing a combination of TFTs of each part of the LCD.

FIG. 52 is a schematic layout diagram of a device according to a twelfth embodiment of the present invention.

FIG. 53 is a sectional view of a main part of an EL and FED according to a thirteenth embodiment of the present invention;

[Explanation of symbols]

1: glass (or quartz) substrate, 4: step, 6: indium (or indium gallium or gallium) melt,
6A: indium (or indium gallium or gallium), 7: single crystal silicon layer, 9: Mo / Ta layer, 1
DESCRIPTION OF SYMBOLS 1 ... Gate electrode, 12 ... Gate oxide film, 14, 17 ... N
Type impurity ions, 15: LDD portion, 18, 19: N ⁺ type source or drain region, 21: P type impurity ions, 2
2, 23 ... P ⁺ type source or drain region, 25, 36
... insulating films, 26, 27, 31, 41 ... electrodes, 28 ... flattening films, 28A ... rough surfaces (irregularities), 29 ... reflective films (or electrodes), 30 ... LCD (TFT) substrates, 33, 34 ... orientation Film, 35: liquid crystal, 37, 46: color filter layer, 43
… Black mask layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 618C 626C (72) Inventor Yuichi Sato 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Sony Incorporated (72) Inventor Yagi Hajime 6-35 Kita-Shinagawa, Shinagawa-ku, Tokyo F-term in Sony Corporation (reference) 2H092 GA59 JA25 JA29 JA38 JA42 JB13 JB23 JB32 JB56 KA03 KA07 KA12 KA16 KA18 MA02 MA14 MA15 MA16 MA18 MA19 MA20 MA24 MA27 MA32 MA35 MA37 MA41 NA22 NA25 NA27 NA29 PA06 5F052 AA11 CA10 DA01 DB10 EA11 EA16 FA12 HA06 JA01 JA04

Claims (80)

[Claims] 1. A display device comprising: a display portion on which a pixel electrode is disposed; and a peripheral driver circuit portion disposed around the display portion on a first substrate. In a method for manufacturing an electro-optical device having a predetermined optical material interposed therebetween, a step of forming a step on one surface of the first substrate; and forming a step on the first substrate including the step, Forming a melt layer of a low-melting-point metal containing a semiconductor material such as silicon, and then performing a grapho-epitaxial growth of the semiconductor material of the melt layer by a cooling process (preferably a slow cooling process) using the step as a seed. Depositing a single-crystal semiconductor layer such as a single-crystal silicon layer; and performing a predetermined process on the single-crystal semiconductor layer to form at least an active element of an active element and a passive element. Toss , A method of manufacturing an electro-optical device. 2. a step of subjecting the single-crystal silicon layer to predetermined processing after the deposition of the single-crystal silicon layer to form a channel region, a source region, and a drain region; and forming a gate portion above the channel region. Forming a first thin film transistor of a top gate type which forms at least a part of the peripheral drive circuit section. 3. The step is formed as a concave part whose side surface is perpendicular to the bottom surface or inclined toward the lower end in the cross section, and this step is used as a seed during the grapho-epitaxial growth of the single crystal silicon layer. A method for manufacturing the electro-optical device according to claim 1. Drive substrate for electro-optical devices. 4. The electro-optical device according to claim 1, wherein a melt of the low-melting-point metal containing silicon is applied to the heated first substrate, held for a predetermined time, and then subjected to the cooling process. Manufacturing method. 5. A glass substrate is used as the first substrate, and the low melting point metal is at least one selected from the group consisting of indium, gallium, tin, bismuth, lead, zinc, antimony and aluminum. A method for manufacturing the electro-optical device according to claim 1. 6. When indium is used as the low melting point metal, the molten liquid layer is applied to the first substrate heated to 850 to 1100 ° C., and indium / gallium or gallium is used as the low melting point metal. Sometimes the melt layer is heated to 300-1100 ° C. or 400-110.
6. The method according to claim 5, wherein the first substrate is heated to 0.degree.
2. The method for manufacturing an electro-optical device according to item 1. 7. The method for manufacturing an electro-optical device according to claim 1, wherein a diffusion barrier layer is formed on the first substrate, and a melt liquid layer of the low melting point metal is formed thereon. 8. The group 3 or 5 in the low melting point metal melt layer.
The method of manufacturing an electro-optical device according to claim 1, wherein an impurity element of a group III is mixed to control an impurity species and / or a concentration thereof in the single crystal silicon layer. 9. The electro-optical device according to claim 2, wherein the first thin film transistor is provided inside and / or outside a substrate recess formed by the step formed on the first substrate and / or a film thereon. Production method. 10. The electro-optical device according to claim 2, wherein the step is formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the first thin film transistor. Manufacturing method. 11. After the single-crystal silicon layer is deposited, an upper gate portion including a gate insulating film and a gate electrode is formed on the single-crystal silicon layer, and the upper gate portion is used as a mask to form the upper gate portion on the single-crystal silicon layer. The method for manufacturing an electro-optical device according to claim 2, wherein the channel region, the source region, and the drain region are formed by introducing a Group 3 or Group 5 impurity element. 12. In the peripheral driver circuit portion, in addition to the first thin film transistor, a polycrystalline or amorphous silicon layer is used as a channel region, and a top gate type, a bottom gate type or a bottom gate type having a gate portion above and / or below the channel region. Dual gate type thin film transistor or
The method for manufacturing an electro-optical device according to claim 2, wherein a diode, a resistor, a capacitance, an inductance element, or the like using the single-crystal silicon layer, the polycrystalline silicon layer, or the amorphous silicon layer is provided. 13. The method according to claim 2, wherein a switching element for switching the pixel electrode in the display unit is provided on the first substrate. 14. The first thin film transistor is at least a top gate type selected from a top gate type, a bottom gate type, or a dual gate type having a gate portion above and / or below a channel region, and
14. The method of manufacturing an electro-optical device according to claim 13, wherein a second thin film transistor of the top gate type, the bottom gate type, or the dual gate type is formed as the switching element. 15. When the second thin film transistor is a bottom gate type or a dual gate type, a lower gate electrode made of a heat resistant material is provided below the channel region, and a gate insulating film is formed on the gate electrode. 15. The method of manufacturing an electro-optical device according to claim 14, wherein after forming the lower gate portion, the second thin film transistor is formed through a process common to the first thin film transistor including the step of forming the step. . 16. The method according to claim 15, wherein the upper gate electrode of the second thin film transistor and the gate electrode of the first thin film transistor are formed of a common material. 17. After forming the single-crystal silicon layer on the lower gate portion, introducing a Group 3 or Group 5 impurity element into the single-crystal silicon layer to form source and drain regions, and then activate the single-crystal silicon layer. The method for manufacturing an electro-optical device according to claim 15, wherein the processing is performed. 18. The source and drain regions of the first and second thin film transistors are formed by ion implantation of the impurity element using a resist as a mask after the formation of the single crystal silicon layer, and the activation process is performed after the ion implantation. The method of manufacturing an electro-optical device according to claim 15, further comprising: forming a gate electrode of the first thin film transistor and, if necessary, an upper gate electrode of the second thin film transistor after forming the gate insulating film. 19. When the thin film transistor is a top gate type, after forming the single crystal silicon layer, each source and drain region of the first and second thin film transistors is formed by ion implantation of an impurity element using a resist as a mask, 15. The method of manufacturing an electro-optical device according to claim 14, wherein an activation process is performed after the ion implantation, and thereafter, each gate portion including a gate insulating film and a gate electrode of the first and second thin film transistors is formed. 20. When the thin film transistor is of a top gate type, after forming the single crystal silicon layer, each gate insulating film of the first and second thin film transistors and each gate electrode made of a heat-resistant material are formed. 15. The method of manufacturing an electro-optical device according to claim 14, wherein a gate portion is formed, each of the source and drain regions is formed by ion implantation of an impurity element using the gate portion as a mask, and an activation process is performed after the ion implantation. . 21. The method of manufacturing an electro-optical device according to claim 14, wherein an n-channel, p-channel, or complementary insulated gate field-effect transistor is configured as the thin film transistor of the peripheral driver circuit unit and the display unit. 22. The thin film transistor of the peripheral drive circuit portion is formed by a set of a complementary type and an n-channel type, a set of a complementary type and a p-channel type, or a set of a complementary type, an n-channel type and a p-channel type. The method for manufacturing an electro-optical device according to claim 21, wherein 23. At least a part of the thin film transistor of the peripheral drive circuit section and / or the display section is formed by an LDD (Li
(ghtly doped drain) structure, and the LDD structure is a single type having an LDD portion between a gate and a source or a drain, or a double type having an LDD portion between a gate and a source and a drain. 15. The method for manufacturing an electro-optical device according to 14. 24. The electro-optical device according to claim 23, wherein a resist mask used for forming the LDD structure is left, and ion implantation for forming a source region and a drain region is performed using a resist mask covering the resist mask. Device manufacturing method. 25. A step is formed on one surface of the first substrate, and a single crystal, polycrystal or amorphous silicon layer is formed on the substrate including the step, and the single crystal, polycrystal or amorphous silicon is formed. The method for manufacturing an electro-optical device according to claim 14, wherein the silicon layer is used as a channel region, a source region, and a drain region, and the second thin film transistor having a gate portion above and / or below the silicon layer is formed. 26. The step is formed as a concave portion whose side surface is perpendicular to the bottom surface or inclined toward the lower end in the cross section, and this step is used as a seed during the grapho-epitaxial growth of the single crystal silicon layer. A method for manufacturing the electro-optical device according to claim 25. 27. The method according to claim 25, wherein a source or drain electrode of the first and / or second thin film transistor is formed on a region including the step. 28. The electro-optical device according to claim 25, wherein the second thin film transistor is provided inside and / or outside a substrate recess formed by the step formed on the first substrate and / or a film thereon. Production method. 29. The method of manufacturing an electro-optical device according to claim 25, wherein the impurity species and / or concentration of Group 3 or Group 5 of the single crystal, polycrystal or amorphous silicon layer is controlled. 30. The electro-optical device according to claim 25, wherein the step is formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor. Production method. 31. The method of manufacturing an electro-optical device according to claim 25, wherein the gate electrode under the single crystal, polycrystal, or amorphous silicon layer has a trapezoidal shape at a side end thereof. 32. The method of manufacturing an electro-optical device according to claim 25, wherein a diffusion barrier layer is provided between the first substrate and the single crystal, polycrystal, or amorphous silicon layer. 33. The method according to claim 1, wherein a glass substrate or a heat-resistant organic substrate is used as the first substrate. 34. The method according to claim 1, wherein the first substrate is optically opaque or transparent. 35. The method according to claim 1, wherein the pixel electrode is provided for a reflective or transmissive display unit. 36. The method of manufacturing an electro-optical device according to claim 1, wherein a laminated structure of the pixel electrode and a color filter layer is provided in the display unit. 37. When the pixel electrode is a reflective electrode, an unevenness is formed on a resin film, and a pixel electrode is provided thereon.
2. The method according to claim 1, wherein when the pixel electrode is a transparent electrode, the surface is flattened by a transparent flattening film, and the pixel electrode is provided on the flattened surface. 38. The method of manufacturing an electro-optical device according to claim 13, wherein the display section is configured to emit light or modulate light by being driven by the switching element. 39. The method according to claim 13, wherein a plurality of the pixel electrodes are arranged in a matrix on the display unit, and the switching element is connected to each of the pixel electrodes. 40. A liquid crystal display device, an electroluminescence device, a field emission display device, a light emitting polymer display device,
2. The light emitting diode display device is manufactured as a light emitting diode display device.
2. The method for manufacturing an electro-optical device according to item 1. 41. A method of manufacturing a drive substrate for an electro-optical device, comprising: a display portion on which a pixel electrode is disposed; and a peripheral drive circuit portion disposed around the display portion on the substrate. Forming a step on the surface of the substrate; forming a molten liquid layer of a low melting point metal containing a semiconductor material such as silicon on the substrate including the step; and then cooling (preferably gradually cooling) A) subjecting the semiconductor material of the melt layer to grapho-epitaxial growth using the step as a seed to deposit a single-crystal semiconductor layer such as a single-crystal silicon layer; Forming at least an active element of the element and the passive element. 42. After depositing the single-crystal silicon layer, performing a predetermined process on the single-crystal silicon layer to form a channel region, a source region, and a drain region; and forming a gate portion above the channel region. Forming a first gate-gate-type first thin film transistor that forms at least a part of the peripheral drive circuit unit. 42. The method of manufacturing a drive substrate for an electro-optical device according to claim 41, further comprising: 43. The step is formed as a concave part whose side surface is perpendicular to the bottom surface or inclined toward the lower end in the cross section, and this step is used as a seed during the grapho-epitaxial growth of the single crystal silicon layer. A method for manufacturing a drive substrate for an electro-optical device according to claim 41. 44. The drive for an electro-optical device according to claim 41, wherein the cooling treatment is performed after applying a molten liquid of the low melting point metal containing silicon to the heated substrate and holding the substrate for a predetermined time. Substrate manufacturing method. 45. A glass substrate is used as the substrate,
42. The method according to claim 41, wherein the low melting point metal layer is at least one selected from the group consisting of indium, gallium, tin, bismuth, lead, zinc, antimony, and aluminum. . 46. When indium is used as said low melting point metal, said molten liquid layer is applied to said substrate heated to 850 to 1100 ° C., and when indium, gallium or gallium is used as said low melting point metal, said molten layer is melted. 300-1100 ° C or 400-1100 ° C for liquid layer
The method for manufacturing a drive substrate for an electro-optical device according to claim 46, wherein the method is applied to the substrate heated to a temperature. 47. A diffusion barrier layer is formed on the first substrate, and a melt layer of the low melting point metal is formed thereon.
A method for manufacturing a drive substrate for an electro-optical device according to claim 41. 48. An impurity element belonging to Group 3 or Group 5 in the molten liquid layer of the low melting point metal, thereby controlling the impurity species and / or the concentration of the impurity in the single crystal silicon layer.
A method for manufacturing a drive substrate for an electro-optical device according to claim 41. 49. The driving substrate for an electro-optical device according to claim 42, wherein the first thin film transistor is provided inside and / or outside a substrate recess formed by the step formed on the substrate and / or a film thereon. Manufacturing method. 50. The electro-optical device according to claim 42, wherein the step is formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the first thin film transistor. Of manufacturing a driving substrate for a semiconductor device. 51. After the deposition of the single-crystal silicon layer, an upper gate portion including a gate insulating film and a gate electrode is formed on the single-crystal silicon layer, and the upper gate portion is used as a mask to form the upper gate portion on the single-crystal silicon layer. 43. The method of manufacturing a driving substrate for an electro-optical device according to claim 42, wherein the channel region, the source region, and the drain region are formed by introducing a Group 3 or Group 5 impurity element. 52. In the peripheral driver circuit portion, in addition to the first thin film transistor, a polycrystalline or amorphous silicon layer is used as a channel region, and a top gate type, a bottom gate type or a bottom gate type having a gate portion above and / or below the channel region. Dual gate type thin film transistor or
43. A diode, a resistor, a capacitance, an inductance element, or the like using the single crystal silicon layer, the polycrystal silicon layer, or the amorphous silicon layer is provided.
3. A method for manufacturing a drive substrate for an electro-optical device according to claim 1. 53. The method according to claim 42, wherein a switching element for switching the pixel electrode in the display unit is provided on the substrate. 54. The first thin film transistor is at least a top gate type selected from a top gate type, a bottom gate type, or a dual gate type having a gate portion above and / or below a channel region; and
The method for manufacturing a driving substrate for an electro-optical device according to claim 53, wherein the top gate type, the bottom gate type, or the dual gate type second thin film transistor is formed as the switching element. 55. When the second thin film transistor is a bottom gate type or a dual gate type, a lower gate electrode made of a heat resistant material is provided below the channel region, and a gate insulating film is formed on the gate electrode. 55. The drive for an electro-optical device according to claim 54, wherein after forming the lower gate portion, the second thin film transistor is formed through steps common to the first thin film transistor including the step of forming the step. Substrate manufacturing method. 56. The method of manufacturing a driving substrate for an electro-optical device according to claim 55, wherein an upper gate electrode of the second thin film transistor and a gate electrode of the first thin film transistor are formed of a common material. 57. After forming the single crystal silicon layer on the lower gate portion, introducing a Group 3 or Group 5 impurity element into the single crystal silicon layer to form source and drain regions, The method for manufacturing a drive substrate for an electro-optical device according to claim 55, wherein the process is performed. 58. After the formation of the single-crystal silicon layer, the source and drain regions of the first and second thin film transistors are formed by ion implantation of the impurity element using a resist as a mask, and after the ion implantation, the activation process is performed. 58. The driving substrate for an electro-optical device according to claim 57, wherein after forming a gate insulating film, a gate electrode of the first thin film transistor and, if necessary, an upper gate electrode of the second thin film transistor are formed. Manufacturing method. 59. When the thin film transistor is a top gate type, after forming the single crystal silicon layer, each source and drain region of the first and second thin film transistors is formed by ion implantation of an impurity element using a resist as a mask, 55. The driving substrate for an electro-optical device according to claim 54, wherein an activation process is performed after the ion implantation, and thereafter, each gate portion including a gate insulating film and a gate electrode of the first and second thin film transistors is formed. Manufacturing method. 60. When the thin film transistor is a top gate type, after forming the single crystal silicon layer, a gate insulating film of the first and second thin film transistors and a gate electrode made of a heat resistant material are formed to form each gate portion. To form
55. The method of manufacturing a driving substrate for an electro-optical device according to claim 54, wherein the source and drain regions are formed by ion implantation of an impurity element using these gate portions as a mask, and an activation process is performed after the ion implantation. 61. The driving substrate for an electro-optical device according to claim 54, wherein an n-channel type, a p-channel type, or a complementary type insulated gate field effect transistor is formed as the thin film transistor of the peripheral driving circuit portion and the display portion. Manufacturing method. 62. The thin film transistor of the peripheral drive circuit portion is formed of a set of a complementary type and an n-channel type, a set of a complementary type and a p-channel type, or a set of a complementary type, an n-channel type and a p-channel type. 62. The method for manufacturing a drive substrate for an electro-optical device according to claim 61. 63. At least a part of the thin film transistor of the peripheral driving circuit section and / or the display section is formed by an LDD (Li
(ghtly doped drain) structure, and the LDD structure is a single type having an LDD portion between a gate and a source or a drain, or a double type having an LDD portion between a gate and a source and a drain. 54. The method for manufacturing a drive substrate for an electro-optical device according to 54. 64. The electro-optical device according to claim 63, wherein a resist mask used for forming the LDD structure is left, and ion implantation for forming a source region and a drain region is performed using a resist mask covering the resist mask. A method for manufacturing a drive substrate for an apparatus. 65. A step is formed on one surface of the substrate, a single crystal, polycrystal or amorphous silicon layer is formed on the substrate including the step, and the single crystal, polycrystal or amorphous silicon layer is formed. 55. The method for manufacturing a driving substrate for an electro-optical device according to claim 54, wherein the second thin film transistor having a channel portion, a source region, and a drain region and having a gate portion above and / or below the second thin film transistor is formed. 66. The step is formed as a recess whose side surface is perpendicular to the bottom surface or inclined toward the lower end in the cross section, and the step is used as a seed during the graphoepitaxial growth of the single crystal silicon layer. A method for manufacturing a drive substrate for an electro-optical device according to claim 65. 67. The method according to claim 65, wherein a source or drain electrode of the first and / or second thin film transistor is formed on a region including the step. 68. The driving substrate for an electro-optical device according to claim 65, wherein the second thin film transistor is provided inside and / or outside of a substrate recess formed by the step formed on the substrate and / or a film thereon. Manufacturing method. 69. The method for manufacturing a driving substrate for an electro-optical device according to claim 65, wherein the impurity species and / or the concentration of Group 3 or Group 5 of the single crystal, polycrystal or amorphous silicon layer is controlled. 70. The electro-optical device according to claim 65, wherein the step is formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor. Method for manufacturing a drive substrate. 71. The method of manufacturing a driving substrate for an electro-optical device according to claim 65, wherein the gate electrode under the single crystal, polycrystal or amorphous silicon layer has a trapezoidal shape at a side end thereof. 72. A diffusion barrier layer is provided between the substrate and the single crystal, polycrystalline or amorphous silicon layer.
A method for manufacturing a drive substrate for an electro-optical device according to claim 65. 73. The method according to claim 41, wherein a glass substrate or a heat-resistant organic substrate is used as the substrate. 74. The method according to claim 41, wherein the substrate is optically opaque or transparent. 75. The method of manufacturing a driving substrate for an electro-optical device according to claim 41, wherein the pixel electrode is provided for a reflective or transmissive display unit. 76. The method according to claim 41, wherein a laminated structure of the pixel electrode and the color filter layer is provided in the display unit. 77. When the pixel electrode is a reflective electrode, unevenness is formed on a resin film, and a pixel electrode is provided thereon,
42. The method according to claim 41, wherein when the pixel electrode is a transparent electrode, the surface is flattened by a transparent flattening film, and the pixel electrode is provided on the flattened surface. . 78. The method of manufacturing a driving substrate for an electro-optical device according to claim 53, wherein the display section is configured to emit light or adjust light by being driven by the switching element. 79. The manufacturing of a driving substrate for an electro-optical device according to claim 53, wherein the plurality of pixel electrodes are arranged in a matrix on the display section, and the switching element is connected to each of the pixel electrodes. Method. 80. A liquid crystal display device, an electroluminescence device, a field emission display device, a light emitting polymer display device,
42. The method for manufacturing a drive substrate for an electro-optical device according to claim 41, wherein the method is used for a light emitting diode display device.