JP2000155334A - Electro-optic device, drive substrate for electro-optic device and their production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a process for producing an active matrix substrate containing a high-performance driver by uniformly depositing a single crystal silicon thin film having high electron/positive hole mobility at relatively low temperature and an electro-optic device, such as thin-film semiconductor device for display using the same. SOLUTION: A material layer 50 having good lattice matching with a single crystal semiconductor on one main surface of a first substrate 1 and a semiconductor is deposited on the material layer 50. The semiconductor film is subjected to a irradiation treatment with a laser, by which a single crystal semiconductor layer 7 is heteroepitaxially grown with the material layer 50 as a seed. At least active elements among the active elements and passive elements are formed by subjecting the single crystal semiconductor layer 7 to a prescribed treatment.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electro-optical device, a driving substrate for the electro-optical device, and a method for manufacturing the same, and more particularly, to using a single crystal silicon layer heteroepitaxially grown on an insulating substrate for an active region. The present invention relates to a structure having a top-gate thin-film insulated-gate field-effect transistor (hereinafter, referred to as a top-gate MOSTFT; a top-gate type includes a staggered type and a coplanar type) and a manufacturing method thereof.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device has a display portion using amorphous silicon for a TFT and an external driving circuit IC, and a display using a polycrystalline silicon for a TFT by a solid phase growth method. (Japanese Unexamined Patent Publication (Kokai) No. 6-242433), and an integrated type of a display unit and a drive circuit using excimer laser-annealed polycrystalline silicon for a TFT (Japanese Unexamined Patent Publication No. 7-131)
030) is known.

[0003]

However, in the above-mentioned conventional amorphous silicon TFT, although the productivity is good, the electron mobility is as low as about 0.5 to 1.0 cm ² / v · sec. (Hereafter, pM
It is called OSFT. ) Can not be made. Therefore, this pMOST is formed on the same glass substrate as the display unit.
Since a peripheral drive unit using FT cannot be formed, and a driver IC is mounted externally and mounted by a TAB method or the like, cost reduction is difficult, and there is a limit to high definition. is there. Furthermore, electron mobility is 0.5-1.
Since it is as low as about 0 cm ² / v · sec, sufficient on-current cannot be obtained, and the transistor size is inevitably increased when used in a display portion, which is disadvantageous for increasing the pixel aperture ratio. I have.

Further, the conventional polycrystalline silicon TF described above is used.
At T, the electron mobility is 70 to 100 cm ² / v · s
ec, which can cope with high definition. Therefore, recently, an LCD using a polycrystalline silicon TFT integrated with a driving circuit has been developed.
(Liquid crystal display devices) are attracting attention. However, 1
In the case of a large LCD of 5 inches or more, since the electron mobility of polycrystalline silicon is 70 to 100 cm ² / v · sec, the driving capability is insufficient, and eventually, an external driving circuit IC is required. ing.

In a TFT using polycrystalline silicon formed by a solid phase growth method, annealing is performed at a temperature of 600 ° C. or more for more than 10 hours, and a gate Si is formed by thermal oxidation at about 1000 ° C.
Since O ₂ needs to be formed, a dedicated semiconductor manufacturing apparatus must be used. Therefore, the wafer size is 8
Since the diameter is limited to 12 inches φ, high-heat-resistant and expensive quartz glass must be adopted, and it is difficult to reduce the cost. Therefore, the obtained product is currently EV
F and data / AV projector applications.

Further, in the above-described conventional polycrystalline silicon TFT by excimer laser annealing, stability of excimer laser output, increase in apparatus price due to increase in size, increase in yield /
Problems such as quality deterioration are piled up.

[0007] In particular, when a large glass substrate of 1 m square or the like is used, the above-mentioned problems are magnified, and it becomes more difficult to improve performance / quality and reduce costs.

An object of the present invention is to provide an active matrix substrate with a built-in high-performance driver by forming a single-crystal silicon thin film having a high electron / hole mobility at a relatively low temperature and uniformly, particularly in a peripheral driving circuit portion. Enables the manufacture of electro-optical devices such as display thin film semiconductor devices using the same, and has an LDD structure (Li
ghtly doped drain structure) n-channel MOSTF
T (hereinafter referred to as nMOSTFT) or pMOS
TFT or complementary thin-film insulated gate field-effect transistor with high driving capability (hereinafter referred to as cMOSTFT)
And a peripheral drive circuit composed of this cMOSTFT, nMOSTFT, or pMOSTFT, or a mixture of these, enabling a high-quality, high-definition, narrow frame, high-efficiency, large-screen display panel. It can be used even with a large glass substrate having a relatively low strain point, has high productivity, does not require expensive manufacturing equipment, enables cost reduction, and has a threshold adjustment. An object of the present invention is to enable high-speed operation and a large screen by low resistance.

[0009]

According to the present invention, a pixel electrode (for example, a plurality of pixel electrodes arranged in a matrix: the same applies hereinafter) and a peripheral drive circuit portion disposed around the display portion are provided as first components. An electro-optical device in which a predetermined optical material such as a liquid crystal is interposed between the first substrate and the driving substrate for the electro-optical device, and a driving substrate for the electro-optical device. A material layer having good lattice matching with a single crystal semiconductor (eg, single crystal silicon) is formed over one surface, and a semiconductor (eg, a semiconductor layer) formed over the material layer is formed over the first substrate including the material layer. A film made of silicon) is heated and melted by a laser irradiation treatment, and then cooled and solidified, whereby a single crystal semiconductor layer (for example, a single crystal silicon layer) formed by heteroepitaxial growth using the material layer as a seed. Con) is formed, the single crystal semiconductor layer is said solutions to problems that constitutes at least the active element of the active and passive components.

In the present invention, the concept of a single crystal semiconductor includes not only single crystal silicon but also a single crystal compound semiconductor such as single crystal gallium arsenide (Ga.As) and single crystal silicon germanium (Si.Ge). (The same applies hereinafter). Further, in the present invention, a single crystal is a concept including a single crystal containing sub-grain boundaries and dislocations (the same applies hereinafter). The active element is a concept including a thin film transistor or another element such as a diode, and the passive element is a concept including a resistance, an inductance, a capacitor, and the like (the same applies hereinafter).

A typical example of such a thin film transistor is a field effect transistor (FET) (which includes an MO transistor).
There are S type and junction type, but either type is acceptable. ) And bipolar transistors, but the present invention can be applied to any of the transistors (the same applies hereinafter). More specifically, as the passive element, silicon nitride (hereinafter referred to as Si) is formed by using the single-crystal silicon layer or the like (electrode) having a reduced resistance.
Called N. ), Etc., formed by sandwiching a high dielectric film.

Further, according to the present invention, in the method for manufacturing the electro-optical device and the driving substrate therefor, a material layer having good lattice matching with a single crystal semiconductor (for example, single crystal silicon) is formed on one surface of the first substrate. Forming a semiconductor (for example, silicon) on the material layer; and subjecting the film made of the semiconductor to a laser irradiation treatment to heat and melt the film, and then solidify the material by cooling. A step of heteroepitaxially growing a single-crystal semiconductor layer (for example, single-crystal silicon) using the layer as a seed, and a step of performing a predetermined process on the single-crystal semiconductor layer to form at least an active element of an active element and a passive element (for example, Forming a channel region, a source region, and a drain region by performing a predetermined process on the single crystal silicon layer after the deposition of the single crystal silicon layer Forming a gate portion including a gate insulating film and a gate electrode above the channel region, and further forming a source and drain electrode, and forming a first gate thin film transistor of at least a part of the peripheral driver circuit portion [ Particularly, a step of forming a passive element such as a resistor, a capacitance, an inductance, etc.).

According to the present invention, in particular, the material layer (for example, a crystalline sapphire film) having a good lattice matching with single crystal silicon
Is used as a seed, the semiconductor film formed on the material layer is heated and melted by laser irradiation treatment, and then cooled and solidified to form a single crystal semiconductor layer such as a single crystal silicon layer by heteroepitaxial growth. The top gate type MOSTFT of the peripheral drive circuit of the drive substrate such as the active matrix substrate and the display unit
Peripheral drive circuit In an electro-optical device such as an LCD integrated with a peripheral drive circuit, it is used as an active element such as a top gate type MOSTFT of the peripheral drive circuit and at least an active element among passive elements such as resistance, inductance, and capacitance. (A) to (G).

(A) A material layer (for example, a crystalline sapphire film) having good lattice matching with single crystal silicon is formed on a substrate,
By heteroepitaxially growing the material layer as a seed, a single crystal semiconductor layer such as a single crystal silicon layer having a high electron mobility of 540 cm ² / v · sec or more can be obtained. And the like can be manufactured.

(B) In particular, the single-crystal silicon layer has high electron and hole mobilities comparable to those of a single-crystal silicon substrate as compared with a conventional amorphous silicon layer or polycrystalline silicon layer. The top gate type MOSTFT has a high switching characteristic [preferably, an LDD which reduces the electric field strength to reduce the leakage current.
(Lightly doped drain) structure], a display portion comprising an nMOS, pMOSTFT or cMOSTFT;
High drive capability cMOS, nMOS or pMOSTF
A configuration integrated with a peripheral circuit composed of T or a mixture of them becomes possible, and a display panel with high image quality, high definition, narrow frame, high efficiency, and large screen is realized. In particular, polycrystalline silicon has a high hole mobility pM for LCD TFTs.
Although it is difficult to form an OSTFT, in the single-crystal silicon layer according to the present invention, since a hole shows a sufficiently high mobility, a peripheral driving circuit for driving electrons and holes individually or in combination of both. Can be produced, and this is referred to as LDD of nMOS or pMOS or cMOS.
A panel integrated with a display-use TFT having a structure can be realized. In the case of a small to medium-sized panel, there is a possibility that one of a pair of peripheral vertical drive circuits can be omitted.

(C) Since a single crystal semiconductor layer such as a single crystal silicon layer can be formed by using the aforementioned material layer as a seed for heteroepitaxial growth and subjecting the semiconductor film to laser irradiation treatment on this material layer. In addition, a single-crystal silicon layer or the like can be uniformly formed on a substrate at a low temperature. Therefore, a glass substrate having a relatively low strain point, a heat-resistant organic substrate, or the like can be easily obtained, a low-cost substrate having good physical properties can be used, and the substrate can be enlarged.

(D) Since annealing at a medium temperature for a long time (about 600 ° C., about ten and several hours) as in the case of the solid phase growth method is not required, productivity is high, and expensive manufacturing equipment is not required and cost is reduced. Becomes possible.

(E) In this heteroepitaxial growth, a wide range of P-type or P-type is adjusted by adjusting the crystallinity of the material layer such as crystalline sapphire, the irradiation energy and irradiation time of the laser, and the heating temperature and cooling rate of the substrate. Since an N-type conductivity type and a high-mobility single-crystal silicon layer can be easily obtained, Vth (threshold) adjustment becomes easy, and high-speed operation by lowering resistance becomes possible.

(F) A semiconductor (amorphous silicon or polycrystalline silicon) film on the material layer, or a single crystal semiconductor layer (single crystal silicon layer) obtained by subjecting the film to laser irradiation, is coated with an N-type or P-type film. Impurities (boron, phosphorus, antimony, arsenic, bismuth, aluminum, etc.) are mixed (introduced) into the single crystal semiconductor layer (single crystal silicon layer) and / or its concentration, that is, P-type / N The conductivity type such as the mold and / or the carrier concentration can be arbitrarily controlled.

(G) Since the material layer such as a crystalline sapphire film serves as a diffusion barrier for various atoms, diffusion of impurities from the glass substrate can be suppressed.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail.
In the present invention, a single crystal semiconductor layer, in particular, a single crystal silicon layer is subjected to a predetermined treatment to form a channel region, a source region, and a drain region, and further, a top-gate type having a gate portion above the channel region. It is preferable that one thin film transistor is formed and arranged so as to constitute at least a part of the peripheral drive circuit portion.

An insulating substrate is preferably used as the first substrate on which the first thin film transistor is formed. The material layer is made of sapphire (Al
₂ O ₃ ), a spinel structure (eg, MgO · Al
₂ O ₃ ), calcium fluoride (CaF ₂ ), strontium fluoride (SrF ₂ ), barium fluoride (Ba)
F ₂ ), boron phosphide (BP), yttrium oxide ((Y ₂ O ₃ ) _m ) and zirconium oxide ((Zr
It is preferably formed of a substance selected from the group consisting of O ₂ ) _1-m ) and the like.

The single crystal silicon layer can be formed by subjecting a semiconductor film made of amorphous silicon or polycrystalline silicon to laser irradiation using such a material as a seed. That is, the semiconductor layer is irradiated with a laser such as an argon laser or an excimer laser, heated and melted, and further cooled (preferably gradually cooled), so that the material layer (for example, sapphire crystal) is seeded. The semiconductor (silicon) can be heteroepitaxially grown to form a single crystal silicon layer (5 to 100 nm thick, preferably 30 to 50 nm thick). As the laser beam used for the laser irradiation process,
Line beam (for example, 275 × 0.3 to 0.4 mm ² )
And an area beam (for example, 100 × 100 mm ² ) can be used.

When a short-wavelength pal laser beam (for example, an excimer laser) is used for the laser irradiation process, the laser wavelength is 100 to 400 (nm), and the practical range is 150 to 350.
(Nm) (e.g., XeCl; 308 nm wavelength), and a pulse width of 100 nsec or less (preferably 10 to 50 nsec)
c), the peak intensity of the pulse is 10 ⁶ W / cm ² to 10 ⁸
W / cm ² , fluence (energy of one pulse) is 1 J / cm ² or less (preferably 50 mJ / cm 2
^{2 to} 500 mJ / cm ² , more preferably 200 mJ / cm ²
cm ^{2 to} 500 mJ / cm ² ). Then, it is preferable to irradiate such a short-wavelength pulsed laser beam with an overlap scanning of 95% or more.
As for the formation of the single crystal silicon layer by such a laser irradiation treatment, a method of locally irradiating a laser irradiation treatment only on a predetermined place, that is, only on a TFT forming region, instead of the whole, and epitaxially growing the same can be adopted. . When forming a single crystal silicon layer by such a laser irradiation process, the substrate temperature is set to 200 to 500.
It is preferred to heat to ° C.

In such laser irradiation processing, irradiation energy, irradiation time, irradiation and scanning method,
The melting state and the cooling state are affected by conditions such as the presence or absence of a low reflection film and the atmosphere (in a vacuum or an inert gas) at the time of irradiation, and silicon crystallinity (eg, electron / hole mobility, leak current, etc.) is affected. Therefore, it is necessary to determine conditions for obtaining the desired silicon crystallinity in advance by experiments and the like. Further, by mixing an N-type or P-type carrier impurity into a semiconductor film made of amorphous silicon or polycrystalline silicon in advance, the obtained single-crystal silicon layer contains an N-type or P-type carrier impurity at an arbitrary concentration. It can be formed into something.

In the present invention, as described above, an insulating substrate is suitably used as the substrate, and particularly, a glass substrate having a low strain point or a heat-resistant organic substrate is used. Therefore, a single crystal silicon layer can be formed over a large glass substrate (for example, 1 m ² or more), and the substrate temperature when forming the single crystal silicon layer by laser irradiation treatment is 200 to 500 ° C. as described above. Since the glass substrate can be kept at a low temperature of about 470 to 670 ° C.
And low glass can be used. Such a substrate is inexpensive, easily thinned, and can be manufactured on a long rolled substrate. Therefore, a single-crystal silicon layer formed by heteroepitaxial growth can be continuously or discontinuously formed on such a long rolled glass plate or a heat-resistant organic substrate by the above method.

Since the constituent elements are easily diffused from the inside of the glass into the upper layer of the glass having a low strain point, a diffusion barrier layer such as silicon nitride (SiN) is used for the purpose of suppressing the diffusion. Membrane (thickness eg 50-
(About 200 nm) is preferable.

As a method of forming a semiconductor (for example, amorphous silicon or polycrystalline silicon) on the material layer, a known method such as a sputtering method or a plasma CVD method can be adopted. By adding an N-type or P-type carrier impurity such as, for example, or mixing a doping gas such as PH ₃ or B ₂ H ₆ into the supply gas, the single-crystal silicon layer can be converted into an N-type or P-type. can do. If the single crystal silicon layer is made N-type or P-type in this way, the nMOSTFT or p-type
The fabrication of the MOSTFT can be facilitated, and the fabrication of the cMOSTFT can also be facilitated.

As described above, a single-crystal silicon layer formed by heteroepitaxial growth on a substrate is replaced with a top-gate MOST constituting at least a part of a peripheral drive circuit.
By forming the channel region, the source region, and the drain region of the FT as a formation layer, the impurity species in each of these regions and / or the concentration thereof can be controlled.

The thin film transistors of the peripheral driver circuit section and the display section constitute an n-channel, p-channel or complementary insulated gate field-effect transistor. For example, a pair of a complementary type and an n-channel type, and a complementary type. It is composed of a set of a p-channel type or a set of a complementary type, an n-channel type and a p-channel type. In addition, at least a part of the thin film transistor of the peripheral driver circuit unit and / or the display unit has L
It preferably has a DD (Lightly doped drain) structure. Note that the LDD structure may be provided not only between the gate and the drain but also between the gate and the source or between the gate and the source and between the gate and the drain (this is referred to as a double LDD).

Particularly, regarding the MOSTFT, an nMOS, pMOS or cMOS LD
A D-type TFT is formed, and cM
It is preferable to configure OS, nMOS, pMOSTFT, or a state in which these are mixed.

In the present invention, a step is provided on the substrate and / or the film thereon, and the step is formed together with the material layer.
It may be used as a seed during epitaxial growth of a single crystal silicon layer (single crystal semiconductor layer). Here, the step may be a concave portion such that the side surface is perpendicular to the bottom surface in a cross-sectional view, or is inclined (preferably) forms a base angle of 90 ° or less toward the lower end side. SiN
Etc. (or both of them). Also,
The step is preferably formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the active element, for example, the thin film transistor. Further, the passive element, for example, the element may be formed along at least one side of an element region where a resistor is formed.

In this case, the step as a seed for epitaxial growth may be formed at a predetermined position on the insulating substrate as the substrate, and the material layer may be formed on the insulating substrate including the step. Alternatively, the step may be formed in the material layer, and the single crystal silicon layer (single crystal semiconductor layer) may be formed over the material layer including the step. In any case, in addition to the material layer serving as a seed for normal heteroepitaxial growth in which crystal growth is performed while inheriting the crystal orientation of the base, the step is formed by crystal growth in accordance with the shape of the base. Since it acts as a seed, a single crystal silicon layer with higher crystallinity can be formed.

The first thin film transistor comprising the MOSTFT or the like may be provided in the concave portion of the substrate formed by the step, but may be provided outside the concave portion located near the concave portion, or both inside the concave portion and outside the concave portion. Good. The step can be formed by dry etching such as reactive ion etching.

In this case, the step is formed on one surface of the first substrate, and a single-crystal silicon layer, a polycrystalline silicon layer, or an amorphous silicon layer is formed on the substrate including the step. . And a channel region of the second thin film transistor from such a silicon layer;
Forming a source region and a drain region, respectively, having a gate portion above and / or below the channel region;
A top-gate, bottom-gate, or dual-gate thin film transistor may be formed.

Also in this case, the side surface is perpendicular to the bottom surface in a cross-sectional view, or 90 ° (preferably) to the lower end side.
The step similar to that described above may be formed as a concave part having an inclined shape having the following base angle, and this step may be used as a seed during epitaxial growth of the single crystal silicon layer.

With respect to the second thin film transistor,
The first substrate and / or the film formed thereon is provided inside and / or outside of the substrate recessed portion due to the step, and is formed by grapho-epitaxial growth similarly to the first thin film transistor.
Furthermore, the source, drain, and channel regions can be formed using a single crystal silicon layer formed by heteroepitaxial growth.

The second thin film transistor also
As in the case described above, the N-type or P-type impurity species and / or the concentration thereof can be controlled by mixing N-type or P-type during the formation of the single-crystal, polycrystalline, or amorphous silicon layer. it can. Further, the step may be formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor.

Further, it is preferable that a gate electrode under the single crystal, polycrystal or amorphous silicon layer is trapezoidal at a side end thereof, and that the first substrate and the single crystal or polycrystal are formed. Alternatively, it is preferable to provide a diffusion barrier layer between the diffusion barrier layer and the amorphous silicon layer. A source or drain electrode of the first and / or second thin film transistor;
Preferably, it is formed on a region including the step.

It is preferable that the first thin film transistor is of a top gate type, a bottom gate type or a dual gate type having a gate portion above and / or below a channel region. Further, a switching element for switching a pixel electrode in the display unit is
It is preferable that the second thin film transistor be any of the top gate type, the bottom gate type, and the dual gate type.

In this case, the gate electrode provided below the channel region is formed of a heat-resistant material, or the upper gate electrode of the second thin film transistor and the gate electrode of the first thin film transistor are formed of a common material. can do.

In the peripheral drive circuit section, in addition to the first thin film transistor, a polycrystalline or amorphous silicon layer is used as a channel region, and a top gate type and a bottom gate type having a gate portion above and / or below the channel region. Or a dual-gate thin film transistor,
Alternatively, a diode using the single crystal silicon layer or the polycrystalline silicon layer or the amorphous silicon layer, a resistor,
A capacitance, an inductance element, or the like may be provided.

The peripheral driver circuit section and / or the thin film transistor of the display section may be configured as a single gate or a multi-gate. When the n-channel or p-channel thin film transistor of the peripheral driver circuit portion and / or the display portion is a dual gate type, the upper or lower gate electrode is electrically open or an arbitrary negative voltage (n channel Type) or a positive voltage (p-channel type). It is preferable to operate as a bottom-gate or top-gate thin film transistor.

The thin film transistor of the peripheral drive circuit section is the n-channel, p-channel or complementary first thin film transistor. The thin film transistor of the display portion is an n-channel type, a p-channel type, or a complementary type, regardless of whether a single crystal silicon layer, a polycrystalline silicon layer, or an amorphous silicon layer is used as a channel region.

In the present invention, after the growth of the single crystal silicon layer, an upper gate portion including a gate insulating film and a gate electrode is formed on the single crystal silicon layer, and the upper gate portion is used as a mask to form the single crystal silicon layer. The channel region, the source region, and the drain region may be formed by introducing an impurity element belonging to Group 3 or Group 5 of the periodic table, that is, an N-type or P-type impurity into the layer.

When the second thin film transistor is a bottom gate type or a dual gate type, a lower gate electrode made of a heat resistant material is provided below the channel region, and a gate insulating film is formed on the gate electrode. After forming the lower gate portion, the second thin film transistor can be formed through steps common to the first thin film transistor including the step of forming the step. In this case, the upper gate electrode of the second thin film transistor and the gate electrode of the first thin film transistor may be formed of a common material.

After forming the single-crystal silicon layer on the lower gate portion, an impurity element of Group 3 or 5 of the periodic table is introduced into the single-crystal silicon layer to form source and drain regions. After that, an activation process can be performed.

After the formation of the single crystal silicon layer, the source and drain regions of the first and second thin film transistors are formed by ion-implanting an impurity element using a resist as a mask. After forming the gate insulating film, the gate electrode of the first thin film transistor and, if necessary, the upper gate structure of the second thin film transistor may be formed.

When the thin film transistor is a top gate type, after forming the single crystal silicon layer, each source and drain region of the first and second thin film transistors is formed by ion-implanting an impurity element using a resist as a mask. And then perform activation after ion implantation,
Thereafter, each gate portion including the gate insulating film and the gate electrode of the first and second thin film transistors may be formed.

Alternatively, when the thin film transistor is a top gate, after forming the single crystal silicon layer, each gate insulating film of the first and second thin film transistors and each gate electrode made of a heat-resistant material are formed. A gate portion may be formed, and the source and drain regions may be formed by ion-implanting an impurity element using these gate portions as a mask, and an activation process may be performed after the ion implantation.

Alternatively, ion implantation for forming a source region and a drain region may be performed using a resist mask that covers the resist mask used in forming the LDD structure. Further, the substrate may be made optically opaque or transparent, and a reflective or transmissive display pixel electrode may be provided.

When the display section has a laminated structure of the pixel electrode and the color filter layer, the color filter is formed on the display array section to improve the aperture ratio and brightness of the display panel. In addition, the cost can be reduced by omitting the color filter substrate and improving the productivity.

In this case, when the pixel electrode is a reflective electrode, irregularities are formed on the resin film to obtain optimum reflection characteristics and viewing angle characteristics, the pixel electrode is provided thereon, and the pixel electrode is transparent. When it is an electrode, it is preferable to flatten the surface with a transparent flattening film, and to provide a pixel electrode on this flattened surface.

The display section is configured to emit light or modulate light by being driven by the MOSTFT. For example, a liquid crystal display (LCD), an electroluminescence display (E)
L), field emission display (FED), light emitting polymer display (LEPD), light emitting diode display (LE
D) or the like. In this case, a plurality of the pixel electrodes may be arranged in a matrix on the display unit, and the switching element may be connected to each of the pixel electrodes.

A control unit for controlling the operation of the peripheral drive circuit unit and / or the display unit may be provided on the first substrate. This control unit is formed by a CPU (including a microprocessor), a memory (SRAM, DRAM, flash), or a system LSI including a combination of these. In the case where such a control unit is provided on the first substrate, a predetermined process is performed on the single-crystal semiconductor layer, and an element for forming the control unit, for example, a CMOS.
Active elements such as TFT, nMOSTFT, and pMOSTFT, and passive elements such as resistors, capacitors, and inductances are formed. Note that such a control unit may be formed in the same region as a vertical drive circuit or a horizontal drive circuit serving as a peripheral drive circuit unit, or may be formed in another region.

Next, a preferred embodiment of the present invention will be described in more detail. <First Embodiment> A first embodiment of the present invention will be described with reference to FIGS.

In the embodiment of the present invention, the material layer (for example, a crystalline sapphire film) is formed on the surface including the above-mentioned steps (concave portions) provided on the heat-resistant substrate, and this material layer is used as a seed. The silicon film (semiconductor film) formed on this material layer is heated and melted by laser irradiation treatment, and then cooled and solidified, whereby a single crystal silicon layer (single crystal semiconductor layer) is heteroepitaxially grown. The present invention relates to an active matrix reflective liquid crystal display (LCD) having a MOSTFT.

First, the overall layout of the reflection type LCD will be described with reference to FIGS. As shown in FIG. 9, the active matrix reflection type LCD has a main substrate 1
(This forms an active matrix substrate, that is, a driving substrate) and a counter substrate 32 are spacers (not shown).
A liquid crystal (not shown) is provided between the main substrate 1 and the opposing substrate 32.
Is enclosed. On the surface of the main substrate 1, a display unit including pixel electrodes 29 (or 41) arranged in a matrix, a switching element for driving the pixel electrodes, and a peripheral drive circuit unit connected to the display unit are provided. Is provided.

The switching element of the display section is an nMOS, pMOS or cMOS according to the present invention, and is formed of a top gate type MOSTFT having an LDD structure. Also, in the peripheral drive circuit section, as a circuit element, a cMOS or nMO of a top gate type MOSTFT according to the present invention is used.
The S or p MOSTFTs are each formed as a single type or in a mixed state.

The one peripheral drive circuit section is a horizontal drive circuit that supplies a data signal and drives the TFT of each pixel for each horizontal line. Also, the other peripheral drive circuit section
This is a vertical drive circuit that drives the gate of the TFT of each pixel for each scanning line, and is usually provided on both sides of the display unit. In this example, these drive circuits can be configured in either a dot-sequential analog system or a line-sequential digital system.

As shown in FIG. 10, the above-mentioned TFT is arranged at the intersection of the gate bus line and the data bus line which are orthogonal to each other. Image information is written to the liquid crystal capacitor (C _LC ) via this TFT, and the next information Holds electric charge until comes. In this case, it is not enough to hold the channel resistance of the TFT alone. To compensate for this, a storage capacitor (auxiliary capacitor) (C _S ) is added in parallel with the liquid crystal capacitor to compensate for a decrease in the liquid crystal voltage due to leak current. To do.

In such an LCD TFT, the required performance is different between the characteristics of the TFT used for the pixel portion (display portion) and the characteristics of the TFT used for the peripheral driving circuit. Securing current is an important issue. For this reason, as described later, the display unit
By providing a TFT having a D structure, a structure in which an electric field is hardly applied between a gate and a drain is provided, an effective electric field applied to a channel region is reduced, an off current is reduced, and a change in characteristics is reduced. However, in order to obtain such a configuration, there are problems in that the process becomes complicated, the element size increases, and the off-state current decreases. Therefore, it is necessary to optimize the design according to the intended use. is there.

Usable liquid crystals include TN liquid crystal (nematic liquid crystal used in the TN mode of active matrix drive), STN (super twisted nematic), GH (guest host), PC (phase change). , FLC (ferroelectric liquid crystal), AFL
Liquid crystals for various modes such as C (antiferroelectric liquid crystal) and PDLC (polymer dispersed liquid crystal) can be used.

Next, the circuit system of the peripheral drive circuit unit and the outline of the drive system will be described with reference to FIG. The drive circuit is divided into a gate-side drive circuit and a data-side drive circuit, and it is necessary to form a shift register on both the gate side and the data side. As the shift register, pMOSTF
Although there are those using both T and nMOSTFT (so-called CMOS circuit) and those using only one of the MOSTFTs, cMOSTFT or CMOS circuits are generally used in terms of operation speed, reliability, and low power consumption. It is a target.

The scanning drive circuit is composed of a shift register and a buffer, and sends a pulse synchronized with the horizontal scanning period to each line from the shift register. On the other hand, the data-side driving circuit has two driving methods, a dot sequential method and a line sequential method. In the dot sequential method shown in FIG. 11, the circuit configuration is relatively simple, and the display signal is directly written to each pixel sequentially within one horizontal scanning time while the display signal is controlled by a shift register through an analog switch. (R,
G and B schematically show pixels for each color).

Next, an active matrix reflective LCD according to the present embodiment will be described based on a manufacturing method (process) thereof with reference to FIGS. In FIGS. 1 to 5, the left side of each drawing shows the manufacturing method (step) of the display unit, and the right side shows the manufacturing method (step) of the peripheral circuit unit.

First, as shown in FIG. 1A, on one main surface of an insulating substrate 1 made of borosilicate glass, quartz glass, transparent crystallized glass or the like, a photoresist 2 is formed at least in a TFT forming region. The substrate 1 is formed into a predetermined pattern, and the substrate 1 is formed into an appropriate shape and dimensions by general-purpose photolithography and etching (photoetching), such as performing reactive ion etching (RIE) using F ⁺ ions 3 of CF ₄ plasma using the mask as a mask. A plurality of steps 4 are formed.

In this case, quartz glass is used as the insulating substrate 1,
Transparent crystal glass, ceramics, etc. (However, an opaque ceramic substrate or a low-transparency crystallized glass cannot be used in a transmission type LCD described later) (8).
１２12 inches φ, 700-800 μm thick) can be used. The step 4 serves as a seed at the time of epitaxial growth of single crystal silicon, which will be described later, and has a depth d of about 0.1 μm, a width w of about 5 to 10 μm, and a length (in a direction perpendicular to the paper surface) of about 10 to 20 μm. The angle between the bottom surface and the side surface (base angle) is substantially a right angle. The substrate 1
In particular, when the substrate 1 is formed of a glass substrate, a SiN film is formed in advance to a thickness of, for example, about 50 to 200 nm in order to prevent diffusion of Na ions and the like from the substrate 1 itself, If necessary, a silicon oxide film (hereinafter S
It is called an iO ₂ film. Is preferably formed to a thickness of, for example, about 100 nm.

Next, as shown in FIG. 1B, after the photoresist 2 is removed, one main surface of the insulating substrate 1 is removed.
A crystalline sapphire film 50 is formed in the TFT forming region including the step 4.
Is formed to a thickness of about 20 to 200 nm. This crystalline sapphire film 50 is formed by high-density plasma CVD or catalyst C.
It is manufactured by oxidizing trimethylaluminum gas or the like with an oxidizing gas (oxygen / moisture) and crystallizing it by a VD method (see JP-A-63-40314). Since the crystalline sapphire film 50 has a function of a Na ion stopper, the formation of the SiN film and the SiO ₂ film can be omitted when the film thickness is sufficiently hot.

Next, amorphous silicon or polycrystalline silicon is removed by sputtering or plasma CVD.
A silicon film (not shown) is formed to a thickness of about 100 nm, preferably about 30 to 70 nm. At this time, the target is a single crystal silicon doped with an appropriate amount (for example, 0.1 to 1.0 ppm) of N-type or P-type carrier impurities, for example, phosphorus or boron, and sputtering is performed using the target to obtain the type of the carrier impurities. And / or a silicon film whose concentration is adjusted may be formed. In plasma CVD, an appropriate amount (for example, 0.1 to 1.0 ppm) of N ₃ type PH ₃ or AsH ₃ is mixed into a monosilane or disilane gas or the like, or an appropriate amount of B ₂ H ₆ (for example, P type) is used. (0.1 to 1.0 ppm), a silicon film in which the type and / or concentration of carrier impurities is adjusted may be formed.

Subsequently, the silicon film is irradiated with a laser beam to heat and melt the film, and then cooled (slowly cooled) to be solidified, so that the crystalline sapphire thin film 50 and the step 4 are both used as seeds for heteroatomizing silicon. By epitaxial growth, a single-crystal silicon layer 7 is formed on the entire surface including the step 4 to a thickness of about 5 to 100 nm, preferably about 30 to 50 nm, as shown in FIG.

As the laser irradiation treatment, specifically, an argon laser, an excimer laser, or the like is used. As the excimer laser irradiation process, for example, XeCl (308
nm wavelength), in which case the irradiation is performed with an overlap scanning of 95% or more. In addition,
As for the formation of the single crystal silicon layer 7 by such a laser irradiation process, as described above, a method of locally irradiating a laser irradiation process only at a predetermined place, that is, only a TFT forming region, and performing heteroepitaxial growth is also available. Can be adopted. In forming the single-crystal silicon layer 7 by such a laser irradiation process, it is preferable to heat and adjust the substrate temperature to 200 to 500 ° C. The heating of the substrate 1 may be performed by heating the entire substrate uniformly using an electric furnace, or by locally heating only a predetermined location, for example, only a TFT forming region, using an optical laser, an electron beam, or the like. It is possible.

In such laser irradiation processing, irradiation energy, irradiation time, irradiation and scanning method,
The melting state and the cooling state are affected by conditions such as the presence or absence of a low reflection film and the atmosphere (in a vacuum or an inert gas) at the time of irradiation, and silicon crystallinity (eg, electron / hole mobility, leak current, etc.) is affected. Therefore, it is necessary to determine conditions for obtaining the desired silicon crystallinity in advance by experiments and the like. Further, by mixing an N-type or P-type carrier impurity into a semiconductor film made of amorphous silicon or polycrystalline silicon in advance, the obtained single-crystal silicon film 4 contains an arbitrary concentration of N-type or P-type carrier impurity. Can be formed.

In the single-crystal silicon layer 7 deposited as described above, for example, the (100) plane is heteroepitaxially grown on the substrate because the crystalline sapphire film 50 shows good lattice matching with single-crystal silicon. In this case, the single crystal silicon layer 7 having higher crystallinity can be obtained by heteroepitaxial growth of the step 4 taking into account a known phenomenon called grapho-epitaxial growth. As shown in FIG. 7, when a vertical wall such as the above-described step 4 is formed on the amorphous substrate (glass) 1 and an epitaxy layer is formed thereon, as shown in FIG. 7B, the (100) plane grows along the plane of the step 4 as shown in FIG. The size of the single crystal grain increases in proportion to the temperature and time. However, when the temperature and time are reduced and shortened, the interval between the steps must be shortened.

The shape of the step is shown in FIGS.
By changing variously as in (f), the crystal orientation of the growth layer can be controlled. When fabricating MOS transistors, the (100) plane is most often employed. In short, the cross-sectional shape of the step 4 may be such that the angle of the bottom corner (base angle) may be a right angle, or may be inclined inward or outward from the upper end to the lower end. It is sufficient if it has. Usually, the bottom angle of the step 4 is desirably a right angle or 90 ° or less, and the corner of the bottom surface preferably has a slight curvature.

As described above, single-crystal silicon layer 7 is formed on substrate 1 by heteroepitaxial growth by laser irradiation.
Then, a top gate type MOS TFT using the single crystal silicon layer 7 as a channel region is manufactured as follows. First, since the impurity concentration of the single crystal silicon layer 7 formed by the epitaxial growth varies, the entire surface is doped with an appropriate amount of a P-type carrier impurity, for example, boron ions, to adjust the specific resistance. Further, only the pMOSTFT formation region is selectively doped with an N-type carrier impurity to form an N-type well. For example, the pMOSTFT portion is masked with a photoresist (not shown), and P-type impurity ions (for example, B ⁺ ) are
At a dose of 2.7 × 10 ¹¹ atoms / cm ² to adjust the specific resistance. Further, as shown in FIG. 1 (4), in order to control the impurity concentration in the pMOSTFT formation region, the nMOSTFT portion is masked with a photoresist 60, and N-type impurity ions (for example, P ⁺ ) 65 are applied at 1 × 10 ¹¹ at 10 kV. Doping is performed at a dose of atoms / cm ² to form an N-type well 7A.

Next, as shown in FIG. 2 (5), SiO ₂ (about 100 n) is formed on the entire surface of the single crystal silicon layer 7 by plasma CVD, high density plasma CVD, catalytic CVD or the like.
m thickness) and SiN (approximately 200 nm thickness) are successively formed in this order to form a gate insulating film 8.
A sputtered film 9 of a tantalum (Mo.Ta) alloy having a thickness of 50
It is formed to a thickness of about 0 to 600 nm.

Next, as shown in FIG. 2 (6), the TFT in the display area is formed by a general-purpose photolithography technique.
Forming a photoresist pattern 10 in each step region (in the concave portion) of the TFT portion of the portion and the peripheral drive region,
Further, by successively etching using this as a mask, the gate electrode 11 of Mo / Ta alloy and (SiN /
A gate insulating film 12 having a laminated structure of SiO ₂ ) is formed, and the single crystal silicon layer 7 is exposed. In addition, Mo ・
Sputtered film 9 made of Ta alloy were treated with acid-based etching solution, SiN is CF ₄ gas plasma etching, Si
O ₂ is treated with a hydrofluoric acid-based etchant.

Next, as shown in FIG. 2 (7), all of the nMOS and pMOSTFTs in the peripheral driving region and the gate portion of the nMOSTFT in the display region are formed by photoresist 13
Then, phosphorus ions 14 are applied to the exposed source / drain regions of the nMOS TFT at, for example, 1 × 10 kV at 10 kV.
Doping (ion implantation) is performed at a dose of ¹³ atoms / cm ² to form an LDD portion 15 made of an N ⁻ -type layer in a self-aligned (self-aligned) manner.

Next, as shown in FIG. 3 (8), all of the pMOS TFTs in the peripheral drive region and nM
The gate portion of the OSTFT and the gate and LDD portion of the nMOSTFT in the display area are covered with a photoresist 16 and the exposed area is doped with phosphorus or arsenic ions
Doping (ion implantation) is performed at 0 kv with a dose of 5 × 10 ¹⁵ atoms / cm ² , and the source 18 and the drain 19 and the LDD 1 made of the N ⁺ type layer of the nMOS TFT are formed.
5 is formed.

Next, as shown in FIG. 3 (9), the nMOSTFT in the peripheral drive area and the nMOSTF in the display area
T and the gate portion of the pMOSTFT are covered with a photoresist 20 and boron ions 21
(Ion implantation) at a dose of 5 × 10 ¹⁵ atoms / cm ² at, for example, 10 kv, and pMOSTF
The source part 22 and the drain part 23 of the P ⁺ layer of T are formed. This step is unnecessary in the case of the nMOS peripheral drive circuit because there is no pMOSTFT.

Next, as shown in FIG.
A photoresist 24 is formed to make an active element portion such as an FT or a diode or a passive element portion such as a resistor or an inductance into an island. Then, the single crystal silicon layer 7 other than all the active element portions and the passive element portions in the peripheral drive region and the display region is removed by etching using a hydrofluoric acid-based etchant.

Next, as shown in FIG. 4 (11), an SiO ₂ film (about 200 nm thick) and a phosphosilicate glass (PSG) film (about 200 nm thick) were formed on the entire surface by plasma CVD, high-density plasma CVD, catalytic CVD, or the like. (Thickness of 300 nm) is formed continuously in this order, and the protective film 25 is formed.

Then, in this state, the single crystal silicon layer 7 is activated. For this activation, for example, a lamp of halogen or the like is used, and the annealing condition is set to about 1000.
C. for about 10 seconds. Therefore, a material that can withstand such annealing conditions is required as a gate electrode material, but the above-mentioned Mo / Ta alloy has a high melting point,
The structure can withstand such annealing conditions.
Further, since the gate electrode material made of the Mo.Ta alloy has a high melting point and can withstand annealing conditions, it can be formed not only as a gate portion but also as a wiring over a wide range. When annealing is performed using an excimer laser, XeCl (wavelength of 308 nm) is used.
It is desirable to perform irradiation processing on the entire surface or selectively only the active element portion and the passive element portion with 90% or more overlap scanning.

Next, as shown in FIG. 4 (12), contact windows are opened in the source / drain portions of all the TFTs of the peripheral drive circuit and the source portion of the display TFT by general-purpose photolithography and etching techniques. .

Then, aluminum or aluminum alloy (for example, aluminum containing 1% Si or 1 to 1)
Sputtered film of copper, aluminum, etc.
And a source electrode 26 of all the TFTs of the peripheral drive circuit and the display portion and a drain electrode 27 of the peripheral drive circuit portion by general-purpose photolithography and etching technology. Form a gate line. Thereafter, in a forming gas (N ₂ + H ₂ ), about 400 ° C./1
Sintering with h.

Next, as shown in (13) of FIG. 4, an insulating film 36 made of a PSG film (about 300 nm thick) and a SiN film (about 300 nm thick) is formed by plasma CVD, high-density plasma CVD, catalytic CVD, or the like. Is formed on the entire surface.
Next, a contact window is opened in the drain portion of the display TFT. Note that SiO ₂ , PSG and SiN in the pixel portion are used.
The film does not need to be removed.

Here, as a basic requirement of the reflection type liquid crystal display device, a function of reflecting incident light and a function of scattering incident light must be provided inside the liquid crystal panel. This is because the direction of the observer with respect to the display is substantially determined, but the direction of the incident light cannot be uniquely determined. For this reason, it is necessary to design a reflector assuming that a point light source exists in an arbitrary direction. Therefore, as shown in (14) of FIG.
A photosensitive resin film 28 having a thickness of about 3 .mu.m is formed. Subsequently, as shown in FIG. 5 (15), a concavo-convex pattern for obtaining optimum reflection characteristics and viewing angle characteristics is formed by general-purpose photolithography and etching technology. It is formed in the pixel portion and is reflowed to form a lower reflective surface made of the roughened surface 28A. At the same time, a resin window for contact of the drain portion of the display TFT is opened.

Then, as shown in FIG. 5 (16), aluminum or aluminum having a thickness of about 400 to 500 nm is formed on the entire surface.
% Sputtered film such as aluminum containing Si, and by general-purpose photolithography and etching technology,
The sputtered film other than the pixel portion is removed, and a reflective film 29 made of, for example, aluminum having an uneven shape connected to the drain portion 19 of the display TFT is formed. This reflection film 29 also functions as a pixel electrode for display. Thereafter, sintering is performed in a forming gas at about 300 ° C. for 1 hour to make the contact sufficient. Note that silver or a silver alloy may be used instead of an aluminum-based material to increase the reflectance.

As described above, the single-crystal silicon layer 7 is formed by laser irradiation using the crystalline sapphire film 50 and the step 4 as seeds for heteroepitaxial growth.
A display unit using the single-crystal silicon layer 7 and a peripheral drive circuit unit are respectively provided with a top gate type nMOSLDD-T.
C composed of FT, pMOSTFT and nMOSTFT
A display section-peripheral drive circuit section integrated type active matrix substrate 30 incorporating a MOS circuit can be manufactured.

Next, a method of manufacturing a reflective liquid crystal display (LCD) using the active matrix substrate (drive substrate) 30 will be described with reference to FIG. Hereinafter, this active matrix substrate is referred to as a TFT substrate.

When manufacturing the liquid crystal cell of this LCD by surface assembly suitable for a medium / large liquid crystal panel of 2 inches or more, first, the TFT substrate 30 and the entire solid IT
Opposite substrate 32 provided with O (Indium tin oxide) electrode 31
The polyimide-based alignment films 33, 3
4 is formed. For these polyimide-based alignment films 33 and 34, polyimide is applied to a thickness of about 50 to 100 nm by roll coating, spin coating, or the like, and thereafter,
It is formed by curing at 180 ° C. for 2 hours.

Next, the TFT substrate 30 and the counter substrate 3
Rubbing or optical alignment processing is performed on each of the polyimide-based alignment films 33 and 34 of No. 2. Rubbing buff materials include cotton and rayon, but cotton is more stable in terms of buff residue (garbage) and retardation. Photoalignment is a technique for aligning liquid crystal molecules by non-contact linearly polarized ultraviolet irradiation. In addition to the rubbing, the polymer alignment film can be formed by obliquely incident polarized light or non-polarized light. As a polymer compound that can form such a polymer alignment film, for example, a polymethyl methacrylate-based polymer having azobenzene can be given.

Next, in order to remove the rubbing buff residue,
After washing with water or IPA (isopropyl alcohol), a common agent is applied to the TFT substrate 30 side, and a sealing agent is applied to the counter substrate 32 side. Acrylic, epoxy acrylate, or epoxy adhesive containing a conductive filler is used as the common agent, and acrylic, epoxy acrylate, or epoxy adhesive is used as the sealant. As the common agent and the sealant, any of a heat curing type, an ultraviolet irradiation curing type, and an ultraviolet irradiation curing + heat curing type can be used. It is preferable to use a radiation curing + heat curing type.

Next, spacers for obtaining a predetermined gap are sprayed on the counter substrate 32 side, and are superposed on the TFT substrate 30 at a predetermined position. After the alignment marks on the counter substrate 32 and the TFT substrate 30 are precisely aligned, the sealant is temporarily cured by irradiating ultraviolet rays, and then heat-cured collectively.

Next, a scribe break is performed to
A single liquid crystal panel in which the substrate 30 and the counter substrate 32 are overlapped is manufactured. Next, the liquid crystal 35 is applied to both substrates 30-32.
It is injected into the gap between them, and after the injection port is sealed with an ultraviolet adhesive, IPA cleaning is performed. Although the type of liquid crystal is not particularly limited as described above, for example, a high-speed TN (twisted nematic) mode using a nematic liquid crystal is generally used. Next, the liquid crystal 35 is oriented by heating and quenching. Next, a flexible wiring is connected to the panel electrode take-out portion of the TFT substrate 30 by thermocompression bonding of an anisotropic conductive film, and a polarizing plate with a retardation plate is bonded to the counter substrate 32.

When a liquid crystal panel (liquid crystal cell) is manufactured by a single surface assembly suitable for a small liquid crystal panel having a size of 2 inches or less, the TFT substrate 30 and the counter substrate 32 are formed on the element formation surface in the same manner as described above. Polyimide-based alignment films 33 and 34 are formed, respectively, and the polyimide-based alignment films 33 and 34 are subjected to rubbing or alignment treatment using non-contact linearly polarized ultraviolet light.

Next, the TFT substrate 30 and the counter substrate 3
2 is singly divided by dicing or scribe break, and washed with water or IPA. Subsequently, a common agent is applied to the TFT substrate 30, and a sealing agent containing a spacer is applied to the counter substrate 32. Then, the two substrates are overlapped. Subsequent processes are the same as described above, and a description thereof will be omitted.

In the reflection type LCD described above, the opposing substrate 32 is a CF (color filter) substrate, and the color filter layer 46 is provided below the ITO electrode 31.
In such a reflection type LCD, incident light from the counter substrate 32 side is efficiently reflected by the reflection film 29 and emitted from the counter substrate 32 side.

When the reflective film 29 is also used as a pixel electrode for display as in the above-described example, and the polyimide-based alignment film 33 is directly formed thereon,
In the case of No. 3, the unevenness of the reflective film 29 serving as a base may cause unevenness in film thickness, rubbing unevenness, and rubbing may cause scratches or peeling and color unevenness.

Therefore, the reflection film 29 is formed so as not to conduct to the drain of the TFT so that it does not function as a pixel electrode, and a transparent electrode (I
(A TO electrode). In that case, TF
A thickness of 2 to 3 on the reflection film 29 which does not conduct to the drain portion of T
A transparent resin flattening film of about μm is formed, and a transparent electrode (ITO electrode) having a thickness of about 0.13 to 0.15 μm is formed thereon.
Is formed in a state of being electrically connected to the drain portion of the TFT.

As described above, if a transparent electrode is formed via the transparent resin flattening film, the surface of the transparent electrode is naturally flattened, so that the polyimide alignment film 33 formed thereon is also flattened. Therefore, unevenness in film thickness, rubbing unevenness, scratches and peeling due to rubbing, color unevenness, and the like are prevented from occurring, and quality and yield can be improved.

When the TFT substrate 30 has an on-chip color filter (OCCF) structure in which a color filter is provided on the TFT substrate 30 in addition to the substrate structure shown in FIG. 6, the counter substrate 32 has a solid ITO electrode. (Or ITO electrode with black mask is solid) and T
The FT substrate 30 is provided with a color filter.

Also in this case, for the TFT substrate 30, the above-mentioned structure in which a transparent electrode (ITO electrode) is provided separately from the reflective film 29 as a pixel electrode can be adopted. That is, a transparent resin flattening film having a thickness of about 2 to 3 μm is formed on the reflection film 29 formed so as not to conduct to the drain portion of the TFT, and a color filter layer having a thickness of about 1 to 2 μm is formed thereon. I do. Then, a transparent resin flattening film having a thickness of about 1 to 2 μm is further formed thereon, and a transparent electrode (I) having a thickness of about 0.13 to 0.15 μm is formed thereon.
TO electrode) is formed in a state of being electrically connected to the drain of the TFT.

As described above, when the color filter and the transparent electrode are formed via the transparent resin flattening film, the surface of the transparent electrode becomes flat as described above, and the polyimide alignment film 33 becomes flat. Therefore, it is possible to prevent unevenness in film thickness, uneven rubbing, scratches and peeling due to rubbing, uneven color, and the like, and to improve quality and yield. Incidentally, in the case of incorporating an auxiliary capacitance C _S shown in FIG. 10 in the pixel portion, electrostatic collector layer provided on the substrate 1 described above (not shown) may be connected to the drain region 19 of monocrystalline silicon .

As described above, according to the present embodiment, the following remarkable effects can be obtained. (A) A crystalline sapphire film 50 is formed on a substrate 1 provided with a step 4 having a predetermined shape / dimension, and heteroepitaxial growth is performed by using this as a seed by a laser irradiation method (however,
The heating temperature during growth is 200 to 800 ° C., preferably 30 ° C.
0 to 400 ° C.).
Since a single-crystal silicon layer 7 having a high electron mobility of not less than cm ² / v · sec can be obtained, an LCD with a built-in high-performance driver
Can be manufactured. In addition, since the step 4 promotes the epitaxial growth, a single crystal silicon layer 7 having higher crystallinity can be obtained.

(B) The single-crystal silicon layer 7 has a smaller thickness than a conventional amorphous silicon layer or polycrystalline silicon layer.
Since it exhibits high electron and hole mobilities comparable to those of a single crystal silicon substrate, a single crystal silicon top gate type MOS TFT obtained therefrom has nMOS or pMOS or cMO having an LDD structure with high switching characteristics and low leakage current.
STFT display, high drive capability cMOS, nMO
A structure integrated with a peripheral driver circuit section made of S or pMOSTFT or a mixture of them becomes possible, and a display panel with high image quality, high definition, narrow frame, large screen, and high efficiency is realized. Further, since the single crystal silicon layer 7 has a sufficiently high hole mobility, a peripheral drive circuit for driving electrons and holes individually or in combination of both can be manufactured. Alternatively, a panel integrated with a display TFT having a pMOS or cMOS LDD structure can be realized. In the case of a small to medium-sized panel, there is a possibility that one of a pair of peripheral vertical drive circuits can be omitted.

(C) By adopting the laser irradiation treatment method, the heat treatment temperature during the silicon epitaxial growth can be made 800 ° C. or less, so that it can be formed on the insulating substrate at a relatively low temperature (for example, 200 to 600 ° C. or less). The single crystal silicon layer 7 can be formed uniformly. In addition, as the substrate, a substrate material having a low strain point, low cost, and good physical properties, such as quartz glass, crystallized glass, a ceramic substrate, and borosilicate glass (further, a heat-resistant organic substrate) is used. It can be arbitrarily selected, and the size of the substrate can be increased.

(D) Since long-time annealing at an intermediate temperature as in the case of the solid phase growth method is not required, productivity is high, and
In addition, expensive manufacturing equipment is not required and cost can be reduced.

(E) In this heteroepitaxial growth, the crystallinity of the crystalline sapphire film and the like, the irradiation energy and irradiation time of the laser, and the shape and size of the step,
By adjusting the heating temperature and cooling rate of the substrate, the concentration of the added N-type or P-type carrier impurities, etc., a wide range of N-type or P-type conductive type and high mobility single crystal silicon layers can be easily obtained. Vth (threshold) adjustment becomes easy, and high-speed operation by lowering the resistance becomes possible.

(F) If a color filter is formed on the display array unit, cost reduction can be realized by improving the aperture ratio and luminance of the display panel, omitting the color filter substrate, improving productivity, and the like.

(G) Since the material layer such as a crystalline sapphire film serves as a diffusion barrier for various atoms, diffusion of impurities from the glass substrate can be suppressed.

<Second Embodiment> A second embodiment of the present invention will be described with reference to FIGS.

In the present embodiment, the top gate type MOSTFT is provided in the display section and the peripheral drive circuit section in the same manner as in the first embodiment described above. It concerns a type LCD. Therefore, the manufacturing process is the same from the process shown in FIG. 1A to the process shown in FIG. Then, in the embodiment of this example, after these steps, FIG.
As shown in FIG. 2 (14), a window for contacting the drain portion of the display TFT is opened in the protective film 25 and the insulating film 36, and at the same time, in order to improve the transmittance, an unnecessary portion of the pixel opening portion of the Si is unnecessary.
The O ₂ , PSG and SiN films are removed.

Next, as shown in (15) of FIG.
On the entire surface, a flattening film 28B of a photosensitive acrylic transparent resin is formed to a thickness of about 2 to 3 μm by spin coating or the like,
TF for display by general-purpose photolithography technology
A window is opened in the flattening film 28B on the drain side of T, and this is cured under predetermined conditions.

Next, as shown in (16) of FIG.
An ITO sputtered film having a thickness of about 130 to 150 nm is formed on the entire surface, and a transparent electrode (pixel electrode) 41 made of ITO in contact with the drain portion 19 of the display TFT is formed by general-purpose photolithography and etching technology. Then, heat treatment (in forming gas, 200
(250 ° C./1 h), the contact resistance between the drain of the display TFT and ITO is reduced, and the transparency of ITO is improved.

Then, as shown in FIG.
And a transmission type LCD is assembled in the same manner as in the first embodiment. However, a polarizing plate is also attached to the TFT substrate side. In this transmissive LCD, transmitted light is obtained as indicated by a solid arrow, but it may be configured such that transmitted light from the counter substrate 32 side is obtained as indicated by an alternate long and short dashed arrow.

In the case of this transmission type LCD, an on-chip color filter (OCCF) structure and an on-chip black (OCB) structure can be manufactured as follows.

That is, (1) in FIG. 1 to (12) in FIG.
The steps up to are performed in the same manner as described above. Then, as shown in FIG. 14 (13), the PSG / SiO
_After opening the drain portion of the _second insulating film 25 to form an aluminum buried layer 41A for the drain electrode,
An N / PSG insulating film 36 is formed.

Next, as shown in (14) of FIG. 14, a photoresist 61 in which each color of R, G, and B is dispersed in a pigment for each segment is formed to a predetermined thickness (1 to 1.5 μm). As shown in (15) of FIG. 14, patterning is performed by using a general-purpose photolithography technique, leaving only predetermined positions (each pixel portion), and each color filter layer 61 (R), 61
(G) and 61 (B) are formed (on-chip color filter structure). At this time, the window of the drain part is also opened. In this example, an opaque ceramic substrate, glass having low transmittance, and a heat-resistant resin substrate cannot be used.

Next, as shown in FIG. 14 (15),
In a contact hole communicating with the drain of the display TFT, a light shielding layer 43 serving as a black mask layer of the display TFT is formed by metal patterning over the color filter layer. For example, a film of titanium or molybdenum is formed to a thickness of about 200 to 250 nm by a sputtering method, and then patterned into a predetermined shape that covers the display TFT and shields light (on-chip black structure).

Next, as shown in FIG. 14 (16),
A flattening film 28B made of a transparent resin is formed, and a transparent electrode 41 is buried in a through hole provided in the flattening film so as to be connected to the light shielding layer 43.

As described above, by forming the color filter layer 61 and the light shielding layer 43 on the display array portion, the aperture ratio of the liquid crystal display panel can be improved, and the power consumption of the display module including the backlight can be reduced. Can be realized.

<Third Embodiment> A third embodiment of the present invention will be described with reference to FIGS.

In the present embodiment, the peripheral drive circuit section is formed by the same top gate type pM as in the first embodiment.
It is composed of a CMOS drive circuit composed of an OSTFT and an nMOSTFT. In addition, although the display section is of a reflective type, the TFTs have various gate structures and various combinations.

That is, in the first embodiment described above, as shown in FIG.
While the MOSLDD-TFT is provided, FIG.
In the example shown in (B), the display unit has a bottom gate type nMO.
An SLDD-TFT is provided, and in the example shown in FIG.
A D-TFT is provided. These bottom gate type MOS
Both TFT and dual-gate MOSTFT
Top gate type MOS of peripheral drive circuit section as described later
It can be manufactured in the same process as the TFT. In the case where the gate structure of the TFT of the display portion is changed in this way, especially in the case of a dual gate type, the driving capability is improved by the upper and lower gate portions, which is suitable for high-speed switching. It can be selectively used to operate as a top gate type or a bottom gate type depending on the case.

The bottom gate type MO shown in FIG.
In the STFT, reference numeral 71 in the figure denotes a gate electrode made of Mo, Ta, or the like. Reference numeral 72 denotes an SiN film, 7
Reference numeral 3 denotes an SiO ₂ film, and a gate insulating film is formed by the SiN film and the SiO ₂ film. On this gate insulating film, a channel region and the like using a single crystal silicon layer 7 are formed similarly to the top gate type MOSTFT. Further, the dual gate type MOST shown in FIG.
In FT, the lower gate is a bottom gate type MOSTFT
Except that the upper gate portion has a gate insulating film 7
3 is formed of a SiO ₂ film and a SiO ₂ film, and an upper gate electrode 74 is provided thereon. However, in each case, each gate portion is provided outside the step 4 which acts as a seed during heteroepitaxial growth and at the same time promotes the growth of the single crystal silicon film and has an effect of increasing the crystallinity.

Next, the above-mentioned bottom gate type MOSTFT
The method of manufacturing the dual gate type MOSTFT will be described with reference to FIGS. 16 to 20. Since the method of manufacturing the top gate type MOSTFT in the peripheral drive circuit section is the same as the steps shown in FIGS. 1 to 5, illustration and description thereof are omitted here.

In the display section, a bottom gate type MOST
To manufacture the FT, first, as shown in FIG. 16A, a molybdenum / tantalum (Mo.Ta)
An alloy sputtered film 71A is formed to a thickness of about 300 to 400 nm.

Next, as shown in FIG. 16 (2), a photoresist 70 is formed in a predetermined pattern, and using this as a mask, the sputtered film 71A is taper-etched, and the side end surface 71a is gently inclined at 20 to 45 °. A gate electrode 71 having a trapezoidal cross section is formed.

Next, after removing the photoresist 70, as shown in FIG. 16C, a SiN film (about 200 nm thick) 72 and a SiO ₂ film are formed on the substrate 1 including the sputtered film 71A by a plasma CVD method or the like. (About 100 nm thick) 7
3 are stacked in this order to form a gate insulating film.

Next, in the same manner as in the step shown in FIG. 1A, a photoresist 2 is formed in a predetermined pattern in the TFT formation region as shown in FIG. A plurality of steps 4 having an appropriate shape and dimensions are formed on the gate insulating film on 1 (and also on the substrate 1). As described above, the step 4 serves as a seed for heteroepitaxial growth of single crystal silicon, which will be described later, and at the same time, has the function of promoting the growth of the crystalline sapphire film and increasing its crystallinity. The width is about 0.3 to 0.4 μm, the width w is about 2 to 3 μm, the length (the direction perpendicular to the paper surface) is about 10 to 20 μm, and the angle (base angle) between the bottom surface and the side surface is substantially a right angle. You.

Next, in the same manner as in the step shown in FIG. 1B, the photoresist 2 is formed as shown in FIG.
Is removed, a crystalline sapphire film 50 is formed on one main surface of the insulating substrate 1 in a TFT formation region including the step 4 to a thickness of about 20 to 200 nm.

Next, amorphous silicon or polycrystalline silicon is removed by sputtering, plasma CVD, or the like.
A film is formed to a thickness of about 100 nm to form a silicon film (not shown). Subsequently, in the same manner as in the step shown in FIG. 1C, the silicon film is irradiated with a laser, and the film is heated and melted, and then cooled (slowly cooled) and solidified, thereby obtaining the crystalline scifi. Silicon is heteroepitaxially grown using both the thin film 50 and the step 4 as seeds, and a single crystal silicon layer 7 is formed to a thickness of about 5 to 100 nm, preferably about 30 to 50 nm on the entire surface including the step 4 as shown in FIG. Form. At this time, since the side end surface 71a of the underlying gate electrode 71 is a gentle slope, heteroepitaxial growth by the step 4 and the crystalline sapphire film 50 is not hindered on this surface, and the single-crystal silicon Layer 7 will grow.

Then, after passing through the steps shown in FIGS. 1 (4) to 2 (6), the steps shown in FIG. 17 (7) are carried out in the same manner as in the step shown in FIG. 2 (7). NMOST of the display section
The gate portion of the FT is covered with a photoresist 13, and the exposed source / drain regions of the nMOS TFT are doped (ion-implanted) with phosphorus ions 14 to form an LDD portion 15 made of an N ⁻ -type layer in a self-aligned manner. At this time, the surface height difference (or pattern) is easily recognized due to the presence of the bottom gate electrode 71. Therefore, the alignment (mask alignment) of the photoresist 13 is easily performed, and alignment deviation hardly occurs.

Next, in the same manner as in the step shown in FIG. 3 (8), the gate portion and the LDD portion of the nMOS TFT are covered with the photoresist 16 as shown in FIG.
The exposed region is doped with phosphorus or arsenic ions 17 (ion implantation) to form a source portion 18 and a drain portion 19 made of an N ⁺ type layer of the nMOS TFT.

Next, in the same manner as in the step shown in FIG. 3D, the entire nMOS TFT is covered with the photoresist 20 as shown in FIG.
Doping (ion implantation) into the peripheral drive circuit
A source portion and a drain portion of the P ⁺ layer of the MOSTFT are formed.

Next, in the same manner as in the step shown in FIG. 3 (10), the photoresist 2 is formed to make the active element section and the passive element section into islands as shown in FIG. 18 (10).
4 is provided, and the single crystal silicon layer 7 is selectively removed by etching.

Next, in the same manner as in the step shown in FIG. 4 (11), as shown in FIG.
D, a SiO ₂ film 53 (thickness of about 300 nm) and a phosphosilicate glass (PSG) film 54 (thickness of about 300 nm) are continuously formed in this order on the entire surface by high-density plasma CVD, catalytic CVD, or the like. Note that the SiO ₂ film 53 and the PSG film 54 correspond to the above-described protective film 25. Then, in this state, the single crystal silicon layer 7 is activated in the same manner as described above.

Next, in the same manner as in the step shown in FIG. 4 (12), as shown in FIG. 19 (12), a contact window is opened in the source section by general-purpose photolithography and etching techniques. And the thickness of 400 to 5
A sputtered film of an aluminum alloy or the like having a thickness of about 00 nm is formed, and a data line and a gate line are formed at the same time when the source electrode 26 of the TFT is formed by general-purpose photolithography and etching technology. Thereafter, sintering is performed at about 400 ° C./1 h in a forming gas.

Next, in the same manner as in the step shown in (13) of FIG. 4, as shown in (13) of FIG. 19, the PSG film (about 300
An insulating film 36 made of an SiN film (thickness: about 300 nm) and a SiN film (about 300 nm thick) is formed on the entire surface, and a contact window is opened in the drain of the display TFT.

Next, in the same manner as in the step shown in FIG. 5 (14), a photosensitive resin film 28 having a thickness of 2 to 3 μm is formed by spin coating or the like as shown in FIG. 19 (14). 19 in the same manner as the process shown in FIG.
As shown in (15), a concave / convex pattern for obtaining optimal reflection characteristics and viewing angle characteristics is formed in the pixel portion by general-purpose photolithography and etching techniques, and is reflowed to form a lower portion of the reflection surface including the concave / convex rough surface 28A. To form
At the same time, a resin window for contact of the drain portion of the display TFT is opened.

Next, in the same manner as in the step shown in FIG. 5 (16), 400
A sputtered film of an aluminum alloy or the like having a thickness of about 500 nm is formed, and an aluminum reflective film 29 having an uneven shape connected to the drain portion 19 of the display TFT is formed by general-purpose photolithography and etching technology.

As described above, single crystal silicon layer 7 is formed by laser irradiation treatment using crystalline sapphire film 50 including step 4 as a seed for heteroepitaxial growth, and a bottom portion is formed on the display portion using single crystal silicon layer 7. Gate type nMOS LDD-TFT (pMOS at the periphery)
CMOS drive circuit composed of TFT and nMOS TFT)
The active matrix substrate 30 integrated with the display unit and the peripheral drive circuit unit incorporating the above can be manufactured.

FIG. 20 shows an example in which the gate insulating film of the bottom gate type MOSTFT provided in the display portion is formed by an anodic oxidation method of Mo · Ta.

In this example, after the step shown in FIG. 16B, the molybdenum-tantalum alloy film 71 is subjected to a known anodic oxidation treatment as shown in FIG. _A gate insulating film 74 of ₂ O ₅ is formed to a thickness of 100 to 200 nm.

Thereafter, steps 4 and a crystalline sapphire film 50 are formed as shown in FIG. 20 (4) in the same manner as the steps shown in FIGS. 17 (4) to (6). A silicon film is formed by forming amorphous silicon or polycrystalline silicon. Next, the silicon film is heated and melted by a laser irradiation method, and then cooled (slowly cooled) and solidified, whereby heteroepitaxial growth is performed using the crystalline sapphire film 50 as a seed to form the single crystal silicon layer 7. Next, the active matrix substrate 30 is manufactured as shown in FIG. 20 (5) in the same manner as in the steps shown in FIGS. 17 (7) to 19 (15).

In the display section, a dual gate type MOS
In order to manufacture a TFT, first, FIG.
A process similar to the process shown in (6) is performed.

Next, as shown in FIG. 21 (7), a step 4 is formed on the insulating films 72 and 73 and the substrate 1, and furthermore,
Amorphous silicon or polycrystalline silicon is formed on the crystalline sapphire film 50 and the step 4 to form a silicon film (not shown). Next, the silicon film is heated and melted by laser irradiation treatment, and further cooled (slowly cooled) and solidified, whereby the single crystal silicon layer 7 is heteroepitaxially grown using the crystalline sapphire film 50 and the step 4 as seeds. Next, in the same manner as in the step shown in FIG.
D, SiO ₂ film (about 100 nm thick) by catalytic CVD, etc.
And SiN (about 200 nm thick) are successively formed in this order, and an insulating film 80 (this corresponds to the gate insulating film 8 described above)
And a sputtered film 81 (which corresponds to the above-described sputtered film 9) made of a Mo.Ta alloy
It is formed to a thickness of about 00 nm.

Next, in the same manner as in the step shown in FIG. 2 (6), a photoresist pattern 10 is formed as shown in FIG. 21 (8), and Mo.multidot.
Top gate electrode 82 of Ta alloy and gate insulating layer 83
Is formed to expose the single crystal silicon layer 7.

Next, in the same manner as in the step shown in FIG. 2 (7), the top gate portion of the nMOSTFT is covered with the photoresist 13 as shown in FIG. The source / drain regions are doped with phosphorus ions 14 (ion implantation) to form N ⁻
The LDD part 15 of the mold layer is formed.

Next, in the same manner as in the step shown in FIG. 3 (8), the gate portion and the LDD portion of the nMOS TFT are covered with the photoresist 16 as shown in FIG. Arsenic ions 17 are doped (ion-implanted) to form a source portion 18 and a drain portion 19 made of an N ⁺ type layer of the nMOS TFT.

Next, in the same manner as in the step shown in FIG. 3 (9), as shown in FIG.
Is covered with a photoresist 20 and boron ions 21 are doped (ion-implanted) in the exposed regions to form the source and drain portions of the P ⁺ layer of the pMOSTFT of the peripheral drive circuit portion.

Next, in the same manner as in the step shown in FIG. 3 (10), a photoresist 24 is provided for islanding the active element section and the passive element section as shown in FIG. The single crystal silicon layer other than the element portion and the passive element portion is selectively removed by general-purpose photolithography and etching techniques.

Next, in the same manner as in the step shown in FIG. 4 (11), as shown in FIG.
D, S by high density plasma CVD, catalytic CVD, etc.
An iO ₂ film 53 (about 200 nm thick) and a phosphosilicate glass (PSG) film 54 (about 300 nm thick) are formed on the entire surface. These films 53 and 54 correspond to the protective film 25 described above. Then, the single crystal silicon layer 7 is activated.

Next, in the same manner as in the step shown in FIG. 4 (12), a contact window is opened in the source portion as shown in FIG. 22 (14). And 400 to 50 on the whole surface
A sputtered film made of an aluminum alloy or the like having a thickness of about 0 nm is formed, and the data line and the gate line are formed at the same time as the source electrode 26 is formed by general-purpose photolithography and etching technology.

Next, in the same manner as in the step shown in FIG. 4 (13), as shown in FIG. 23 (15), an insulating film made of a PSG film (about 300 nm thick) and a SiN film (about 300 nm thick) 36 is formed on the entire surface, and TF for display is further formed.
A contact window is opened in the drain portion of T.

Next, as shown in FIG. 23 (16),
A photosensitive resin film 28 having a thickness of about 2 to 3 μm is formed on the entire surface by spin coating or the like. Subsequently, (15) and (1) in FIG.
In the same manner as in the step shown in 6), as shown in FIG. 23 (17), the lower part of the reflection surface composed of the rough surface 28A is formed in the pixel portion, and at the same time, the contact resin window of the drain portion of the display TFT is formed. Opening is performed, and a reflection film 29 made of a concavo-convex shape aluminum alloy or the like for obtaining optimum reflection characteristics and viewing angle characteristics is formed, which is connected to the drain portion 19 of the display TFT.

As described above, the single crystal silicon layer 7 is formed by laser irradiation using the crystalline sapphire film 50 and the step 4 as seeds for heteroepitaxial growth.
A dual gate type nMOS LDDTFT is used for a display unit using the single crystal silicon layer 7 and a pM
The display-peripheral drive circuit unit integrated active matrix substrate 30 in which CMOS drive circuits each including an OSTFT and an nMOSTFT are built can be manufactured.

<Fourth Embodiment> A fourth embodiment of the present invention will be described with reference to FIGS.

In this embodiment, unlike the above-described embodiment, the gate electrode of the top gate portion is formed of a material having relatively low heat resistance such as aluminum.

First, the case where a top gate type MOSTFT is provided in both the display section and the peripheral drive circuit section will be described. In this example, first, the steps are performed in the same manner as the steps (1) to (4) of FIG. 1 in the first embodiment described above, and then the peripheral driving is performed as shown in (4) of FIG. An N-type well 7A is formed in the pMOSTFT portion of the circuit portion.

Next, as shown in (5) of FIG. 24, all of the nMOS and pMOSTFTs in the peripheral drive region and the gate portion of the nMOSTFT in the display region are connected to the photoresist 1.
3, phosphorus ions 14 are applied to the exposed source / drain regions of the nMOS TFT at, for example, 1 × 10 kV at 10 kV.
^By doping (ion implantation) at a dose of ¹³ atoms / cm ² , an LDD portion 15 made of an N ⁻ -type layer is formed in a self-aligned manner.

Next, as shown in FIG. 25 (6), all of the pMOS TFTs in the peripheral drive region and n in the peripheral drive region
Gate portion of MOSTFT and nMOSTFT in display area
And the LDD portion are covered with a photoresist 16 and phosphorus or arsenic ions 17
By doping (ion implantation) at 0 kV and a dose of 5 × 10 ¹⁵ atoms / cm ² , the source 18 and the drain 19 and the LDD 15 made of the N ⁺ type layer of the nMOS TFT are formed. In this case, the resist 13 is left as shown by a dashed line in FIG.
Is provided, it is possible to perform the mask alignment at the time of forming the resist 16 using the resist 13 as a guide, thereby facilitating the mask alignment and reducing the misalignment.

Next, as shown in FIG. 25 (7), the nMOSTFT in the peripheral driving region and the nMOST in the display region are used.
The entirety of the FT and the gate portion of the pMOS TFT are covered with a photoresist 20 and boron ions 21
(Ion implantation) at a dose of 5 × 10 ¹⁵ atoms / cm ^{2 at} 10 kV, for example,
The source part 22 and the drain part 23 of the P ⁺ layer are formed.

Next, the resist 20 is removed.
As shown in FIG. 25 (8), the single crystal silicon layers 7, 7A
Is activated in the same manner as described above, and a gate insulating film 12 and a gate electrode material (aluminum or 1% S
i-containing aluminum or the like) 11 is formed. The gate electrode material layer 11 can be formed by a vacuum evaporation method or a sputtering method.

[0167] Then, by patterning the respective gate portion in the same manner as described above, then, an island and an active element portion and the passive element portion, further as shown in (9) in FIG. 26, SiO ₂ film on the entire surface (Approximately 200 nm thick) and a phosphosilicate glass (PSG) film (approximately 300 nm thick) are successively formed in this order to form a protective film 25.

Next, as shown in (10) of FIG.
By general-purpose photolithography and etching technology, contact windows are opened in the source / drain portions of all the TFTs of the peripheral drive circuit and the source portions of the display TFT.

Then, a sputtering film of aluminum or aluminum containing 1% Si having a thickness of 500 to 600 nm is formed on the entire surface, and the peripheral drive circuit and the source electrodes 26 of all TFTs in the display section are formed by general-purpose photolithography and etching technology. A data line and a gate line are formed at the same time as the formation of the drain electrode 27 of the peripheral driving circuit. Thereafter, sintering is performed in a forming gas (N ₂ + H ₂ ) at about 400 ° C. for 1 hour.

Next, (13) in FIG. 4 to (16) in FIG.
In the same manner as in the step shown in FIG. 1, a top gate type nMOSLDD-TF having a gate electrode of aluminum or aluminum containing 1% Si is provided for the display section using the single crystal silicon layer 7 and the peripheral drive circuit section, respectively.
CM composed of T, pMOSTFT and nMOSTFT
An active matrix substrate 30 integrated with a display unit and a peripheral driving circuit unit, in which an OS driving circuit is built, can be manufactured.

In this embodiment, since the gate electrode 11 made of aluminum or aluminum containing 1% Si is formed after the activation process of the single crystal silicon layer 7, the influence of the heat during the activation process is reduced. Since it has no relation to the heat resistance of the material, the heat resistance of the top gate electrode material is relatively low, and even low-cost aluminum or aluminum containing 1% Si can be used. This is because the display unit has a bottom gate type MOSTF
The same applies to the case of T.

Next, a dual gate type MOST is provided in the display section.
A case where a top gate type MOSTFT is provided in the FT and the peripheral driving circuit will be described. In this example, first, the process is performed in the same manner as the processes shown in (1) of FIG. 16 to (6) of FIG. 17 in the above-described third embodiment.
As shown in (6), pMOSTF of the peripheral drive circuit section
An N-type well 7A is formed in the T portion.

Next, in the same manner as in the step shown in FIG. 24 (5), as shown in FIG.
The portion is doped with phosphorus ions 14 to form an LDD portion 15.

Next, in the same manner as in the step shown in FIG. 25 (6), as shown in FIG. 28 (8), the display section and the nMOSTFT section of the peripheral drive circuit section are doped with phosphorus ions 17 to form an N ⁺ type. A source region 18 and a drain region 19 are formed.

Next, in the same manner as in the step shown in FIG. 25 (7), as shown in FIG. 28 (9), the pMOSTFT part of the peripheral drive circuit section is doped with boron ions 21 and
^{A +} type source region 22 and a drain region 23 are respectively formed.

Next, the resist 20 is removed.
As shown in FIG. 28 (10), the single crystal silicon layer 7 is patterned to make the active element portion and the passive element portion into islands. Thereafter, as shown in FIG. 29 (11), the single crystal silicon layers 7, 7A are formed. Is activated in the same manner as described above, and a gate insulating film 80 is formed on the surface of the display portion, while a gate insulating film 12 is formed on the surface of the peripheral drive circuit portion.

Next, as shown in FIG. 29 (12),
An aluminum alloy or the like formed on the entire surface by sputtering is patterned to form each upper gate electrode 83 of the display section and each gate electrode 11 of the peripheral drive circuit section.

Next, as shown in FIG. 29 (13),
An SiO ₂ film (about 200 nm thick) and a phosphosilicate glass (PSG) film (about 300 nm thick) are successively formed on the entire surface in this order, and a protective film 25 is formed.

Next, the source electrode 26 of all the TFTs in the peripheral driving circuit and the display section and the drain electrode 27 of the peripheral driving circuit section were formed in the same manner as described above, so that the single crystal silicon layer 7 was used. A dual gate type nMOS LDD-TFT, pMO using an aluminum alloy or the like as a gate electrode for the display section and the peripheral drive circuit section, respectively
A display-peripheral drive circuit unit integrated active matrix substrate 30 incorporating a CMOS drive circuit composed of STFTs and nMOS TFTs can be manufactured.

Also in the present embodiment, after the activation treatment of single crystal silicon layer 7, gate electrodes 11, 83 of aluminum or the like are formed.
Because the effect of heat during the activation process has no relation to the heat resistance of the gate electrode material, it is used as a top gate electrode material with relatively low heat resistance and even for low-cost aluminum alloys. As a result, the range of choice of electrode materials is expanded. Although the source electrode 26 (and the drain electrode) can be formed simultaneously in the step (11) of FIG. 29, this is advantageous in the manufacturing process.

In any of the above embodiments, for example, a bottom gate type or a top gate type MOS
When a TFT is manufactured, as shown in FIG. 30A, when a step 4 is provided, the single crystal silicon film 7 grown thereon is thin, so that the step is disconnected (poor connection) or thinned (increased resistance). ) May occur, the source electrode 26
(Or drain electrode)
As shown in FIGS. 30B and 30C, it is desirable to dispose electrodes on a region including the step 4.

In the step shown in FIG. 24 (5) or the step shown in FIG. 27 (7), a top gate insulating film is formed on the single crystal silicon layer 7, and ion implantation and activation are performed. After the processing is sequentially performed, the top gate electrode, the source, and the drain electrode may be simultaneously formed using an aluminum alloy or the like.

As described above, the step 4 is formed on the substrate 1 (and also on a film of SiN or the like thereon) as shown in FIG.
As shown in (B), the crystalline sapphire film 50 on the substrate 1
(This also has a function of stopping diffusion of ions from the glass substrate 1). Instead of the crystalline sapphire film 50 or under the crystalline sapphire film, a gate insulating film 73 may be provided, and the step 4 may be formed thereon. 31 (C), (D), and (E) show examples in which the crystalline sapphire film 50 is provided with a step 4.

<Fifth Embodiment> A fifth embodiment of the present invention will be described with reference to FIGS.

In the present embodiment, various examples will be described in which each TFT is formed outside the above-described step 4 (ie, on the substrate 1 other than the step). Note that the single-crystal silicon layer 7 and the gate / source / drain electrodes 26 and 27 are schematically illustrated.

First, FIG. 32 shows a top gate type MOSTF.
T is shown. 32A, a recess due to the step 4 is formed on one side of the source along the source region, and the gate insulating film 12 and the gate electrode 11 are formed on the single crystal silicon layer 7 on the flat surface of the substrate other than the recess. Is formed. Similarly, in FIG. 32B, the concave portion due to the step 4 is formed in an L-shaped pattern not only in the source region but also in the channel length direction to the end of the drain region, that is, over two sides. In FIG. 32 (c), the concave portion due to the step 4 is formed in a rectangular shape over four sides so as to surround the TFT active region. In FIG. 32 (d), a concave portion due to the step 4 is formed over three sides. However, adjacent concave portions are not continuous. In FIG. 32 (e), the concave portion due to the step 4 is formed in an L-shaped pattern over two sides. However, adjacent concave portions are not continuous.

As described above, it is possible to form the concave portions due to the steps 4 of the various patterns, and since the TFT is provided on a flat surface other than the concave portions, the degree of freedom in manufacturing the TFT is increased.
The fabrication itself becomes easier.

Next, FIG. 33 shows a bottom gate type MOSTF.
T is shown. As shown in FIGS. 33A to 33D, the steps 4 (or concave portions) of various patterns shown in FIG. 32 can be similarly formed in the bottom gate type MOSTFT. That is, FIG. 33A is an example corresponding to FIG. 32A,
Formed on a flat surface other than the recessed portion. Similarly, FIG. 33B corresponds to FIG.
(C) is an example corresponding to FIGS. 32 (c) and (d). FIG. 33D shows an example in which a step 4 is provided in the crystalline sapphire film 50.

Next, FIG. 34 shows a dual gate type MOS.
3 shows a TFT. As shown in FIGS. 32A and 32B,
Also in the dual gate type MOSTFT, steps 4 (or recesses) of various patterns shown in FIG. 32 can be formed in the same manner. For example, on the flat surface inside the step 4 shown in FIG. A dual-gate MOSTFT can be manufactured.

<Sixth Embodiment> A sixth embodiment of the present invention will be described with reference to FIGS.

In this embodiment, the example shown in FIG. 35 is a double gate type TFT in which a plurality of TFTs having a self-aligned LDD structure, for example, a plurality of top gate type LDD-TFTs are connected.
It relates to the OSTFT. That is, in this example, as shown in FIG. 35, the gate electrode 11 is branched into two, one of which is a first LDD-TF as a first gate.
A second LDD-TF for T and the other as a second gate
Used for T (however, an N ⁺ -type region 100 is provided between gate electrodes at the center of the single crystal silicon layer to reduce the resistance). In this case, a different voltage may be applied to each gate, and even if one of the gates becomes inoperable for some reason, carriers are transferred between the source and the drain by using the remaining gates. Can be a reliable device.

The first LDD-TFT and the second LDD-TFT
Since two thin film transistors for driving each pixel are formed by connecting two D-TFTs in series, the voltage applied between the source and the drain of each thin film transistor in the off state can be greatly reduced. it can. Therefore, the leakage current flowing during the off state can be reduced, and the contrast and the image quality of the liquid crystal display can be improved satisfactorily. Further, since the two LDD-TFTs are connected by using only the same semiconductor layer as that of the low-concentration drain region in the LDD-TFT, the connection distance between the transistors can be reduced, and the LDD-TFT can be reduced. Can be prevented from increasing the required area even if two are connected. The first,
The second gates may be completely separate from each other and operate independently.

In the example shown in FIG. 36A, the bottom gate type MOSTFT has a double gate structure.
The example shown in FIG. 36B is a dual gate type MOST.
The FT has a double gate structure.

These double gate type MOS TFTs have the same advantages as the above-mentioned top gate type.
In particular, the dual gate type has an advantage that even if one of the upper and lower gate portions becomes inoperable, the other gate portion can be used.

FIG. 37 shows each of the aforementioned double-gate MOSs.
1 shows an equivalent circuit diagram of a TFT. In the above description, the gate is branched into two, but the gate may be branched or divided into three or more. Even in these double-gate or multi-gate structures, the channel region can be configured to have two or more branched gate electrodes having the same potential or to have divided gate electrodes having different potentials or the same potential. .

<Seventh Embodiment> Referring to FIG.
A seventh embodiment of the present invention will be described. In this embodiment mode, one of the upper and lower gate portions is operated as a transistor in the dual gate type TFT of the nMOSTFT, but the other gate portion is operated as follows.

That is, in the example shown in FIG.
In the MOSTFT, an arbitrary negative voltage is always applied to the gate electrode on the top gate side to reduce the back channel leakage current. By opening the top gate electrode, it can be used as a bottom gate type. In the example shown in FIG. 38B, an arbitrary negative voltage is always applied to the bottom gate electrode to reduce the leakage current of the back channel. Also in this case, by opening the bottom gate electrode, it can be used as a top gate type. Note that in the case of a pMOSTFT, the back channel leakage current can be reduced by always applying an arbitrary positive voltage to the gate electrode.

In any case, the interface between the single crystal silicon layer 7 and the insulating film has poor crystallinity and a leak current easily flows, but the leak current can be cut off by applying a negative voltage to the electrode as described above. This is advantageous in combination with the effect of the LDD structure. In addition, a leak current may flow due to light incident from the glass substrate 1 side. However, since the light is blocked by the bottom gate electrode, the leak current can be reduced.

<Eighth Embodiment> An eighth embodiment of the present invention will be described with reference to FIGS.

In the embodiment of this example, the above-mentioned step (recess) is not provided on the substrate, and the above-mentioned material layer (for example, a crystalline sapphire film) is formed on the flat surface of the substrate, and this material layer is seeded. The present invention relates to an active matrix reflective liquid crystal display (LCD) in which a single-crystal silicon layer is heteroepitaxially grown by a laser irradiation method and a top-gate type MOSTFT is formed using the single-crystal silicon layer.

The active matrix reflective LCD will be described in accordance with the manufacturing process. In FIGS. 39 to 43, the left side of each drawing shows the manufacturing method (step) of the display section, and the right side shows the manufacturing method (step) of the peripheral drive circuit section.

First, as shown in FIG. 39 (1), borosilicate glass, quartz glass, transparent crystallized glass, and high heat resistant glass (8 to 12 inch φ, 700 to 80
0 μm thickness) on one main surface of the insulating substrate 1.
A crystalline sapphire film 50 having a thickness of 20 to
It is formed to a thickness of about 200 nm. This crystalline sapphire film 5
No. 0 is manufactured by oxidizing trimethylaluminum gas or the like with an oxidizing gas (oxygen or moisture) and crystallizing the same by a high-density plasma CVD method or a catalytic CVD method (see JP-A-63-40314). .

Next, in the same manner as in the step shown in FIG. 1 (3), amorphous silicon or polycrystalline silicon is formed as shown in FIG. 39 (2), followed by laser irradiation. The silicon film is heated and melted, and then cooled and solidified, so that the single-crystal silicon film 7 is formed from the crystalline sapphire film 50 as a seed to several μm to 0.005 μm.
Heteroepitaxial growth is performed to a thickness of m (for example, 0.1 μm).

In the single-crystal silicon layer 7 deposited as described above, for example, the (100) plane is heteroepitaxially grown on the substrate because the crystalline sapphire film 50 shows good lattice matching with single-crystal silicon.

Thus, after the single-crystal silicon layer 7 is deposited on the substrate 1 by heteroepitaxial growth by laser irradiation, the same procedure as described above is performed.
A top gate type MOS TFT using the single crystal silicon layer 7 as a channel region is manufactured as follows.

First, a specific resistance is adjusted by doping a suitable amount of a P-type carrier impurity, for example, boron ions, over the entire surface of the single crystal silicon layer 7 formed by the epitaxial growth.
Further, only the pMOSTFT formation region is selectively doped with an N-type carrier impurity to form an N-type well. For example, a pMOSTFT portion is formed by a photoresist (not shown).
And p-type impurity ions (eg, B ⁺ )
V is doped at a dose of 2.7 × 10 ¹¹ atoms / cm ² to adjust the specific resistance. Also, (3) in FIG.
As shown in ( ¹ ), in order to control the impurity concentration in the pMOSTFT formation region, the nMOSTFT portion is masked with a photoresist 60, and N-type impurity ions (for example, P ⁺ ) 65 are
Doping with V is performed at a dose of 1 × 10 ¹¹ atoms / cm ² to form an N-type well 7A.

Next, as shown in (4) of FIG. 40, SiO ₂ (about 100) is formed on the entire surface of the single crystal silicon layer 7 by plasma CVD, high-density plasma CVD, catalytic CVD, or the like.
nm thick) and SiN (about 200 nm thick) are sequentially formed in this order to form a gate insulating film 8.
Sputtered film 9 of tantalum (Mo.Ta) alloy (300 to
(Thickness: 400 nm).

Next, as shown in (5) of FIG. 40, the TFT in the display area is formed by a general-purpose photolithography technique.
The photoresist pattern 10 is formed in each step region (in the concave portion) of the TFT portion in the peripheral portion and the peripheral drive region, and the photoresist pattern 10 is used as a mask for continuous etching to form the gate electrode 11 of the Mo.Ta alloy. And (Si
A gate insulating film 12 having a laminated structure of (N / SiO ₂ ) is formed, and the single crystal silicon layer 7 is exposed. Note that M
The sputtered film 9 made of an o-Ta alloy is treated with an acid-based etchant, and SiN is plasma-etched with CF ₄ gas.
SiO ₂ is treated with a hydrofluoric acid-based etchant.

Next, as shown in (6) of FIG. 40, all of the nMOS and pMOSTFT in the peripheral drive region and the gate portion of the nMOSTFT in the display region are formed by photoresist 1
3 and cover the exposed source / drain regions of the nMOS TFT with phosphorus ions 14 at, for example, 20 kV and 5 × 1.
By doping (ion implantation) at a dose of 0 ¹³ atoms / cm ^2, the LDD portion 15 made of an N ⁻ -type layer is formed in a self-aligned (self-aligned) manner.

Next, as shown in FIG. 41 (7), all of the pMOS TFTs in the peripheral drive region and n in the peripheral drive region
Gate portion of MOSTFT and nMOSTFT in display area
And the LDD portion are covered with a photoresist 16 and phosphorus or arsenic ions 17
By doping (ion implantation) at 0 kV and a dose of 5 × 10 ¹⁵ atoms / cm ² , the source 18 and the drain 19 and the LDD 15 made of the N ⁺ type layer of the nMOS TFT are formed.

Next, as shown in FIG. 41 (8), the nMOSTFT in the peripheral drive region and the nMOSTT in the display region are used.
The entirety of the FT and the gate of the pMOSTFT are covered with a photoresist 20 and boron ions 2
1 at 5 × 10 ¹⁵ atoms / cm ^{2 at} 10 kV, for example.
Doping (ion implantation) at a dose of pMOST
The source part 22 and the drain part 23 of the P ⁺ layer of the FT are formed. This step is unnecessary in the case of the nMOS peripheral drive circuit because there is no pMOSTFT.

Next, as shown in (9) of FIG.
A photoresist 24 is formed to make an active element portion such as an FT or a diode or a passive element portion such as a resistor or an inductance into an island. Then, the single crystal silicon layer 7 other than all the active element portions and the passive element portions in the peripheral drive region and the display region is removed using a hydrofluoric acid-based etchant.

Next, as shown in FIG. 42 (10),
An SiO ₂ film (about 200 nm thick) and a phosphosilicate glass (PSG) film (about 300 nm thick) are entirely formed by plasma CVD, high-density plasma CVD, catalytic CVD, or the like.
Are successively formed in this order, and the protective film 25 is formed.

Then, in this state, the single crystal silicon layer 7 is activated. For this activation, for example, a lamp of halogen or the like is used, and the annealing condition is set to about 1000.
C. for about 10 seconds. Therefore, a high melting point Mo / Ta alloy that can withstand such annealing conditions is used as the gate electrode material. The gate electrode material is provided not only as a gate portion but also as a wiring over a wide range. When annealing is performed using an excimer laser, XeCl (wavelength of 308 nm) is used.
It is preferable to selectively irradiate the entire surface or only the active element portion and the passive element portion with 90% or more overlap scanning.

Next, as shown in FIG. 42 (11),
By general-purpose photolithography and etching technology, contact windows are opened in the source / drain portions of all the TFTs of the peripheral drive circuit and the source portions of the display TFT.

Then, aluminum or 1% S
a sputtered film of aluminum containing i with a thickness of 500 to 60
It is formed to a thickness of about 0 nm. Further, by using general-purpose photolithography and etching techniques, the source electrodes 26 of all the TFTs in the peripheral driving circuit and the display section and the drain electrodes 27 of the peripheral driving circuit section are formed, and at the same time, the data line and the gate line are formed. To form Thereafter, sintering is performed at about 400 ° C. for 1 hour in a forming gas (N ₂ + H ₂ ).

Next, as shown in FIG. 42 (12),
An insulating film 36 made of a PSG film (about 300 nm thick) and a SiN film (about 300 nm thick) is formed on the entire surface by plasma CVD, high-density plasma CVD, catalytic CVD, or the like. Next, a contact window is opened in the drain portion of the display TFT. It should be noted that SiO ₂ , PSG and S
It is not necessary to remove the iN film.

Next, for the same purpose as described in FIG. 5 (14), as shown in FIG. 43 (13), a photosensitive resin film 28 having a thickness of 2 to 3 μm is formed on the entire surface by spin coating or the like. As shown in (14) of FIG. 43, an uneven pattern for obtaining optimal reflection characteristics and viewing angle characteristics is formed at least in the pixel portion by general-purpose photolithography and etching techniques, and reflowed to form an uneven rough surface 28A. The lower surface of the reflecting surface is formed. At the same time, a resin window for contact of the drain portion of the display TFT is opened.

Next, as shown in FIG. 43 (15),
A sputtered film of aluminum or aluminum containing 1% Si having a thickness of about 400 to 500 nm is formed on the entire surface, and the sputtered film other than the pixel portion is removed by general-purpose photolithography and etching techniques. An aluminum reflection portion 29 having an uneven shape connected to the aluminum reflection portion 29 is formed. This reflection film 29 also functions as a pixel electrode for display. Thereafter, sintering is performed in a forming gas at about 300 ° C. for 1 hour to make the contact sufficient. Note that silver or a silver alloy may be used instead of an aluminum-based material to increase the reflectance.

As described above, the single-crystal silicon layer 7 is formed by the laser irradiation process using the crystalline sapphire film 50 as a seed for heteroepitaxial growth, and the display unit and the peripheral drive circuit unit using the single-crystal silicon layer 7 are formed. Respectively, a top gate type nMOS LDD-TFT, p
A display section-peripheral drive circuit section integrated type active matrix substrate 30 incorporating a CMOS circuit composed of a MOSTFT and an nMOSTFT can be manufactured.

Using this active matrix substrate (drive substrate) 30, a reflection type liquid crystal display (LCD) is manufactured in the same manner as described with reference to FIG.

In this embodiment, it is clear that the excellent effects described in the first embodiment can be obtained. In addition, since the single-crystal silicon layer 7 is heteroepitaxially grown only by the crystalline sapphire film 50 without providing a step on the substrate 1, the step of forming the step can be omitted, and the manufacturing process can be further simplified and the growth can be simplified. Thus, problems such as disconnection of the single crystal silicon layer can be solved.

<Ninth Embodiment> A ninth embodiment of the present invention will be described with reference to FIGS.

This embodiment has a top gate type MOSTFT in the display section and the peripheral drive circuit section, as in the above-described eighth embodiment. It is related to LCD. Therefore, the manufacturing steps are the same from the step shown in FIG. 39A to the step shown in FIG.
Then, in the embodiment of this example, after these steps, as shown in FIG.
At the same time, a window for contacting the drain of the display TFT is opened, and at the same time, in order to improve the transmittance, unnecessary S pixels are not formed in the pixel opening.
The iO ₂ , PSG and SiN films are removed.

Next, as shown in FIG. 45 (14),
On the entire surface, a flattening film 28B of a photosensitive acrylic transparent resin is formed to a thickness of about 2 to 3 μm by spin coating or the like,
TF for display by general-purpose photolithography technology
A window of the flattening film 28B on the drain side of T is opened and cured under predetermined conditions.

Next, as shown in FIG. 45 (15),
An ITO sputtered film having a thickness of about 130 to 150 nm is formed on the entire surface, and an ITO transparent electrode (pixel electrode) 41 that is in contact with the drain portion 19 of the display TFT is formed by general-purpose photolithography and etching technology.
And heat treatment (200-250 in forming gas)
C./1 h), the contact resistance between the drain of the display TFT and ITO is reduced, and the transparency of ITO is improved.

Then, as shown in FIG.
And a transmission type LCD is assembled in the same manner as in the eighth embodiment. However, a polarizing plate is also attached to the TFT substrate side. In this transmissive LCD, transmitted light can be obtained as shown by a solid line arrow, but it can be configured such that transmitted light from the counter substrate 32 side can be obtained as shown by an alternate long and short dash line arrow.

In the case of this transmission type LCD, an on-chip color filter (OCCF) structure and an on-chip black (OCB) structure can be manufactured as follows.

That is, (1) in FIG. 39 to (1) in FIG.
The steps up to 1) are performed in the same manner as described above. Then, as shown in FIG. 47 (12), the PSG /
After opening the drain portion of the SiO ₂ insulating film 25 to form an aluminum buried layer 41A for the drain electrode, an insulating film 36 of SiN / PSG is formed.

Next, as shown in FIG. 47 (13),
After forming a photoresist 61 having a predetermined thickness (1 to 1.5 μm) in which each color of R, G, and B is dispersed in a pigment for each segment, as shown in (14) of FIG. 47, a general-purpose photolithography technique is used. The color filter layers 61 (R) and 61 (R) are patterned while leaving only predetermined positions (each pixel portion).
(G) Form 61 (B) (on-chip color filter structure). At this time, the window of the drain part is also opened. In addition,
In this example, an opaque ceramic substrate, glass having low transmittance, and a heat-resistant resin substrate cannot be used.

Next, as shown in (14) of FIG.
In a contact hole communicating with the drain of the display TFT, a light shielding layer 43 serving as a black mask layer is formed by metal patterning over the color filter layer. For example, titanium or molybdenum is deposited to a thickness of 2 by sputtering.
A film is formed to a thickness of about 100 to 250 nm, and then patterned into a predetermined shape that covers the display TFT and shields light (on-chip black structure).

Next, as shown in (15) of FIG.
A flattening film 28B made of a transparent resin is formed, and a transparent electrode 41 is buried in a through hole provided in the flattening film so as to be connected to the light shielding layer 43.

As described above, by forming the color filter 61 and the light shielding layer 43 on the display array portion, the aperture ratio of the liquid crystal display panel is improved, and the power consumption of the display module including the backlight is reduced. Can be realized.

<Tenth Embodiment> A tenth embodiment of the present invention will be described with reference to FIGS.

In the present embodiment, the peripheral drive circuit section is provided with the same top gate type pM as the eighth embodiment.
It is composed of a CMOS drive circuit composed of an OSTFT and an nMOSTFT. Further, although the display section is of a reflection type, the TFTs have various gate structures and various combinations.

That is, in the above-described eighth embodiment, as shown in FIG. 48A, a top gate type n
While the MOSLDD-TFT is provided, FIG.
In the example shown in (B), the display unit has a bottom gate type nMO.
An SLDD-TFT is provided, and in the example shown in FIG.
A D-TFT is provided. These bottom gate type MOS
Both TFT and dual-gate MOSTFT
Top gate type MOS of peripheral drive circuit section as described later
It can be manufactured in the same process as the TFT. In the case where the gate structure of the TFT of the display portion is changed in this way, especially in the case of a dual gate type, the driving capability is improved by the upper and lower gate portions, which is suitable for high-speed switching. It can be selectively used to operate as a top gate type or a bottom gate type depending on the case.

The bottom gate type MO shown in FIG.
In the STFT, reference numeral 71 in the figure denotes a gate electrode such as Mo / Ta. Reference numeral 72 denotes an SiN film and reference numeral 73 denotes an SiO ₂ film, and the SiN film and the SiO ₂ film form a gate insulating film. On this gate insulating film, a channel region and the like using a single crystal silicon layer 7 are formed similarly to the top gate type MOSTFT. Also, the dual gate type MOSTF shown in FIG.
In T, the lower gate portion is the same as the bottom gate type MOSTFT, but the upper gate portion is the gate insulating film 73.
Is formed of a SiO ₂ film and a SiN film, and an upper gate electrode 74 is provided thereon.

Next, the above-mentioned bottom gate type MOSTFT
49 will be described with reference to FIGS. 49 to 53, and further, a method of manufacturing the dual gate type MOSTFT will be described with reference to FIGS. 54 to 56. Note that the method of manufacturing the top gate type MOSTFT in the peripheral drive circuit section is the same as the steps shown in FIGS. 39 to 43, and thus illustration and description thereof are omitted here.

In the display section, a bottom gate type MOST
To manufacture the FT, first, as shown in FIG. 49A, a molybdenum / tantalum (Mo.Ta)
An alloy sputtered film 71A is formed to a thickness of about 500 to 600 nm.

Next, as shown in FIG. 49 (2), a photoresist 70 is formed in a predetermined pattern, and using this as a mask, the sputtered film 71A is taper-etched, and the side end surface 71a is gently inclined at 20 to 45 °. A gate electrode 71 having a trapezoidal cross section is formed.

Next, after removing the photoresist 70, as shown in FIG. 49 (3), a SiN film (about 200 nm thick) 72 and a SiO ₂ film are formed on the substrate 1 including the sputtered film 71A by a plasma CVD method or the like. (About 100 nm thick) 7
3 are stacked in this order to form a gate insulating film.

Next, in the same manner as in the step shown in FIG. 39A, the crystalline sapphire film 5 is formed on the TFT forming region on one main surface of the insulating substrate 1 as shown in FIG.
0 is formed to a thickness of about 20 to 200 nm.

Next, in the same manner as in the step shown in FIG. 39B, amorphous silicon or polycrystalline silicon is formed on the crystalline sapphire film 50 as shown in FIG. (Not shown) is formed. Subsequently, the silicon film is heated and melted by laser irradiation treatment as described above, and further cooled (slowly cooled) to be solidified, whereby single-crystal silicon is heteroepitaxially grown on the crystalline sapphire film 50. To be precipitated. At this time, the side edge 71a of the underlying gate electrode 71 has a gentle slope. Without this, the single crystal silicon layer 7 grows.

Next, (3) in FIG. 39 to (5) in FIG.
After the step shown in FIG. 40, in the same manner as in the step shown in FIG.
The gate portion of the FT is covered with a photoresist 13, and the exposed source / drain regions of the nMOS TFT are doped (ion-implanted) with phosphorus ions 14 to form an LDD portion 15 made of an N ⁻ -type layer in a self-aligned manner. At this time, the surface height difference (or pattern) is easily recognized by the presence of the bottom gate electrode 71, and the alignment (mask alignment) of the photoresist 13 is easily performed, so that misalignment hardly occurs.

Next, in the same manner as in the step shown in FIG. 41 (7), the gate portion and the LDD portion of the nMOS TFT are covered with the photoresist 16 as shown in FIG. Arsenic ions 17 are doped (ion-implanted) to form a source portion 18 and a drain portion 19 made of an N ⁺ type layer of the nMOS TFT.

Next, in the same manner as in the step shown in FIG. 41 (8), as shown in FIG.
Is covered with a photoresist 20, and boron ions 21 are doped (ion-implanted) to form a source portion and a drain portion of a P ⁺ layer of a pMOS TFT of a peripheral drive circuit portion.

Next, in the same manner as in the step shown in FIG. 41 (9), as shown in FIG. 51 (9), the photoresist 24
Is provided, and the single crystal silicon layer 7 is selectively removed by etching.

Next, in the same manner as in the step shown in FIG. 42 (10), as shown in FIG.
A SiO ₂ film 53 (about 300 nm thick) and a phosphosilicate glass (PSG) film 54 (about 300 nm thick) are continuously formed in this order on the entire surface by VD, high-density plasma CVD, catalytic CVD, or the like. Note that the SiO ₂ film 53 and the PSG
The film 54 corresponds to the protective film 25 described above. Then, in this state, the single crystal silicon layer 7 is activated in the same manner as described above.

Next, in the same manner as in the step shown in FIG. 42 (11), as shown in FIG. 52 (11), a contact window is opened in the source portion by general-purpose photolithography and etching techniques. And the thickness 400
A sputtered film of aluminum or aluminum containing 1% Si is formed to a thickness of about 500 nm, and the source electrode 2 of the TFT is formed by general-purpose photolithography and etching technology.
At the same time as forming 6, a data line and a gate line are formed. Then, in the forming gas,
Sinter at about 400 ° C. for 1 hour.

Next, in the same manner as in the step shown in FIG. 42 (12), as shown in FIG. 52 (12), the PSG film (about 30
An insulating film 36 of 0 nm thick and a SiN film (about 300 nm thick) is formed on the entire surface, and a contact window is opened in the drain of the display TFT.

Next, in the same manner as in the step shown in FIG. 43 (13), a photosensitive resin film 28 having a thickness of about 2 to 3 μm is formed by spin coating or the like as shown in FIG. 52 (13). Subsequently, in the same manner as in the step shown in FIG. 43 (14), as shown in FIG. 52 (14), by using general-purpose photolithography and etching techniques, an uneven shape for obtaining optimal reflection characteristics and viewing angle characteristics is obtained. A pattern is formed in the pixel portion, and reflow is performed to form a lower reflective surface made of the roughened surface 28A. At the same time, a resin window for contact of the drain portion of the display TFT is opened.

Next, in the same manner as in the step shown in FIG. 43 (15), the entire surface is formed as shown in FIG. 52 (14).
A sputtered film of aluminum or aluminum containing 1% Si having a thickness of 0 to 500 nm is formed, and an uneven aluminum reflection portion 29 connected to the drain portion 19 of the display TFT is formed by general-purpose photolithography and etching technology.
To form

As described above, single crystal silicon layer 7 is formed by laser irradiation treatment using crystalline sapphire film 50 as a seed for heteroepitaxial growth, and a bottom gate type nMO is formed on a display portion using this single crystal silicon layer 7.
SLDD-TFT (pMOSTFT and nM in peripheral area)
A display unit-peripheral drive circuit unit integrated active matrix substrate 30 incorporating a CMOS drive circuit comprising OSTFTs) can be manufactured.

FIG. 53 shows an example in which the gate insulating film of the bottom gate type MOSTFT provided in the display portion is formed by an anodic oxidation method of Mo · Ta.

In this example, the molybdenum-tantalum alloy film 71 is subjected to a known anodic oxidation treatment as shown in FIG. 53 (3) after the process shown in FIG. _A gate insulating film 74 of ₂ O ₅ is formed to a thickness of 100 to 200 nm.

Thereafter, a crystalline sapphire film 50 is formed as shown in FIG. 53 (4) in the same manner as in the steps (4) to (5) of FIG. Polycrystalline silicon is formed to form a silicon film (not shown). Next, the silicon film is heated and melted by laser irradiation treatment, and further cooled (slowly cooled) to be solidified, thereby heteroepitaxially growing on the crystalline sapphire film 50 to form the single crystal silicon film 7. Next, the active matrix substrate 30 is manufactured as shown in FIG. 53 (5) in the same manner as the steps shown in FIGS. 50 (6) to 52 (14).

In the display section, a dual gate type MOS
In order to manufacture a TFT, first, FIG.
The same processing as the step (5) is performed.

Next, as shown in FIG. 54 (6), a crystalline sapphire film 50 is formed on the insulating films 72 and 73.
Subsequently, amorphous silicon or polycrystalline silicon is formed on the crystalline sapphire film 50 to form a silicon film. Next, the silicon film is heated and melted by a laser irradiation process, and further cooled (slowly cooled), so that the single-crystal silicon layer 7 is formed using the crystalline sapphire film 50 as a seed.
Is heteroepitaxially grown. Next, in the same manner as in the step shown in FIG.
Si over the entire upper surface by plasma CVD, catalytic CVD, etc.
O ₂ film (about 100 nm thick) and SiN film (about 200 nm thick)
Are sequentially formed in this order to form an insulating film 80 (which corresponds to the above-described insulating film 8).
A sputtered film 81 made of an alloy (this corresponds to the aforementioned sputtered film 9) is formed to a thickness of about 500 to 600 nm.

Next, in the same manner as in the step shown in FIG. 40 (5), a photoresist pattern 10 is formed as shown in FIG.
-Top gate electrode 82 of Ta alloy and gate insulating film 8
3 is formed to expose the single crystal silicon layer 7.

Next, in the same manner as in the step shown in FIG. 40 (6), as shown in FIG.
Is covered with a photoresist 13, and the source / drain regions of the exposed nMOSTFT for display are doped (ion-implanted) with phosphorus ions 14, and N
^- -type layer to form the LDD portion 15.

Next, in the same manner as in the step shown in FIG. 41 (7), the gate portion and the LDD portion of the nMOS TFT are covered with the photoresist 16 as shown in FIG. Arsenic ions 17 are doped (ion-implanted) to form a source portion 18 and a drain portion 19 made of an N ⁺ type layer of the nMOS TFT.

Next, in the same manner as in the step shown in FIG. 41 (8), as shown in FIG.
The gate portion of T is covered with a photoresist 20 and the exposed region is doped with boron ions 21 (ion implantation).
Then, the source portion and the drain portion of the P ⁺ layer of the pMOSTFT of the peripheral drive circuit portion are formed.

Next, in the same manner as in the step shown in FIG. 41 (9), a photoresist 24 is provided for islanding the active element portion and the passive element portion as shown in FIG. The single crystal silicon layer other than the element portion and the passive element portion is selectively removed by general-purpose photolithography and etching techniques.

Next, in the same manner as in the step shown in FIG. 42 (10), as shown in FIG.
VD, high-density plasma CVD, catalytic CVD, etc.
An SiO ₂ film 53 (about 200 nm thick) and a phosphosilicate glass (PSG) film 54 (about 300 nm thick) are formed on the entire surface. These films 53 and 54 correspond to the protective film 25 described above. Then, the single crystal silicon layer 7 is activated.

Next, in the same manner as in the step shown in FIG. 42 (11), a contact window is opened in the source portion as shown in FIG. 55 (13). And 400 to 5 on the whole surface
A sputtered film made of aluminum having a thickness of about 00 nm or aluminum containing 1% Si is formed, and the source electrode 2 is formed by general-purpose photolithography and etching techniques.
At the same time as forming 6, a data line and a gate line are formed.

Next, in the same manner as in the step shown in FIG. 43 (13), as shown in FIG. 56 (14), an insulating film 36 consisting of a PSG film (about 300 nm thick) and a SiN film (about 300 nm thick). Is formed on the entire surface, and TF for display is further formed.
A contact window is opened in the drain portion of T.

Next, as shown in (15) of FIG.
A photosensitive resin film 28 having a thickness of about 2 to 3 μm is formed on the entire surface by spin coating or the like. Subsequently, (14) in FIG.
Similarly to the process shown in (15), (16) in FIG.
As shown in (1), the lower part of the reflective surface composed of the roughened surface 28A is formed in the pixel part, and at the same time, the resin window for the contact of the drain part of the display TFT is opened and further connected to the drain part 19 of the display TFT. Reflection portion 29 made of an aluminum alloy or the like having an uneven shape for obtaining excellent reflection characteristics and viewing angle characteristics.
To form

As described above, the single crystal silicon layer 7 formed by using the crystalline sapphire film 50 as a seed for heteroepitaxial growth by laser irradiation is formed.
A dual gate type nMOS LDD-TFT is used for a display unit using the single crystal silicon layer 7 and a p-type transistor is used for a peripheral drive circuit unit.
The display-peripheral drive circuit unit integrated type active matrix substrate 30 in which CMOS drive circuits each including a MOSTFT and an nMOSTFT are built can be manufactured.

<Eleventh Embodiment> The eleventh embodiment of the present invention will be described with reference to FIGS.

In the present embodiment, unlike the above-described embodiments, the gate electrode of the top gate portion is formed of a material having relatively low heat resistance such as an aluminum alloy.

First, a case where a top gate type MOSTFT is provided in both the display portion and the peripheral drive circuit portion will be described. In this example, first, the steps are performed in the same manner as the steps shown in (1) to (3) of FIG. 39 in the above-described eighth embodiment, and then, as shown in (3) of FIG. An N-type well 7A is formed in the pMOSTFT portion of the circuit portion.

Next, as shown in (4) of FIG. 57, all of the nMOS and pMOSTFTs in the peripheral driving region and the gate portion of the nMOSTFT in the display region are formed by photoresist 1
3 and cover the exposed source / drain regions of the nMOS TFT with phosphorus ions 14 at, for example, 20 kV and 5 × 10 5
^By doping (ion implantation) at a dose of ¹³ atoms / cm ² , an LDD portion 15 made of an N ⁻ -type layer is formed in a self-aligned manner.

Next, as shown in FIG. 58 (5), all the pMOS TFTs in the peripheral drive region and n in the peripheral drive region
Gate portion of MOSTFT and nMOSTFT in display area
And the LDD portion are covered with a photoresist 16 and phosphorus or arsenic ions 17
By doping (ion implantation) at 0 kV and a dose of 5 × 10 ¹⁵ atoms / cm ² , the source 18 and the drain 19 and the LDD 15 made of the N ⁺ type layer of the nMOS TFT are formed. In this case, the resist 13 is left as shown by a dashed line in FIG.
Is provided, it is possible to perform the mask alignment at the time of forming the resist 16 using the resist 13 as a guide, thereby facilitating the mask alignment and reducing the misalignment.

Next, as shown in FIG. 58 (6), the nMOSTFT in the peripheral drive region and the nMOST in the display region are used.
The entire FT and the gate portion of the pMOSTFT are covered with a photoresist 20, and the exposed region is doped (ion-implanted) with boron ions 21 at, for example, 10 kV and at a dose of 5 × 10 ¹⁵ atoms / cm ² , and the PMOS TFT P
The source part 22 and the drain part 23 of the ⁺ layer are formed.

Next, the resist 20 is removed.
As shown in FIG. 58 (7), the single-crystal silicon layers 7, 7A
Is activated in the same manner as described above, and a gate insulating film 12 and a gate electrode material (aluminum or 1% S
i-containing aluminum or the like) 11 is formed. The gate electrode material layer 11 can be formed by a vacuum evaporation method or a sputtering method.

[0276] Then, by patterning the respective gate portion in the same manner as described above, then, an island and an active element portion and the passive element portion, further as shown in (8) in FIG. 59, SiO ₂ film on the entire surface (About 200 nm thick) and a phosphor silicate glass (PSG) film (about 300 nm) are successively formed in this order to form a protective film 25.

Next, as shown in FIG. 59 (9), contact windows are opened in the source / drain portions of all the TFTs of the peripheral drive circuit and the source portion of the display TFT by general-purpose photolithography and etching techniques. .

Then, a sputtered film of aluminum or aluminum containing 1% Si having a thickness of 500 to 600 nm is formed on the entire surface, and the source electrodes 26 of all the TFTs in the peripheral driving circuit and the display section are formed by general-purpose photolithography and etching technology. A data line and a gate line are formed at the same time as the formation of the drain electrode 27 of the peripheral driving circuit. Thereafter, sintering is performed in a forming gas (N ₂ + H ₂ ) at about 400 ° C. for 1 hour.

Next, (12) in FIG. 42 to (1) in FIG.
By performing in the same manner as in the step shown in 5), a top gate type nMOS LDD-TFT, pMOSTFT and nMOT using aluminum as a gate electrode are respectively provided in the display section using the single crystal silicon layer 7 and the peripheral drive circuit section.
It is possible to manufacture an active matrix substrate 30 incorporating a display section and a peripheral drive circuit section, in which a CMOS drive circuit constituted by an STFT is built.

In the present embodiment, the gate electrode 11 made of aluminum or aluminum containing 1% Si is formed after the activation treatment of the single crystal silicon layer 7, so that the influence of heat during the activation treatment is not limited to the gate electrode. Since it has no relation to the heat resistance of the material, the heat resistance of the top gate electrode material is relatively low, and low-cost aluminum or aluminum or copper containing 1% Si can be used. This is because the display unit is a bottom gate type MO
The same is true for the STFT.

Next, a dual gate type MOST is provided in the display section.
A case where a top gate type MOSTFT is provided in the FT and the peripheral driving circuit will be described. In this example, first, the same processes as those shown in FIGS. 27 (6) to 29 (13) in the third embodiment are performed, and the display portion and the peripheral drive circuit portion are respectively made of aluminum alloy. -Gate type nMOSLDD-TF with gate electrode etc.
CM composed of T, pMOSTFT and nMOSTFT
An active matrix substrate 30 integrated with a display unit and a peripheral driving circuit unit, in which an OS driving circuit is built, can be manufactured.

<Twelfth Embodiment> A twelfth embodiment of the present invention will be described with reference to FIGS.

The example shown in FIG. 60 relates to a TFT having a self-aligned LDD structure, for example, a double-gate MOSTFT in which a plurality of top-gate LDD-TFTs are connected in the eighth embodiment.

In the example shown in FIG. 61A, the bottom gate type MOSTFT has a double gate structure.
The example shown in FIG. 61B is a dual gate type MOST.
The FT has a double gate structure.

These double-gate MOSTFTs have the same advantages as those shown in FIGS. 35 to 37.

<Thirteenth Embodiment> A thirteenth embodiment of the present invention will be described with reference to FIGS.

As described above, the top gate type, bottom gate type, and dual gate type TFTs each have a difference in structure or function or a feature. In some cases, it may be advantageous to provide various combinations of TFTs between these components.

For example, as shown in FIG. 62, when any one of a top gate type, a bottom gate type, and a dual gate type MOSTFT is adopted for the display portion, the top gate type MOSTFT and the bottom gate type MOSTFT are used for the peripheral driving circuit.
Of the TFT and the dual gate type MOSTFT, it is possible to employ at least a top gate type or to mix them. There are twelve (No. 1 to No. 12) combinations. In particular, when a dual gate structure is used for the MOSTFT of the peripheral drive circuit,
Such a dual gate structure can be easily changed to a top gate type or a bottom gate type by selecting upper and lower gate portions, and a TFT having a large driving capability is required in a part of the peripheral driving circuit. In some cases, a dual gate type may be required. For example, it is considered necessary when the present invention is applied to the organic EL or FED of the present invention as an electro-optical device other than the LCD.

FIGS. 63 and 64 show the MOSTFT of the display section.
65 and FIG. 66 show the case where the MOSTFT of the display section has the LDD structure when FIG.
Reference numeral 8 denotes a TF having an LDD structure in which a MOSTFT in a peripheral drive circuit section has an LDD structure.
69, FIG. 69 and FIG. 70 show respective MOSTs of the peripheral drive circuit unit and the display unit when both the peripheral drive circuit unit and the display unit include the MOSD with the LDD structure.
It is a figure which shows the various examples (No.1-No.216) which showed the combination of FT according to channel conductivity type.

As described above, the combination of each gate structure shown in FIG. 62 is specifically as shown in FIGS. In this case, the same combination is possible even when the peripheral drive circuit section is made of a MOS TFT mixed with other gate types of the top gate type. FIG.
The various combinations of the TFTs shown in FIGS.
The present invention is not limited to the case where the channel region or the like is formed of single-crystal silicon, but is similarly applicable to the case where the channel region is formed of polycrystalline silicon or amorphous silicon (however, only the display portion).

<Fourteenth Embodiment> A fourteenth embodiment of the present invention will be described with reference to FIGS.

In the present embodiment, in the active matrix drive LCD, a TFT using the above-described single crystal silicon layer based on the present invention is provided in a peripheral drive circuit portion thereof in order to improve the drive capability. However, this is not limited to the top gate type, other gate types may be mixed, the channel conductivity type may be various, and a MOSTF using a polycrystalline silicon layer other than a single crystal silicon layer may be used.
T may be included. On the other hand, the MOS
Although it is desirable to use a single crystal silicon layer for the TFT, the present invention is not limited to this, and a TFT using a polycrystalline silicon or amorphous silicon layer may be used.
A mixture of two types of silicon layers may be used. However, when the display portion is formed of an nMOS TFT, a practical switching speed can be obtained even if the display portion is formed using an amorphous silicon layer, but the TFT area can be reduced in single crystal silicon or polycrystalline silicon, and the pixel area can be reduced. It is more advantageous than amorphous silicon in reducing defects. In the above-described heteroepitaxial growth, not only single-crystal silicon but also polycrystalline silicon is produced at the same time, so-called CGS (Continuous grain silicide).
On) structures may be included, but can also be used to form active and passive devices.

FIG. 71 shows examples (A), (B) and (C) of various combinations of MOSTFTs between the parts, and FIG. 72 shows specific examples. When single crystal silicon is used, the current capability is improved, so that the element can be made smaller, a high definition and a large screen can be realized, and the aperture ratio and the luminance in the display portion can be improved.

In the peripheral drive circuit section, the above-described MOS is used.
It goes without saying that not only the TFT but also an electronic circuit in which a diode, a capacitance, a resistance, an inductance and the like are integrated may be integrally formed on an insulating substrate (a glass substrate or the like).

<Fifteenth Embodiment> A fifteenth embodiment of the present invention will be described with reference to FIG.

In the embodiment of this embodiment, the embodiments described above are applied to the passive matrix drive, while the embodiments described above relate to the example of the active matrix drive.

That is, in the present embodiment, the display section is provided with no switching element such as the MOSTFT described above, and the incident light of the display section is determined only by the potential difference caused by the voltage applied between the pair of electrodes formed on the opposing substrate. Alternatively, the reflected light is dimmed. Such dimming elements include reflective and transmissive LCDs, ELs (electroluminescent display elements), FEDs (field emission display elements), LEPDs (light emitting polymer display elements), and LEDs (light emitting diode display elements). Also included.

<Sixteenth Embodiment> Referring to FIG. 74, a sixteenth embodiment of the present invention will be described.

In this embodiment, the present invention is applied to an electro-optical device other than an LCD, such as an organic or inorganic EL (electroluminescence element), an FED (field emission display element), or the like.
It is applied to LEPD (light emitting polymer display element), LED (light emitting diode display element) and the like.

FIG. 74A shows an active matrix driven EL element. This EL element is, for example, an organic EL layer (or ZnS: M) using an amorphous organic compound.
An inorganic EL layer using n) 90 is provided on the substrate 1, the transparent electrode (ITO) 41 described above is formed below the substrate 1, and the cathode 91 is formed above the same. Thus, light of a predetermined color can be obtained through the color filter layer 61.

In this EL element, a MOSTFT is formed on the substrate 1 in order to apply a data voltage to the transparent electrode 41 by active matrix driving. This MOSTFT is formed by a sapphire film 50 (and a step) on the substrate 1. 4) Single-crystal silicon MOSTFT according to the present invention using a single-crystal silicon layer obtained by heteroepitaxial growth by laser irradiation using seed as a seed
(That is, nMOSLDD-TFT). Also,
A similar TFT is provided in a peripheral driving circuit. Since the EL element having such a configuration is driven by a MOSLDD-TFT using a single crystal silicon layer, the switching speed is high and the leakage current is small.

[0302] The above filter 61
If the L layer 90 emits a specific color, it can be omitted. In the case of an EL element, since a driving voltage is high, it is advantageous to provide a high-withstand-voltage driver element (such as a high-withstand-voltage cMOSTFT and a bipolar element) in addition to the MOSTFT in the peripheral drive circuit portion.

FIG. 74B shows an FED driven by passive matrix. In this FED, electrons emitted from the cold cathode 94 by the voltage applied between the electrodes 92 and 93 are incident on the opposing phosphor layer 96 by selecting the gate line 95 in a vacuum portion between the opposing glass substrates 1-32. Thus, light emission of a predetermined color is obtained.

Here, the emitter line 92 is led to a peripheral drive circuit and driven by a data voltage. The peripheral drive circuit is provided with a MOSTFT made of a single crystal silicon layer formed according to the present invention. , Emitter line 9
2 which contributes to high-speed driving. The FED can be driven in an active matrix by connecting the MOSTFT to each pixel.

In the element shown in FIG.
If a known light emitting polymer is used instead of the layer 90, a passive matrix or active matrix driven light emitting polymer display device (LEPD) can be formed. In addition, a device similar to the FED using the diamond thin film on the cathode side in the element of FIG. 74B can also be configured. Further, in a light emitting diode, for example, a gallium-based (gallium.
A light-emitting portion made of a film of aluminum, arsenic, etc.) can be driven. Alternatively, it is conceivable to grow the film of the light emitting portion by single crystal by the epitaxial growth method of the present invention.

The embodiments of the present invention described above can be variously modified based on the technical concept of the present invention.

For example, to prevent diffusion of ions from a glass substrate, a SiN film (for example, 50 to 200 nm) is formed on the substrate surface.
m thick) and, if necessary, a SiO ₂ film (for example, 10
(Thickness of 0 nm), or the step 4 described above may be formed in these films. The above-described step can be formed by an ion milling method or the like in addition to RIE. Further, as described above, it is a matter of course that the step 4 may be formed within the thickness of the crystalline sapphire film or the sapphire substrate itself other than forming the step 4 on the substrate 1.

The sapphire (Al ₂ O ₃ )
Instead, a spinel structure (for example, magnesia spinel) having good lattice matching with single crystal silicon (Mgo.Al ₂
O ₃ ), CaF ₂ , SrF ₂ , BaF ₂ , BP, (Y
₂ O ₃ ) _m , (ZrO ₂ ) _{1-m and the} like can be used.

Although the present invention is suitable for a peripheral drive circuit and a TFT of a display unit, the present invention also provides an active region of an element such as a diode and a passive region such as a resistor, a capacitor, and an inductance according to the present invention. It is also possible to form with a single crystal silicon layer.

[0310]

As described above, according to the present invention, a semiconductor film formed on a material layer (for example, a crystalline sapphire film) having good lattice matching with single crystal silicon is used as a seed. By heating and melting by laser irradiation treatment and further solidifying by cooling, heteroepitaxial growth is performed to form a single crystal semiconductor layer such as a single crystal silicon layer,
This epitaxial growth layer is used as a top gate type MO for a peripheral drive circuit of a drive substrate such as an active matrix substrate.
Active elements such as STFT and a top gate type MOSTFT of a peripheral drive circuit in an electro-optical device such as an LCD integrated with a display unit and a peripheral drive circuit, and at least an active element among passive elements such as resistance, inductance, and capacitance. Since it is used, it has the following remarkable effects (A) to (G).

(A) A material layer (for example, a crystalline sapphire film) having good lattice matching with single crystal silicon is formed on a substrate,
By heteroepitaxially growing the material layer as a seed, a single crystal semiconductor layer such as a single crystal silicon layer having a high electron mobility of 540 cm ² / v · sec or more can be obtained. And the like can be manufactured.

(B) In particular, the single crystal silicon layer has high electron and hole mobilities comparable to those of a single crystal silicon substrate as compared with a conventional amorphous silicon layer or a polycrystalline silicon layer. Gate type M
The OSTFT has a high switching characteristic [preferably, an LDD (Li
ghtly doped drain) structure] nMOS or pM
A display unit composed of an OSTFT or a cMOSTFT, a cMOS, an nMOS, or a pMOSTFT having a high driving capability;
Alternatively, it becomes possible to integrate a peripheral drive circuit section composed of a mixture of these, and a display panel with high image quality, high definition, narrow frame, high efficiency, and large screen is realized. In particular, polycrystalline silicon has a high hole mobility p as a TFT for LCD.
Although it is difficult to form a MOSTFT, in the single-crystal silicon layer according to the present invention, since a hole shows a sufficiently high mobility, a peripheral driving circuit for driving electrons and holes individually or in combination of both. Can be produced, and this is referred to as LDD of nMOS or pMOS or cMOS.
A panel integrated with a display-use TFT having a structure can be realized. In the case of a small to medium-sized panel, there is a possibility that one of a pair of peripheral vertical drive circuits can be omitted.

(C) A single crystal semiconductor layer such as a single crystal silicon layer can be formed by using the material layer as a seed for heteroepitaxial growth and subjecting the semiconductor film to laser irradiation on the material layer. In addition, a single-crystal silicon layer or the like can be uniformly formed on a substrate at a low temperature. Therefore, a glass substrate having a relatively low strain point, a heat-resistant organic substrate, or the like can be easily obtained, a low-cost substrate having good physical properties can be used, and the substrate can be enlarged.

(D) Since annealing at a medium temperature for a long time (about 600 ° C., more than ten hours) as in the case of the solid phase growth method is not required, productivity is high, and expensive manufacturing equipment is not required and cost is reduced. Becomes possible.

(E) In this heteroepitaxial growth, a wide range of p-type or p-type is adjusted by adjusting the crystallinity of the material layer such as crystalline sapphire, the irradiation energy and irradiation time of the laser, and the heating temperature and cooling rate of the substrate. Since an N-type conductivity type and a high-mobility single-crystal silicon layer can be easily obtained, Vth (threshold) adjustment becomes easy, and high-speed operation can be performed by lowering the resistance.

(F) In addition, a semiconductor (amorphous silicon or polycrystalline silicon) film on the material layer, or a single crystal semiconductor layer (single crystal silicon layer) obtained by irradiating the film with a laser, is n-type or p-type. Impurities (boron, phosphorus, antimony, arsenic, bismuth, aluminum, etc.) are mixed (introduced) into the single crystal semiconductor layer (single crystal silicon layer) and / or its concentration, that is, P-type / N The conductivity type such as the mold and / or the carrier concentration can be arbitrarily controlled.

(G) Since the above-mentioned material layer such as a crystalline sapphire film serves as a diffusion barrier for various atoms, diffusion of impurities from the glass substrate can be suppressed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of an LCD (Liquid Crystal Display) according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 3 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 4 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 5 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 6 is a sectional view of an essential part of the LCD.

FIG. 7 is a schematic perspective view for explaining the state of silicon crystal growth on an amorphous substrate.

FIG. 8 is a schematic sectional view showing various step shapes and a silicon growth direction in the grapho-epitaxial growth technique.

FIG. 9 is a perspective view showing an overall schematic layout of the LCD according to the first embodiment of the present invention.

FIG. 10 is an equivalent circuit diagram of the LCD.

FIG. 11 is a schematic configuration diagram of the same LCD.

FIG. 12 is a cross-sectional view showing a manufacturing process of the LCD according to the second embodiment of the present invention in the order of steps.

FIG. 13 is a cross-sectional view of a main part of the LCD.

FIG. 14 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 15 is a sectional view of a main part of an LCD according to a third embodiment of the present invention.

FIG. 16 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 17 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 18 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 19 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 20 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 21 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 22 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 23 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 24 is a sectional view illustrating the manufacturing process of the LCD according to the fourth embodiment of the present invention in the order of steps.

FIG. 25 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 26 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 27 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 28 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 29 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 30 is a fragmentary cross-sectional view of the same at the time of manufacturing the LCD;

FIG. 31 is a fragmentary cross-sectional view of the same at the time of manufacturing the LCD;

FIG. 32 is a plan view or a sectional view showing various TFTs of an LCD according to a fifth embodiment of the present invention.

FIG. 33 is a cross-sectional view showing various TFTs at the time of manufacturing the LCD.

FIG. 34 is a cross-sectional view of a main part of the same LCD.

FIG. 35 is a sectional view or a plan view of a main part of an LCD according to a sixth embodiment of the present invention.

FIG. 36 is a sectional view of a principal part of various TFTs of the LCD.

FIG. 37 is an equivalent circuit diagram of a TFT of the LCD.

FIG. 38 shows T of the LCD according to the seventh embodiment of the present invention.
It is principal part sectional drawing of FT.

FIG. 39 is a cross-sectional view showing a manufacturing process of the LCD according to the eighth embodiment of the present invention in the order of steps;

FIG. 40 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 41 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 42 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 43 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 44 is a cross-sectional view of a main part of the same LCD.

FIG. 45 is a sectional view showing the manufacturing process of the LCD according to the ninth embodiment of the present invention in the order of steps.

FIG. 46 is a cross-sectional view of a main part of the LCD.

FIG. 47 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 48 is a cross-sectional view of a main part of an LCD according to a tenth embodiment of the present invention.

FIG. 49 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 50 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 51 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 52 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 53 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 54 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 55 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 56 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 57 is a cross-sectional view showing a manufacturing process of the LCD according to the eleventh embodiment of the present invention in the order of steps;

FIG. 58 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 59 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 60 is a sectional view or plan view of a main part of an LCD according to a twelfth embodiment of the present invention.

FIG. 61 is a cross-sectional view of a principal part of various TFTs of the LCD.

FIG. 62 is a diagram showing a combination of TFTs of each part of the LCD according to the thirteenth embodiment of the present invention.

FIG. 63 is a diagram showing combinations of TFTs of each part of the LCD.

FIG. 64 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 65 is a diagram showing combinations of TFTs of each part of the LCD.

FIG. 66 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 67 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 68 is a view showing a combination of TFTs of each part of the LCD.

FIG. 69 is a view showing a combination of TFTs in each part of the LCD.

FIG. 70 is a diagram showing combinations of TFTs of each part of the LCD.

FIG. 71 is a schematic layout diagram of an LCD according to a fourteenth embodiment of the present invention.

FIG. 72 is a view showing a combination of TFTs in each part of the LCD.

FIG. 73 is a schematic layout diagram of a device according to a fifteenth embodiment of the present invention;

FIG. 74 is a sectional view of a main part of an EL and FED according to a sixteenth embodiment of the present invention;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate, 4 ... Step, 7 ... Single crystal silicon layer, 9 ... Sputtered film, 11 ... Gate electrode, 12 ... Gate oxide film, 1
4, 17 ... N-type impurity ions, 15 ... LDD part, 18,
19 ... N ⁺ type source or drain region, 21 ... P type impurity ion, 22, 23 ... P ⁺ source or drain region,
25, 36 ... insulating films, 26, 27, 31, 41 ... electrodes,
29: reflective film, 30: LCD (TFT) substrate, 50: crystalline sapphire film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/786 H01L 29/78 612B 5F110 21/336 613A 616A 616M 617N 627G F-term (Reference) 2H090 HA03 HB03X HB07X HD02 HD03 HD05 HD06 JA02 JB03 JB04 JC01 JD01 KA05 KA06 KA08 KA09 KA11 KA14 KA15 LA04 LA15 2H091 FA02Y FA11Z FA35Y FD04 GA07 GA13 GA16 HA07 HA08 HA10 HA11 HA12 LA11 LA15 2H092 GA59 J28 JA24 JA25 J26 JA26 JA26 KA05 KA10 KA12 KA18 KA19 MA04 MA05 MA07 MA08 MA18 MA19 MA24 MA27 MA30 MA37 MA41 NA04 NA07 NA19 NA21 NA27 PA01 PA06 PA08 PA09 PA10 PA11 PA13 2H093 NA16 NA42 NA43 NC22 NC28 NC29 NC33 NC34 NC50 ND17 NE06 NF05 NF13 NF05 NF13 NF05 A5 BB07 DA02 GA01 GB06 HA08 JA01 JA10 5F110 AA01 AA06 AA08 AA17 AA18 BB02 BB04 CC02 CC06 CC08 DD01 DD02 DD04 DD07 DD12 DD13 DD14 DD17 DD21 DD24 EE03 EE04 EE06 EE23 EE28 EE30 EE44 FF01 FF02 FF03 FF09 FF10 FF29 FF30 GG01 GG02 GG13 GG13 GG13 GG04 HL11 HL23 HL27 HM12 HM15 NN03 NN04 NN23 NN24 NN25 NN27 NN35 NN46 NN54 NN71 NN72 NN73 NN78 PP03 PP04 PP06 PP08 PP23 PP27 PP36 QQ04 QQ05 QQ09 QQ11 QQ12 QQ19

Claims (190)

[Claims] 1. A display device comprising: a display portion on which a pixel electrode is disposed; and a peripheral driver circuit portion disposed around the display portion on a first substrate. An electro-optical device having a predetermined optical material interposed therebetween, wherein a material layer having good lattice matching with a single crystal semiconductor is formed on one surface of the first substrate; A single-crystal semiconductor formed by heteroepitaxially growing a film made of a semiconductor formed on the material layer on a substrate by heating and melting by laser irradiation treatment and further cooling and solidifying the film using the material layer as a seed; An electro-optical device, wherein a layer is formed, and the single crystal semiconductor layer forms at least an active element of an active element and a passive element. 2. The electro-optical device according to claim 1, wherein the film made of the semiconductor is amorphous silicon or polycrystalline silicon, and the single crystal semiconductor layer is a single crystal silicon layer. 3. The method according to claim 1, wherein the single crystal semiconductor layer is an N-type or P-type semiconductor layer.
3. The electro-optical device according to claim 2, wherein the specific resistance is adjusted by mixing the type of carrier impurity. 4. A top-gate first thin film transistor having a single crystal semiconductor layer as a channel region, a source region, and a drain region and having a gate portion above the channel region, wherein at least one of the peripheral driver circuit portions is provided. The electro-optical device according to claim 2, which constitutes a part. 5. An insulating substrate is used as the first substrate, and the material layer is sapphire, spinel structure, calcium fluoride, strontium fluoride, barium fluoride,
3. A material formed from a material selected from the group consisting of boron phosphide, yttrium oxide and zirconia.
An electro-optical device according to claim 1. 6. The electro-optical device according to claim 2, wherein a diffusion barrier layer is provided between the first substrate and the single crystal semiconductor layer. 7. The electro-optical device according to claim 2, wherein the gate portion below the single-crystal silicon layer has a trapezoidal shape at a side end thereof. 8. The method according to claim 1, wherein the peripheral drive circuit section includes the first drive circuit.
A top-gate, bottom-gate or dual-gate thin-film transistor having a polycrystalline or amorphous silicon layer as a channel region and a gate portion above and / or below the channel region, or the single-crystal silicon Diode using a layer or a polycrystalline silicon layer or an amorphous silicon layer,
5. The electro-optical device according to claim 4, wherein a resistance, a capacitance, an inductance element, and the like are provided. 9. The electro-optical device according to claim 4, wherein a switching element for switching the pixel electrode is provided on the first substrate in the display unit. 10. The first thin film transistor is a top-gate type, a bottom-gate type, or a dual-gate type having a gate portion above and / or below a channel region, and the switching is performed. The device is a top gate type, bottom gate type, or dual gate type second thin film transistor having a gate portion above and / or below a channel region.
An electro-optical device according to claim 1. 11. The gate electrode provided below the channel region is made of a heat-resistant material.
An electro-optical device according to claim 1. 12. The electro-optical device according to claim 10, wherein the thin film transistors in the peripheral driver circuit portion and the display portion constitute an n-channel, p-channel, or complementary insulated gate field-effect transistor. 13. The thin film transistor of the peripheral drive circuit section comprises a set of a complementary type and an n-channel type, a set of a complementary type and a p-channel type, or a set of a complementary type, an n-channel type and a p-channel type. The electro-optical device according to claim 12, wherein: 14. A single type in which at least a part of the thin film transistor of the peripheral driver circuit portion and / or the display portion has an LDD structure, and the LDD structure has an LDD portion between a gate and a source or a drain, or The electro-optical device according to claim 10, wherein the electro-optical device is of a double type having an LDD portion between a gate, a source, and a drain. 15. The thin film transistor of the peripheral driver circuit portion and / or the display portion is configured as a single gate or a multi-gate, and in the case of a multi-gate, two or more branched same potentials in a channel region, or The electro-optical device according to claim 10, further comprising divided gate electrodes having different potentials or the same potential. 16. When the n-channel or p-channel thin film transistor of the peripheral driver circuit section and / or the display section is a dual gate type, an upper or lower gate electrode is electrically open or an arbitrary negative electrode is provided. Voltage (n
Channel type) or positive voltage (p-channel type)
11. The electro-optical device according to claim 10, wherein is applied to operate as a bottom gate type or top gate type thin film transistor. 17. When the thin film transistor of the peripheral driver circuit portion is the n-channel, p-channel, or complementary first thin film transistor, and the thin film transistor of the display portion has a single crystal silicon layer as a channel region, n-channel, p-channel, or complementary;
13. An n-channel type, a p-channel type or a complementary type when the polycrystalline silicon layer is used as a channel region, and an n-channel type, a p-channel type or a complementary type when the amorphous silicon layer is used as a channel region. An electro-optical device according to claim 1. 18. A step is formed on the first substrate and / or a film thereon, the material layer is formed on the first substrate having the step formed thereon, and the single crystal semiconductor is formed on the material layer. 3. The electro-optical device according to claim 2, wherein a layer is formed. 19. The step is formed as a concave portion whose side surface is perpendicular to the bottom surface in the cross section or inclined toward the lower end, and the step serves as a seed for epitaxial growth of the single crystal silicon layer together with the material layer. 19. The electro-optical device according to claim 18, wherein 20. A step is formed on the first substrate and / or a film thereon, the material layer is formed on the first substrate having the step formed thereon, and the single crystal semiconductor is formed on the material layer. The electro-optical device according to claim 4, wherein a layer is formed. 21. The electric device according to claim 20, wherein the first thin film transistor is provided inside and / or outside a concave portion of the substrate formed by the step formed on the first substrate and / or a film thereon. Optical device. 22. The electro-optical device according to claim 20, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the thin film transistor as the active element. 23. The electro-optical device according to claim 2, wherein a step is formed in the material layer, and the single crystal silicon layer is formed on the material layer including the step. 24. The step is formed as a concave part whose side surface is perpendicular to the bottom surface in the cross section or inclined toward the lower end, and this step serves as a seed for epitaxial growth of the single crystal silicon layer together with the material layer. 22. The electro-optical device according to claim 21, wherein 25. The electro-optical device according to claim 4, wherein a step is formed in the material layer, and the single crystal silicon layer is formed on the material layer including the step. 26. The electric device according to claim 25, wherein the first thin film transistor is provided inside and / or outside a substrate recess formed by the step formed on the first substrate and / or a film thereon. Optical device. 27. The electro-optical device according to claim 23, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the thin film transistor as the active element. 28. A step is formed on the first substrate and / or a film thereon, and a single crystal, polycrystalline or amorphous silicon layer is formed on the first substrate including the step, and 11. The electro-optical device according to claim 10, wherein the thin film transistor includes the single crystal, polycrystal, or amorphous silicon layer as a channel region, a source region, and a drain region, and has a gate portion above and / or below the channel region. 29. The step is formed as a concave portion whose side surface is perpendicular to the bottom surface or inclined toward the lower end in a cross section, and the step is formed together with the material layer as a seed during epitaxial growth of the single crystal semiconductor layer. 29. The electro-optical device according to claim 28, wherein: 30. The electro-optical device according to claim 28, wherein a source or drain electrode of the first and / or second thin film transistor is formed on a region including the step. 31. The electric device according to claim 28, wherein the second thin film transistor is provided inside and / or outside a concave portion of the substrate formed by the step formed on the first substrate and / or a film thereon. Optical device. 32. The electric device according to claim 28, wherein the step is formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor. Optical device. 33. The electro-optical device according to claim 28, wherein the gate electrode under the single crystal, polycrystal, or amorphous silicon layer has a trapezoidal shape at a side end thereof. 34. The electro-optical device according to claim 28, wherein a diffusion barrier layer is provided between the first substrate and the single crystal, polycrystal, or amorphous silicon layer. 35. The electro-optical device according to claim 2, wherein the first substrate is a glass substrate or a heat-resistant organic substrate. 36. The electro-optical device according to claim 2, wherein the first substrate is optically opaque or transparent. 37. The electro-optical device according to claim 2, wherein the pixel electrode is provided for a reflective or transmissive display unit. 38. The electro-optical device according to claim 2, wherein the display section has a laminated structure of the pixel electrode and a color filter layer. 39. When the pixel electrode is a reflective electrode, irregularities are formed on the resin film, and the pixel electrode is provided thereon. When the pixel electrode is a transparent electrode, the surface is formed by a transparent flattening film. The electro-optical device according to claim 2, wherein the pixel electrode is planarized, and the pixel electrode is provided on the planarized surface. 40. The electro-optical device according to claim 9, wherein the display unit emits light or modulates light when driven by the switching element. 41. The electro-optical device according to claim 9, wherein a plurality of the pixel electrodes are arranged in a matrix on the display unit, and the switching element is connected to each of the pixel electrodes. 42. The electro-optical device according to claim 2, configured as a liquid crystal display, an electroluminescence display, a field emission display, a light emitting polymer display, a light emitting diode display, or the like. 43. The electro-optical device according to claim 1, wherein a control unit that controls an operation of the peripheral drive circuit unit and / or the display unit is provided on the first substrate. 44. The electro-optical device according to claim 43, wherein the control unit is configured by a CPU, a memory, or a system LSI in which these are mounted. 45. A driving substrate for an electro-optical device, comprising a display portion on which a pixel electrode is disposed and a peripheral driving circuit portion disposed around the display portion on the substrate, wherein one surface of the substrate is provided. A material layer having good lattice matching with the single crystal semiconductor is formed thereon, and a film made of the semiconductor formed on the material layer is heated and melted by a laser irradiation process on the substrate including the material layer, and further cooled. By being solidified, a single crystal semiconductor layer is formed by heteroepitaxial growth using the material layer as a seed, and the single crystal semiconductor layer constitutes at least the active element of the active element and the passive element. A driving substrate for an electro-optical device, which is a feature of the present invention. 46. The driving substrate for an electro-optical device according to claim 45, wherein the film made of the semiconductor is amorphous silicon or polycrystalline silicon, and the single crystal semiconductor layer is a single crystal silicon layer. 47. The driving substrate for an electro-optical device according to claim 46, wherein the specific resistance of the single crystal semiconductor layer is adjusted by mixing N-type or P-type carrier impurities. 48. The single crystal semiconductor layer may include a channel region,
47. The electro-optical device according to claim 46, wherein a top-gate first thin film transistor having a gate portion above the channel region as a source region and a drain region forms at least a part of the peripheral driver circuit portion. Driving board for equipment. 49. An insulating substrate is used as the substrate,
The method according to claim 46, wherein the material layer is formed of a material selected from the group consisting of sapphire, spinel structure, calcium fluoride, strontium fluoride, barium fluoride, boron phosphide, yttrium oxide and zirconia. Drive substrate for electro-optical devices. 50. The driving substrate for an electro-optical device according to claim 46, wherein a diffusion barrier layer is provided between the substrate and the single crystal semiconductor layer. 51. The gate portion under the single-crystal silicon layer has a trapezoidal shape at a side end thereof.
A driving substrate for the electro-optical device according to the above. 52. In the peripheral driver circuit portion, in addition to the first thin film transistor, a top gate type having a polycrystalline or amorphous silicon layer as a channel region and having a gate portion above and / or below the channel region.
A bottom-gate or dual-gate thin film transistor, or a diode using the single-crystal silicon layer or the polycrystalline silicon layer or the amorphous silicon layer,
49. The driving substrate for an electro-optical device according to claim 48, further comprising a resistor, a capacitance, an inductance element, and the like. 53. The driving substrate for an electro-optical device according to claim 48, wherein a switching element for switching the pixel electrode is provided on the substrate in the display unit. 54. The first thin-film transistor is a top-gate type, a bottom-gate type, or a dual-gate type having a gate portion above and / or below a channel region, and the switching is performed. The element is a top gate type, bottom gate type, or dual gate type second thin film transistor having a gate portion above and / or below a channel region.
4. A drive substrate for an electro-optical device according to claim 3. 55. The gate electrode provided below the channel region is made of a heat-resistant material.
A driving substrate for the electro-optical device according to the above. 56. The electro-optical device according to claim 54, wherein the thin film transistors of the peripheral driver circuit portion and the display portion form an n-channel, p-channel, or complementary insulated gate field-effect transistor. Drive board. 57. The thin film transistor of the peripheral drive circuit portion is formed of a set of a complementary type and an n-channel type, a set of a complementary type and a p-channel type, or a set of a complementary type, an n-channel type and a p-channel type. A driving substrate for an electro-optical device according to claim 56. 58. A single type in which at least a part of the thin film transistor of the peripheral driver circuit portion and / or the display portion has an LDD structure, and the LDD structure has an LDD portion between a gate and a source or a drain, or 55. The driving substrate for an electro-optical device according to claim 54, wherein the driving substrate is of a double type having an LDD portion between a gate, a source, and a drain. 59. The thin film transistor of the peripheral driver circuit portion and / or the display portion is configured as a single gate or a multi-gate, and in the case of a multi-gate, two or more branched and equal potentials in a channel region, or 55. The driving substrate for an electro-optical device according to claim 54, further comprising divided gate electrodes having different potentials or the same potential. 60. When the n-type or p-channel type thin film transistor of the peripheral driver circuit portion and / or the display portion is a dual gate type, an upper or lower gate electrode is electrically opened or an arbitrary negative electrode is provided. Voltage (n
Channel type) or positive voltage (p-channel type)
55. The driving substrate for an electro-optical device according to claim 54, wherein the driving substrate is operated as a bottom gate type or top gate type thin film transistor. 61. The thin film transistor of the peripheral driver circuit portion is the n-channel, p-channel, or complementary first thin film transistor, and the thin film transistor of the display portion uses a single crystal silicon layer as a channel region. n-channel, p-channel, or complementary;
57. An n-channel type, a p-channel type, or a complementary type when the polycrystalline silicon layer is used as a channel region, and an n-channel type, a p-channel type, or a complementary type when the amorphous silicon layer is used as a channel region. A driving substrate for the electro-optical device according to the above. 62. A step is formed on the substrate and / or a film thereon, the material layer is formed on the substrate on which the step is formed, and the single crystal semiconductor layer is formed on the material layer. A driving substrate for an electro-optical device according to claim 46. 63. The step is formed as a concave portion whose side surface is perpendicular to the bottom surface or inclined toward the lower end in the cross section, and the step is formed together with the material layer as a seed during epitaxial growth of the single crystal silicon layer. 63. The driving substrate for an electro-optical device according to claim 62, wherein the driving substrate is formed. 64. A step is formed on the substrate and / or a film thereon, the material layer is formed on the substrate on which the step is formed, and the single crystal semiconductor layer is formed on the material layer. A driving substrate for an electro-optical device according to claim 48. 65. The method according to claim 64, wherein the first thin film transistor is provided in and / or outside a substrate recess formed by the step formed on the substrate and / or a film thereon.
A driving substrate for the electro-optical device according to the above. 66. The electro-optical device according to claim 64, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the thin film transistor as the active element. Drive board. 67. The driving substrate for an electro-optical device according to claim 46, wherein a step is formed in the material layer, and the single crystal silicon layer is formed on the material layer including the step. 68. The step is formed as a concave portion whose side surface is perpendicular to the bottom surface in the cross section or inclined toward the lower end, and this step serves as a seed during epitaxial growth of the single crystal silicon layer together with the material layer. The driving substrate for an electro-optical device according to claim 65, wherein the driving substrate is formed. 69. The driving substrate for an electro-optical device according to claim 48, wherein a step is formed in the material layer, and the single crystal silicon layer is formed on the material layer including the step. 70. The method according to claim 69, wherein the first thin film transistor is provided inside and / or outside a substrate recess formed by the step formed on the substrate and / or a film thereon.
A driving substrate for the electro-optical device according to the above. 71. The electro-optical device according to claim 67, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the thin film transistor as the active element. Drive board. 72. A step is formed on the substrate and / or a film thereon, and a single crystal, polycrystalline or amorphous silicon layer is formed on the substrate including the step, and the second thin film transistor is 55. The driving substrate for an electro-optical device according to claim 54, wherein a crystalline, polycrystalline or amorphous silicon layer is used as a channel region, a source region, and a drain region, and a gate portion is provided above and / or below the channel region. 73. The step is formed as a concave portion whose side surface is perpendicular to the bottom surface in the cross section or inclined toward the lower end, and this step serves as a seed for epitaxial growth of the single crystal semiconductor layer together with the material layer. The driving substrate for an electro-optical device according to claim 72, wherein the driving substrate is formed. 74. The driving substrate for an electro-optical device according to claim 72, wherein a source or drain electrode of the first and / or second thin film transistor is formed on a region including the step. 75. The second thin film transistor is provided inside and / or outside a substrate recess due to the step formed on the substrate and / or a film thereon.
A driving substrate for the electro-optical device according to the above. 76. The electric device according to claim 72, wherein the step is formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor. Driving substrate for optical devices. 77. The driving substrate for an electro-optical device according to claim 72, wherein a gate electrode under the single crystal, polycrystal, or amorphous silicon layer has a trapezoidal shape at a side end thereof. 78. The driving substrate for an electro-optical device according to claim 72, wherein a diffusion barrier layer is provided between the substrate and the single crystal, polycrystal, or amorphous silicon layer. 79. The driving substrate for an electro-optical device according to claim 46, wherein the substrate is a glass substrate or a heat-resistant organic substrate. 80. The driving substrate for an electro-optical device according to claim 46, wherein the substrate is optically opaque or transparent. 81. The driving substrate for an electro-optical device according to claim 46, wherein the pixel electrode is provided for a reflective or transmissive display unit. 82. The driving substrate for an electro-optical device according to claim 46, wherein the display section has a laminated structure of the pixel electrode and a color filter layer. 83. When the pixel electrode is a reflective electrode, irregularities are formed on the resin film, and the pixel electrode is provided thereon. When the pixel electrode is a transparent electrode, the surface is formed by a transparent flattening film. 47. The driving substrate for an electro-optical device according to claim 46, wherein the pixel electrode is planarized and the pixel electrode is provided on the planarized surface. 84. The driving substrate for an electro-optical device according to claim 53, wherein the display section emits light or modulates light when driven by the switching element. 85. The driving substrate for an electro-optical device according to claim 53, wherein a plurality of the pixel electrodes are arranged in a matrix on the display section, and the switching element is connected to each of the pixel electrodes. 86. The drive for an electro-optical device according to claim 46, wherein the drive is configured as a drive substrate for a liquid crystal display, an electroluminescence display, a field emission display, a light emitting polymer display, a light emitting diode display, or the like. substrate. 87. The driving substrate for an electro-optical device according to claim 45, wherein a control unit for controlling an operation of the peripheral driving circuit unit and / or the display unit is provided on the substrate. 88. The driving substrate for an electro-optical device according to claim 87, wherein the control unit is configured by a CPU, a memory, or a system LSI in which these are mounted. 89. A display unit on which a pixel electrode is provided, and a peripheral drive circuit unit provided around the display unit on a first substrate, wherein the first substrate, the second substrate, A method of manufacturing an electro-optical device having a predetermined optical material interposed therebetween, wherein a step of forming a material layer having good lattice matching with a single crystal semiconductor on one surface of the first substrate; A step of forming a semiconductor on the layer; and a step of subjecting the film made of the semiconductor to laser irradiation treatment, heating and melting the film, and further cooling and solidifying the film to heteroepitaxially grow a single crystal semiconductor layer using the material layer as a seed. And performing a predetermined process on the single crystal semiconductor layer to form at least an active element of an active element and a passive element. 90. The method according to claim 89, wherein the semiconductor film is amorphous silicon or polycrystalline silicon, and the single crystal semiconductor layer is a single crystal silicon layer. 91. The electro-optical device according to claim 90, wherein an impurity type and / or a concentration of the semiconductor film obtained by mixing an N-type or P-type carrier impurity during the formation of the semiconductor is controlled. Production method. A temperature of the first substrate is 200 to 5 when the single crystal semiconductor layer is heteroepitaxially grown.
The method for manufacturing an electro-optical device according to claim 90, wherein the temperature is set to 00 ° C. 93. The specific resistance of the single crystal semiconductor layer is adjusted by mixing an N-type or P-type carrier impurity into the single crystal semiconductor layer prior to performing the predetermined treatment on the single crystal semiconductor layer. A method for manufacturing an electro-optical device. 94. After growing the single crystal semiconductor layer, performing a predetermined process on the single crystal semiconductor layer to form a channel region, a source region, and a drain region; and forming a gate portion above the channel region. 90. The method of manufacturing an electro-optical device according to claim 90, further comprising: forming a top-gate first thin film transistor that forms at least a part of the peripheral drive circuit unit. 95. An insulating substrate is used as the first substrate, and the material layer is made of sapphire, spinel structure, calcium fluoride, strontium fluoride, barium fluoride,
The method for manufacturing an electro-optical device according to claim 90, wherein the method is formed using a material selected from the group consisting of boron phosphide, yttrium oxide, and zirconia oxide. 96. The method according to claim 90, wherein a diffusion barrier layer is formed on the first substrate, and the single crystal semiconductor layer is formed thereon. 97. The method of manufacturing an electro-optical device according to claim 90, wherein the gate portion under the single-crystal semiconductor layer has a trapezoidal shape at a side end thereof. 98. In the peripheral driver circuit portion, in addition to the first thin film transistor, a top gate type in which a polycrystalline or amorphous silicon layer is used as a channel region and a gate portion is provided above and / or below the channel region.
A bottom-gate or dual-gate thin film transistor, or a diode using the single-crystal silicon layer or the polycrystalline silicon layer or the amorphous silicon layer,
The method for manufacturing an electro-optical device according to claim 94, further comprising providing a resistance, a capacitance, an inductance element, and the like. 99. The method according to claim 94, wherein a switching element for switching the pixel electrode is provided on the first substrate in the display unit. 100. The first thin film transistor is a top gate type having a gate portion above and / or below a channel region, a bottom gate type, or a top gate type of a dual gate type. 100. The method for manufacturing an electro-optical device according to claim 99, wherein a second thin film transistor of a top gate type, a bottom gate type, or a dual gate type having a gate portion above and / or below the channel region is formed. 101. The method of manufacturing an electro-optical device according to claim 100, wherein a gate electrode provided below said channel region is formed of a heat-resistant material. 102. When the second thin film transistor is a bottom gate type or a dual gate type, a lower gate electrode made of a heat resistant material is provided below the channel region, and a gate insulating film is formed on the gate electrode. The method for manufacturing an electro-optical device according to claim 100, wherein after forming the lower gate portion by performing a common step with the first thin film transistor including a step of forming the material layer, the second thin film transistor is formed. 103. After forming the single-crystal semiconductor layer on the lower gate portion, an N-type or P-type carrier impurity is introduced into the single-crystal semiconductor layer to form source and drain regions, and then activated. 102. Perform processing.
The manufacturing method of the electro-optical device according to the above. 104. After the formation of the single crystal semiconductor layer, each source and drain region of the second thin film transistor is formed by ion implantation of the impurity using a resist as a mask, and the activation is performed after the ion implantation. The method for manufacturing an electro-optical device according to claim 103, wherein an upper gate electrode of the second thin film transistor is formed after forming the film. 105. In the case where the second thin film transistor is a top gate type, after forming the single crystal semiconductor layer, each source and drain region of the second thin film transistor is formed by ion implantation of impurities using a resist as a mask. The method for manufacturing an electro-optical device according to claim 100, wherein an activation process is performed after the ion implantation, and then a gate portion including a gate insulating film and a gate electrode of the second thin film transistor is formed. 106. In the case where the second thin film transistor is a top-gate type, after forming the single crystal semiconductor layer, a gate insulating film of the second thin film transistor and a gate electrode made of a heat-resistant material are formed. To form
The manufacturing of the electro-optical device according to claim 100, wherein the source and drain regions of the first and second thin film transistors are formed by ion implantation of an impurity element using the gate portion as a mask, and an activation process is performed after the ion implantation. Method. 107. The method of manufacturing an electro-optical device according to claim 100, wherein an n-channel, p-channel, or complementary insulated gate field effect transistor is formed as the thin film transistor of the peripheral driver circuit portion and the display portion. . 108. The thin film transistor of the peripheral driver circuit portion is formed of a set of a complementary type and an n-channel type, a set of a complementary type and a p-channel type, or a set of a complementary type, an n-channel type and a p-channel type. 108. The method for manufacturing an electro-optical device according to claim 107, wherein 109. At least a part of the thin film transistor of the peripheral driver circuit portion and / or the display portion has an LDD structure, and the LDD structure is a single type having an LDD portion between a gate and a source or a drain, or has 103. The method for manufacturing an electro-optical device according to claim 102, wherein the device is of a double type having an LDD portion between the source and the drain. 110. The electro-optical device according to claim 109, wherein a resist mask used for forming the LDD structure is left, and ion implantation for forming a source region and a drain region is performed using a resist mask covering the resist mask. Manufacturing method. 111. A single crystal, polycrystal, or amorphous silicon layer is formed on one surface of the first substrate, and the single crystal, polycrystal, or amorphous silicon layer is used as a channel region, a source region, and a drain region. 108. The method of manufacturing an electro-optical device according to claim 107, wherein the second thin film transistor having a gate portion above and / or below the second thin film transistor is formed. 112. When the thin film transistor of the peripheral driver circuit portion is the first thin film transistor of an n-channel type, a p-channel type, or a complementary type, and the thin film transistor of the display portion is a single crystal silicon layer in a channel region, n A channel type, a p-channel type, or a complementary type; an n-channel type, a p-channel type, or a complementary type when a polycrystalline silicon layer is used as a channel region; and an n-channel type when an amorphous silicon layer is used as a channel region.
112. The method of manufacturing an electro-optical device according to claim 111, wherein the method is a p-channel type or a complementary type. 113. A step is formed on the first substrate and / or a film thereon, the material layer is formed on the first substrate having the step formed thereon, and the single crystal semiconductor is formed on the material layer. The method for manufacturing an electro-optical device according to claim 90, wherein the layer is formed. 114. The step is formed as a concave portion whose side surface is perpendicular to the bottom surface or inclined toward the lower end in a cross section, and the step is formed together with the material layer as a seed during epitaxial growth of the single crystal semiconductor layer. 114. The method of manufacturing an electro-optical device according to claim 113. 115. A step is formed on the first substrate and / or a film thereon, the material layer is formed on the first substrate having the step formed thereon, and the single crystal semiconductor is formed on the material layer. The method for manufacturing an electro-optical device according to claim 94, wherein a layer is formed. 116. The first thin film transistor is provided inside and / or outside a substrate recess due to the step formed on the first substrate and / or a film thereon.
6. The method for manufacturing an electro-optical device according to item 5. 117. The method of manufacturing an electro-optical device according to claim 115, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the thin film transistor as the active element. Method. 118. The method according to claim 90, wherein a step is formed in the material layer, and the single crystal semiconductor layer is formed over the material layer including the step. 119. The step is formed as a concave portion whose side surface is perpendicular to the bottom surface in the cross section or inclined toward the lower end, and the step is formed together with the material layer as a seed during epitaxial growth of the single crystal semiconductor layer. 119. The method of manufacturing an electro-optical device according to claim 118, wherein: 120. The method according to claim 94, wherein a step is formed in the material layer, and the single crystal semiconductor layer is formed on the material layer including the step. 121. The first thin film transistor is provided in and / or outside a substrate recess due to the step formed in the first substrate and / or a film thereon.
0. A method for manufacturing an electro-optical device according to item 0. 122. The method of manufacturing an electro-optical device according to claim 118, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the thin film transistor as the active element. Method. 123. A step is formed on the first substrate and / or a film thereon, and a single crystal, polycrystal, or amorphous silicon layer is formed on the first substrate having the step formed thereon. Crystal, polycrystalline, or amorphous silicon layer as a channel region, a source region, and a drain region,
The second thin film transistor having a gate portion above and / or below the channel region is formed.
00. The method for manufacturing an electro-optical device according to item 00. 124. The step is formed as a concave portion whose side surface is perpendicular to the bottom surface or inclined toward the lower end in the cross section, and the step is formed together with the material layer as a seed during epitaxial growth of the single crystal semiconductor layer. The method for manufacturing an electro-optical device according to claim 123, wherein 125. The method of manufacturing an electro-optical device according to claim 123, wherein a source or drain electrode of said first and / or second thin film transistor is formed on a region including said step. 126. The second thin film transistor is provided in and / or outside a substrate recess due to the step formed in the first substrate and / or a film thereon.
4. The method for manufacturing an electro-optical device according to item 3. 127. The electro-optical device according to claim 123, wherein the step is formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor. Manufacturing method. 128. The method of manufacturing an electro-optical device according to claim 123, wherein the gate electrode under the single crystal, polycrystal, or amorphous silicon layer has a trapezoidal shape at a side end thereof. 129. The method for manufacturing an electro-optical device according to claim 123, wherein a diffusion barrier layer is provided between said first substrate and said single crystal, polycrystal or amorphous silicon layer. 130. The method according to claim 90, wherein the first substrate is a glass substrate or a heat-resistant organic substrate. 131. The method according to claim 90, wherein the first substrate is optically opaque or transparent. 132. The method of manufacturing an electro-optical device according to claim 90, wherein the pixel electrode is provided for a reflective or transmissive display unit. 133. The method of manufacturing an electro-optical device according to claim 90, wherein a laminated structure of the pixel electrode and a color filter layer is provided in the display unit. 134. When the pixel electrode is a reflective electrode, an unevenness is formed on a resin film, and a pixel electrode is provided thereon. When the pixel electrode is a transparent electrode, the surface is flattened by a transparent flattening film. The method for manufacturing an electro-optical device according to claim 90, wherein the pixel electrode is provided on the flattened surface. 135. The method of manufacturing an electro-optical device according to claim 99, wherein said display unit is configured to emit light or adjust light when driven by said switching element. 136. The method of manufacturing an electro-optical device according to claim 99, wherein the plurality of pixel electrodes are arranged in a matrix on the display section, and the switching element is connected to each of the pixel electrodes. 137. The method for manufacturing an electro-optical device according to claim 90, wherein the method is configured as a liquid crystal display, an electroluminescence display, a field emission display, a light emitting polymer display, a light emitting diode display, or the like. 138. A step of performing a predetermined process on the single crystal semiconductor layer to form an element for constituting a control unit for controlling an operation of the peripheral driver circuit unit and / or the display unit. The manufacturing method of the electro-optical device according to the above. 139. An element for forming the control unit is a CMOSTFT, an nMOSTFT, or a pMOSTFT.
139. The method for manufacturing an electro-optical device according to claim 138, comprising an active element such as a passive element such as a resistor, a capacitor, and an inductance. 140. A method of manufacturing a driving substrate for an electro-optical device, comprising: a display portion on which a pixel electrode is disposed; and a peripheral driving circuit portion disposed around the display portion on the substrate. Forming a material layer having good lattice matching with the single crystal semiconductor on one surface; forming a semiconductor film over the material layer; heating the film made of the semiconductor by laser irradiation; Melting and further solidifying by cooling, a step of heteroepitaxially growing a single-crystal semiconductor layer using the material layer as a seed, and performing a predetermined treatment on the single-crystal semiconductor layer to form at least the active element of the active element and the passive element. Forming a driving substrate for an electro-optical device. 141. The method of manufacturing a driving substrate for an electro-optical device according to claim 140, wherein the film made of the semiconductor is amorphous silicon or polycrystalline silicon, and the single crystal semiconductor layer is a single crystal silicon layer. 142. An impurity species and / or a concentration of the semiconductor film obtained by mixing an N-type or P-type carrier impurity during the film formation of the semiconductor,
A method for manufacturing a drive substrate for an electro-optical device according to claim 141. 143. The temperature of the substrate when heteroepitaxially growing the single crystal semiconductor layer is set to 200 to 500.
142. The method of manufacturing a drive substrate for an electro-optical device according to claim 141, wherein the temperature is set to ° C. 144. An N-type or P-type semiconductor layer is formed on the single crystal semiconductor layer before the predetermined processing is performed on the single crystal semiconductor layer.
Adjust the specific resistance by mixing the carrier impurities of the mold,
A method for manufacturing a drive substrate for an electro-optical device according to claim 141. 145. a step of performing a predetermined process on the single crystal semiconductor layer to form a channel region, a source region, and a drain region after the growth of the single crystal semiconductor layer; and forming a gate portion above the channel region. 142. The method of manufacturing a driving substrate for an electro-optical device according to claim 141, further comprising: forming a top gate type first thin film transistor that forms at least a part of the peripheral driving circuit unit. 146. An insulating substrate as the substrate, wherein the material layer is selected from the group consisting of sapphire, spinel structure, calcium fluoride, strontium fluoride, barium fluoride, boron phosphide, yttrium oxide and zirconia. 142. The method of manufacturing a drive substrate for an electro-optical device according to claim 141, wherein the drive substrate is formed of a material. 147. The diffusion barrier layer is formed on the substrate, and the single crystal semiconductor layer is formed thereon.
42. The method for manufacturing a drive substrate for an electro-optical device according to 41. 148. The method of manufacturing a driving substrate for an electro-optical device according to claim 141, wherein said gate portion under said single crystal semiconductor layer has a trapezoidal shape at a side end thereof. 149. In the peripheral driver circuit portion, in addition to the first thin film transistor, a polycrystalline or amorphous silicon layer is used as a channel region, and a top gate type and a bottom type having a gate portion above and / or below the channel region. 148. An electro-optical device according to claim 145, wherein a gate, a dual-gate thin film transistor, or a diode, a resistor, a capacitance, an inductance element, or the like using the single crystal silicon layer, the polycrystal silicon layer, or the amorphous silicon layer is provided. A method for manufacturing a drive substrate. 150. The method of manufacturing a driving substrate for an electro-optical device according to claim 145, wherein in the display unit, a switching element for switching the pixel electrode is provided on the substrate. 151. The first thin film transistor is a top gate type having a gate portion above and / or below a channel region, a bottom gate type, or a top gate type of a dual gate type. The method for manufacturing a driving substrate for an electro-optical device according to claim 150, wherein a second thin film transistor of a top gate type, a bottom gate type, or a dual gate type having a gate portion above and / or below the channel region is formed. 152. The method of manufacturing a driving substrate for an electro-optical device according to claim 151, wherein a gate electrode provided below said channel region is formed of a heat-resistant material. 153. When the second thin film transistor is a bottom gate type or a dual gate type, a lower gate electrode made of a heat resistant material is provided below the channel region, and a gate insulating film is formed on the gate electrode. 154. The driving substrate for an electro-optical device according to claim 151, wherein after forming the lower gate portion, the second thin film transistor is formed through a process common to the first thin film transistor including a process of forming the material layer. Manufacturing method. 154. After forming the single-crystal semiconductor layer on the lower gate portion, an N-type or P-type carrier impurity is introduced into the single-crystal semiconductor layer to form source and drain regions, and then activated. 153. Perform processing.
A method for manufacturing a driving substrate for an electro-optical device according to the above. 155. After the formation of the single crystal semiconductor layer, each source and drain region of the second thin film transistor is formed by ion implantation of the impurity using a resist as a mask, and after the ion implantation, the activation is performed to form a gate insulating layer. 157. The method according to claim 154, further comprising: forming an upper gate electrode of the second thin film transistor after forming the film. 156. In the case where the second thin film transistor is a top-gate type, after forming the single crystal semiconductor layer, each source and drain region of the second thin film transistor is formed by ion implantation of impurities using a resist as a mask. 152. The method of manufacturing a driving substrate for an electro-optical device according to claim 151, wherein an activation process is performed after the ion implantation, and thereafter, a gate portion including a gate insulating film and a gate electrode of the second thin film transistor is formed. 157. In the case where the second thin film transistor is of a top-gate type, a gate insulating film of the second thin film transistor and a gate electrode made of a heat-resistant material are formed after the formation of the single crystal semiconductor layer to form a gate portion. To form
153. The electro-optical device according to claim 151, wherein each of the source and drain regions of the first and second thin film transistors is formed by ion implantation of an impurity element using the gate portion as a mask, and an activation process is performed after the ion implantation. A method for manufacturing a drive substrate. 158. The driving device for an electro-optical device according to claim 151, wherein an n-channel, p-channel, or complementary insulated gate field-effect transistor is configured as the thin film transistor of the peripheral driver circuit portion and the display portion. Substrate manufacturing method. 159. The thin film transistor of the peripheral driver circuit portion is formed of a set of a complementary type and an n-channel type, a set of a complementary type and a p-channel type, or a set of a complementary type, an n-channel type and a p-channel type. 158. The method for manufacturing a drive substrate for an electro-optical device according to claim 158. 160. At least a part of the thin film transistor of the peripheral driver circuit portion and / or the display portion has an LDD structure, and the LDD structure is a single type having an LDD portion between a gate and a source or a drain, or a gate type. 153. The method of manufacturing a driving substrate for an electro-optical device according to claim 153, wherein the driving substrate is a double type having an LDD portion between the source and the drain. 161. The electro-optical device according to claim 160, wherein a resist mask used for forming the LDD structure is left, and ion implantation for forming a source region and a drain region is performed using a resist mask covering the resist mask. Of manufacturing a driving substrate for a semiconductor device. 162. A single crystal, polycrystal, or amorphous silicon layer is formed on one surface of the substrate, and the single crystal, polycrystal, or amorphous silicon layer is used as a channel region, a source region, and a drain region. as well as/
162. The method for manufacturing a driving substrate for an electro-optical device according to claim 161, wherein the second thin film transistor having a gate portion below is formed. 163. The thin film transistor of the peripheral driver circuit portion is the n-channel, p-channel, or complementary first thin film transistor, and the thin film transistor of the display portion is n when a single crystal silicon layer is used as a channel region. A channel type, a p-channel type, or a complementary type; an n-channel type, a p-channel type, or a complementary type when a polycrystalline silicon layer is used as a channel region; and an n-channel type when an amorphous silicon layer is used as a channel region.
163. The method for manufacturing a driving substrate for an electro-optical device according to claim 162, wherein the driving substrate is a p-channel type or a complementary type. 164. A step is formed on the substrate and / or a film thereon, the material layer is formed on the substrate on which the step is formed, and the single crystal semiconductor layer is formed on the material layer. 146. A method for manufacturing a drive substrate for an electro-optical device according to item 141. 165. In the cross section, the step is formed as a concave part whose side surface is perpendicular to the bottom surface or inclined toward the lower end, and the step is formed together with the material layer as a seed during epitaxial growth of the single crystal semiconductor layer. 164. The method for manufacturing a drive substrate for an electro-optical device according to claim 164. 166. A step is formed on the substrate and / or a film thereon, the material layer is formed on the substrate on which the step is formed, and the single crystal semiconductor layer is formed on the material layer. 145. A method of manufacturing a drive substrate for an electro-optical device according to item 145. 167. The driving substrate for an electro-optical device according to claim 166, wherein the first thin film transistor is provided in and / or outside a substrate recess formed by the step formed on the substrate and / or a film thereon. Manufacturing method. 168. The electro-optical device according to claim 166, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the thin film transistor as the active element. A method for manufacturing a drive substrate. 169. The method for manufacturing a driving substrate for an electro-optical device according to claim 141, wherein a step is formed in said material layer, and said single crystal semiconductor layer is formed on said material layer including said step. 170. The step is formed as a concave portion whose side surface is perpendicular to the bottom surface or inclined toward the lower end in a cross section, and the step is formed together with the material layer as a seed during epitaxial growth of the single crystal semiconductor layer. 170. The method of manufacturing a drive substrate for an electro-optical device according to claim 169. 171. The method for manufacturing a driving substrate for an electro-optical device according to claim 145, wherein a step is formed in the material layer, and the single crystal semiconductor layer is formed on the material layer including the step. 172. The driving substrate for an electro-optical device according to claim 171, wherein the first thin film transistor is provided inside and / or outside a substrate recess formed by the step formed on the substrate and / or a film thereon. Manufacturing method. 173. The electro-optical device according to claim 169, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the thin film transistor as the active element. A method for manufacturing a drive substrate. 174. A step is formed on the substrate and / or a film thereon, and a single crystal, polycrystal, or amorphous silicon layer is formed on the substrate on which the step is formed, and the single crystal, polycrystal, or The second region having an amorphous silicon layer as a channel region, a source region, and a drain region, and having a gate portion above and / or below the channel region;
The method for manufacturing a driving substrate for an electro-optical device according to claim 151, wherein the thin film transistor is formed. 175. In the cross section, the step is formed as a concave portion such that the side surface is perpendicular to the bottom surface or inclined toward the lower end, and the step is formed together with the material layer as a seed during epitaxial growth of the single crystal semiconductor layer. 175. The method for manufacturing a drive substrate for an electro-optical device according to claim 174. 176. The method according to claim 174, wherein the source or drain electrode of the first and / or second thin film transistor is formed on a region including the step. 177. The driving substrate for an electro-optical device according to claim 174, wherein the second thin film transistor is provided inside and / or outside a substrate recess formed by the step formed on the substrate and / or a film thereon. Manufacturing method. 178. The electro-optical device according to claim 174, wherein the step is formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor. Of manufacturing a driving substrate for a semiconductor device. 179. The method for manufacturing a driving substrate for an electro-optical device according to claim 174, wherein the gate electrode under the single crystal, polycrystal, or amorphous silicon layer has a trapezoidal shape at a side end thereof. 180. The method according to claim 174, wherein a diffusion barrier layer is provided between the substrate and the single crystal, polycrystal, or amorphous silicon layer. 181. The method for manufacturing a driving substrate for an electro-optical device according to claim 141, wherein said substrate is a glass substrate or a heat-resistant organic substrate. 182. The method according to claim 141, wherein the substrate is optically opaque or transparent. 183. The method for manufacturing a driving substrate for an electro-optical device according to claim 141, wherein said pixel electrode is provided for a reflective or transmissive display portion. 184. The method for manufacturing a driving substrate for an electro-optical device according to claim 141, wherein a laminated structure of the pixel electrode and a color filter layer is provided in the display unit. 185. When the pixel electrode is a reflective electrode, an unevenness is formed on a resin film, and a pixel electrode is provided thereon. When the pixel electrode is a transparent electrode, the surface is flattened by a transparent flattening film. 142. The method for manufacturing a driving substrate for an electro-optical device according to claim 141, wherein the pixel electrode is provided on the flattened surface. 186. The method of manufacturing a driving substrate for an electro-optical device according to claim 150, wherein said display unit is configured to emit light or adjust light when driven by said switching element. 187. The method of manufacturing a driving substrate for an electro-optical device according to claim 150, wherein a plurality of said pixel electrodes are arranged in a matrix on said display section, and said switching element is connected to each of said pixel electrodes. . 188. The method for manufacturing a drive substrate for an electro-optical device according to claim 141, wherein the method is configured as a liquid crystal display device, an electroluminescence display device, a field emission display device, a light emitting polymer display device, a light emitting diode display device, or the like. . 189. A step of performing a predetermined process on the single crystal semiconductor layer to form an element for constituting a control unit for controlling an operation of the peripheral driver circuit unit and / or the display unit. A method for manufacturing a driving substrate for an electro-optical device according to the above. 190. An element for constituting the control unit is a CMOSTFT, an nMOSTFT, or a pMOSTFT.
189. The method for manufacturing a drive substrate for an electro-optical device according to claim 189, comprising an active element such as a passive element such as a resistor, a capacitor, and an inductance.