JP2000216394A - Electrooptic device, its driving substrate and its fabrication - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a high image quality, high definition, narrow frame, high efficiency, large screen display panel by employing a single crystal silicon layer as channel region and source-drain region and fabricating a thin film transistor as a part of a peripheral driving circuit part beneath the channel region. SOLUTION: A silicon oxide film is formed on the surface of an insulating substrate 1 and after photoresist 2 is removed, a crystalline sapphire film 50 is formed in the TFT forming region including a step 4 on one major surface of the insulating substrate 1. A polysilicon film 5 is then formed thereon and a low melting point metal layer 6 of tin is formed on the silicon film 5. It is then cooled gradually and a single crystal silicon layer 7 is formed using the corner part on the bottom face of the step 4 and the crystalline sapphire film 50 as the seed of epitaxial growth. Finally, a thin film transistor is fabricated as a part of a peripheral driving circuit beneath the channel region of the silicon layer 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electro-optical device, a driving substrate for the electro-optical device, and a method for manufacturing the same, and more particularly, to using a single crystal silicon layer heteroepitaxially grown on an insulating substrate for an active region. The present invention relates to a structure having a bottom-gate thin-film insulated-gate field-effect transistor (hereinafter, referred to as a bottom-gate MOSTFT) and a method of manufacturing the same.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device has a display portion using amorphous silicon for a TFT and an external driving circuit IC, and a display using a polycrystalline silicon for a TFT by a solid phase growth method. (Japanese Unexamined Patent Publication (Kokai) No. 6-242433), and an integrated type of a display unit and a drive circuit using excimer laser-annealed polycrystalline silicon for a TFT (Japanese Unexamined Patent Publication No. 7-131)
030) is known.

[0003]

However, in the above-mentioned conventional amorphous silicon TFT, although the productivity is good, the electron mobility is as low as about 0.5 to 1.0 cm ² / v · sec. (Hereafter, pM
It is called OSFT. ) Can not be made. Therefore, this pMOST is formed on the same glass substrate as the display unit.
Since a peripheral drive unit using FT cannot be formed, and a driver IC is mounted externally and mounted by a TAB method or the like, cost reduction is difficult, and there is a limit to high definition. is there. Furthermore, electron mobility is 0.5-1.
Since it is as low as about 0 cm ² / v · sec, sufficient on-current cannot be obtained, and the transistor size is inevitably increased when used in a display portion, which is disadvantageous for increasing the pixel aperture ratio. I have.

Further, the conventional polycrystalline silicon TF described above is used.
At T, the electron mobility is 70 to 100 cm ² / v · s
ec, which can cope with high definition. Therefore, recently, an LCD using a polycrystalline silicon TFT integrated with a driving circuit has been developed.
(Liquid crystal display devices) are attracting attention. However, 1
In the case of a large LCD of 5 inches or more, since the electron mobility of polycrystalline silicon is 70 to 100 cm ² / v · sec, the driving capability is insufficient, and eventually, an external driving circuit IC is required. ing.

In a TFT using polycrystalline silicon formed by a solid phase growth method, annealing is performed at a temperature of 600 ° C. or more for more than 10 hours, and a gate Si is formed by thermal oxidation at about 1000 ° C.
Since O ₂ needs to be formed, a dedicated semiconductor manufacturing apparatus must be used. Therefore, the wafer size is 8
Since the diameter is limited to 12 inches φ, high-heat-resistant and expensive quartz glass must be adopted, and it is difficult to reduce the cost. Therefore, the obtained product is currently EV
F and data / AV projector applications.

Further, in the above-described conventional polycrystalline silicon TFT by excimer laser annealing, stability of excimer laser output, increase in apparatus price due to increase in size, increase in yield /
Problems such as quality deterioration are piled up.

[0007] In particular, when a large glass substrate of 1 m square or the like is used, the above-mentioned problems are magnified, and it becomes more difficult to improve performance / quality and reduce costs.

An object of the present invention is to provide an active matrix substrate with a built-in high-performance driver by forming a single-crystal silicon thin film having a high electron / hole mobility at a relatively low temperature and uniformly, particularly in a peripheral driving circuit portion. Enables the manufacture of electro-optical devices such as display thin film semiconductor devices using the same, and has an LDD structure (Li
ghtly doped drain structure) n-channel MOSTF
T (hereinafter referred to as nMOSTFT) or pMOS
TFT or complementary thin-film insulated gate field-effect transistor with high driving capability (hereinafter referred to as cMOSTFT)
And a peripheral drive circuit composed of this cMOSTFT, nMOSTFT, or pMOSTFT, or a mixture of these, enabling a high-quality, high-definition, narrow frame, high-efficiency, large-screen display panel. It can be used even with a large glass substrate having a relatively low strain point, has high productivity, does not require expensive manufacturing equipment, enables cost reduction, and has a threshold adjustment. An object of the present invention is to enable high-speed operation and a large screen by low resistance.

[0009]

According to the present invention, a pixel electrode (for example, a plurality of pixel electrodes arranged in a matrix: the same applies hereinafter) and a peripheral drive circuit portion disposed around the display portion are provided as first components. An electro-optical device in which a predetermined optical material such as a liquid crystal is interposed between the first substrate and the driving substrate for the electro-optical device, and a driving substrate for the electro-optical device. A gate portion including a gate electrode and a gate insulating film is formed on one surface, and a material layer having good lattice matching with a single crystal semiconductor is formed on the one surface of the first substrate. A semiconductor film made of a semiconductor and a low melting point metal layer made of tin or lead or an alloy of tin and lead are formed on the first substrate containing tin, or tin or lead or tin and lead containing a semiconductor Low melting point gold made of alloy with A layer is formed, the semiconductor is dissolved in the low-melting metal layer by heat treatment, and the dissolved semiconductor is formed by heteroepitaxial growth using the material layer as a seed by cooling treatment to form a single crystal semiconductor layer. The single crystal semiconductor layer is used as a channel region, a source region and a drain region,
A solution to the above problem is that a bottom gate type first thin film transistor having the gate portion below the channel region forms at least a part of the peripheral drive circuit portion.

In the present invention, the concept of a single crystal semiconductor includes not only single crystal silicon but also a single crystal compound semiconductor such as single crystal gallium arsenide (Ga.As) and single crystal silicon germanium (Si.Ge). (The same applies hereinafter). Further, in the present invention, a single crystal is a concept including a single crystal containing sub-grain boundaries and dislocations (the same applies hereinafter).

Further, the thin film transistor is
There are a field effect transistor (FET) (there is a MOS type and a junction type, whichever may be used) and a bipolar transistor, and the present invention can be applied to any of the transistors (the same applies hereinafter).

Further, the present invention provides the method for manufacturing the electro-optical device and the driving substrate thereof, wherein a step of forming a gate portion comprising a gate electrode and a gate insulating film on one surface of the first substrate; Forming a material layer having good lattice matching with the single crystal semiconductor on the one surface of the first substrate; and forming a semiconductor film made of a semiconductor and tin or lead or tin and lead on the material layer. Forming a low-melting-point metal layer made of an alloy, or forming a low-melting-point metal layer made of tin or lead or an alloy of tin and lead containing a semiconductor; Dissolving the semiconductor in the layer; and dissolving the semiconductor in the low-melting metal layer, and then heteroepitaxially growing the semiconductor using the material layer as a seed by cooling to deposit a single crystal semiconductor layer. Forming a channel region, a source region, and a drain region by performing predetermined processing on the single crystal semiconductor layer; forming the gate portion below the channel region, forming at least a part of the peripheral driver circuit portion; Forming a first gate transistor of a bottom gate type.

According to the present invention, a low melting point metal layer in which a semiconductor material such as polycrystalline silicon or amorphous silicon is dissolved is converted from the material layer having good lattice matching with a single crystal semiconductor (for example, single crystal silicon). Sapphire film)
A single-crystal semiconductor layer such as a single-crystal silicon layer is formed by heteroepitaxial growth with a seed as a seed, and this is formed as a bottom-gate MOSTFT of a peripheral drive circuit of a drive substrate such as an active matrix substrate, or a display-peripheral drive circuit integrated type. In the electro-optical device such as an LCD, a peripheral drive circuit has a bottom gate type MOSTFT, so that the following remarkable functions (A) to (H) can be obtained.

(A) A material layer (for example, a crystalline sapphire film) having good lattice matching with single crystal silicon is formed on a substrate,
By heteroepitaxially growing the material layer as a seed, a single crystal semiconductor layer such as a single crystal silicon layer having a high electron mobility of 540 cm ² / v · sec or more can be obtained. And the like can be manufactured.

(B) In particular, the single-crystal silicon layer has high electron and hole mobilities comparable to those of a single-crystal silicon substrate as compared with a conventional amorphous silicon layer or polycrystalline silicon layer. Bottom-gate MOSTFTs have high switching characteristics [preferably, LDDs that reduce the electric field strength and reduce the leakage current.
(Lightly doped drain) structure], a display portion comprising an nMOS, pMOSTFT or cMOSTFT;
High drive capability cMOS, nMOS or pMOSTF
It is possible to realize a configuration in which a peripheral drive circuit section composed of T or a mixture thereof is integrated, and a display panel with high image quality, high definition, a narrow frame, high efficiency, and a large screen is realized. In particular, it is difficult to form a pMOSTFT having a high hole mobility as a TFT for LCD in polycrystalline silicon. However, in a single crystal silicon layer according to the present invention, even a hole exhibits a sufficiently high mobility, so that electrons and electrons are positive. A peripheral drive circuit for driving the holes individually or in a combination of both can be manufactured, and a panel in which this is integrated with an nMOS, pMOS, or cMOS LDD structure display TFT can be realized. In the case of a small to medium-sized panel, there is a possibility that one of a pair of peripheral vertical drive circuits can be omitted.

(C) Polycrystalline silicon, amorphous silicon, and the like can be formed by a plasma CVD method or a low pressure CVD method under the condition that the substrate temperature is 100 to 400 ° C. The metal layer can be formed by a known method such as a vacuum evaporation method or a sputtering method. Further, since the heat treatment temperature at the time of the silicon epitaxial growth can be set to 600 ° C. or less, the metal layer is insulated. A single crystal silicon layer can be uniformly formed on a substrate at a relatively low temperature (for example, 400 to 450 ° C.). Therefore, a glass substrate or a heat-resistant resin substrate having a relatively low strain point can be easily obtained, a low-cost substrate having good physical properties can be used, and the substrate can be enlarged.

(D) Since there is no need for annealing at medium temperature for a long time (about 600 ° C., about ten and several hours) or excimer laser annealing as in the case of the solid phase growth method, productivity is high.
Expensive manufacturing equipment is not required, and costs can be reduced.

(E) In this heteroepitaxial growth, the crystallinity of the material layer such as crystalline sapphire, the composition ratio of polycrystalline silicon or amorphous silicon to the low melting point metal layer, and the heating temperature and cooling rate of the substrate are adjusted. Since a wide range of a P-type or N-type conductivity type and a high-mobility single-crystal silicon layer can be easily obtained, Vth (threshold) adjustment becomes easy, and high-speed operation by lowering resistance becomes possible.

(F) When forming a semiconductor (amorphous silicon or polycrystalline silicon) film on the material layer or a semiconductor-containing low melting point metal layer, an N-type or P-type carrier impurity (boron, phosphorus, antimony, Arsenic, bismuth, aluminum, etc.)
The impurity species and / or the concentration thereof in the single crystal semiconductor layer (single crystal silicon layer) composed of the epitaxial growth layer, that is, the conductivity type such as P type / N type and / or the carrier concentration can be arbitrarily controlled.

(G) Since the material layer such as a crystalline sapphire film serves as a diffusion barrier for various atoms, diffusion of impurities from the glass substrate can be suppressed.

(H) The low-melting-point metal layer is obtained by forming it from tin or lead or an alloy of tin and lead, or tin or lead or an alloy of tin and lead containing a semiconductor. Even if tin or lead is mixed in the single-crystal silicon layer (single-crystal semiconductor layer), these are mixed in the fourth table of the periodic table.
The element is a group element and does not become a carrier in the silicon layer, so that the silicon layer has a high resistance. Therefore, Vth adjustment and resistance adjustment of the TFT by ion doping (implantation) or the like become easy, and a high-performance circuit configuration can be realized. In addition, tin and lead remaining in the silicon layer electrically inactivate crystal defects, so that the obtained silicon layer has a reduced junction leak and an increased electron mobility.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail.
In the present invention, a single-crystal semiconductor layer, in particular, a single-crystal silicon layer is subjected to a predetermined process to form a channel region, a source region, and a drain region. Are formed and arranged so as to constitute at least a part of.

As the first substrate on which the first thin film transistor is formed, an insulating substrate is preferably used. The material layer is made of sapphire (Al
₂ O ₃ ), a spinel structure (eg, MgO · Al
₂ O ₃ ), calcium fluoride (CaF ₂ ), strontium fluoride (SrF ₂ ), barium fluoride (Ba)
F ₂ ), boron phosphide (BP), yttrium oxide ((Y ₂ O ₃ ) _m ) and zirconium oxide ((Zr
It is preferably formed of a substance selected from the group consisting of O ₂ ) _1-m ) and the like.

On such a material layer, the semiconductor film made of polycrystalline silicon or amorphous silicon is formed under reduced pressure C.
The semiconductor film is formed to a thickness of, for example, several μm to 0.005 μm by a low-temperature film forming technique at a substrate temperature of 100 to 400 ° C. such as a VD method or a sputtering method, and the low melting point metal layer is formed by a vacuum evaporation method or a sputtering method. For example, number 10 to number 1
It is preferable that the heat treatment is performed after depositing to a thickness of 00 times.

In this case, a semiconductor film made of polycrystalline silicon or amorphous silicon is formed by the low-temperature film forming technique, and the low-melting-point metal layer is deposited on or under this semiconductor film. A melting point metal layer is deposited, and then the above heat treatment is performed. Further, N-type or P-type carrier impurities (boron, phosphorus, antimony, arsenic, bismuth, etc.) are previously mixed into a semiconductor film made of polycrystalline silicon or amorphous silicon, or N-type or N-type By mixing P-type carrier impurities, the obtained single-crystal silicon layer can be formed to contain an arbitrary concentration of N-type or P-type carrier impurities.

As a method of mixing carrier impurities into the semiconductor film, an N-type or P-type carrier impurity such as P or B is added to the target during the formation of the semiconductor, or PH ₃ or P 3 is added to the supply gas. A method of mixing a doping gas such as B ₂ H ₆ or a method of ion-implanting impurities into the formed semiconductor film can be adopted. If the single-crystal silicon layer is made N-type or P-type in this way, the nMOSTFT or pMOSTF
T can be easily manufactured, and thereby the cMOS
The fabrication of the TFT can be facilitated.

When the low-melting-point metal layer is formed of tin or lead, the heat treatment is performed using a hydrogen-based (hydrogen or nitrogen-
Under a hydrogen mixture or an argon-hydrogen mixture: the same applies hereinafter) at 350 to 1100 ° C (preferably tin /
When the temperature is 400 to 600 ° C. for silicon and 500 to 800 ° C. for lead / silicon) to form a tin / silicon alloy or a lead / silicon alloy melt, and the low melting point metal is formed of an alloy of tin and lead. The heat treatment is performed in a hydrogen atmosphere at 300 to 1100 ° C. (preferably 350 to 600
C.) to form a tin / lead / silicon alloy melt. The substrate can be heated by a method of uniformly heating the entire substrate using an electric furnace, a lamp, or the like, or by a method of locally heating only a predetermined location using an optical laser, an electron beam, or the like.

The silicon-containing low melting point metal (tin / silicon or tin / lead / silicon) formed in this manner increases as the proportion of the low melting point metal (tin or lead or tin / lead) increases. The melting point decreases. Therefore,
By reducing the proportion of silicon, a melt of a silicon-containing low-melting metal can be formed at a low temperature.

As the substrate, an insulating substrate is used. In particular, a glass substrate having a relatively low strain point or a heat-resistant resin substrate can be used because a molten liquid of a silicon-containing low melting point metal can be formed at a low temperature. Can be. Therefore, a single crystal silicon layer can be formed over a large glass substrate (for example, 1 m ² or more). Such a substrate is inexpensive, easily thinned, and can be manufactured on a long rolled substrate. Therefore, a single-crystal silicon layer formed by heteroepitaxial growth can be continuously or discontinuously formed on such a long rolled glass plate or heat-resistant resin substrate by the above-described method.

Since the constituent elements are easily diffused from the inside of the glass into the upper layer of the glass having a low strain point, a diffusion barrier layer such as silicon nitride (SiN) is used for the purpose of suppressing the diffusion. Membrane (thickness eg 50-
(About 200 nm) is preferable. When the diffusion barrier layer is formed as described above, the polycrystalline silicon film, the amorphous silicon film, or the silicon-containing low melting point metal layer is formed on the diffusion barrier layer.

The single crystal silicon layer is deposited by hetero-epitaxial growth of the low melting point metal in which silicon is melted by gradually cooling the low melting metal using the material layer as a seed. After that, the low melting point metal layer on the single crystal silicon layer is dissolved and removed with hydrochloric acid or the like, and thereafter, the single crystal silicon layer is subjected to a predetermined treatment, whereby an active element and a passive element can be manufactured.

As described above, by dissolving and removing the low-melting-point metal thin film such as tin deposited on the single-crystal silicon layer after cooling using hydrochloric acid or the like, tin or lead remains in the silicon layer as an impurity. Can be prevented. Even if these tin and lead remain in the silicon layer, they do not become carriers in the silicon layer because they are elements of Group 4 of the periodic table, so that the silicon layer has a high resistance. State is maintained.

The single-crystal silicon layer thus formed is used as a layer for forming a channel region, a source region, and a drain region of a top-gate type MOSTFT constituting at least a part of a peripheral driving circuit. The impurity species in the region and / or its concentration can be controlled.

The thin film transistors of the peripheral driving circuit section and the display section constitute an n-channel, p-channel or complementary insulated gate field-effect transistor, for example, a set of a complementary type and an n-channel type, and a complementary type. It consists of a set of a p-channel type or a set of a complementary type, an n-channel type and a p-channel type. Further, it is preferable that at least a part of the thin film transistor of the peripheral drive circuit section and / or the display section has an LDD (Lightly doped drain) structure. Note that the LDD structure may be provided not only between the gate and the drain but also between the gate and the source or between the gate and the source and between the gate and the drain (this is referred to as a double LDD).

In particular, regarding the MOSTFT, an nMOS, pMOS or cMOS LD
A D-type TFT is formed, and cM
It is preferable to configure OS, nMOS, pMOSTFT, or a state in which these are mixed.

In the present invention, a step is provided on the substrate and / or a film thereon, and the step is formed together with the material layer.
It may be used as a seed during epitaxial growth of a single crystal silicon layer (single crystal semiconductor layer). Here, the term “seed” means that it functions as a seed for crystal growth, that is, at least one of normal heteroepitaxial growth and graphoepitaxial growth.

As the step, the side surface is perpendicular to the bottom surface in a sectional view, or toward the lower end (preferably).
As a concave portion having an inclined shape with a base angle of 0 ° or less,
It is formed on an insulating substrate or a film such as SiN thereon (or both). Further, it is preferable that the step is formed along at least one side of an element region formed by the channel region, the source region and the drain region of the active element, for example, the thin film transistor. Further, the passive element, for example, the element may be formed along at least one side of an element region where a resistor is formed.

In this case, the step as a seed for crystal growth may be formed at a predetermined position on the insulating substrate as the substrate, and the material layer may be formed on the insulating substrate including the step. Alternatively, the step may be formed in the material layer, and the single crystal silicon layer (single crystal semiconductor layer) may be formed on the material layer including the step. In any case, in addition to the material layer serving as a seed for normal heteroepitaxial growth in which crystal growth is performed while inheriting the crystal orientation of the base, the step is formed by crystal growth in accordance with the shape of the base. Since it acts as a seed, a single crystal silicon layer with higher crystallinity can be formed.

The first thin film transistor formed of the MOSTFT or the like may be provided in the concave portion of the substrate formed by the step, but may be provided outside the concave portion located near the concave portion, or both inside the concave portion and outside the concave portion. Good. The step can be formed by dry etching such as reactive ion etching.

In this case, the step is formed on one surface of the first substrate, and a single-crystal silicon layer, a polycrystalline silicon layer, or an amorphous silicon layer is formed on the substrate including the step. . A channel region, a source region, and a drain region of the second thin film transistor are formed from such a silicon layer, respectively, and a gate portion is provided above and / or below the channel region. A dual-gate thin film transistor may be formed.

Also in this case, the side surface is perpendicular to the bottom surface in a cross-sectional view, or 90 ° to the lower end (preferably).
The step similar to that described above may be formed as a concave part having an inclined shape having the following base angle, and this step may be used as a seed during crystal growth of the single crystal silicon layer.

With respect to the second thin film transistor,
The first substrate and / or the film formed thereon is provided inside and / or outside of the substrate recessed portion due to the step, and is formed by grapho-epitaxial growth similarly to the first thin film transistor.
Furthermore, the source, drain, and channel regions can be formed using a single crystal silicon layer formed by heteroepitaxial growth.

This second thin film transistor is also
As in the case described above, the N-type or P-type impurity species and / or the concentration thereof can be controlled by mixing N-type or P-type during the formation of the single-crystal, polycrystalline, or amorphous silicon layer. it can. Further, the step may be formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor.

Further, it is preferable that a gate electrode under the single-crystal, polycrystal or amorphous silicon layer is trapezoidal at a side end thereof, and the first substrate and the single-crystal or polycrystal are formed. Alternatively, it is preferable to provide a diffusion barrier layer between the diffusion barrier layer and the amorphous silicon layer. A source or drain electrode of the first and / or second thin film transistor;
Preferably, it is formed on a region including the step.

The first thin film transistor is at least a bottom gate type of a top gate type, a bottom gate type, or a dual gate type having a gate portion above and / or below a channel region. Further, a switching element for switching a pixel electrode in the display unit is
It is preferable that the second thin film transistor be any of the top gate type, the bottom gate type, and the dual gate type.

In this case, the gate electrode provided below the channel region is formed of a heat-resistant material, or the upper gate electrode of the second thin film transistor and the gate electrode of the first thin film transistor are formed of a common material. can do.

In the peripheral driver circuit section, in addition to the first thin film transistor, a polycrystalline or amorphous silicon layer is used as a channel region, and a top gate type having a gate portion above and / or below the channel region;
A bottom-gate or dual-gate thin film transistor, or a diode, a resistor, a capacitor, an inductance element, or the like using the single-crystal silicon layer, the polycrystalline silicon layer, or the amorphous silicon layer may be provided.

The thin film transistor of the peripheral drive circuit section and / or the display section may be configured as a single gate or a multi-gate. When the n-channel or p-channel thin film transistor of the peripheral driver circuit portion and / or the display portion is a dual gate type, the upper or lower gate electrode is electrically open or an arbitrary negative voltage (n channel Type) or a positive voltage (p-channel type). It is preferable to operate as a bottom-gate or top-gate thin film transistor.

The thin film transistor of the peripheral drive circuit section is an n-channel type, a p-channel type or a complementary type of the first thin film transistor.
Thin film transistor. Further, the thin film transistor of the display portion, a single crystal silicon layer, a polycrystalline silicon layer,
Regardless of which of the amorphous silicon layers is used as the channel region, the channel region is an n-channel type, a p-channel type, or a complementary type.

In the present invention, after the growth of the single-crystal silicon layer, an upper gate portion including a gate insulating film and a gate electrode is formed on the single-crystal silicon layer, and the single-crystal silicon layer is formed using the upper gate portion as a mask. The channel region, the source region, and the drain region may be formed by introducing an impurity element belonging to Group 3 or Group 5 of the periodic table, that is, an N-type or P-type impurity into the layer.

When the second thin film transistor is a bottom gate type or a dual gate type, a lower gate electrode made of a heat resistant material is provided below the channel region, and a gate insulating film is formed on the gate electrode. After forming the lower gate portion, the second thin film transistor can be formed through steps common to the first thin film transistor including the step of forming the step. In this case, the upper gate electrode of the second thin film transistor and the gate electrode of the first thin film transistor may be formed of a common material.

After forming the single-crystal silicon layer on the lower gate portion, an impurity element of Group 3 or 5 of the periodic table is introduced into the single-crystal silicon layer to form source and drain regions. After that, an activation process can be performed.

After the formation of the single crystal silicon layer, the source and drain regions of the first and second thin film transistors are formed by ion-implanting an impurity element using a resist as a mask. After forming the gate insulating film, the upper gate structure of the second thin film transistor may be formed.

When the thin film transistor is a top gate type, after forming the single crystal silicon layer, the source and drain regions of the first and second thin film transistors are formed by ion-implanting an impurity element using a resist as a mask. And then perform activation after ion implantation,
Thereafter, a gate portion including a gate insulating film and a gate electrode of the second thin film transistor may be formed.

Alternatively, when the thin film transistor is a top gate type, after forming the single crystal silicon layer, a gate insulating film of the second thin film transistor and a gate electrode made of a heat resistant material are formed to form a gate portion. Further, source and drain regions may be formed by ion-implanting an impurity element using the gate portion and the resist as a mask, and an activation process may be performed after the ion-implantation.

Alternatively, ion implantation for forming a source region and a drain region can be performed using a resist mask that covers the resist mask used in forming the LDD structure. Further, the substrate may be made optically opaque or transparent, and a reflective or transmissive display pixel electrode may be provided.

When the display section has a laminated structure of the pixel electrode and the color filter layer, the color filter is formed on the display array section to improve the aperture ratio and brightness of the display panel. In addition, the cost can be reduced by omitting the color filter substrate and improving the productivity. In this case, when the pixel electrode is a reflective electrode, irregularities are formed on the resin film to obtain optimal reflection characteristics and viewing angle characteristics, and a pixel electrode is provided thereon, and the pixel electrode is a transparent electrode. At times, it is preferable to flatten the surface with a transparent flattening film and to provide a pixel electrode on this flattened surface.

The display section is configured to emit light or modulate light by being driven by the MOSTFT. For example, a liquid crystal display (LCD), an electroluminescence display (E)
L), field emission display (FED), light emitting polymer display (LEPD), light emitting diode display (LE
D) or the like. In this case, a plurality of the pixel electrodes may be arranged in a matrix on the display unit, and the switching element may be connected to each of the pixel electrodes.

A control section for controlling the operation of the peripheral drive circuit section and / or the display section may be provided on the first substrate. The control unit includes a CPU (Central Processing Unit, including a microprocessor), a memory (SR
AM, DRAM, flash ferroelectricity, etc.), or a system LSI or the like obtained by combining them.
A so-called computer system may be integrated with a system-on-panel. In the case where such a control unit is provided on the first substrate, the single crystal semiconductor layer is subjected to a predetermined process, and elements for forming the control unit, for example, cMOSTFT, nMOSTFT, pMOSTF
Active elements such as T and diodes, and passive elements such as resistors, capacitors, and inductances are formed. Note that such a control unit may be formed in the same region as a vertical drive circuit or a horizontal drive circuit serving as a peripheral drive circuit unit, or may be formed in another region.

Next, a preferred embodiment of the present invention will be described in more detail. <First Embodiment> A first embodiment of the present invention will be described with reference to FIGS.

In the embodiment of the present invention, the material layer (for example, a crystalline sapphire film) is formed on the surface including the step (recess) provided on the heat-resistant substrate, and the material layer is used as a seed. An active matrix reflective liquid crystal display device (LCD) in which a single-crystal silicon layer is crystal-grown (including both heteroepitaxial growth and grapho-epitaxial growth) from tin / silicon formed on a substrate, and a bottom-gate type MOSTFT is formed using this. ).

First, the overall layout of the reflection type LCD will be described with reference to FIGS. In this active matrix reflective LCD, as shown in FIG. 11, a main substrate 1 (which constitutes an active matrix substrate, that is, a driving substrate) and a counter substrate 32 are bonded together via a spacer (not shown). It has a flat panel structure, in which liquid crystal (not shown) is sealed between the main substrate 1 and the counter substrate 32. On the surface of the main substrate 1, a display unit including pixel electrodes 29 (or 41) arranged in a matrix, a switching element for driving the pixel electrodes, and a peripheral drive circuit unit connected to the display unit are provided. Is provided.

The switching element of the display section is an nMOS, pMOS or cMOS according to the present invention, and is formed of a top gate type MOSTFT having an LDD structure. Also, in the peripheral drive circuit section, as a circuit element, a cMOS or nMO of a top gate type MOSTFT according to the present invention is used.
The S or p MOSTFTs are each formed as a single type or in a mixed state.

The one peripheral drive circuit section is a horizontal drive circuit that supplies a data signal and drives the TFT of each pixel for each horizontal line. Also, the other peripheral drive circuit section
This is a vertical drive circuit that drives the gate of the TFT of each pixel for each scanning line, and is usually provided on both sides of the display unit. In this example, these drive circuits can be configured in either a dot-sequential analog system or a line-sequential digital system.

As shown in FIG. 12, the above-mentioned TFT is arranged at the intersection of the orthogonal gate bus line and data bus line, and image information is written into the liquid crystal capacitance (C _LC ) via this TFT, and the next information is written. Holds electric charge until comes. In this case, it is not enough to hold only the channel resistance of the TFT. To compensate for this, a storage capacitance (auxiliary capacitance) (C _S ) is added in parallel with the liquid crystal capacitance to compensate for a decrease in the liquid crystal voltage due to leak current. To do.

In such an LCD TFT, the required performance is different between the characteristics of the TFT used for the pixel portion (display portion) and the characteristics of the TFT used for the peripheral driving circuit. Securing current is an important issue. For this reason, as described later, the display unit
By providing a TFT having a D structure, an electric field is hardly applied between the gate and the drain, an effective electric field applied to the channel region is reduced, an off current is reduced, and a change in characteristics is reduced. However, in order to obtain such a configuration, there are problems in that the process becomes complicated, the element size increases, and the off-state current decreases. Therefore, it is necessary to optimize the design according to the intended use. is there.

Usable liquid crystals include TN liquid crystal (nematic liquid crystal used for TN mode of active matrix driving), STN (super twisted nematic), GH (guest host), PC (phase change). , FLC (ferroelectric liquid crystal), AFL
Liquid crystals for various modes such as C (antiferroelectric liquid crystal) and PDLC (polymer dispersed liquid crystal) can be used.

Next, the circuit system of the peripheral drive circuit unit and the outline of the drive system will be described with reference to FIG. The drive circuit is divided into a gate-side drive circuit and a data-side drive circuit, and it is necessary to form a shift register on both the gate side and the data side. As the shift register, pMOSTF
Although there are those using both T and nMOSTFT (so-called CMOS circuit) and those using only one of the MOSTFTs, cMOSTFT or CMOS circuits are generally used in terms of operation speed, reliability, and low power consumption. It is a target.

The scanning drive circuit is composed of a shift register and a buffer, and sends a pulse synchronized with the horizontal scanning period to each line from the shift register. On the other hand, the data-side driving circuit has two driving methods, a dot sequential method and a line sequential method. The dot sequential system shown in FIG. 13 has a relatively simple circuit configuration, and the display signal is sequentially written directly to each pixel within one horizontal scanning time while the display signal is controlled by a shift register through an analog switch. (R,
G and B schematically show pixels for each color).

Next, an active matrix reflective LCD according to the present embodiment will be described based on a manufacturing method (process) thereof with reference to FIGS. In FIGS. 1 to 7, the left side of each drawing shows a manufacturing method (step) of the display unit, and the right side shows a manufacturing method (step) of the peripheral circuit unit.

First, as shown in FIG. 1A, a sputtered film 71A of a molybdenum / tantalum (Mo.Ta) alloy is formed on one main surface of an insulating substrate 1 such as quartz glass or transparent crystallized glass. It is formed to a thickness of about 300 to 400 nm. Next, as shown in FIG. 1B, a photoresist 70 is formed in a predetermined pattern, and the sputtered film 71A is taper-etched using the photoresist 70 as a mask to form a side end 7A.
1a forms a trapezoidal gate electrode 71 gently inclined at 20 to 45 °.

Next, as shown in FIG. 1C, after removing the photoresist, an SiN film (about 1 nm) is formed on the substrate 1 including the sputtered film 71A by a plasma CVD method or the like.
(Thickness: 00 nm) 72 and SiO ₂ film (about 200 nm thick) 73
Are formed in this order to form a gate insulating film.

Next, as shown in (4) of FIG. 2, a photoresist 2 is formed in a predetermined pattern on at least a TFT formation region on one main surface of the insulating substrate 1, and using this as a mask, for example, F _{4 of} CF ₄ plasma ^- such as performing a reactive ion etching (RIE) by ion 3 to form a plurality of stepped 4 of suitable shape and dimensions to the substrate 1 by a general purpose photolithography and etching (photoetching).

In this case, the insulating substrate 1 is made of quartz glass,
High heat resistance (8 to 12 inch φ, 700 to 8) of transparent crystallized glass, ceramics, etc. (However, an opaque ceramic substrate cannot be used in a transmission type LCD described later.)
00 μm thick) can be used. The step 4 serves as a seed for epitaxial growth of single-crystal silicon described later, that is, a seed for crystal growth including grapho-epitaxial growth and heteroepitaxial growth, and has a depth d of about 0.1 to 0.4 μm and a width w. The length (direction orthogonal to the paper surface) is about 2 to 10 μm, the length is about 10 to 20 μm, and the angle between the bottom surface and the side surface (base angle) is substantially a right angle.

The surface of the substrate 1, especially when the substrate 1 is made of a glass substrate, is exposed to Na from the substrate 1 itself.
In order to prevent diffusion of ions and the like, an SiN film is
It is preferable to form the layer to a thickness of about 0 to 200 nm and, if necessary, to form a silicon oxide film (hereinafter referred to as SiO ₂ film) to a thickness of about 100 nm, for example.

Next, as shown in FIG. 2 (5), after removing the photoresist 2, on one main surface of the insulating substrate 1,
A crystalline sapphire film 50 is formed in the TFT forming region including the step 4.
Is formed to a thickness of about 20 to 200 nm. This crystalline sapphire film 50 is formed by high-density plasma CVD or catalyst C.
It is manufactured by oxidizing trimethylaluminum gas or the like with an oxidizing gas (oxygen / moisture) and crystallizing it by a VD method (see JP-A-63-40314). Since the crystalline sapphire film 50 has a function of a Na ion stopper, the formation of the SiN film and the SiO ₂ film can be omitted when the film thickness is sufficiently hot.

Next, a known catalytic CVD method or plasma C
Substrate temperature of about 100 by VD method or sputtering
Under the temperature of 400 ° C., polycrystalline silicon is coated on the entire surface of the crystalline sapphire film 50 including the step 4 by several μm to 0.005 μm.
m (for example, 0.1 μm), and (6) in FIG.
The silicon film 5 is formed as shown in FIG. 4. Alternatively, the silicon film 5 may be formed by forming amorphous silicon instead of the polycrystalline silicon film.

When the silicon film 5 is formed, a single crystal silicon doped with an appropriate amount (eg, 0.1 to 1.0 ppm) of an N-type or P-type carrier impurity such as phosphorus or boron is used as a target. By sputtering, a silicon film in which the type and / or concentration of the carrier impurity is adjusted may be formed.

When a film is formed by the plasma CVD method, an appropriate amount of N ₃ type PH ₃ or AsH ₃ (for example, 0.1 to 1.0 pp) is added to monosilane or disilane gas or the like.
m) The silicon film 5 in which the type and / or the concentration of the carrier impurity is adjusted by mixing or mixing an appropriate amount (for example, 0.1 to 1.0 ppm) of P-type B ₂ H _6. It may be.

Then, as shown in FIG. 2 (7), tin (Sn) is formed on the silicon film 5 by sputtering or vapor deposition.
Is formed to a thickness several tens times to several hundreds times (for example, 10 to 15 μm) the silicon film 5 to form a low melting point metal layer 6 made of tin. Instead of mixing the impurities into the silicon film 5 described above, at the time of forming the low melting point metal layer 6, an appropriate amount of aluminum, indium, gallium, bismuth, antimony, etc. is mixed as impurities into the obtained low melting point metal layer 6, The N-type or P-type low melting point metal layer 6 may be formed.

Next, the substrate 1 is placed in a hydrogen-based atmosphere such as hydrogen or a nitrogen-hydrogen mixture or an argon-hydrogen mixture for 50 hours.
Heat to 0-600 ° C and hold in this state for about 5 minutes.
Then, by this heating, the silicon film 5 is dissolved in the tin melt forming the low melting point metal layer 6. In this melt, silicon exhibits a property of being deposited at a temperature significantly lower than the original deposition temperature. As a method for heating the substrate 1, a method for uniformly heating the entire substrate using an electric furnace or the like, or a method for heating the substrate 1 only at a predetermined place using an optical laser, an electron beam, or the like,
A method of locally heating only the FT formation region is employed.

Then, by gradually cooling, the silicon dissolved in the tin is used as a seed (seed) for crystal growth using the corners on the bottom surface of the step 4 and the crystalline sapphire film 50 as shown in FIG. The single crystal silicon is deposited to thereby form a single crystal silicon layer 7 having a thickness of about 5 to 100 nm, preferably about 30 to 50 nm.

In the single-crystal silicon layer 7 deposited as described above, since the crystalline sapphire film 50 shows good lattice matching with single-crystal silicon, for example, the (100) plane is heteroepitaxially grown on the substrate. In this case, the step 4 also contributes to epitaxial growth in consideration of a known phenomenon called grapho-epitaxial growth, so that the single crystal silicon layer 7 with higher crystallinity can be obtained. In this regard, as shown in FIG. 9, when a vertical wall such as the above-described step 4 is formed on an amorphous substrate (glass) 1 and an epitaxy layer is formed thereon, a random wall as shown in FIG. 9B, the (100) plane grows along the plane of the step 4 as shown in FIG. The size of the single crystal grains increases in proportion to the temperature and time, but when the temperature and time are reduced or shortened, the interval between the steps must be shortened.

The shapes of the steps are shown in FIGS.
By changing variously as in (f), the crystal orientation of the growth layer can be controlled. When fabricating MOS transistors, the (100) plane is most often employed. In short, the cross-sectional shape of the step 4 may be such that the angle of the bottom corner (base angle) may be a right angle, or may be inclined inward or outward from the upper end to the lower end. It is sufficient if it has. Usually, the bottom angle of the step 4 is desirably a right angle or 90 ° or less, and the corner of the bottom surface preferably has a slight curvature.

After the single-crystal silicon layer 7 is deposited on the substrate 1 by epitaxial growth in this way, as shown in FIG. 3 (9), the film 6A mainly composed of tin deposited on the surface side is formed by ( 3 (8) is dissolved and removed with hydrochloric acid, sulfuric acid or the like. At this time, post-processing is performed so that a low-grade silicon oxide film is not generated. Subsequently, a bottom gate type MOST using the single crystal silicon layer 7 as a channel region
FT for peripheral drive circuit, top gate type MOST
The FT is manufactured on the display unit as follows.

First, since the impurity concentration of the single crystal silicon layer 7 formed by the epitaxial growth described above varies, the specific resistance is adjusted by doping an appropriate amount of a P-type carrier impurity, for example, boron ions over the entire surface. Also, pM
N-type carrier impurities are selectively doped only in the OSTFT formation region to form an N-type well. For example, pM
The OSTFT portion is masked with a photoresist (not shown), and P-type impurity ions (for example, B ⁺ ) are applied at 10 kV.
Doping is performed at a dose of 7 × 10 ¹¹ atoms / cm ² to adjust the specific resistance.

Further, as shown in FIG.
In order to control the impurity concentration in the OSTFT formation region, an nMOS
The TFT portion is masked with a photoresist 60, and N-type impurity ions (for example, P ⁺ ) 65 are applied at 10 kV to 1 × 10 ¹¹ at.
An N-type well 7A is formed by doping with a dose of oms / cm ² .

Next, as shown in (11) of FIG. 4, SiO ₂ (about 100%) is formed on the entire surface of the single-crystal silicon layer 7 by plasma CVD, high-density plasma CVD, catalytic CVD, or the like.
nm thick) and SiN (approximately 200 nm thick) in this order to form a gate insulating film 8, and a molybdenum-tantalum (Mo.Ta) alloy sputtered film 9 having a thickness of 5 nm.
It is formed to a thickness of about 00 to 600 nm.

Next, as shown in FIG. 4 (12), the TFT in the display area is formed by a general-purpose photolithography technique.
Photoresist pattern 10 in the step region (in the concave portion)
Is formed, and is successively etched using this as a mask to form a gate electrode 11 of a Mo.Ta alloy and a gate insulating film 12 having a laminated structure of (SiN / SiO ₂ ). The layer 7 is exposed. The sputtered film 9 made of the Mo.Ta alloy is treated with an acid-based etching solution, SiN is treated with plasma etching of CF ₄ gas, and SiO ₂ is treated with a hydrofluoric acid-based etching solution.

Next, as shown in (13) of FIG. 4, all of the nMOS and pMOSTFT in the peripheral driving region and the gate portion of the nMOSTFT in the display region are formed by photoresist 1
3, phosphorus ions 14 are applied to the exposed source / drain regions of the nMOSTFT, for example, at 1 × 1 at 10 kV.
Doping (ion implantation) is performed at a dose of 0 ¹³ atoms / cm ² to form an LDD portion 15 made of an N ⁻ -type layer in a self-aligned manner (self-aligned).

Next, as shown in FIG. 5 (14), all of the pMOS TFTs in the peripheral drive region and n in the peripheral drive region
Gate portion of MOSTFT and nMOSTFT in display area
And the LDD portion are covered with a photoresist 16 and phosphorus or arsenic ions 17
Doping (ion implantation) is performed at 0 kv with a dose of 5 × 10 ¹⁵ atoms / cm ² , and the source 18 and the drain 19 and the LDD 1 made of the N ⁺ type layer of the nMOS TFT are formed.
5 is formed.

Next, as shown in FIG. 5 (15), the nMOSTFT in the peripheral driving region and the nMOST in the display region are used.
The entirety of the FT and the gate of the pMOSTFT are covered with a photoresist 20 and boron ions 2
1 at 5 × 10 ¹⁵ atoms / cm ^{2 at} 10 kv, for example.
Doping (ion implantation) at a dose of pMOST
The source part 22 and the drain part 23 of the P ⁺ layer of the FT are formed. This step is unnecessary in the case of the nMOS peripheral drive circuit because there is no pMOSTFT.

Next, as shown in FIG.
A photoresist 24 is formed to make an active element portion such as an FT or a diode or a passive element portion such as a resistor or an inductance into an island. Then, the single crystal silicon layer 7 other than all the active element portions and the passive element portions in the peripheral drive region and the display region is removed by etching using a hydrofluoric acid-based etchant.

Next, as shown in FIG. 6 (17), an SiO ₂ film (about 200 nm thick) and a phosphosilicate glass (PSG) film (about (Thickness of 300 nm) is formed continuously in this order, and the protective film 25 is formed.

Then, in this state, the single crystal silicon layer 7 is activated. For this activation, for example, a lamp of halogen or the like is used, and the annealing condition is set to about 1000.
C. for about 10 seconds. Therefore, a material that can withstand such annealing conditions is required as a gate electrode material, but the above-mentioned Mo / Ta alloy has a high melting point,
The structure can withstand such annealing conditions.
Further, since the gate electrode material made of the Mo.Ta alloy has a high melting point and can withstand annealing conditions, it can be formed not only as a gate portion but also as a wiring over a wide range. Here, an annealing process using an expensive excimer laser is not performed. However, when this annealing process is performed, XeCl (308 nm wavelength) is applied to the entire surface or only the active element portion and the passive element portion are selectively removed.
It is desirable to carry out irradiation treatment with 0% or more overlap scanning.

Next, as shown in FIG. 6 (18), contact windows for the source / drain portions of all the TFTs of the peripheral drive circuit and the source portions of the display TFTs are opened by general-purpose photolithography and etching techniques. .

Then, aluminum or aluminum alloy (for example, aluminum containing 1% Si or 1 to
Sputtered film of copper, aluminum, etc.
And a source electrode 26 of all the TFTs of the peripheral drive circuit and the display portion and a drain electrode 27 of the peripheral drive circuit portion by general-purpose photolithography and etching technology. Form a gate line. Thereafter, in a forming gas (N ₂ + H ₂ ), about 400 ° C./1
Sintering with h.

Next, as shown in (19) of FIG. 6, an insulating film 36 made of a PSG film (about 300 nm thick) and a SiN film (about 300 nm thick) is formed by plasma CVD, high-density plasma CVD, catalytic CVD, or the like. Is formed on the entire surface.
Next, a contact window is opened in the drain portion of the display TFT. Note that SiO ₂ , PSG and SiN in the pixel portion are used.
The film does not need to be removed.

Here, as a basic requirement of the reflection type liquid crystal display device, a function of reflecting incident light and a function of scattering incident light must be provided inside the liquid crystal panel. This is because the direction of the observer with respect to the display is substantially determined, but the direction of the incident light cannot be uniquely determined. For this reason, it is necessary to design a reflector assuming that a point light source exists in an arbitrary direction. Therefore, as shown in (20) of FIG.
A photosensitive resin film 28 having a thickness of about 3 μm is formed. Subsequently, as shown in FIG. 7 (21), a general-purpose photolithography and etching technique is used to form a concavo-convex pattern for obtaining optimum reflection characteristics and viewing angle characteristics. It is formed in the pixel portion and is reflowed to form a lower reflective surface made of the roughened surface 28A. At the same time, a resin window for contact of the drain portion of the display TFT is opened.

Next, as shown in FIG. 7 (22), aluminum or aluminum having a thickness of about 400 to 500 nm is formed on the entire surface.
% Sputtered film such as aluminum alloy containing Si,
Further, the sputtered film other than the pixel portion is removed by a general-purpose photolithography and etching technique, and a reflective film 29 made of a concavo-convex shaped aluminum alloy or the like connected to the drain portion 19 of the display TFT is formed. This reflection film 29
It also functions as a pixel electrode for display. Thereafter, sintering is performed in a forming gas at about 300 ° C. for 1 hour to make the contact sufficient. Note that silver or a silver alloy may be used instead of an aluminum-based material to increase the reflectance.

As described above, a single-crystal silicon layer 7 is formed using the sapphire film 50 including the step 4 as a seed for epitaxial growth, and a top-gate type nMOSLDD-TFT is formed on a display unit using the single-crystal silicon layer 7. ,
Also, a bottom gate type pMOSTFT is used for the peripheral drive circuit.
In addition, it is possible to manufacture an active matrix substrate 30 that integrates a display section and a peripheral drive circuit section and that incorporates a CMOS circuit configured with nMOS TFTs.

Next, a method of manufacturing a reflective liquid crystal display (LCD) using the active matrix substrate (drive substrate) 30 will be described with reference to FIG. Hereinafter, this active matrix substrate is referred to as a TFT substrate.

When the liquid crystal cell of this LCD is manufactured by a surface assembly suitable for a medium / large liquid crystal panel of 2 inches or more, first, the TFT substrate 30 and the entire solid IT
Opposite substrate 32 provided with O (Indium tin oxide) electrode 31
The polyimide-based alignment films 33, 3
4 is formed. For these polyimide-based alignment films 33 and 34, polyimide is applied to a thickness of about 50 to 100 nm by roll coating, spin coating, or the like, and thereafter,
It is formed by curing at 180 ° C. for 2 hours.

Next, the TFT substrate 30 and the counter substrate 3
Rubbing or optical alignment processing is performed on each of the polyimide-based alignment films 33 and 34 of No. 2. Rubbing buff materials include cotton and rayon, but cotton is more stable in terms of buff residue (garbage) and retardation. Photoalignment is a technique for aligning liquid crystal molecules by non-contact linearly polarized ultraviolet irradiation. In addition to the rubbing, the polymer alignment film can be formed by obliquely incident polarized light or non-polarized light. As a polymer compound that can form such a polymer alignment film, for example, a polymethyl methacrylate-based polymer having azobenzene can be given.

Next, in order to remove the rubbing buff residue,
After washing with water or IPA (isopropyl alcohol), a common agent is applied to the TFT substrate 30 side, and a sealing agent is applied to the counter substrate 32 side. Acrylic, epoxy acrylate, or epoxy adhesive containing a conductive filler is used as the common agent, and acrylic, epoxy acrylate, or epoxy adhesive is used as the sealant. As the common agent and the sealant, any of a heat curing type, an ultraviolet irradiation curing type, and an ultraviolet irradiation curing + heat curing type can be used. It is preferable to use a radiation curing + heat curing type.

Next, spacers for obtaining a predetermined gap are sprayed on the counter substrate 32 side, and are superposed on the TFT substrate 30 at a predetermined position. After the alignment marks on the counter substrate 32 and the TFT substrate 30 are precisely aligned, the sealant is temporarily cured by irradiating ultraviolet rays, and then heat-cured collectively.

Next, a scribe break is performed to
A single liquid crystal panel in which the substrate 30 and the counter substrate 32 are overlapped is manufactured. Next, the liquid crystal 35 is applied to both substrates 30-32.
It is injected into the gap between them, and after the injection port is sealed with an ultraviolet adhesive, IPA cleaning is performed. Although the type of liquid crystal is not particularly limited as described above, for example, a high-speed TN (twisted nematic) mode using a nematic liquid crystal is generally used. Next, the liquid crystal 35 is oriented by heating and quenching. Next, a flexible wiring is connected to the panel electrode take-out portion of the TFT substrate 30 by thermocompression bonding of an anisotropic conductive film, and a polarizing plate with a retardation plate is bonded to the counter substrate 32.

When a liquid crystal panel (liquid crystal cell) is manufactured by a single surface assembly suitable for a small liquid crystal panel having a size of 2 inches or less, the TFT substrate 30 and the counter substrate 32 are formed on the element formation surface in the same manner as described above. Polyimide-based alignment films 33 and 34 are formed, respectively, and the polyimide-based alignment films 33 and 34 are subjected to rubbing or alignment treatment using non-contact linearly polarized ultraviolet light.

Next, the TFT substrate 30 and the counter substrate 3
2 is singly divided by dicing or scribe break, and washed with water or IPA. Subsequently, a common agent is applied to the TFT substrate 30, and a sealing agent containing a spacer is applied to the counter substrate 32. Then, the two substrates are overlapped. Subsequent processes are the same as described above, and a description thereof will be omitted.

In the reflection type LCD described above, the opposing substrate 32 is a CF (color filter) substrate, and the color filter layer 46 is provided below the ITO electrode 31.
In such a reflection type LCD, incident light from the counter substrate 32 side is efficiently reflected by the reflection film 29 and emitted from the counter substrate 32 side.

When the reflective film 29 is also used as a pixel electrode for display as in the above-described example, and the polyimide-based alignment film 33 is directly formed thereon,
In the case of No. 3, the unevenness of the reflective film 29 serving as a base may cause unevenness in film thickness, rubbing unevenness, and rubbing may cause scratches or peeling and color unevenness.

Therefore, the reflection film 29 is formed so as not to conduct to the drain portion of the TFT so that it does not function as a pixel electrode, and a transparent electrode (I
(A TO electrode). In that case, TF
A thickness of 2 to 3 on the reflection film 29 which does not conduct to the drain portion of T
A transparent resin flattening film of about μm is formed, and a transparent electrode (ITO electrode) having a thickness of about 0.13 to 0.15 μm is formed thereon.
Is formed in a state of being electrically connected to the drain portion of the TFT.

As described above, if a transparent electrode is formed via the transparent resin flattening film, the surface of the transparent electrode is naturally flat, and the polyimide alignment film 33 formed thereon is also flat. Therefore, unevenness in film thickness, rubbing unevenness, scratches and peeling due to rubbing, color unevenness, and the like are prevented from occurring, and quality and yield can be improved.

When the TFT substrate 30 has an on-chip color filter (OCCF) structure in which a color filter is provided on the TFT substrate 30 in addition to the substrate structure shown in FIG. (Or ITO electrode with black mask is solid) and T
The FT substrate 30 is provided with a color filter.

Also in this case, for the TFT substrate 30, the above-described structure in which a transparent electrode (ITO electrode) is provided separately from the reflective film 29 as a pixel electrode can be adopted. That is, a transparent resin flattening film having a thickness of about 2 to 3 μm is formed on the reflection film 29 formed so as not to conduct to the drain portion of the TFT, and a color filter layer having a thickness of about 1 to 2 μm is formed thereon. I do. Then, a transparent resin flattening film having a thickness of about 1 to 2 μm is further formed thereon, and a transparent electrode (I) having a thickness of about 0.13 to 0.15 μm is formed thereon.
TO electrode) is formed in a state of being electrically connected to the drain of the TFT.

As described above, if the color filter and the transparent electrode are formed via the transparent resin flattening film, the surface of the transparent electrode becomes flat as described above, and the polyimide alignment film 33 becomes flat. Therefore, it is possible to prevent unevenness in film thickness, uneven rubbing, scratches and peeling due to rubbing, uneven color, and the like, and to improve quality and yield. Incidentally, in the case of incorporating an auxiliary capacitance C _S shown in FIG. 12 in the pixel portion, electrostatic collector layer provided on the substrate 1 described above (not shown) may be connected to the drain region 19 of monocrystalline silicon .

As described above, according to the present embodiment, the following remarkable effects can be obtained. (A) A crystalline sapphire film 50 is formed on a substrate 1 provided with a step 4 having a predetermined shape / dimension, and this is used as a seed for heteroepitaxial growth (however, the heating temperature during growth is 50
0-600 ° C.).
Since a single crystal silicon layer 7 having a high electron mobility of not less than cm ² / v · sec can be obtained, an LCD with a built-in high-performance driver can be obtained.
Can be manufactured. In addition, since the step 4 promotes the epitaxial growth, a single crystal silicon layer 7 having higher crystallinity can be obtained.

(B) This single-crystal silicon layer 7 has a smaller thickness than a conventional amorphous silicon layer or polycrystalline silicon layer.
Since it exhibits high electron and hole mobilities comparable to a single crystal silicon substrate, the resulting single crystal silicon bottom gate type MOSTFT has nMOS or pMOS or cMO having an LDD structure with high switching characteristics and low leakage current.
STFT display, high drive capability cMOS, nMO
A structure integrated with a peripheral driver circuit section made of S or pMOSTFT or a mixture of them becomes possible, and a display panel with high image quality, high definition, narrow frame, large screen, and high efficiency is realized. Further, since the single crystal silicon layer 7 has a sufficiently high hole mobility, a peripheral drive circuit for driving electrons and holes individually or in combination of both can be manufactured. Alternatively, a panel integrated with a display TFT having a pMOS or cMOS LDD structure can be realized. In the case of a small to medium-sized panel, there is a possibility that one of a pair of peripheral vertical drive circuits can be omitted.

(C) The substrate temperature of polycrystalline silicon, amorphous silicon, etc.
It can be formed by a plasma CVD method or a low pressure CVD method under the condition of a temperature of ° C., and the low melting point metal layer can be formed by a known method such as a vacuum evaporation method or a sputtering method. In addition, since the heat treatment temperature during the above-described silicon epitaxial growth can be set to 600 ° C. or less, a single-crystal silicon layer is uniformly formed at a relatively low temperature (for example, 400 to 450 ° C.) on an insulating substrate. can do.

(D) Since long-time annealing at an intermediate temperature and excimer laser annealing as in the case of the solid phase growth method are not required, productivity is high, and cost reduction is possible without using expensive manufacturing equipment. become.

(E) In this crystal growth (epitaxial growth), the crystallinity of the crystalline sapphire film or the like, the tin / silicon composition ratio, the shape and size of the step, the heating temperature and cooling rate of the substrate, the N-type or P-type to be added. By adjusting the carrier impurity concentration and the like, a wide range of conductive type such as N-type or P-type and a high mobility single crystal silicon layer can be easily obtained, so that Vth (threshold) can be easily adjusted and low resistance can be obtained. High speed operation is also possible due to the development.

(F) If color filters are formed on the display array section, cost reduction can be realized by improving the aperture ratio and luminance of the display panel, omitting the color filter substrate, improving productivity, and the like.

(G) Since the material layer such as a crystalline sapphire film serves as a diffusion barrier for various atoms, diffusion of impurities from the glass substrate can be suppressed.

(H) Since the low-melting-point metal layer 6 is formed of tin, even if tin is mixed into the obtained single-crystal silicon layer 7, this is an element of Group 4 of the periodic table. Therefore, the single crystal silicon layer 7 does not become a carrier in the silicon layer, so that the single crystal silicon layer 7 has a high resistance. Therefore, Vth adjustment and resistance adjustment of the TFT by ion doping (implantation) or the like become easy, and a high-performance circuit configuration can be realized. Further, tin remaining in the single crystal silicon layer 7 electrically inactivates crystal defects, so that the obtained single crystal silicon layer 7 has reduced junction leakage and improved electron mobility. Become.

<Second Embodiment> Referring to FIG.
A second embodiment of the present invention will be described.

The present embodiment relates to an active matrix reflective LCD like the first embodiment described above, and differs from the first embodiment in the point that the silicon film 5 is different from the first embodiment. And the order of forming the low melting point metal layer 6 is changed. That is, in the present embodiment, after the step shown in FIG.
As shown in FIG. 1, first, a crystalline sapphire film 5 including a step 4 is formed.
A low-melting metal layer 6 made of, for example, tin is formed on the entire surface on the substrate 0 to a thickness of about 10 to 20 μm by a sputtering method or a vacuum evaporation method.

Next, as shown in FIG. 14 (7), amorphous silicon is deposited on the low melting point metal layer 6 by a known plasma CVD method, and several μm to 0.005 μm
A silicon film 5 having a thickness (for example, 0.1 μm) is formed. In this case, regarding the formation temperature of the silicon film 5, the melting point of the low melting point metal 6, that is, the melting point of tin (231.97)
° C).
It is difficult to form a polycrystalline silicon film (at 600 to 650 ° C.). Therefore, amorphous silicon is formed by plasma CVD to form the silicon film 5 on the low melting point metal layer 6.

Next, the substrate 1 is placed in a hydrogen atmosphere at 110
The temperature is kept at 0 ° C. or lower (particularly, 400 to 600 ° C.) for several minutes to several tens minutes (for example, about 5 minutes), whereby the silicon film 5 is dissolved in the tin melt. Then, by gradually cooling, the silicon dissolved in tin is used as a seed (seed) for crystal growth at the corner of the bottom surface of the step 4, as shown in FIG. )
As a result, single-crystal silicon is deposited to a thickness of 5 to 100 n.
The single crystal silicon layer 7 having a thickness of m, preferably about 30 to 50 nm is formed.

In this case, the single crystal silicon layer 7 has the (100) plane epitaxially grown on the substrate similarly to the above-described embodiment.
By changing variously as in (a) to (f), the crystal orientation of the growth layer can be controlled.

As described above, after the single-crystal silicon layer 7 is deposited on the substrate 1 by crystal growth (heteroepitaxial growth), tin formed on the surface side is mainly used as in the first embodiment. A film as a component is dissolved and removed with hydrochloric acid or the like, and further, a step of performing a predetermined process on the single crystal silicon layer 7 is performed to manufacture each TFT of the display portion and the peripheral drive circuit portion.

In this embodiment, the crystalline sapphire film 5
, A low melting point metal layer 6 is formed thereon, and a silicon film 5 is formed thereon.
Is formed, and then subjected to heat melting and cooling, but crystal growth (heteroepitaxial growth) of single crystal silicon from a low melting metal melt occurs in the same manner as in the first embodiment.

<Third Embodiment> Referring to FIG.
A third embodiment of the present invention will be described. The present embodiment relates to an active matrix reflective LCD like the first embodiment described above, and differs from the first embodiment in that the silicon film 5 and the low melting point metal are different from those of the first embodiment. The point is that a silicon-containing low melting point metal layer 6A is formed instead of forming each of the layers 6. That is, in the present embodiment, after the step shown in FIG. 2 (5), a predetermined amount of tin is deposited on the entire surface of the crystalline sapphire film 50 including the step 4 as shown in FIG. (0.03% to 0.0005% by weight, preferably 0.014% to
0.0035% by weight) of a low melting point metal layer 6A containing silicon by sputtering or vacuum evaporation.
It is formed to about 20 μm.

Next, the substrate 1 is placed in a hydrogen-based atmosphere at 110
The temperature is maintained at 0 ° C. or lower (particularly, 400 to 600 ° C.) for several minutes to several tens minutes (for example, about 5 minutes).
The silicon in A is dissolved in the tin melt. Then, by gradually cooling, the silicon dissolved in tin,
Using the crystalline sapphire film 50 (and furthermore, the step 4) as a seed, heteroepitaxial growth is performed as shown in FIG. 15 (7), whereby single crystal silicon is deposited and has a thickness of 5 to 100 nm, preferably 30 to 50 nm. A single crystal silicon layer 7 is formed.

In this case, the (100) plane of the single crystal silicon layer 7 is epitaxially grown on the substrate in the same manner as described above.
By changing variously as in (f), the crystal orientation of the growth layer can be controlled. After the single-crystal silicon layer 7 is deposited on the substrate 1 by heteroepitaxial growth in this manner, the tin-based film formed on the surface side is formed with hydrochloric acid or the like in the same manner as in the first embodiment. Through the process of dissolving and removing the single crystal silicon layer 7 and subjecting the single crystal silicon layer 7 to a predetermined process, the TFTs of the display portion and the peripheral drive circuit portion are manufactured.

In the present embodiment, although a low-melting metal layer 6A containing silicon is formed on the step 4 and then heated and melted and cooled, heteroepitaxial growth of single crystal silicon from the low-melting metal melt is performed. Occurs in the same manner as in the first embodiment.

<Fourth Embodiment> Referring to FIGS. 16 to 18, a fourth embodiment of the present invention will be described. In the embodiment of the present embodiment, the top gate type MOSTFT is provided in the display unit and the bottom gate type MOSTFT is provided in the peripheral drive circuit unit, as in the first embodiment. Unlike the embodiment, the present invention relates to a transmission type LCD. Therefore, the manufacturing steps are the same from the step shown in FIG. 1A to the step shown in FIG. Then, in the embodiment of the present example, after these steps, as shown in FIG.
5. At the same time as opening a window for the drain portion contact of the display TFT in the insulating film 36, unnecessary portions of the SiO ₂ , PSG and SiN films in the pixel opening are removed to improve the transmittance. In this example, an opaque ceramic substrate cannot be used.

Next, as shown in FIG.
On the entire surface, a flattening film 28B of a photosensitive acrylic transparent resin is formed to a thickness of about 2 to 3 μm by spin coating or the like,
TF for display by general-purpose photolithography technology
A window is opened in the flattening film 28B on the drain side of T, and this is cured under predetermined conditions.

Next, as shown in (22) of FIG.
An ITO sputtered film having a thickness of about 130 to 150 nm is formed on the entire surface, and a transparent electrode (pixel electrode) 41 made of ITO in contact with the drain portion 19 of the display TFT is formed by general-purpose photolithography and etching technology. Then, heat treatment (in forming gas, 200
(250 ° C./1 h), the contact resistance between the drain of the display TFT and ITO is reduced, and the transparency of ITO is improved.

[0139] Then, as shown in FIG.
And a transmission type LCD is assembled in the same manner as in the first embodiment. However, a polarizing plate is also attached to the TFT substrate side. In this transmissive LCD, transmitted light is obtained as indicated by a solid arrow, but it may be configured such that transmitted light from the counter substrate 32 side is obtained as indicated by an alternate long and short dashed arrow.

In the case of this transmission type LCD, an on-chip color filter (OCCF) structure and an on-chip black (OCB) structure can be manufactured as follows.

That is, (1) in FIG. 1 to (18) in FIG.
The steps up to are performed in the same manner as described above. Then, as shown in FIG. 18 (19), the PSG / SiO
_After opening the drain portion of the _second insulating film 25 to form an aluminum buried layer 41A for the drain electrode,
An N / PSG insulating film 36 is formed.

Next, as shown in FIG. 18 (20), a photoresist 61 in which each color of R, G and B is dispersed in a pigment for each segment is formed to a predetermined thickness (1 to 1.5 μm). As shown in FIG. 18 (21), patterning is performed by using a general-purpose photolithography technique, leaving only predetermined positions (each pixel portion), and each color filter layer 61 (R), 61
(G) and 61 (B) are formed (on-chip color filter structure). At this time, the window of the drain part is also opened.

Next, as shown in (21) of FIG.
In a contact hole communicating with the drain of the display TFT, a light shielding layer 43 serving as a black mask layer of the display TFT is formed by metal patterning over the color filter layer. For example, a film of titanium or molybdenum is formed to a thickness of about 200 to 250 nm by a sputtering method, and is then patterned into a predetermined shape that covers the display TFT and shields light (on-chip black structure).

Next, as shown in FIG. 18 (22),
A flattening film 28B made of a transparent resin is formed, and a transparent electrode 41 is buried in a through hole provided in the flattening film so as to be connected to the light shielding layer 43.

As described above, by forming the color filter layer 61 and the light shielding layer 43 on the display array portion, the aperture ratio of the liquid crystal display panel can be improved, and the power consumption of the display module including the backlight can be reduced. Can be realized.

<Fifth Embodiment> A fifth embodiment of the present invention will be described. In the embodiment of this example, the above-described steps (concave portions) and a crystalline sapphire film are formed on a glass substrate having a low strain point, and a single-crystal silicon layer is heteroepitaxially grown from a tin-lead-silicon alloy melt using these as seeds. And an active matrix reflective liquid crystal display device (LC
D).

That is, in the present embodiment, the first
In the process shown in FIG. 1A in the embodiment, the strain point or the maximum use temperature of the substrate 1 is, for example, 60%.
A glass substrate as low as about 0 ° C., for example, a glass substrate such as borosilicate glass or aluminosilicate glass is used. this is,
It is inexpensive and easy to increase the size, and the thickness of the thin plate is increased (for example, 5
(00 × 600 × 0.1 to 1.1 mm thick), it can be rolled / lengthened. Of course, a quartz substrate or a crystallized glass substrate can also be used.

After forming the step 4 and the crystalline sapphire film 50 in the same manner as described above, as shown in FIG. 2 (6), a known plasma CVD method, a sputtering method, or a known reduced pressure CVD method. Thus, polycrystalline silicon or amorphous silicon is deposited on the entire surface including the step 4 to form a silicon film 5 having a thickness of several μm to 0.005 μm (for example, 0.1 μm).

Next, as shown in FIG. 2 (7), tin (S) is deposited on the silicon film 5 by sputtering or vapor deposition.
n) a lead (Pb) alloy (for example, a eutectic solder of Sn: Pb = 6: 4) several tens times to several hundreds times the silicon film 5
The film is formed to have a double thickness (for example, 10 to 20 μm), and the low melting point metal layer 6 made of a tin-lead alloy is formed.

Next, the substrate 1 was placed under a hydrogen-based atmosphere for 400 hours.
Heat to ~ 600 ° C and hold in this state for about 5 minutes. Then, the silicon film 5 is dissolved in the tin / lead melt forming the low melting point metal layer 6 by this heating. In this melt, silicon exhibits a property of being deposited at a temperature significantly lower than the original deposition temperature.

Next, by gradually cooling, tin
The silicon dissolved in the lead is used as a seed for crystal growth using the corner of the bottom surface of the step 4 and the sapphire film 50 as shown in FIG.
As shown in (8) above, heteroepitaxial growth is performed, thereby depositing single-crystal silicon to a thickness of 5 to 10
A single-crystal silicon layer 7 having a thickness of 0 nm, preferably about 30 to 50 nm is formed.

In this case, the single crystal silicon layer 7 has the (100) plane epitaxially grown on the substrate as in the above-described embodiment.
By changing variously as in (a) to (f), the crystal orientation of the growth layer can be controlled.

As described above, after the single crystal silicon layer 7 is deposited on the substrate 1 by heteroepitaxial growth,
In the same manner as in the first embodiment described above, the film mainly composed of tin and lead formed on the surface side is dissolved and removed with hydrochloric acid or the like, and further, the single crystal silicon layer 7 is subjected to a predetermined process. Then, each TFT of the display section and the peripheral drive circuit section is manufactured. Note that the structure shown in FIG. 8 is also applied to the present embodiment.

According to the present embodiment, in addition to the functions and effects described in the above-described first embodiment, the following remarkable functions and effects can be obtained. (I) The single crystal silicon layer 7 can be formed uniformly on the glass substrate 1 by epitaxial growth at a lower temperature of about 400 to 600 ° C.

(J) Since the single-crystal silicon layer 7 can be formed not only on a glass substrate but also on an insulating substrate such as a resin substrate, a substrate material having a low strain point, low cost and good physical properties can be obtained. It can be arbitrarily selected, and the size of the substrate can be increased. Glass substrates and heat-resistant resin substrates can be manufactured at a lower cost than quartz substrates and ceramic substrates, and can be made thinner / longer / rolled. It is possible to manufacture a large-sized glass substrate or the like that has been lengthened / rolled with good productivity and at low cost. As a glass substrate,
Low glass strain point (or maximum operating temperature) (eg, 500
C.) When glass is used, when its constituent elements diffuse from the inside of the glass into the upper layer and affect the transistor characteristics, a barrier layer thin film (for example, silicon nitride: having a thickness of 50 to 50 mm) is used for the purpose of controlling this. (About 200 nm).

(K) In this low-temperature heteroepitaxial growth, a wide range of N is adjusted by adjusting the composition ratio of the low-melting metal layer 6 made of tin / lead, the heating temperature and the cooling rate, and the concentration of N-type or P-type carrier impurities to be added. Since a single-crystal silicon layer having a high mobility and a high conductivity type and a P-type conductivity type can be easily obtained, Vt
Adjustment of h (threshold) becomes easy, and high-speed operation by lowering the resistance becomes possible.

<Sixth Embodiment> A sixth embodiment of the present invention will be described.

This embodiment is different from the fifth embodiment in that the fifth embodiment is a reflection type LCD.
In the manufacturing process, a single-crystal silicon layer 7 is formed by low-temperature heteroepitaxial growth using a low-melting-point metal layer 6 made of a tin-lead alloy, as described in the fifth embodiment. be able to.

Then, using this single crystal silicon layer 7,
A transmissive LCD can be manufactured in the same manner as shown in FIGS. 16 to 18 in the above-described fourth embodiment. However, in this example, an opaque ceramic substrate or an opaque or low transmittance resin substrate cannot be used.

Therefore, in the present embodiment, the fifth
The fourth embodiment and the fourth embodiment can have excellent functions and effects. That is, in addition to the functions and effects of the first embodiment described above, it is possible to use a low-cost and thin and long substrate 1 such as a heat-resistant resin substrate such as borosilicate glass or heat-resistant polyimide. The conductivity type of the single crystal silicon layer 7 and Vth
Is easy to adjust, and by forming the color filter 42 and the black mask 43 on the display array portion,
Also, the aperture ratio of the liquid crystal display panel can be improved, and the power consumption of the display module including the backlight can be reduced.

<Seventh Embodiment> The seventh embodiment of the present invention will be described with reference to FIGS.

In the present embodiment, the peripheral drive circuit section is formed of the same bottom gate type pM as in the first embodiment.
It is composed of a CMOS drive circuit composed of an OSTFT and an nMOSTFT. In addition, although the display section is of a reflective type, the TFTs have various gate structures and various combinations.

That is, in the above-described first embodiment, as shown in FIG. 19A, a top gate type n
While the MOSLDD-TFT is provided, FIG.
In the example shown in (B), the display unit has a bottom gate type nMO.
An SLDD-TFT is provided, and in the example shown in FIG.
A D-TFT is provided. These bottom gate type MOS
Both TFT and dual-gate MOSTFT
As will be described later, the bottom gate type MOS of the peripheral drive circuit section
It can be manufactured in the same process as the TFT. In the case where the gate structure of the TFT of the display portion is changed in this way, especially in the case of a dual gate type, the driving capability is improved by the upper and lower gate portions, which is suitable for high-speed switching. It can be selectively used to operate as a top gate type or a bottom gate type depending on the case.

The bottom gate type MO shown in FIG.
In the STFT, reference numeral 71 in the figure denotes a gate electrode made of Mo, Ta, or the like. Reference numeral 72 denotes an SiN film, 7
Reference numeral 3 denotes an SiO ₂ film, and a gate insulating film is formed by the SiN film and the SiO ₂ film. On this gate insulating film, a channel region using a single crystal silicon layer 7 and the like are formed similarly to the top gate type MOSTFT. Further, the dual gate type MOS shown in FIG.
In a TFT, the lower gate part is a bottom gate type MOSTF
Although the same as T, the upper gate portion has a gate insulating film 73 formed of a SiO ₂ film and a SiO ₂ film, on which an upper gate electrode 74 is provided. However, in each case, each gate portion is disposed outside the step 4 which acts as a seed during epitaxial growth and at the same time promotes the growth of the single crystal silicon film and has the effect of increasing the crystallinity.

Next, the above-mentioned bottom gate type MOSTFT
20 will be described with reference to FIGS. 20 to 24, and further, a method of manufacturing the dual gate type MOSTFT will be described with reference to FIGS. Since the method of manufacturing the bottom gate type MOSTFT in the peripheral drive circuit portion is the same as the process shown in FIGS. 1 to 7, illustration and description thereof are omitted here.

In the display section, a bottom gate type MOST
In order to manufacture the FT, first, a molybdenum / tantalum (Mo.Ta) alloy is sputtered on the substrate 1 as shown in FIG. 20 (1) in the same manner as the process shown in FIG. 1 (1). The film 71A is formed to a thickness of about 300 to 400 nm.

Next, in the same manner as in the step shown in FIG. 1B, the photoresist 7 is formed as shown in FIG.
0 is formed in a predetermined pattern, and using this as a mask, the sputtered film 71A is taper-etched so that the side end face 71a is
A gate electrode 71 having a trapezoidal cross section, which is gently inclined at ~ 45 °, is formed.

Next, after the photoresist 70 is removed, plasma CVD is performed on the substrate 1 including the sputtered film 71A as shown in FIG. 19 (3) in the same manner as in the step shown in FIG. 1 (3). The SiN film (about 100 n
m thickness) 72 and a SiO ₂ film (about 200 nm thickness) 73 are laminated in this order to form a gate insulating film.

Next, in the same manner as in the step shown in FIG. 2D, a photoresist 2 is formed in a TFT forming region in a predetermined pattern as shown in FIG. A plurality of steps 4 having an appropriate shape and dimensions are formed on the gate insulating film on 1 (and also on the substrate 1). As described above, the step 4 serves as a seed for heteroepitaxial growth of single crystal silicon, which will be described later, and at the same time, has the function of promoting the growth of the crystalline sapphire film and increasing its crystallinity. The width is about 0.1 to 0.4 μm, the width w is about 2 to 10 μm, the length (in the direction perpendicular to the paper surface) is about 10 to 20 μm, and the angle between the bottom surface and the side surface (base angle) is substantially a right angle. You.

Next, in the same manner as in the step shown in FIG. 2 (5), the photoresist 2 is formed as shown in FIG. 20 (5).
Is removed, a crystalline sapphire film 50 is formed on one main surface of the insulating substrate 1 in a TFT formation region including the step 4 to a thickness of about 20 to 200 nm. Then, in the same manner as in the step shown in FIG. 2 (6), as shown in FIG. 21 (6), polycrystalline silicon or amorphous silicon is formed by sputtering, plasma CVD or the like, and the silicon film 5 is formed. Form.

Then, in the same manner as in the step shown in FIG. 2 (7), as shown in FIG. 21 (7), tin is deposited on the silicon film 5 several ten to several hundred times thicker than the silicon film 5. (For example, 10 to 15 μm) to form the low melting point metal layer 6. Note that, instead of forming the low melting point metal layer 6 by forming tin, the low melting point metal layer 6 may be formed by forming lead or a tin-lead alloy.

Next, the substrate 1 is placed in a hydrogen atmosphere at 500
The silicon film 5 is heated to 〜600 ° C. and maintained in this state for about 5 minutes, thereby dissolving the silicon film 5 in a tin melt forming the low melting point metal layer 6. Subsequently, by gradually cooling, the silicon dissolved in tin is heteroepitaxially grown to a thickness of 5 to 10 as shown in FIG.
It is deposited as a single-crystal silicon layer 7 having a thickness of 0 nm, preferably about 30 to 50 nm. At this time, since the side end surface 71a of the underlying gate electrode 71 is a gentle slope, heteroepitaxial growth by the step 4 and the crystalline sapphire film 50 is not hindered on this surface, and the single-crystal silicon Layer 7 will grow.

Next, as shown in FIG. 21 (9), the film 6A mainly composed of tin formed on the surface side is dissolved and removed with hydrochloric acid or the like, and if necessary, an appropriate amount of impurity ions is doped. Adjust the specific resistance.

Next, (10) in FIG. 3 to (12) in FIG.
After the process shown in FIG. 21 is performed, the display unit n is displayed as shown in (10) of FIG. 21 in the same manner as the process shown in (13) of FIG.
The gate portion of the MOSTFT is covered with a photoresist 13, and the exposed source / drain regions of the nMOSTFT are doped (ion-implanted) with phosphorus ions 14 to form an LDD portion 15 made of an N ⁻ -type layer in a self-aligned manner. At this time, the surface height difference (or pattern) is easily recognized due to the presence of the bottom gate electrode 71. Therefore, the alignment (mask alignment) of the photoresist 13 is easily performed, and alignment deviation hardly occurs.

Next, in the same manner as in the step shown in FIG. 5 (14), as shown in FIG.
The gate portion and the LDD portion of T are covered with a photoresist 16 and the exposed region is doped (ion-implanted) with phosphorus or arsenic ions 17 to form a source portion 18 and a drain portion 19 made of an N ⁺ type layer of an nMOS TFT. .

Next, in the same manner as in the step shown in FIG. 5 (15), the nMOSTF is formed as shown in FIG.
The entirety of T is covered with a photoresist 20 and boron ions 21 are doped (ion-implanted) to form a source portion and a drain portion of the P ⁺ layer of the pMOSTFT of the peripheral drive circuit portion.

Next, in the same manner as in the step shown in FIG. 5 (16), the photoresist 2 is formed to make the active element portion and the passive element portion into islands as shown in FIG. 22 (13).
4 is provided, and the single crystal silicon layer 7 is selectively removed by etching.

Next, in the same manner as in the step shown in FIG. 6 (17), as shown in FIG.
D, a SiO ₂ film 53 (thickness of about 300 nm) and a phosphosilicate glass (PSG) film 54 (thickness of about 300 nm) are continuously formed in this order on the entire surface by high-density plasma CVD, catalytic CVD, or the like. Note that the SiO ₂ film 53 and the PSG film 54 correspond to the above-described protective film 25. Then, in this state, the single crystal silicon layer 7 is activated in the same manner as described above.

Next, in the same manner as in the step shown in (18) of FIG. 6, as shown in (15) of FIG. 23, a contact window of the source portion is opened by general-purpose photolithography and etching techniques. And the thickness of 400 to 5
A sputtered film of an aluminum alloy or the like having a thickness of about 00 nm is formed, and a data line and a gate line are formed at the same time when the source electrode 26 of the TFT is formed by general-purpose photolithography and etching technology. Thereafter, sintering is performed at about 400 ° C./1 h in a forming gas.

Next, in the same manner as in the step shown in (19) of FIG. 6, as shown in (16) of FIG. 23, the PSG film (about 300
An insulating film 36 made of an SiN film (thickness: about 300 nm) and a SiN film (about 300 nm thick) is formed on the entire surface, and a contact window is opened in the drain of the display TFT.

Next, in the same manner as in the step shown in FIG. 7 (20), a photosensitive resin film 28 having a thickness of 2 to 3 μm is formed by spin coating or the like as shown in FIG. 23 (17). As shown in (18) of FIG. 23, an uneven pattern for obtaining optimum reflection characteristics and viewing angle characteristics is formed in the pixel portion by general-purpose photolithography and etching techniques, and is formed by reflow to form an uneven rough surface 28A. The lower part of the reflecting surface is formed. At the same time, a resin window for contact of the drain portion of the display TFT is opened.

Next, in the same manner as in the step shown in FIG. 7 (22), 400
A sputtered film of aluminum alloy or the like having a thickness of about 500 nm is formed, and a reflection film 29 having an uneven shape connected to the drain portion 19 of the display TFT is formed by general-purpose photolithography and etching technology.

As described above, the crystalline sapphire film 5
A single-crystal silicon layer 7 is formed using 0 and the step 4 as seeds for heteroepitaxial growth, and a bottom gate type nMOS LDD-
A display-peripheral drive circuit unit integrated active matrix substrate 30 incorporating a TFT (a CMOS drive circuit including a bottom gate type pMOSTFT and an nMOSTFT in the peripheral portion) can be manufactured.

FIG. 24 shows an example in which the gate insulating film of the bottom gate type MOSTFT provided in the display portion is formed by an anodic oxidation method of Mo · Ta.

In this example, after the step shown in FIG. 20B, the molybdenum-tantalum alloy film 71 is subjected to a known anodic oxidation treatment as shown in FIG. _A gate insulating film 74 of ₂ O ₅ is formed to a thickness of 100 to 200 nm.

Thereafter, steps 4 and a crystalline sapphire film 50 are formed as shown in FIG. 24 (4) in the same manner as the steps shown in FIGS. 20 (4) to 21 (9). Subsequently, a silicon film 5 is formed by depositing amorphous silicon or polycrystalline silicon. Next, (10) in FIG.
23 to 18 in the same manner as in the process shown in FIG.
The active matrix substrate 30 is manufactured as shown in (5).

In the display section, a dual gate type MOS
In order to manufacture a TFT, first, FIG.
A process similar to the process shown in (9) is performed.

Next, as shown in FIG. 25 (10),
A step 4 is formed on the insulating films 72 and 73 and the substrate 1, and a single-crystal silicon layer 7 is heteroepitaxially grown using the crystalline sapphire film 50 and the step 4 as seeds. Next, in the same manner as in the step shown in FIG. 4 (11), plasma CVD,
SiO ₂ film (about 100 nm thick) and S
iN (about 200 nm thick) is continuously formed in this order,
An insulating film 80 (this corresponds to the above-described gate insulating film 8) is formed, and a sputtered film 81 made of a Mo.Ta alloy is further formed.
(This corresponds to the aforementioned sputtered film 9) from 300 to 400
It is formed to a thickness of about nm.

Next, in the same manner as in the step shown in FIG. 4 (12), a photoresist pattern 10 is formed as shown in FIG.
An o-Ta alloy top gate electrode 82 and a gate insulating layer 83 are formed to expose the single crystal silicon layer 7.

Next, in the same manner as in the process shown in FIG. 4 (13), the nMOSTF
T top gate portion is covered with photoresist 13;
Doping (ion implantation) phosphorus ions 14 into the exposed source / drain regions of the display nMOS TFT,
An LDD portion 15 of an N ⁻ type layer is formed.

Next, in the same manner as in the step shown in FIG. 5 (14), as shown in FIG.
Is covered with a photoresist 16 and phosphorus or arsenic ions 17 are doped (ion-implanted) into the exposed regions to form a source portion 18 and a drain portion 19 made of an N ⁺ -type layer of an nMOS TFT. .

Next, in the same manner as in the step shown in FIG. 5 (15), as shown in FIG.
The gate portion of T is covered with a photoresist 20 and the exposed region is doped with boron ions 21 (ion implantation).
Then, the source portion and the drain portion of the P ⁺ layer of the pMOSTFT of the peripheral drive circuit portion are formed.

Next, in the same manner as in the step shown in FIG. 5 (16), a photoresist 24 is provided to make the active element section and the passive element section into islands as shown in FIG. The single crystal silicon thin film layer other than the element part and the passive element part is selectively removed by general-purpose photolithography and etching techniques.

Next, in the same manner as in the step shown in FIG. 6 (17), as shown in FIG.
D, S by high density plasma CVD, catalytic CVD, etc.
An iO ₂ film 53 (about 200 nm thick) and a phosphosilicate glass (PSG) film 54 (about 300 nm thick) are formed on the entire surface. These films 53 and 54 correspond to the protective film 25 described above. Then, the single crystal silicon layer 7 is activated.

Next, a contact window is opened in the source portion as shown in FIG. 26 (17) in the same manner as the step shown in FIG. 6 (18). And 400 to 50 on the whole surface
A sputtered film made of an aluminum alloy or the like having a thickness of about 0 nm is formed, and the data line and the gate line are formed at the same time as the source electrode 26 is formed by general-purpose photolithography and etching technology.

Next, in the same manner as in the step shown in FIG. 6 (19), as shown in FIG. 27 (18), an insulating film made of a PSG film (about 300 nm thick) and a SiN film (about 300 nm thick) 36 is formed on the entire surface, and TF for display is further formed.
A contact window is opened in the drain portion of T.

Next, as shown in FIG. 27 (19),
A photosensitive resin film 28 having a thickness of about 2 to 3 μm is formed on the entire surface by spin coating or the like. Subsequently, (21) and (2) in FIG.
In the same manner as in the process shown in 2), as shown in FIG. 27 (20), the lower part of the reflection surface composed of the rough surface 28A is formed in the pixel portion, and at the same time, the contact resin window of the drain portion of the display TFT is formed. Opening is performed, and a reflection film 29 made of a concavo-convex shape aluminum alloy or the like for obtaining optimum reflection characteristics and viewing angle characteristics is formed, which is connected to the drain portion 19 of the display TFT.

As described above, the crystalline sapphire film 5
A single-crystal silicon layer 7 is formed using 0 and the step 4 as seeds for heteroepitaxial growth, and a dual-gate type nMOS LDD is formed on a display unit using the single-crystal silicon layer 7.
TFT is replaced with a bottom gate type pMOS in the peripheral drive circuit.
It is possible to manufacture an active matrix substrate 30 integrated with a display section and a peripheral drive circuit section, in which CMOS drive circuits each including a TFT and an nMOSTFT are formed.

<Eighth Embodiment> Referring to FIGS. 28 to 33, an eighth embodiment of the present invention will be described.

In the present embodiment, unlike the above-described embodiments, the gate electrode of the top gate portion is formed of a material having relatively low heat resistance such as an aluminum alloy.

First, the top gate type MOSTF
T, and a bottom gate type MOSTF
The case where T is provided will be described. In this example,
FIG. 1 (1) to FIG. 3 in the first embodiment described above.
Performed in the same manner as in the step shown in FIG.
8 (10), the pMOST of the peripheral drive circuit section
An N-type well 7A is formed in the FT section.

Next, as shown in FIG. 28 (11),
All of the nMOS and pMOSTFTs in the peripheral driving region and the gate portion of the nMOSTFT in the display region are covered with a photoresist 13, and phosphorus ions 14 are applied to the exposed source / drain regions of the nMOSTFT by, for example, 10 kV at 1 × 1.
By doping (ion implantation) at a dose of 0 ¹³ atoms / cm ² , an LDD portion 15 made of an N ⁻ -type layer is formed in a self-aligned manner.

Next, as shown in FIG. 29 (12),
All of the pMOSTFTs in the peripheral drive area, the gates of the nMOSTFTs in the peripheral drive area, and the
The gate of T and the LDD portion are covered with a photoresist 16, and the exposed region is doped (ion-implanted) with phosphorus or arsenic ions 17 at, for example, 20 kV at a dose of 5 × 10 ¹⁵ atoms / cm ² to form an nMOS TFT. N ⁺
LDD with Source 18 and Drain 19 Made of Mold Layer
The part 15 is formed. In this case, the resist 13 is left as shown by a dashed line in FIG.
If the resist 6 is provided, the resist 16 is
The alignment of the mask at the time of formation can be performed, thereby facilitating mask alignment and reducing misalignment.

Next, as shown in FIG. 29 (13),
NMOS TFT in peripheral drive area and nMOS in display area
The entirety of the TFT and the gate of the pMOSTFT are covered with a photoresist 20 and boron ions 2
1 is doped (ion-implanted) at, for example, 10 kV with a dose of 5 × 10 ¹⁵ atoms / cm ² , and pMOSTF
The source part 22 and the drain part 23 of the P ⁺ layer of T are formed.

Next, the resist 20 is removed.
As shown in FIG. 29 (14), the single-crystal silicon layers 7, 7
A is activated in the same manner as described above, and a gate insulating film 12 and a gate electrode material (aluminum or 1%
An aluminum alloy containing Si 11) is formed. The gate electrode material layer 11 can be formed by a vacuum evaporation method or a sputtering method.

[0206] Then, by patterning the respective gate portion in the same manner as described above, then, an island and an active element portion and the passive element portion, further as shown in (15) in FIG. 30, SiO ₂ film on the entire surface (Approximately 200 nm thick) and a phosphosilicate glass (PSG) film (approximately 300 nm thick) are successively formed in this order to form a protective film 25.

Next, as shown in FIG. 30 (16),
By general-purpose photolithography and etching technology, contact windows are opened in the source / drain portions of all the TFTs of the peripheral drive circuit and the source portions of the display TFT.

Then, a 500-600 nm thick aluminum or aluminum alloy containing 1% Si or the like is formed on the whole surface by a general-purpose photolithography and etching technique, and all the TFs of the peripheral drive circuit and the display section are formed.
T source electrode 26 and drain electrode 2 of peripheral drive circuit section
7 and a data line and a gate line are formed at the same time. Then, forming gas (N ₂ +
Sinter in H ₂ ) at about 400 ° C./1 h.

Next, (19) in FIG. 6 to (22) in FIG.
In the same manner as in the step shown in FIG. 1, a top gate type nMOS LDD-TFT having a gate electrode of aluminum or aluminum containing 1% Si in a display portion using the single crystal silicon layer 7 and a peripheral drive circuit portion And a CMOS drive circuit composed of a bottom gate type pMOSTFT and an nMOSTFT, respectively.
Active matrix substrate 30 integrated with peripheral drive circuit section
Can be produced.

In the present embodiment, the gate electrode 11 made of aluminum or aluminum containing 1% Si is formed after the activation treatment of the single crystal silicon layer 7, so that the influence of heat during the activation treatment is not affected by the gate electrode. Since it has no relation to the heat resistance of the material, the heat resistance of the top gate electrode material is relatively low, and low-cost aluminum or an aluminum alloy containing 1% Si can be used. This is because the display unit is a bottom gate type MOS
The same applies to the case of a TFT.

Next, a dual gate type MOST is provided in the display section.
A case in which a bottom gate type MOS TFT is provided in the FT and the peripheral driving circuit will be described. In this example, first, the process is performed in the same manner as the processes shown in (1) of FIG. 20 to (9) of FIG. 21 in the above-described seventh embodiment, and then, FIG.
As shown in (10), the pMOST of the peripheral drive circuit section
An N-type well 7A is formed in the FT section.

Next, in the same manner as in the step shown in FIG. 28 (11), as shown in FIG.
The FT portion is doped with phosphorus ions 14 to form an LDD portion 15.

Next, in the same manner as in the step shown in FIG. 29 (12), as shown in FIG. 32 (12), the display section and the nMOSTFT section of the peripheral drive circuit section are doped with phosphorus ions 17 to form an N ⁺ type. Source region 18 and drain region 19
Are formed respectively.

Next, in the same manner as in the step shown in FIG. 29 (13), as shown in FIG. 32 (13), the pMOSTFT portion of the peripheral drive circuit section is doped with boron ions 21 to form a P ⁺ type source region. 22 and a drain region 23 are respectively formed.

Then, the resist 20 is removed.
As shown in FIG. 32 (14), the single crystal silicon layer 7 is patterned to make the active element portion and the passive element portion into islands. Thereafter, as shown in FIG. 33 (15), the single crystal silicon layers 7, 7A are formed. Is activated in the same manner as described above, and a gate insulating film 80 is formed on the surface.

Next, as shown in FIG. 33 (16),
By patterning an aluminum alloy or the like formed on the entire surface by sputtering, each upper gate electrode 83 of the display section is formed.

Next, as shown in FIG. 33 (17),
An SiO ₂ film (about 200 nm thick) and a phosphosilicate glass (PSG) film (about 300 nm thick) are successively formed on the entire surface in this order, and a protective film 25 is formed.

Next, in the same manner as described above, the source electrode 26 of all the TFTs in the peripheral driving circuit and the display section and the drain electrode 27 of the peripheral driving circuit section were formed, so that the single crystal silicon layer 7 was used. Dual gate type nMOS with aluminum alloy etc. as gate electrode for display
CM comprising LDD-TFT and bottom gate type pMOSTFT and nMOSTFT in peripheral drive circuit
An active matrix substrate 30 integrated with a display section and a peripheral drive circuit section, in which an OS drive circuit is built, can be manufactured.

Also in this embodiment, since the gate electrode 83 made of an aluminum alloy or the like is formed after the activation process of the single crystal silicon layer 7, the influence of heat during the activation process depends on the heat resistance of the gate electrode material. Irrelevant, the heat resistance is relatively low as the material of the top gate electrode, a low-cost aluminum alloy or the like can be used, and the choice of the electrode material is widened. The source electrode 26 (and also the drain electrode) can be formed at the same time in the step (15) in FIG. 32, but this is advantageous in the manufacturing process.

In any of the above-described embodiments, for example, when manufacturing a bottom gate type, a top gate type, or a dual gate type MOSTFT, FIG.
As schematically shown in FIG. 4A, when the step 4 is provided, the single-crystal silicon film 7 grown on the step 4 may be thin, resulting in step disconnection (poor connection) or thinning (increase in resistance). In order to surely connect with the source electrode 26 (or the drain electrode), it is desirable to dispose the electrode on a region including the step 4, as shown in FIGS.

In the step shown in FIG. 28 (11) or the step shown in FIG. 31 (11), a top gate insulating film is formed on the single crystal silicon layer 7, and ion implantation and activation are performed. After the processing is sequentially performed, the top gate electrode, the source, and the drain electrode may be simultaneously formed using an aluminum alloy or the like.

As described above, the step 4 is formed on the substrate 1 (and also on a film of SiN or the like thereon) as shown in FIG. 35 (A).
As shown in (B), the crystalline sapphire film 50 on the substrate 1
(This also has a function of stopping diffusion of ions from the glass substrate 1). Instead of the crystalline sapphire film 50 or under the crystalline sapphire film, a gate insulating film 73 may be provided, and the step 4 may be formed thereon. FIGS. 35 (C), (D) and (E) show examples in which a step 4 is provided in the crystalline sapphire film 50, respectively.

<Ninth Embodiment> Referring to FIGS. 36 to 38, a ninth embodiment of the present invention will be described.

In this embodiment, various examples will be described in which each TFT is formed outside the above-described step 4 (ie, on the substrate 1 other than the step). Note that the single-crystal silicon layer 7 and the gate / source / drain electrodes 26 and 27 are schematically illustrated.

First, FIG. 36 shows a top gate type MOSTF.
T is shown. In FIG. 36A, a concave portion due to the step 4 is formed along one side of the source side along the source region, and the gate insulating film 12 and the gate electrode 11 are formed on the single crystal silicon layer 7 on the substrate flat surface other than the concave portion. Is formed. Similarly, in FIG. 36B, the concave portion due to the step 4 is formed in an L-shaped pattern not only in the source region but also up to the end of the drain region along the channel length direction, that is, over two sides. In FIG. 36 (c), the concave portion due to the step 4 is formed in a rectangular shape over four sides so as to surround the TFT active region. In FIG. 36 (d), a concave portion due to the step 4 is formed over three sides. However, adjacent concave portions are not continuous. In FIG. 36E, the concave portion due to the step 4 is formed in an L-shaped pattern over two sides. However, adjacent concave portions are not continuous.

As described above, it is possible to form recesses due to the steps 4 of the various patterns, and since the TFT is provided on a flat surface other than the recesses, the degree of freedom in manufacturing the TFT is increased.
The fabrication itself becomes easier.

Next, FIG. 37 shows a bottom gate type MOSTF.
T is shown. As shown in FIGS. 37 (a) to 37 (d), steps 4 (or recesses) of various patterns shown in FIG. 36 can be similarly formed in the bottom gate type MOSTFT. That is, FIG. 37 (a) is an example corresponding to FIG. 36 (a),
Formed on a flat surface other than the recessed portion. Similarly, FIG. 37 (b) corresponds to FIG. 36 (b), and FIG.
(C) is an example corresponding to FIGS. 36 (c) and (d). FIG. 37D shows an example in which a step 4 is provided in the crystalline sapphire film 50.

Next, FIG. 38 shows a dual gate type MOS.
3 shows a TFT. As shown in FIGS. 38 (a) and (b),
Also in the dual gate type MOSTFT, the steps 4 (or concave portions) of various patterns shown in FIG. 36 can be formed in the same manner. For example, on the flat surface in the region inside the steps 4 shown in FIG. A dual-gate MOSTFT can be manufactured.

<Tenth Embodiment> A tenth embodiment of the present invention will be described with reference to FIGS.

In this embodiment, the example shown in FIG. 39 is a double gate type TFT in which a plurality of TFTs having a self-aligned LDD structure, for example, a plurality of top gate type LDD-TFTs are connected.
It relates to the OSTFT. That is, in this example, as shown in FIG. 39, the gate electrode 11 is branched into two, one of which is a first LDD-TF as a first gate.
A second LDD-TF for T and the other as a second gate
Used for T (however, an N ⁺ -type region 100 is provided between gate electrodes at the center of the single crystal silicon layer to reduce the resistance). In this case, a different voltage may be applied to each gate, and even if one of the gates becomes inoperable for some reason, carriers are transferred between the source and the drain by using the remaining gates. Can be a reliable device.

The first LDD-TFT and the second LDD-TFT
Since two thin film transistors for driving each pixel are formed by connecting two D-TFTs in series, the voltage applied between the source and the drain of each thin film transistor in the off state can be greatly reduced. it can. Therefore, the leakage current flowing during the off state can be reduced, and the contrast and the image quality of the liquid crystal display can be improved satisfactorily. Further, since the two LDD-TFTs are connected by using only the same semiconductor layer as that of the low-concentration drain region in the LDD-TFT, the connection distance between the transistors can be reduced, and the LDD-TFT can be reduced. Can be prevented from increasing the required area even if two are connected. The first,
The second gates may be completely separate from each other and operate independently.

In the example shown in FIG. 40A, the bottom gate type MOSTFT has a double gate structure.
The example shown in FIG. 40B is a dual gate type MOST.
The FT has a double gate structure.

These double gate type MOS TFTs have the same advantages as the above-mentioned top gate type.
In particular, the dual gate type has an advantage that even if one of the upper and lower gate portions becomes inoperable, the other gate portion can be used.

FIG. 41 shows each of the aforementioned double-gate MOSs.
1 shows an equivalent circuit diagram of a TFT. In the above description, the gate is branched into two, but the gate may be branched or divided into three or more. Even in these double-gate or multi-gate structures, it can be configured to have two or more branched gate electrodes of the same potential or divided gate electrodes of different potentials or the same potential in the channel region. .

<Eleventh Embodiment> The eleventh embodiment of the present invention will be described with reference to FIG. In this embodiment, the nMOS TFT having a dual gate structure T
In the FT, one of the upper and lower gates operates as a transistor, but the other gate operates as follows.

That is, in the example shown in FIG.
In a MOSTFT, an arbitrary negative voltage is always applied to the gate electrode on the top gate side to reduce the leakage current in the back channel. By opening the top gate electrode, it can be used as a bottom gate type. In the example shown in FIG. 42B, an arbitrary negative voltage is always applied to the bottom gate electrode to reduce the leakage current of the back channel. Also in this case, by opening the bottom gate electrode, it can be used as a top gate type. In the case of a pMOSTFT, the back channel leakage current can be reduced by always applying an arbitrary positive voltage to the gate electrode.

In either case, the interface between the single crystal silicon layer 7 and the insulating film has poor crystallinity and a leak current easily flows, but the leak current can be cut off by applying a negative voltage to the electrode as described above. This is advantageous in combination with the effect of the LDD structure. In addition, a leak current may flow due to light incident from the glass substrate 1 side. However, since the light is blocked by the bottom gate electrode, the leak current can be reduced.

<Twelfth Embodiment> Referring to FIGS. 43 to 49, a twelfth embodiment of the present invention will be described.

In the embodiment of this example, the above-mentioned step (recess) is not provided on the substrate, and the above-mentioned material layer (for example, a crystalline sapphire film) is formed on the flat surface of the substrate. A single-crystal silicon layer is heteroepitaxially grown and used as a bottom-gate type MOS TFT.
In an active matrix reflection type liquid crystal display device (LCD) having a peripheral drive circuit portion.

The active matrix reflective LCD will be described in accordance with the manufacturing steps. In FIGS. 43 to 48, the left side of each drawing shows the manufacturing method (step) of the display unit, and the right side shows the manufacturing method (step) of the peripheral drive circuit unit.

First, as shown in (1) of FIG. 43, the insulating substrate 1 made of quartz glass, transparent crystallized glass, and high heat resistant glass (8 to 12 inches φ, 700 to 800 μm thick) or the like is used. On one principal surface, a sputtered film 71A of a molybdenum / tantalum (Mo
It is formed to about 400 nm. Next, (2) of FIG.
As shown in FIG. 7, a photoresist 70 is formed in a predetermined pattern, and the sputtered film 71A is taper-etched using the photoresist 70 as a mask.
The gate electrode 71 gently inclined at a degree is formed.

Next, as shown in FIG. 43C, after removing the photoresist, an SiN film (about 100 nm thick) 72 and SiO _{2 are formed} on the substrate 1 including the sputtered film 71A by a plasma CVD method or the like. Film (about 200 nm thick) 7
3 is formed in this order to form a gate insulating film.

Next, as shown in (4) of FIG. 44, a crystalline sapphire film 50 is formed to a thickness of about 20 to 200 nm on at least one TFT forming region on one main surface of the insulating substrate 1. This crystalline sapphire film 50 can be formed by a high-density plasma CVD method or a catalytic CVD method (Japanese Patent Laid-Open No. 63-40 / 1988).
314) and the like are oxidized with an oxidizing gas (oxygen and moisture) and crystallized.

Next, in the same manner as in the step shown in FIG. 2 (6), as shown in FIG.
Amorphous silicon or polycrystalline silicon is formed on the entire surface of the crystalline sapphire film 50 at a substrate temperature of about 100 to 400 ° C. by a method, a plasma CVD method, a sputtering method, or the like. A silicon film 5 having a thickness of 0.1 μm) is formed.

Next, as shown in FIG. 44 (6), tin is deposited on the silicon film 5 by a vacuum deposition method or the like, and the thickness is several tens to several hundreds times the thickness of the silicon film 5 (for example, 10 to 10 times).
A low melting point metal layer 6 of 15 μm) is formed. As for the formation of the low-melting-point metal layer 6, a tin-lead alloy may be formed (deposited) instead of forming (depositing) tin.

Next, the substrate 1 is placed under a hydrogen-based atmosphere such as hydrogen or a nitrogen-hydrogen mixture or an argon-hydrogen mixture for 50 hours.
Heat to 0-600 ° C and hold in this state for about 5 minutes.
Then, the silicon film 5 is dissolved in the molten liquid of the low melting point metal layer 6 by this heating. In this melt, silicon exhibits a property of being deposited at a temperature significantly lower than the original deposition temperature. As a method for heating the substrate 1, a method of uniformly heating the entire substrate using an electric furnace or the like, or a method of locally heating only a predetermined place, for example, only a TFT forming region, using an optical laser, an electron beam, or the like is adopted. Is done.

Next, by gradually cooling, the silicon dissolved in tin (or lead or tin / lead) is used as a seed for crystal growth using the crystalline sapphire film 50 as shown in FIG. Heteroepitaxially grown, thereby depositing single crystal silicon to a thickness of 5 to 1
A single-crystal silicon layer 7 having a thickness of 00 nm, preferably about 30 to 50 nm is formed. In the single-crystal silicon layer 7 formed in this manner, for example, the (100) plane is heteroepitaxially grown on the substrate because the crystalline sapphire film 50 shows good lattice matching with single-crystal silicon.

After the single-crystal silicon layer 7 is deposited on the substrate 1 by such heteroepitaxial growth, as shown in FIG. 45 (8), the film 6A mainly composed of tin is formed on the surface by using hydrochloric acid, sulfuric acid or the like. And a top gate type or bottom gate type MOS using the single crystal silicon layer 7 as a channel region in the same manner as in the above-described process.
A TFT is manufactured as follows.

First, the entire surface of the single crystal silicon layer 7 formed by the epitaxial growth is doped with an appropriate amount of a P-type carrier impurity, for example, boron ions, to adjust the specific resistance.
Further, only the pMOSTFT formation region is selectively doped with an N-type carrier impurity to form an N-type well. For example, a p-channel TFT portion is masked with a photoresist (not shown), and P-type impurity ions (for example, B ⁺ ) are
Doping is performed at 0 kV at a dose of 2.7 × 10 ¹¹ atoms / cm ² to adjust the specific resistance. Also, (1) in FIG.
0), the nMOSTFT portion is masked with a photoresist 60 to control the impurity concentration in the pMOSTFT formation region, and N-type impurity ions (for example, P
⁺ ) 65 is doped at 10 kV at a dose of 1 × 10 ¹¹ atoms / cm ² to form an N-type well 7A.

Next, as shown in FIG. 45 (9), SiO ₂ (about 200 μm) is formed on the entire surface of the single crystal silicon layer 7 by plasma CVD, high density plasma CVD, catalytic CVD, or the like.
nm thick) and SiN (approximately 100 nm thick) in this order to form a gate insulating film 8.
Sputtered film 9 of tantalum (Mo.Ta) alloy (300 to
(Thickness: 400 nm).

Next, as shown in FIG. 45 (10),
The TF of the display area is obtained by using general-purpose photolithography technology.
A photoresist pattern 10 is formed in each step region (in the concave portion) of the T portion and the TFT portion of the peripheral drive region, and the photoresist pattern 10 is continuously etched using the photoresist pattern as a mask, thereby forming a gate electrode of Mo / Ta alloy. 11 and (Si
A gate insulating film 12 having a laminated structure of (N / SiO ₂ ) is formed, and the single crystal silicon layer 7 is exposed. Note that M
The sputtered film 9 made of an o-Ta alloy is treated with an acid-based etchant, and SiN is plasma-etched with CF ₄ gas.
SiO ₂ is treated with a hydrofluoric acid-based etchant.

Next, as shown in FIG. 45 (11),
All of the nMOS and pMOSTFTs in the peripheral driving region and the gate portion of the nMOSTFT in the display region are covered with a photoresist 13, and phosphorus ions 14 are applied to the exposed source / drain regions of the nMOSTFT at, for example, 20 kV by 5 ×.
By doping (ion implantation) at a dose of 10 ¹³ atoms / cm ^2, the LDD portion 15 made of an N ⁻ -type layer is formed in a self-aligned (self-aligned) manner.

Next, as shown in FIG.
All of the pMOSTFTs in the peripheral drive area, the gates of the nMOSTFTs in the peripheral drive area, and the
The gate of T and the LDD portion are covered with a photoresist 16, and the exposed region is doped (ion-implanted) with phosphorus or arsenic ions 17 at, for example, 20 kV at a dose of 5 × 10 ¹⁵ atoms / cm ² to form an nMOS TFT. N ⁺
LDD with Source 18 and Drain 19 Made of Mold Layer
The part 15 is formed.

Next, as shown in (13) of FIG.
NMOS TFT in peripheral drive area and nMOS in display area
The whole of the TFT and the gate of the pMOSTFT are covered with a photoresist 20, and boron ions 21 are exposed to an exposed region, for example, at 10 kV at 5 × 10 ¹⁵ atoms / cm 2.
Doping (ion implantation) with a dose of ²
The source part 22 and the drain part 23 of the P ⁺ layer of the TFT are formed. This step is unnecessary in the case of the nMOS peripheral drive circuit because there is no pMOSTFT.

Next, as shown in (14) of FIG.
A photoresist 24 is formed in order to make an active element portion such as a TFT or a diode or a passive element portion such as a resistor or an inductance into an island. Then, the single crystal silicon layer 7 other than all the active element portions and the passive element portions in the peripheral drive region and the display region is removed using a hydrofluoric acid-based etchant.

Next, as shown in FIG. 47 (15),
An SiO ₂ film (about 200 nm thick) and a phosphosilicate glass (PSG) film (about 300 nm thick) are entirely formed by plasma CVD, high-density plasma CVD, catalytic CVD, or the like.
Are successively formed in this order, and the protective film 25 is formed.

Then, in this state, the single crystal silicon layer 7 is activated. For this activation, for example, a lamp of halogen or the like is used, and the annealing condition is set to about 1000.
C. for about 10 seconds. Therefore, a high melting point Mo / Ta alloy that can withstand such annealing conditions is used as the gate electrode material. The gate electrode material is provided not only as a gate portion but also as a wiring over a wide range. When annealing is performed using an excimer laser, XeCl (wavelength of 308 nm) is used.
It is preferable to selectively irradiate the entire surface or only the active element portion and the passive element portion with 90% or more overlap scanning.

Next, as shown in (16) of FIG.
By general-purpose photolithography and etching technology, contact windows are opened in the source / drain portions of all the TFTs of the peripheral drive circuit and the source portions of the display TFT. Then, a sputtered film of aluminum or an aluminum alloy containing 1% Si or the like is formed on the entire surface to a thickness of about 500 to 600 nm.
T source electrode 26 and drain electrode 2 of peripheral drive circuit section
7 and a data line and a gate line are formed at the same time. Then, forming gas (N ₂ +
Sinter in H ₂ ) at about 400 ° C./1 h.

Next, as shown in (17) of FIG.
An insulating film 36 made of a PSG film (about 300 nm thick) and a SiN film (about 300 nm thick) is formed on the entire surface by plasma CVD, high-density plasma CVD, catalytic CVD, or the like. Next, a contact window is opened in the drain portion of the display TFT. It should be noted that SiO ₂ , PSG and S
It is not necessary to remove the iN film.

Next, for the same purpose as described in (20) of FIG. 7, as shown in (18) of FIG. 48, a photosensitive resin film 28 having a thickness of 2 to 3 μm is formed on the entire surface by spin coating or the like. 48, as shown in FIG. 48 (19), by using general-purpose photolithography and etching techniques, a concavo-convex pattern is formed at least in the pixel portion to obtain optimal reflection characteristics and viewing angle characteristics, and is reflowed to form a concavo-convex rough surface 28A. The lower surface of the reflecting surface is formed. At the same time, a resin window for contact of the drain portion of the display TFT is opened.

Next, as shown in (20) of FIG.
A sputtered film of aluminum or an aluminum alloy containing 1% Si having a thickness of about 400 to 500 nm is formed on the entire surface, and the sputtered film other than the pixel portion is removed by general-purpose photolithography and etching techniques.
An uneven reflection film 29 connected to the drain portion 19 of T is formed. This reflection film 29 also functions as a pixel electrode for display. Then, during forming gas,
Sintering is performed at about 300 ° C. for 1 hour to provide sufficient contact. Note that silver or a silver alloy may be used instead of an aluminum-based material to increase the reflectance.

As described above, the crystalline sapphire film 5
0 is used as a seed for crystal growth (heteroepitaxial growth) to form a single crystal silicon layer 7, and a top gate type nMOSLDD is formed on a display unit using the single crystal silicon layer 7.
A TFT and a bottom gate type p
It is possible to manufacture an active matrix substrate 30 integrated with a display unit and a peripheral drive circuit unit, in which CMOS circuits each configured by a MOSTFT and an nMOSTFT are respectively manufactured.

Using this active matrix substrate (drive substrate) 30, a reflective liquid crystal display (LCD) shown in FIG. 49 is manufactured in the same manner as described with reference to FIG.

In this embodiment, it is clear that the excellent effects described in the first embodiment can be obtained. In addition, since the single-crystal silicon layer 7 is heteroepitaxially grown only by the crystalline sapphire film 50 without providing a step on the substrate 1, the step of forming the step can be omitted, and the manufacturing process can be further simplified and the growth can be simplified. Thus, problems such as disconnection of the single crystal silicon layer can be solved.

<Thirteenth Embodiment> A thirteenth embodiment of the present invention will be described with reference to FIG.

The twelfth embodiment relates to an active matrix reflective LCD like the twelfth embodiment, and differs from the twelfth embodiment in that a silicon film 5 And the order of forming the low melting point metal layer 6 is changed. That is, in the present embodiment, after the step shown in FIG. 44 (4), as shown in FIG. 50 (5), first, the low melting point metal such as tin is formed on the entire surface of the crystalline sapphire film 50. The layer 6 is formed to a thickness of about 10 to 20 μm by a sputtering method or a vacuum evaporation method.

Next, as shown in FIG. 50 (6), amorphous silicon is deposited on the low-melting-point metal layer 6 by a known plasma CVD method, and several μm to 0.005 μm
A silicon film 5 having a thickness (for example, 0.1 μm) is formed.

Next, the substrate 1 was placed in a hydrogen-based atmosphere at 110
Hold at 0 ° C or less (especially 400 to 600 ° C) for about 5 minutes
Thereby, the silicon film 5 is dissolved in the tin melt. Next, by gradually cooling, the silicon dissolved in tin is heteroepitaxially grown as shown in FIG. 50 (7) using the crystalline sapphire film 50 as a seed for crystal growth. Crystal silicon is deposited to form a single crystal silicon layer 7 having a thickness of 5 to 100 nm, preferably about 30 to 50 nm.

In this case, the (100) plane of the single crystal silicon layer 7 is epitaxially grown on the substrate, as in the above-described embodiment. After the single-crystal silicon layer 7 is deposited on the substrate 1 by heteroepitaxial growth in this way, similarly to the twelfth embodiment, the film mainly composed of tin formed on the surface side is made of hydrochloric acid or the like. Through a process of subjecting the single-crystal silicon layer 7 to a predetermined treatment, and removing the TFTs of the display portion and the peripheral drive circuit portion.
Is made.

In this embodiment, the crystalline sapphire film 5
, A low melting point metal layer 6 is formed thereon, and a silicon film 5 is formed thereon.
Is formed, and then subjected to heat melting and cooling, but heteroepitaxial growth of single crystal silicon from a low melting metal melt occurs in the same manner as in the twelfth embodiment.

<Fourteenth Embodiment> A fourteenth embodiment of the present invention will be described with reference to FIG. The twelfth embodiment relates to an active matrix reflective LCD like the twelfth embodiment, and differs from the twelfth embodiment in that the silicon film 5 and the low melting point metal are different from those of the twelfth embodiment. The point is that a silicon-containing low melting point metal layer 6A is formed instead of forming each of the layers 6. That is, in the present embodiment, after the step shown in FIG. 44 (4), as shown in FIG. 51 (5), a predetermined amount of tin (for example, about 1: 1) is deposited on the entire surface of the crystalline sapphire film 50.
Wt%) low melting point metal layer 6A containing silicon
Is formed to a thickness of about 10 to 20 μm by a sputtering method or a vacuum evaporation method.

Next, the substrate 1 was placed in a hydrogen-based atmosphere at 110
Hold at 0 ° C or less (especially 400 to 600 ° C) for about 5 minutes
Thereby, the silicon in the low melting point metal layer 6A is dissolved in the tin melt. Then, by gradually cooling, the silicon dissolved in tin is crystal-grown (epitaxially grown) as shown in FIG. 49 (3) using the crystalline sapphire film 50 as a seed. Deposited to a thickness of 5 to 100 nm, preferably 30 to 50 nm
A single crystal silicon layer 7 is formed.

In this case, the (100) plane of the single crystal silicon layer 7 is epitaxially grown on the substrate in the same manner as described above. After the single-crystal silicon layer 7 is deposited on the substrate 1 by the crystal growth (epitaxial growth) in this manner, similarly to the above-described first embodiment, the film mainly composed of tin is formed on the surface side. Are dissolved and removed with hydrochloric acid or the like, and further, a predetermined process is performed on the single-crystal silicon layer 7 to manufacture each TFT of the display portion and the peripheral drive circuit portion.

In this embodiment, the crystalline sapphire film 5
Although a low-melting metal layer 6A containing silicon is formed on the substrate 0 and then heated and melted and cooled, the crystal growth (epitaxial growth) of single-crystal silicon from the low-melting metal melt is performed in the twelfth embodiment. This occurs in the same manner as in the first embodiment.

<Fifteenth Embodiment> A fifteenth embodiment of the present invention will be described with reference to FIGS.

In the present embodiment, as in the twelfth embodiment, the top gate type MOSTFT is provided in the display portion and the bottom gate type MOSTFT is provided in the peripheral drive circuit portion. Unlike the embodiment described above, the present invention relates to a transmission type LCD. Therefore, the manufacturing steps are the same from the step shown in FIG. 44 (1) to the step shown in FIG. 47 (17). Then, in the embodiment of this example, after these steps, (18) in FIG.
As shown in FIG.
Concurrently with providing open window for the drain portion contact, for improving the transmittance, unwanted SiO _2, PSG pixel openings
And the SiN film are removed.

Next, as shown in (19) of FIG.
On the entire surface, a flattening film 28B of a photosensitive acrylic transparent resin is formed to a thickness of about 2 to 3 μm by spin coating or the like,
TF for display by general-purpose photolithography technology
A window of the flattening film 28B on the drain side of T is opened and cured under predetermined conditions.

Next, as shown in FIG. 53 (20),
An ITO sputtered film having a thickness of about 130 to 150 nm is formed on the entire surface, and an ITO transparent electrode (pixel electrode) 41 that is in contact with the drain portion 19 of the display TFT is formed by general-purpose photolithography and etching technology.
And heat treatment (200-250 in forming gas)
C./1 h), the contact resistance between the drain of the display TFT and ITO is reduced, and the transparency of ITO is improved.

Then, as shown in FIG.
And a transmission type LCD is assembled in the same manner as in the fourth embodiment. However, a polarizing plate is also attached to the TFT substrate side. In this transmissive LCD, transmitted light can be obtained as shown by a solid line arrow, but it can be configured such that transmitted light from the counter substrate 32 side can be obtained as shown by an alternate long and short dash line arrow.

In the case of this transmission type LCD, an on-chip color filter (OCCF) structure and an on-chip black (OCB) structure can be manufactured as follows.

That is, (1) in FIG. 43 to (1) in FIG.
Steps up to 6) are performed in the same manner as described above. Then, as shown in (17) of FIG. 54, the PSG /
After opening the drain portion of the SiO ₂ insulating film 25 to form an aluminum buried layer 41A for the drain electrode, an insulating film 36 of SiN / PSG is formed.

Next, as shown in (18) of FIG.
After forming a photoresist 61 having a predetermined thickness (1 to 1.5 μm) in which each color of R, G, and B is dispersed in a pigment for each segment, as shown in (19) of FIG. The color filter layers 61 (R) and 61 (R) are patterned while leaving only predetermined positions (each pixel portion).
(G) Form 61 (B) (on-chip color filter structure). At this time, the window of the drain part is also opened. In addition,
In this example, an opaque ceramic substrate, glass having low transmittance, and a heat-resistant resin substrate cannot be used.

Next, as shown in FIG. 54 (19),
In a contact hole communicating with the drain of the display TFT, a light shielding layer 43 serving as a black mask layer is formed by metal patterning over the color filter layer. For example, titanium or molybdenum is deposited to a thickness of 2 by sputtering.
A film is formed to a thickness of about 100 to 250 nm, and then patterned into a predetermined shape that covers the display TFT and shields light (on-chip black structure).

Next, as shown in (20) of FIG.
A flattening film 28B made of a transparent resin is formed, and a transparent electrode 41 is buried in a through hole provided in the flattening film so as to be connected to the light shielding layer 43.

As described above, by forming the color filter 61 and the light shielding layer 43 on the display array portion, the aperture ratio of the liquid crystal display panel can be improved, and the power consumption of the display module including the backlight can be reduced. Can be realized.

<Sixteenth Embodiment> A sixteenth embodiment of the present invention will be described with reference to FIGS.

In the present embodiment, the peripheral drive circuit section is provided with the same bottom gate type p as in the twelfth embodiment.
It is composed of a CMOS drive circuit composed of a MOSTFT and an nMOSTFT. Further, although the display section is of a reflection type, the TFTs have various gate structures and various combinations.

That is, in the twelfth embodiment, the top gate type nMOS LDD-TFT is provided in the display portion as shown in FIG.
In the example shown in (B), the display unit has a bottom gate type nMO.
An SLDD-TFT is provided, and in the example shown in FIG.
A D-TFT is provided.

Both the bottom gate type MOSTFT and the dual gate type MOSTFT can be manufactured in the same step as the top gate type MOSTFT of the peripheral drive circuit portion as described later. In the case where the gate structure of the TFT of the display portion is changed in this way, especially in the case of a dual gate type, the driving capability is improved by the upper and lower gate portions, which is suitable for high-speed switching. It can be selectively used to operate as a top gate type or a bottom gate type depending on the case.

The bottom gate type MO shown in FIG.
In the STFT, reference numeral 71 in the figure denotes a gate electrode such as Mo / Ta. Reference numeral 72 denotes an SiN film and reference numeral 73 denotes an SiO ₂ film, and the SiN film and the SiO ₂ film form a gate insulating film. On this gate insulating film, a channel region using a single crystal silicon layer 7 and the like are formed similarly to the top gate type MOSTFT. Further, the dual gate type MOSTF shown in FIG.
In T, the lower gate portion is the same as the bottom gate type MOSTFT, but the upper gate portion is the gate insulating film 73.
Is formed of a SiO ₂ film and a SiN film, and an upper gate electrode 74 is provided thereon.

Next, the above-mentioned bottom gate type MOSTFT
Will be described with reference to FIGS. 56 to 60, and further, the method of manufacturing the dual gate type MOSTFT will be described with reference to FIGS. Since the method of manufacturing the bottom gate type MOSTFT in the peripheral drive circuit portion is the same as the process shown in FIGS. 43 to 48, illustration and description thereof are omitted here.

In the display section, a bottom gate type MOST
To manufacture the FT, first, as shown in FIG. 56 (1), molybdenum / tantalum (Mo.Ta)
An alloy sputtered film 71A is formed to a thickness of about 300 to 400 nm.

Next, as shown in FIG. 56 (2), a photoresist 70 is formed in a predetermined pattern, and using this as a mask, the sputtered film 71A is tapered and the side end surface 71a is gently inclined at 20 to 45 °. A gate electrode 71 having a trapezoidal cross section is formed.

Next, after removing the photoresist 70, as shown in FIG. 56 (3), an SiN film (about 100 nm thick) 72 and a SiO ₂ film are formed on the substrate 1 including the sputtered film 71A by a plasma CVD method or the like. (About 200 nm thick) 7
3 are stacked in this order to form a gate insulating film.

Next, in the same manner as in the step shown in FIG. 44 (4), as shown in FIG. 57 (4), the crystalline sapphire film 5
0 is formed to a thickness of about 20 to 200 nm. Then
As shown in FIG. 57 (5), a single-crystal silicon layer is heteroepitaxially grown on the crystalline sapphire film 50 in the same manner as the steps shown in FIGS. 44 (5) to 45 (8). 5-100 nm, preferably 30-50 n
An about m single crystal silicon layer 7 is formed. At this time, the side end (side end surface) 71a of the underlying gate electrode 71 is a gentle slope, and the single crystal is formed on this surface without any step interruption without hindering the epitaxial growth due to the step 4. The silicon layer 7 will grow.

Then, after going through the steps shown in FIGS. 45 (9) to (10), the display section is made as shown in FIG. 57 (6) in the same manner as the step shown in FIG. 45 (11). NMOS
The gate portion of the TFT is covered with a photoresist 13 and the exposed source / drain region of the nMOS TFT is doped (ion-implanted) with phosphorus ions 14 to form an LDD portion 15 made of an N ⁻ -type layer in a self-aligned manner. At this time,
The presence of the bottom gate electrode 71 makes it easy to recognize the surface height difference (or pattern), and the photoresist 13
(Mask alignment) is easily performed, and alignment deviation is less likely to occur.

Next, in the same manner as in the step shown in FIG. 46 (12), as shown in FIG.
The gate portion and the LDD portion of T are covered with a photoresist 16 and the exposed region is doped (ion-implanted) with phosphorus or arsenic ions 17 to form a source portion 18 and a drain portion 19 made of an N ⁺ type layer of an nMOS TFT. .

Next, in the same manner as in the step shown in FIG. 46 (13), as shown in FIG.
The entirety of T is covered with a photoresist 20 and boron ions 21 are doped (ion-implanted) to form a source portion and a drain portion of the P ⁺ layer of the pMOSTFT of the peripheral drive circuit portion.

Next, in the same manner as in the step shown in FIG. 46 (14), as shown in FIG. 58 (9), the photoresist 2
4 is provided, and the single crystal silicon layer 7 is selectively removed by etching.

Next, in the same manner as in the step shown in FIG. 47 (15), as shown in FIG.
A SiO ₂ film 53 (about 300 nm thick) and a phosphosilicate glass (PSG) film 54 (about 300 nm thick) are continuously formed in this order on the entire surface by VD, high-density plasma CVD, catalytic CVD, or the like. Note that the SiO ₂ film 53 and the PSG
The film 54 corresponds to the protective film 25 described above. Then, in this state, the single crystal silicon layer 7 is activated in the same manner as described above.

Next, in the same manner as in the step shown in FIG. 47 (16), as shown in FIG. 59 (11), a contact window of the source portion is opened by general-purpose photolithography and etching techniques. And the thickness 400
A sputtering film of aluminum or an aluminum alloy containing 1% Si of about 500 nm is formed, and a data line and a gate line are formed at the same time as forming the source electrode 26 of the TFT by general-purpose photolithography and etching technology. Thereafter, sintering is performed at about 400 ° C./1 h in a forming gas.

Next, in the same manner as in the step shown in FIG. 47 (17), as shown in FIG. 59 (12), the PSG film (about 30
An insulating film 36 of 0 nm thick and a SiN film (about 300 nm thick) is formed on the entire surface, and a contact window is opened in the drain of the display TFT.

Next, in the same manner as in the step shown in FIG. 48 (18), a photosensitive resin film 28 having a thickness of about 2 to 3 μm is formed by spin coating or the like as shown in FIG. Subsequently, as shown in (14) of FIG. 59, an uneven shape pattern for obtaining optimal reflection characteristics and viewing angle characteristics is formed in the pixel portion by general-purpose photolithography and etching techniques, and is reflowed to form an uneven rough surface 28A. The lower surface of the reflecting surface is formed. At the same time, a resin window for contact of the drain portion of the display TFT is opened.

Next, in the same manner as in the step shown in FIG. 48 (20), the entire surface is formed as shown in FIG. 59 (14).
A sputtered film of aluminum or an aluminum alloy containing 1% Si or the like having a thickness of 0 to 500 nm is formed, and an uneven reflection film 29 connected to the drain portion 19 of the display TFT is formed by general-purpose photolithography and etching technology.

As described above, the crystalline sapphire film 5
0 is used as a seed for crystal growth (heteroepitaxial growth) to form a single crystal silicon layer 7, and a bottom gate type nMOS LDD is formed on a display unit using the single crystal silicon layer 7.
-TFT (bottom gate type pMOS TFT in the periphery)
And an active matrix substrate 30 integrated with a display unit and a peripheral driving circuit unit, which incorporates a CMOS driving circuit composed of an nMOS TFT.

FIG. 60 shows an example in which the gate insulating film of the bottom gate type MOSTFT provided in the display portion is formed by an anodic oxidation method of Mo · Ta.

In this example, after the step shown in FIG. 56B, the molybdenum-tantalum alloy film 71 is subjected to a well-known anodic oxidation treatment as shown in FIG. _A gate insulating film 74 of ₂ O ₅ is formed to a thickness of 100 to 200 nm.

Thereafter, a crystalline sapphire film 50 is formed as shown in (4) of FIG. 60 in the same manner as in the steps (4) and (5) of FIG. Is heteroepitaxially grown to form a single-crystal silicon layer 7. Next, (6) to FIG. 59 in FIG.
(5) of FIG. 60 in the same manner as the process shown in (14) of FIG.
The active matrix substrate 30 is manufactured as shown in FIG.

In the display section, a dual gate type MOS
In order to manufacture a TFT, first, FIG.
The same processing as the step (5) is performed.

Next, as shown in FIG. 61 (6), a crystalline sapphire film 50 is formed on the insulating films 72 and 73,
Using this as a seed, single crystal silicon is heteroepitaxially grown to form a single crystal silicon layer 7.
Next, in the same manner as in the step shown in FIG. 45 (9), the entire surface on the single crystal silicon
An SiO ₂ film (about 200 nm thick) and a SiN film (about 100 nm thick) are successively formed in this order by VD or the like, and an insulating film 80 (this corresponds to the above-mentioned insulating film 8) is formed. A sputtered film 81 made of a Mo.Ta alloy (this corresponds to the aforementioned sputtered film 9) is formed to a thickness of about 500 to 600 nm.

Next, in the same manner as in the step shown in FIG. 45 (10), a photoresist pattern 10 is formed as shown in FIG.
A top gate electrode 82 of an o-Ta alloy and a gate insulating film 83 are formed to expose the single crystal silicon layer 7.

Next, in the same manner as in the step shown in FIG. 45 (11), as shown in FIG.
T top gate portion is covered with photoresist 13;
Doping (ion implantation) phosphorus ions 14 into the exposed source / drain regions of the display nMOS TFT,
The LDD portion 15 is formed of the N ⁻ type layer.

Next, in the same manner as in the step shown in FIG. 46 (12), as shown in FIG.
The gate portion and the LDD portion of T are covered with a photoresist 16 and the exposed region is doped (ion-implanted) with phosphorus or arsenic ions 17 to form a source portion 18 and a drain portion 19 made of an N ⁺ type layer of an nMOS TFT. I do.

Next, in the same manner as in the step shown in FIG. 46 (13), as shown in FIG.
The gate portion of the FT is covered with a photoresist 20 and the exposed region is doped with boron ions 21 (ion implantation) to form a source portion and a drain portion of the P ⁺ layer of the pMOSTFT of the peripheral drive circuit portion.

Next, in the same manner as in the step shown in FIG. 46 (14), a photoresist 24 is provided for islanding the active element section and the passive element section as shown in FIG. 62 (11). The single crystal silicon layer other than the element portion and the passive element portion is selectively removed by general-purpose photolithography and etching techniques.

Next, in the same manner as in the step shown in FIG. 47 (15), as shown in FIG.
VD, high-density plasma CVD, catalytic CVD, etc.
An SiO ₂ film 53 (about 200 nm thick) and a phosphosilicate glass (PSG) film 54 (about 300 nm thick) are formed on the entire surface. These films 53 and 54 correspond to the protective film 25 described above. Then, the single crystal silicon layer 7 is activated.

Next, in the same manner as in the step shown in FIG. 47 (16), a contact window is opened in the source portion as shown in FIG. 62 (13). And 400 to 5 on the whole surface
A sputtered film made of aluminum or an aluminum alloy containing 1% Si having a thickness of about 00 nm is formed, and a data line and a gate line are formed at the same time as the source electrode 26 is formed by general-purpose photolithography and etching technology.

Next, in the same manner as in the step shown in FIG. 47 (16), as shown in FIG. 63 (14), an insulating film 36 made of a PSG film (about 300 nm thick) and a SiN film (about 300 nm thick). Is formed on the entire surface, and TF for display is further formed.
A contact window is opened in the drain portion of T.

Next, as shown in FIG. 63 (15),
A photosensitive resin film 28 having a thickness of about 2 to 3 μm is formed on the entire surface by spin coating or the like. Subsequently, (19) in FIG.
Similarly to the process shown in (20), (16) in FIG.
As shown in (1), the lower part of the reflective surface composed of the roughened surface 28A is formed in the pixel part, and at the same time, the resin window for the contact of the drain part of the display TFT is opened and further connected to the drain part 19 of the display TFT. Film 29 made of a concavo-convex shape aluminum alloy or the like for obtaining excellent reflection characteristics and viewing angle characteristics
To form

As described above, the crystalline sapphire film 5
0 is used as a seed for heteroepitaxial growth to form a single crystal silicon layer 7, and a dual gate type nMOS LDD-TFT is formed on a display unit using the single crystal silicon layer 7.
, A bottom gate type pMOSTFT in the peripheral drive circuit
And an active matrix substrate 30 integrated with a display section and a peripheral drive circuit section, in which a CMOS drive circuit composed of an nMOS TFT is formed.

<Seventeenth Embodiment> A seventeenth embodiment of the present invention will be described with reference to FIGS.

In this embodiment, different from the above-described embodiment, the gate electrode of the top gate portion is formed of a material having relatively low heat resistance such as an aluminum alloy.

First, the top gate type MOSTF
T, and a bottom gate type MOSTF
The case where T is provided will be described. In this example,
FIG. 43 (1) to FIG. 43 in the twelfth embodiment.
Performed in the same manner as in the step shown in FIG. 45 (8), and then, as shown in FIG.
An N-type well 7A is formed in the MOSTFT portion.

Next, as shown in FIG. 64 (11),
All of the nMOS and pMOSTFTs in the peripheral drive region and the gate portion of the nMOSTFT in the display region are covered with a photoresist 13, and phosphorus ions 14 are applied to the exposed source / drain regions of the nMOSTFT by, for example, 5 × 1 at 20 kV.
By doping (ion implantation) at a dose of 0 ¹³ atoms / cm ² , an LDD portion 15 made of an N ⁻ -type layer is formed in a self-aligned manner.

Next, as shown in FIG. 65 (12),
All of the pMOSTFTs in the peripheral drive area, the gates of the nMOSTFTs in the peripheral drive area, and the
The gate of T and the LDD portion are covered with a photoresist 16, and the exposed region is doped (ion-implanted) with phosphorus or arsenic ions 17 at, for example, 20 kV at a dose of 5 × 10 ¹⁵ atoms / cm ² to form an nMOS TFT. N ⁺
LDD with Source 18 and Drain 19 Made of Mold Layer
The part 15 is formed. In this case, the resist 13 is left as shown by a dashed line in FIG.
If the resist 6 is provided, the resist 16 is
The alignment of the mask at the time of formation can be performed, thereby facilitating mask alignment and reducing misalignment.

Next, as shown in (13) of FIG.
NMOS TFT in peripheral drive area and nMOS in display area
The entirety of the TFT and the gate of the pMOSTFT are covered with a photoresist 20, and boron ions 21
(Ion implantation) at a dose of 5 × 10 ¹⁵ atoms / cm ^{2 at} 10 kV, for example,
The source part 22 and the drain part 23 of the P ⁺ layer are formed.

Next, the resist 20 is removed.
As shown in FIG. 65 (14), the single-crystal silicon layers 7, 7
A is activated in the same manner as described above, and a gate insulating film 12 and a gate electrode material (aluminum or 1%
An aluminum alloy containing Si 11) is formed. The gate electrode material layer 11 can be formed by a vacuum evaporation method or a sputtering method.

[0328] Then, by patterning the respective gate portion in the same manner as described above, then, an island and an active element portion and the passive element portion, further as shown in (15) in FIG. 66, SiO ₂ film on the entire surface (About 200 nm thick) and a phosphor silicate glass (PSG) film (about 300 nm) are successively formed in this order to form a protective film 25.

Next, as shown in (16) of FIG.
By general-purpose photolithography and etching technology, contact windows are opened in the source / drain portions of all the TFTs of the peripheral drive circuit and the source portions of the display TFT.

Then, a sputtered film of aluminum or an aluminum alloy containing 1% Si having a thickness of 500 to 600 nm is formed on the entire surface, and all the TFs of the peripheral drive circuit and the display section are formed by general-purpose photolithography and etching technology.
T source electrode 26 and drain electrode 2 of peripheral drive circuit section
7 and a data line and a gate line are formed at the same time. Then, forming gas (N ₂ +
Sinter in H ₂ ) at about 400 ° C./1 h.

Next, (17) in FIG. 47 to (1) in FIG.
By performing in the same manner as in the step shown in 9), a top gate type nMOSLDD-TF using an aluminum alloy or the like as a gate electrode is formed on the display portion using the single crystal silicon layer 7.
T and a bottom gate type pMOS in the peripheral drive circuit.
It is possible to manufacture an active matrix substrate 30 in which a display unit and a peripheral drive circuit unit are integrated, in which CMOS drive circuits each including a TFT and an nMOS TFT are manufactured.

In the present embodiment, the gate electrode 11 made of aluminum or an aluminum alloy containing 1% Si is formed after the activation treatment of the single crystal silicon layer 7, so that the influence of heat during the activation treatment is not affected by the gate. Since it has no relation to the heat resistance of the electrode material, the heat resistance is relatively low as the top gate electrode material, and low-cost aluminum or aluminum or copper containing 1% Si can be used. . This is the same when the display section is a bottom gate type MOSTFT.

Next, a dual gate type MOST is provided in the display section.
FT is provided, and bottom gate type MOSTF is provided in the peripheral drive circuit.
The case where T is provided will be described. In this example,
(10) to (10) of FIG. 31 in the eighth embodiment described above.
Performed in the same manner as in the step shown in FIG. 33 (17), a dual gate type nMOS LDD-TFT using an aluminum alloy or the like as a gate electrode in the display portion, and a bottom gate type pMOSTFT and nMOSTF in the peripheral drive circuit portion.
CMOS drive circuits composed of T
The active matrix substrate 30 integrated with the display section and the peripheral drive circuit section can be manufactured.

<Eighteenth Embodiment> The eighteenth embodiment of the present invention will be described with reference to FIGS.

The example shown in FIG. 67 relates to a TFT having a self-aligned LDD structure, for example, a double-gate MOSTFT in which a plurality of top-gate LDD-TFTs are connected in the twelfth embodiment.

In the example shown in FIG. 68A, the bottom gate type MOSTFT has a double gate structure.
The example shown in FIG. 68B is a dual gate type MOST.
The FT has a double gate structure.

These double-gate MOSTFTs have the same advantages as those shown in FIGS.

<Nineteenth Embodiment> A nineteenth embodiment of the present invention will be described with reference to FIGS.

As described above, the top gate type, bottom gate type, and dual gate type TFTs each have a difference in structure or function or a feature. In some cases, it may be advantageous to provide various combinations of TFTs between these components.

For example, as shown in FIG. 69, when any one of a top gate type, a bottom gate type, and a dual gate type MOSTFT is adopted for the display portion, the top gate type MOSTFT and the bottom gate type MOSTFT are used for the peripheral drive circuit.
At least a bottom gate type of the TFT and the dual gate type MOSTFT may be adopted, or both may be mixed. There are twelve (No. 1 to No. 12) combinations. In particular, when a dual gate structure is used for the MOSTFT of the peripheral drive circuit,
Such a dual gate structure can be easily changed to a top gate type or a bottom gate type by selecting upper and lower gate portions, and a TFT having a large driving capability is required in a part of the peripheral driving circuit. In some cases, a dual gate type may be required. For example, it is considered necessary when the present invention is applied to the organic EL or FED of the present invention as an electro-optical device other than the LCD.

FIGS. 70 and 71 show the MOSTFT of the display section.
72 and FIG. 73 show the case where the MOSTFT of the display section has the LDD structure when FIG. 74 and FIG.
Reference numeral 5 denotes a TF having an LDD structure in which a MOSTFT in a peripheral drive circuit section
76, FIG. 76 and FIG. 77 show MOSTs of the peripheral drive circuit unit and the display unit when both the peripheral drive circuit unit and the display unit include the MOSD with the LDD structure.
It is a figure which shows the various examples (No.1-No.216) which showed the combination of FT according to channel conductivity type.

As described above, the combinations for each gate structure shown in FIG. 69 are specifically as shown in FIGS. 70 to 77. In this case, the same combination is possible even when the peripheral drive circuit portion is formed of a MOSTFT in which a bottom gate type and another gate type are mixed. FIG.
The various combinations of the TFTs shown in FIGS.
The present invention is not limited to the case where the channel region or the like is formed of single-crystal silicon, but is similarly applicable to the case where the channel region is formed of polycrystalline silicon or amorphous silicon (however, only the display portion).

<Twentieth Embodiment> FIGS. 78 to 79
Shows a twentieth embodiment of the present invention.

In the present embodiment, a TFT using the above-described single crystal silicon layer based on the present invention is provided in the peripheral drive circuit portion of the active matrix drive LCD in order to improve the drive capability. However, this is not limited to the bottom gate type, other gate types may be mixed, the channel conductivity type may be various, and a MOST using a polycrystalline silicon layer other than a single crystal silicon layer may be used.
FT may be included. In contrast, the MO
For the STFT, although it is desirable to use a single crystal silicon layer, the present invention is not limited to this, and a polycrystalline silicon or amorphous silicon layer may be used, or two of the three types of silicon layers may be mixed. It may be something. However, when the display portion is formed of an nMOS TFT, a practical switching speed can be obtained even if the display portion is formed using an amorphous silicon layer, but the TFT area can be reduced in single crystal silicon or polycrystalline silicon, and the pixel area can be reduced. It is more advantageous than amorphous silicon in reducing defects. In the above-described heteroepitaxial growth, not only single-crystal silicon but also polycrystalline silicon is produced at the same time, so-called CGS (Continuous grain silicide).
On) structures may be included, but can also be used to form active and passive devices.

FIG. 78 shows examples (A), (B), and (C) of various combinations of MOSTFTs between parts, and FIG. 79 shows specific examples. When single crystal silicon is used, the current capability is improved, so that the element can be made smaller, a large screen can be obtained and the aperture ratio can be improved in the display portion.

In the peripheral drive circuit portion, the above-described MOS is used.
It goes without saying that not only the TFT but also an electronic circuit in which a diode, a capacitance, a resistance, an inductance and the like are integrated may be integrally formed on an insulating substrate (a glass substrate or the like).

<Twenty-first Embodiment> A twenty-first embodiment of the present invention will be described with reference to FIG.

In this embodiment, the present invention is applied to passive matrix driving, while each of the above-described embodiments relates to an example of active matrix driving.

That is, in the present embodiment, the display section is provided with no switching element such as the MOSTFT described above, and the incident light of the display section is determined only by the potential difference caused by the voltage applied between the pair of electrodes formed on the opposing substrate. Alternatively, the reflected light is dimmed. Such dimming elements include reflective and transmissive LCDs, as well as organic or inorganic E-lights.
L (electroluminescence display element), FED (field emission display element), LEPD (light emitting polymer display element), LED (light emitting diode display element) and the like are also included.

<Twenty-second Embodiment> Referring to FIG. 81, a twenty-second embodiment of the present invention will be described.

In this embodiment, the present invention is applied to an electro-optical device other than an LCD, such as an organic or inorganic EL (electroluminescence element), an FED (field emission display element),
It is applied to LEPD (light emitting polymer display element), LED (light emitting diode display element) and the like.

FIG. 81A shows an active matrix driven EL element. This EL element is, for example, an organic EL layer (or ZnS: M) using an amorphous organic compound.
An inorganic EL layer using n) 90 is provided on the substrate 1, the transparent electrode (ITO) 41 described above is formed below the substrate 1, and the cathode 91 is formed above the same. Thus, light of a predetermined color can be obtained through the color filter layer 61.

In this EL element, a MOSTFT is formed on the substrate 1 in order to apply a data voltage to the transparent electrode 41 by active matrix driving. The MOSTFT is formed of a crystalline sapphire film 50 on the substrate 1.
A single-crystal silicon MOSTFT (that is, an nMOSLDD-TFT) according to the present invention, which uses a single-crystal silicon layer 7 obtained by heteroepitaxial growth using (step 4) as a seed. Also, a similar T
The FT is also provided in the peripheral drive circuit. An EL element having such a configuration is a MOSL using a single crystal silicon layer.
Since it is driven by the DD-TFT, the switching speed is high and the leakage current is small.

The filter 61 described above
If the L layer 90 emits a specific color, it can be omitted. In the case of an EL element, since a driving voltage is high, it is advantageous to provide a high-withstand-voltage driver element (such as a high-withstand-voltage cMOSTFT and a bipolar element) in addition to the MOSTFT in the peripheral drive circuit portion.

FIG. 81B shows an FED driven by passive matrix. In this FED, electrons emitted from the cold cathode 94 by the voltage applied between the electrodes 92 and 93 are incident on the opposing phosphor layer 96 by selecting the gate line 95 in a vacuum portion between the opposing glass substrates 1-32. Thus, light emission of a predetermined color is obtained.

Here, the emitter line 92 is guided to a peripheral drive circuit and driven by a data voltage. The peripheral drive circuit is provided with a MOSTFT made of a single crystal silicon layer formed according to the present invention. , Emitter line 9
2 which contributes to high-speed driving. The FED can be driven in an active matrix by connecting the MOSTFT to each pixel.

In the device shown in FIG. 81A, EL
If a known light emitting polymer is used instead of the layer 90, a passive matrix or active matrix driven light emitting polymer display device (LEPD) can be formed. In addition, a device similar to the FED using the diamond thin film on the cathode side in the element of FIG. 81B can also be configured. Further, in a light emitting diode, for example, a gallium-based (gallium.
A light-emitting portion made of a film of aluminum, arsenic, etc.) can be driven. Alternatively, it is conceivable to grow the film of the light emitting portion by single crystal by the epitaxial growth method of the present invention.

The embodiments of the present invention described above can be variously modified based on the technical concept of the present invention.

For example, at the time of forming the silicon film 5 described above, an element of Group 3 or 5 of the periodic table having high solubility (for example, boron, phosphorus, antimony, arsenic, aluminum, gallium, indium, bismuth) is appropriately doped. By doing so, the P-type or N-type channel conductivity type of the obtained silicon epitaxial growth layer (single-crystal silicon layer 7) and the carrier concentration thereof can be arbitrarily controlled. Further, the method of the second or fifth embodiment may be applied to the fifth embodiment (using tin / lead or tin).

Also, in order to prevent diffusion of ions from the glass substrate, a SiN film (for example, 50 to 200 nm) is formed on the substrate surface.
Thickness) and, if necessary, a SiO ₂ film (for example, 100
nm thick), and the step 4 described above may be formed in these films. The above-described steps can be formed by an ion milling method or the like in addition to RIE. Further, as described above, it is a matter of course that the step 4 may be formed within the thickness of the crystalline sapphire film or the sapphire substrate itself other than forming the step 4 on the substrate 1.

The sapphire (Al ₂ O ₃ )
Instead, a spinel structure (for example, magnesia spinel) having good lattice matching with single crystal silicon (Mgo.Al ₂
O ₃ ), CaF ₂ , SrF ₂ , BaF ₂ , BP, (Y
₂ O ₃ ) _m , (ZrO ₂ ) _{1-m and the} like can be used.

The present invention is suitable for the TFTs in the peripheral drive circuit section and the display section. In addition, the present invention provides an active area of an element such as a diode and a passive area such as a resistor, a capacitor, and an inductance. It is also possible to form a single-crystal silicon layer by using the method described above.

[0363]

As described above, according to the present invention, the material layer (for example, a crystalline sapphire film) having a good lattice matching with a single-crystal semiconductor (for example, single-crystal silicon) is used as a seed. A single-crystal semiconductor layer is heteroepitaxially grown to form a single-crystal semiconductor layer. This is used as a bottom gate type MOSTFT for a peripheral drive circuit of a drive substrate such as an active matrix substrate, or an electro-optical device such as a display-peripheral drive circuit integrated LCD. Since it is used for a bottom gate type MOSTFT of a peripheral drive circuit in the device, it has the following remarkable effects (A) to (H).

(A) A material layer (for example, a crystalline sapphire film) having good lattice matching with single crystal silicon is formed on a substrate,
By heteroepitaxially growing the material layer as a seed, a single crystal semiconductor layer such as a single crystal silicon layer having a high electron mobility of 540 cm ² / v · sec or more can be obtained. And the like can be manufactured.

(B) In particular, the single-crystal silicon layer has a higher electron and hole mobility than a single-crystal silicon substrate as compared with a conventional amorphous silicon layer or polycrystalline silicon layer. Gate type M
The OSTFT has a high switching characteristic [preferably, an LDD (Li
ghtly doped drain) structure] nMOS or pM
A display unit composed of an OSTFT or a cMOSTFT, and a cMOS, an nMOS, or a pMOSTFT having a high driving capability;
Alternatively, it becomes possible to integrate a peripheral drive circuit section composed of a mixture of these, and a display panel with high image quality, high definition, narrow frame, high efficiency, and large screen is realized. In particular, polycrystalline silicon has a high hole mobility p as a TFT for LCD.
Although it is difficult to form a MOSTFT, in the single-crystal silicon layer according to the present invention, since a hole shows a sufficiently high mobility, a peripheral driving circuit for driving electrons and holes individually or in combination of both. Can be produced, and this is referred to as LDD of nMOS or pMOS or cMOS.
A panel integrated with a display-use TFT having a structure can be realized. In the case of a small to medium-sized panel, there is a possibility that one of a pair of peripheral vertical drive circuits can be omitted.

(C) The substrate temperature of polycrystalline silicon, amorphous silicon, etc. is 100 to 400
It can be formed by a plasma CVD method or a low pressure CVD method under the condition of a temperature of ° C., and the low melting point metal layer can be formed by a known method such as a vacuum evaporation method or a sputtering method. In addition, since the heat treatment temperature during the above-described silicon epitaxial growth can be set to 600 ° C. or less, a single-crystal silicon layer is uniformly formed at a relatively low temperature (for example, 400 to 450 ° C.) on an insulating substrate. can do. Therefore, it is easy to obtain a glass substrate or a heat-resistant resin substrate with a relatively low strain point,
A low-cost substrate with good physical properties can be used, and the size of the substrate can be increased.

(D) The need for long-time (about 600 ° C., tens of hours) annealing at medium temperature and excimer laser annealing as in the case of the solid phase growth method is unnecessary, so that high productivity and expensive manufacturing equipment are required. Is unnecessary and cost can be reduced.

(E) In this heteroepitaxial growth, the crystallinity of a material layer such as a crystalline sapphire film, the composition ratio of polycrystalline silicon or amorphous silicon to a low melting point metal, and the heating temperature and cooling rate of the substrate are adjusted. Since a wide range of a P-type or N-type conductivity type and a high-mobility single-crystal silicon layer can be easily obtained, Vth (threshold) adjustment becomes easy, and high-speed operation by lowering resistance becomes possible.

(F) When forming a semiconductor (amorphous silicon or polycrystalline silicon) film on the material layer or a semiconductor-containing low melting point metal layer, an N-type or P-type carrier impurity (boron, phosphorus, antimony, If an appropriate amount of arsenic, bismuth, aluminum or the like is mixed (introduced), the impurity species and / or the concentration of the single crystal semiconductor layer (single crystal silicon layer), that is, the conductivity type such as P type / N type and / or the carrier concentration Can be arbitrarily controlled.

(G) The material layer such as a crystalline sapphire film serves as a diffusion barrier for various atoms, so that diffusion of impurities from the glass substrate can be suppressed.

(H) The low melting point metal layer was obtained because it was formed of tin or lead or an alloy of tin and lead, or tin or lead or an alloy of tin and lead containing a semiconductor. Even if tin or lead is mixed in the single-crystal silicon layer (single-crystal semiconductor layer), these are mixed in the fourth table of the periodic table.
The element is a group element and does not become a carrier in the silicon layer, so that the silicon layer has a high resistance. Therefore, Vth adjustment and resistance adjustment of the TFT by ion doping (implantation) or the like become easy, and a high-performance circuit configuration can be realized. In addition, tin and lead remaining in the silicon layer electrically inactivate crystal defects, so that the obtained silicon layer has a reduced junction leak and an increased electron mobility.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of an LCD (Liquid Crystal Display) according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 3 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 4 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 5 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 6 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 7 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 8 is a sectional view of a main part of the LCD.

FIG. 9 is a schematic perspective view for explaining the state of silicon crystal growth on an amorphous substrate.

FIG. 10 shows grapho-epitaxial growth technology.
It is a schematic sectional drawing which shows various step shapes and a silicon growth crystal orientation.

FIG. 11 is a perspective view showing an overall schematic layout of the LCD according to the first embodiment of the present invention.

FIG. 12 is an equivalent circuit diagram of the LCD.

FIG. 13 is a schematic configuration diagram of the same LCD.

FIG. 14 is a cross-sectional view showing a manufacturing process of the LCD according to the second embodiment of the present invention in the order of steps.

FIG. 15 is a cross-sectional view showing a process of manufacturing an LCD according to the third embodiment of the present invention in the order of steps.

FIG. 16 is a sectional view illustrating a manufacturing process of an LCD according to a fourth embodiment of the present invention in the order of steps.

FIG. 17 is a sectional view of a main part of the LCD.

FIG. 18 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 19 is a sectional view of a main part of an LCD according to a seventh embodiment of the present invention.

FIG. 20 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 21 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 22 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 23 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 24 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 25 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 26 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 27 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 28 is a cross-sectional view showing a process of manufacturing an LCD according to the eighth embodiment of the present invention in the order of steps.

FIG. 29 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 30 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 31 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 32 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 33 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 34 is a fragmentary cross-sectional view of the same during manufacture of the LCD.

FIG. 35 is a fragmentary cross-sectional view of the same during manufacture of the LCD.

FIG. 36 is a plan view or a sectional view showing various TFTs of an LCD according to a ninth embodiment of the present invention.

FIG. 37 is a cross-sectional view showing various TFTs at the time of manufacturing the LCD.

FIG. 38 is a cross-sectional view of main parts of the same LCD.

FIG. 39 is a cross-sectional view or a plan view of main parts of an LCD according to a tenth embodiment of the present invention.

FIG. 40 is a cross-sectional view of a principal part of various TFTs of the LCD.

FIG. 41 is an equivalent circuit diagram of a TFT of the LCD.

FIG. 42 is a sectional view showing a main part of a TFT of an LCD according to an eleventh embodiment of the present invention;

FIG. 43 is a cross-sectional view showing a manufacturing process of the LCD according to the twelfth embodiment of the present invention in the order of steps;

FIG. 44 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 45 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 46 is a cross-sectional view showing an LCD manufacturing process in the order of steps;

FIG. 47 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 48 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 49 is a cross-sectional view of main parts of the LCD.

FIG. 50 is a cross-sectional view showing a manufacturing process of the LCD according to the thirteenth embodiment of the present invention in the order of steps;

FIG. 51 is a cross sectional view showing the manufacturing process of the LCD according to the fourteenth embodiment of the present invention in the order of steps;

FIG. 52 is a cross sectional view showing the manufacturing process of the LCD according to the fifteenth embodiment of the present invention in the order of steps;

FIG. 53 is a cross-sectional view of a main part of the same LCD.

FIG. 54 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 55 is a cross-sectional view of a principal part of an LCD according to a sixteenth embodiment of the present invention.

FIG. 56 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 57 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 58 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 59 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 60 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 61 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 62 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 63 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 64 is a cross sectional view showing the manufacturing process of the LCD according to the seventeenth embodiment of the present invention in the order of steps;

FIG. 65 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 66 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 67 is a cross-sectional view or a plan view of main parts of an LCD according to an eighteenth embodiment of the present invention.

FIG. 68 is a cross-sectional view of a principal part of various TFTs of the LCD.

FIG. 69 is a diagram showing a combination of TFTs of each part of the LCD according to the nineteenth embodiment of the present invention.

FIG. 70 is a diagram showing combinations of TFTs of each part of the LCD.

FIG. 71 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 72 is a view showing a combination of TFTs in each part of the LCD.

FIG. 73 is a view showing a combination of TFTs of each part of the LCD.

FIG. 74 is a diagram showing combinations of TFTs of each part of the LCD.

FIG. 75 is a view showing a combination of TFTs of each part of the LCD.

FIG. 76 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 77 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 78 is a schematic layout diagram of an LCD according to a twentieth embodiment of the present invention.

FIG. 79 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 80 is a schematic layout diagram of a device according to a twenty-first embodiment of the present invention;

FIG. 81 is a cross-sectional view of a main part of an EL and FED according to a twenty-second embodiment of the present invention;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate, 4 ... Step, 5 ... Silicon film, 6 ... Low melting point metal layer, 7 ... Single crystal silicon layer, 9 ... Sputtered film, 11 ... Gate electrode, 12 ... Gate oxide film, 14, 17 ... N-type impurity Ions, 15 LDD portions, 18, 19 N ⁺ -type source or drain regions, 21 P-type impurity ions, 22, 2
3 ... P ⁺ source or drain region, 25, 36 ... insulating film, 26, 27, 31, 41 ... electrode, 29 ... reflective film, 3
0: LCD (TFT) substrate, 50: crystalline sapphire film

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yuichi Sato 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Hajime Yagi 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation F-term (reference) 2H092 JA01 JA24 JA25 JA26 JA34 JA37 KA02 KA03 KA04 KA05 KA10 KB26 MA05 MA06 MA08 MA15 MA18 MA19 MA27 MA29 MA30 NA07 NA28 PA01 PA02 PA06 PA08 QA07 QA08 QA10 QA11 QA13 A01A01A DB07 FA08 FA14 GC06 GC07 GC09 GC10 JA01 JA02 JA04 5F110 AA06 AA16 AA17 AA28 BB02 BB04 CC02 CC06 DD01 DD02 DD03 DD12 DD13 DD14 DD17 EE06 EE23 EE28 EE30 EE44 FF02 FF03 FF29 FF30 GG02 J03 H12 GG12 GG12 GG12 GG12 H HL23 HM15 NN02 NN03 NN04 NN23 NN24 NN25 NN35 NN44 NN47 NN54 NN74 PP03 PP08 PP23 PP36 QQ11

Claims (180)

[Claims] 1. A display device comprising: a display portion on which a pixel electrode is disposed; and a peripheral drive circuit portion disposed around the display portion on a first substrate. An electro-optical device having a predetermined optical material interposed therebetween, wherein a gate portion including a gate electrode and a gate insulating film is formed on one surface of the first substrate; A material layer having good lattice matching with the single crystal semiconductor is formed on one surface, and a semiconductor film made of a semiconductor and tin or lead or an alloy of tin and lead is formed on the first substrate including the material layer. Is formed, or a low-melting metal layer made of tin or lead containing a semiconductor or an alloy of tin and lead is formed, and the semiconductor is dissolved in the low-melting metal layer by heat treatment. , And the dissolved semiconductor is cooled Accordingly, a single crystal semiconductor layer is formed by heteroepitaxial growth using the material layer as a seed, and the single crystal semiconductor layer is used as a channel region, a source region, and a drain region, and the bottom gate has the gate portion below the channel region. An electro-optical device, wherein a first thin film transistor of the type forms at least a part of the peripheral driving circuit section. 2. The electro-optical device according to claim 1, wherein the film made of the semiconductor is amorphous silicon or polycrystalline silicon, and the single crystal semiconductor layer is a single crystal silicon layer. 3. The method according to claim 1, wherein the single crystal semiconductor layer is an N-type or P-type semiconductor layer.
3. The electro-optical device according to claim 2, wherein the specific resistance is adjusted by mixing the type of carrier impurity. 4. An insulating substrate is used as the first substrate, and the material layer is sapphire, spinel structure, calcium fluoride, strontium fluoride, barium fluoride,
3. A material formed from a material selected from the group consisting of boron phosphide, yttrium oxide and zirconia.
An electro-optical device according to claim 1. 5. The electro-optical device according to claim 2, wherein a diffusion barrier layer is provided between the first substrate and the single crystal semiconductor layer. 6. The electro-optical device according to claim 2, wherein the gate portion below the single-crystal silicon layer has a trapezoidal shape at a side end thereof. 7. The peripheral driving circuit section, wherein the first
A thin film transistor of a top gate type, a bottom gate type or a dual gate type having a polycrystalline or amorphous silicon layer as a channel region and a gate portion above and / or below the channel region, or the single crystal silicon The electro-optical device according to claim 2, wherein a diode, a resistor, a capacitance, an inductance element, or the like using a layer, a polycrystalline silicon layer, or an amorphous silicon layer is provided. 8. The electro-optical device according to claim 2, wherein in the display unit, a switching element for switching the pixel electrode is provided on the first substrate. 9. The electro-optical device according to claim 8, wherein the switching element is a top gate type, a bottom gate type, or a dual gate type second thin film transistor having a gate portion above and / or below a channel region. apparatus. 10. The gate electrode provided below the channel region is made of a heat-resistant material.
An electro-optical device according to claim 1. 11. The thin film transistor of the peripheral driver circuit section and the display section has an n-channel type, a p-channel type,
10. The electro-optical device according to claim 9, wherein the device forms a complementary insulated gate field effect transistor. 12. The thin film transistor of the peripheral drive circuit section comprises a set of a complementary type and an n-channel type, a set of a complementary type and a p-channel type, or a set of a complementary type, an n-channel type and a p-channel type. The electro-optical device according to claim 11. 13. A single type in which at least a part of the thin film transistor of the peripheral driver circuit portion and / or the display portion has an LDD structure, and the LDD structure has an LDD portion between a gate and a source or a drain, or The electro-optical device according to claim 9, wherein the electro-optical device is a double type having an LDD portion between the gate, the source, and the drain. 14. The thin film transistor of the peripheral driver circuit portion and / or the display portion is configured as a single gate or a multi-gate, and in the case of a multi-gate, two or more branched same potentials in a channel region, or The electro-optical device according to claim 9, further comprising divided gate electrodes having different potentials or the same potential. 15. When the n-type or p-channel type thin film transistor of the peripheral driver circuit portion and / or the display portion is a dual gate type, an upper or lower gate electrode is electrically opened or an arbitrary negative electrode is provided. 10. The electro-optical device according to claim 9, wherein a voltage (in the case of an n-channel type) or a positive voltage (in the case of a p-channel type) is applied to operate as a bottom-gate or top-gate thin film transistor. 16. When the thin film transistor of the peripheral driver circuit is the n-channel, p-channel, or complementary first thin film transistor, and the thin film transistor of the display unit uses a single crystal silicon layer as a channel region. n-channel type, p-channel type, or complementary type; n-channel type, p-channel type, or complementary type when a polycrystalline silicon layer is used as a channel region; and n-channel type when an amorphous silicon layer is used as a channel region. The electro-optical device according to claim 11, which is of a p-channel type or a complementary type. 17. A step is formed on the first substrate and / or a film thereon, the material layer is formed on the first substrate having the step formed thereon, and the single crystal semiconductor is formed on the material layer. 3. The electro-optical device according to claim 2, wherein a layer is formed. 18. The step is formed as a concave portion whose side surface is perpendicular to the bottom surface or inclined toward the lower end in a cross section, and the step serves as a seed for epitaxial growth of the single crystal silicon layer together with the material layer. The electro-optical device according to claim 17, wherein 19. A step is formed in the first substrate and / or a film thereon, the material layer is formed on the first substrate having the step formed thereon, and the single crystal semiconductor is formed on the material layer. 3. The electro-optical device according to claim 2, wherein a layer is formed. 20. The electric device according to claim 19, wherein the first thin film transistor is provided in and / or outside a substrate recess formed by the step formed on the first substrate and / or a film thereon. Optical device. 21. The electro-optical device according to claim 19, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the thin film transistor as the active element. 22. The electro-optical device according to claim 2, wherein a step is formed in the material layer, and the single crystal semiconductor layer is formed on the material layer including the step. 23. The electric device according to claim 22, wherein the first thin film transistor is provided inside and / or outside a concave portion of the substrate formed by the step formed on the first substrate and / or a film thereon. Optical device. 24. The step is formed as a concave portion whose side surface is perpendicular to the bottom surface or inclined toward the lower end side in a cross section, and the step forms a seed together with the material layer during the epitaxial growth of the single crystal semiconductor layer. 21. The electro-optical device according to claim 20, wherein 25. The electro-optical device according to claim 22, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the thin film transistor as the active element. 26. A step is formed on the first substrate and / or a film thereon, and a single crystal, polycrystalline or amorphous silicon layer is formed on the first substrate including the step, and 10. The electro-optical device according to claim 9, wherein the thin film transistor includes the single crystal, polycrystal, or amorphous silicon layer as a channel region, a source region, and a drain region, and has a gate portion above and / or below the channel region. 27. The step is formed as a concave portion whose side surface is perpendicular to the bottom surface or inclined toward the lower end in a cross section, and this step serves as a seed together with the material layer during epitaxial growth of the single crystal semiconductor layer. 27. The electro-optical device according to claim 26, wherein: 28. The electro-optical device according to claim 26, wherein a source or drain region of the first and / or second thin film transistor is formed on a region including the step. 29. The electric device according to claim 26, wherein the second thin film transistor is provided inside and / or outside a substrate recess formed by the step formed on the first substrate and / or a film thereon. Optical device. 30. The electric device according to claim 26, wherein the step is formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor. Optical device. 31. The electro-optical device according to claim 26, wherein the gate electrode under the single-crystal, polycrystal, or amorphous silicon layer has a trapezoidal shape at a side end thereof. 32. The electro-optical device according to claim 26, wherein a diffusion barrier layer is provided between the first substrate and the single crystal, polycrystal, or amorphous silicon layer. 33. The electro-optical device according to claim 2, wherein the first substrate is a glass substrate or a heat-resistant resin substrate. 34. The electro-optical device according to claim 2, wherein the first substrate is optically opaque or transparent. 35. The electro-optical device according to claim 2, wherein the pixel electrode is provided for a reflective or transmissive display unit. 36. The electro-optical device according to claim 2, wherein the display section has a laminated structure of the pixel electrode and a color filter layer. 37. When the pixel electrode is a reflective electrode, irregularities are formed on the resin film, and the pixel electrode is provided thereon. When the pixel electrode is a transparent electrode, the surface is formed by a transparent flattening film. The electro-optical device according to claim 2, wherein the pixel electrode is planarized, and the pixel electrode is provided on the planarized surface. 38. The electro-optical device according to claim 8, wherein the display section emits light or modulates light when driven by the switching element. 39. The electro-optical device according to claim 8, wherein a plurality of the pixel electrodes are arranged in a matrix on the display unit, and the switching element is connected to each of the pixel electrodes. 40. The electro-optical device according to claim 2, configured as a liquid crystal display, an electroluminescence display, a field emission display, a light emitting polymer display, a light emitting diode display, or the like. 41. The electro-optical device according to claim 1, wherein a control unit that controls an operation of the peripheral driving circuit unit and / or the display unit is provided on the first substrate. 42. The electro-optical device according to claim 43, wherein the control unit is a system-on-panel integrally formed with a so-called computer system, which is configured by a CPU, a memory, or a system LSI in which these are mounted. 43. A driving substrate for an electro-optical device, comprising a display portion on which a pixel electrode is disposed, and a peripheral driving circuit portion disposed around the display portion on a substrate, wherein one surface of the substrate is provided. A gate portion including a gate electrode and a gate insulating film is formed thereon, and a material layer having good lattice matching with a single crystal semiconductor is formed on the one surface of the substrate, and on the substrate including the material layer A semiconductor film made of a semiconductor and a low-melting metal layer made of tin or lead or an alloy of tin and lead, or a low-melting metal layer made of tin or lead containing a semiconductor or an alloy of tin and lead Is formed, the semiconductor is dissolved in the low melting point metal layer by heat treatment, and the dissolved semiconductor is heteroepitaxially grown by using the material layer as a seed by cooling treatment. A single-crystal semiconductor layer is formed as a channel region, a source region, and a drain region, and a first bottom-gate thin film transistor having the gate portion below the channel region is formed by the peripheral driver circuit portion. A driving substrate for an electro-optical device, which constitutes at least a part of a driving substrate. 44. The driving substrate for an electro-optical device according to claim 43, wherein the film made of the semiconductor is amorphous silicon or polycrystalline silicon, and the single crystal semiconductor layer is a single crystal silicon layer. 45. The driving substrate for an electro-optical device according to claim 44, wherein the specific resistance of the single crystal semiconductor layer is adjusted by mixing N-type or P-type carrier impurities. 46. An insulating substrate is used as the substrate,
The method according to claim 44, wherein the material layer is formed of a material selected from the group consisting of sapphire, spinel structure, calcium fluoride, strontium fluoride, barium fluoride, boron phosphide, yttrium oxide and zirconia. Drive substrate for electro-optical devices. 47. The driving substrate for an electro-optical device according to claim 44, wherein a diffusion barrier layer is provided between the substrate and the single crystal semiconductor layer. 48. The gate portion under the single-crystal silicon layer has a trapezoidal shape at a side end thereof.
A driving substrate for the electro-optical device according to the above. 49. In the peripheral driver circuit portion, in addition to the first thin film transistor, a polycrystalline or amorphous silicon layer is used as a channel region, and a top gate type and a bottom type having a gate portion above and / or below the channel region. The electro-optic according to claim 44, wherein a gate, a dual-gate thin film transistor, or a diode, a resistor, a capacitance, an inductance element, or the like using the single crystal silicon layer, the polycrystal silicon layer, or the amorphous silicon layer is provided. Driving board for equipment. 50. The driving substrate for an electro-optical device according to claim 44, wherein in the display section, a switching element for switching the pixel electrode is provided on the substrate. 51. The switching element is a top gate type, a bottom gate type, or a dual gate type having a gate portion above and / or below a channel region.
51. The driving substrate for an electro-optical device according to claim 50, wherein the driving substrate is a thin film transistor. 52. The gate electrode provided below the channel region is made of a heat-resistant material.
A driving substrate for an electro-optical device according to claim 1. 53. The thin film transistor of the peripheral driver circuit portion and the display portion has an n-channel type, a p-channel type,
52. The driving substrate for an electro-optical device according to claim 51, wherein said driving substrate comprises a complementary insulated gate field effect transistor. 54. The thin film transistor of the peripheral drive circuit section is formed of a set of a complementary type and an n-channel type, a set of a complementary type and a p-channel type, or a set of a complementary type, an n-channel type and a p-channel type. A driving substrate for an electro-optical device according to claim 53. 55. A single type in which at least a part of the thin film transistor of the peripheral driver circuit portion and / or the display portion has an LDD structure, and the LDD structure has an LDD portion between a gate and a source or a drain, or 52. The driving substrate for an electro-optical device according to claim 51, wherein the driving substrate is a double type having an LDD portion between the gate and the source and the drain. 56. The thin film transistor of the peripheral driver circuit portion and / or the display portion is configured as a single gate or a multi-gate, and in the case of a multi-gate, two or more branched same potentials in a channel region, or 52. The driving substrate for an electro-optical device according to claim 51, further comprising divided gate electrodes having different potentials or the same potential. 57. When the n-type or p-channel type thin film transistor of the peripheral driver circuit portion and / or the display portion is a dual gate type, an upper or lower gate electrode is electrically opened or an arbitrary negative electrode is provided. 52. The driving substrate for an electro-optical device according to claim 51, wherein a voltage (for an n-channel type) or a positive voltage (for a p-channel type) is applied to operate as a bottom-gate or top-gate thin film transistor. 58. When the thin film transistor of the peripheral driver circuit portion is the n-channel, p-channel, or complementary first thin film transistor, and the thin film transistor of the display portion uses a single crystal silicon layer as a channel region n-channel type, p-channel type, or complementary type; n-channel type, p-channel type, or complementary type when a polycrystalline silicon layer is used as a channel region; and n-channel type when an amorphous silicon layer is used as a channel region. 54. The driving substrate for an electro-optical device according to claim 53, wherein the driving substrate is a p-channel type or a complementary type. 59. A step is formed in the substrate and / or a film thereon, the material layer is formed on the substrate on which the step is formed, and the single crystal semiconductor layer is formed on the material layer. A driving substrate for an electro-optical device according to claim 44. 60. The step is formed as a concave portion whose side surface is perpendicular to the bottom surface or inclined toward the lower end in a cross section, and the step forms a seed together with the material layer during the epitaxial growth of the single crystal silicon layer. The driving substrate for an electro-optical device according to claim 59, wherein the driving substrate is formed. 61. A step is formed on the substrate and / or a film thereon, the material layer is formed on the substrate on which the step is formed, and the single crystal semiconductor layer is formed on the material layer. A driving substrate for an electro-optical device according to claim 44. 62. The first thin film transistor is provided inside and / or outside a substrate recess due to the step formed on the substrate and / or a film thereon.
A driving substrate for the electro-optical device according to the above. 63. The electro-optical device according to claim 61, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the thin film transistor as the active element. Drive board. 64. The driving substrate for an electro-optical device according to claim 44, wherein a step is formed in the material layer, and the single crystal semiconductor layer is formed on the material layer including the step. 65. The method according to claim 64, wherein the first thin film transistor is provided in and / or outside a substrate recess formed by the step formed on the substrate and / or a film thereon.
A driving substrate for the electro-optical device according to the above. 66. The step is formed as a concave portion whose side surface is perpendicular to the bottom surface or inclined toward the lower end in the cross section, and this step serves as a seed for epitaxial growth of the single crystal semiconductor layer together with the material layer. 63. The driving substrate for an electro-optical device according to claim 62, wherein the driving substrate is formed. 67. The electro-optical device according to claim 64, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the thin film transistor as the active element. Drive board. 68. A step is formed in the substrate and / or a film thereon, a single crystal, polycrystalline or amorphous silicon layer is formed on the substrate including the step, and the second thin film transistor is 52. The driving substrate for an electro-optical device according to claim 51, wherein a crystalline, polycrystalline or amorphous silicon layer is used as a channel region, a source region, and a drain region, and a gate portion is provided above and / or below the channel region. 69. The step is formed as a concave portion whose side surface is perpendicular to the bottom surface or inclined toward the lower end in a cross section, and the step is formed together with the material layer as a seed during epitaxial growth of the single crystal semiconductor layer. The driving substrate for an electro-optical device according to claim 68, wherein the driving substrate is formed. 70. The driving substrate for an electro-optical device according to claim 68, wherein a source or drain region of the first and / or second thin film transistor is formed on a region including the step. 71. The second thin film transistor is provided inside and / or outside a substrate recess due to the step formed on the substrate and / or a film thereon.
A driving substrate for the electro-optical device according to the above. 72. The electric device according to claim 68, wherein the step is formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor. Driving substrate for optical devices. 73. The driving substrate for an electro-optical device according to claim 68, wherein a gate electrode under the single crystal, polycrystal, or amorphous silicon layer has a trapezoidal shape at a side end thereof. 74. The driving substrate for an electro-optical device according to claim 68, wherein a diffusion barrier layer is provided between the substrate and the single crystal, polycrystal, or amorphous silicon layer. 75. The driving substrate for an electro-optical device according to claim 44, wherein the substrate is a glass substrate or a heat-resistant resin substrate. 76. The driving substrate for an electro-optical device according to claim 44, wherein the substrate is optically opaque or transparent. 77. The driving substrate for an electro-optical device according to claim 44, wherein the pixel electrode is provided for a reflective or transmissive display unit. 78. The driving substrate for an electro-optical device according to claim 44, wherein the display section has a laminated structure of the pixel electrode and a color filter layer. 79. When the pixel electrode is a reflective electrode, irregularities are formed on the resin film, and the pixel electrode is provided thereon. When the pixel electrode is a transparent electrode, the surface is formed by a transparent flattening film. The driving substrate for an electro-optical device according to claim 44, wherein the driving substrate is flattened, and the pixel electrode is provided on the flattened surface. 80. The drive substrate for an electro-optical device according to claim 50, wherein the display section emits light or modulates light when driven by the switching element. 81. The driving substrate for an electro-optical device according to claim 50, wherein the plurality of pixel electrodes are arranged in a matrix on the display section, and the switching element is connected to each of the pixel electrodes. 82. The driving substrate for an electro-optical device according to claim 44, configured as a liquid crystal display device, an electroluminescence display device, a field emission display device, a light emitting polymer display device, a light emitting diode display device, or the like. 83. The driving substrate for an electro-optical device according to claim 43, wherein a control unit for controlling the operation of the peripheral driving circuit unit and / or the display unit is provided on the substrate. 84. The electro-optical device according to claim 83, wherein the control unit is a system-on-panel integrally formed with a so-called computer system, which is configured by a CPU, a memory, or a system LSI in which these are mixed. Drive board. 85. A display section on which pixel electrodes are arranged, and a peripheral driver circuit section arranged around the display section are provided on a first substrate, and the first substrate, the second substrate, A method of manufacturing an electro-optical device having a predetermined optical material interposed therebetween, wherein a step of forming a gate portion comprising a gate electrode and a gate insulating film on one surface of the first substrate; Forming a material layer having good lattice matching with the single crystal semiconductor on the one surface of the one substrate; and forming a semiconductor film made of a semiconductor and tin or lead or an alloy of tin and lead on the material layer. Forming a low-melting-point metal layer, or forming a low-melting-point metal layer comprising a semiconductor-containing tin or lead or an alloy of tin and lead; and heat-treating the semiconductor into a low-melting-point metal layer. Dissolving the semiconductor; After cooling, a step of heteroepitaxially growing the semiconductor using the substance layer as a seed by a cooling treatment to deposit a single crystal semiconductor layer; and performing a predetermined treatment on the single crystal semiconductor layer to form a channel region, a source region, and a drain. Forming a region, and forming a bottom-gate first thin film transistor having the gate portion below the channel region and forming at least a part of the peripheral driver circuit portion. A method for manufacturing an electro-optical device. 86. The method according to claim 85, wherein the film made of the semiconductor is amorphous silicon or polycrystalline silicon, and the single crystal semiconductor layer is a single crystal silicon layer. 87. The electro-optical device according to claim 86, wherein an impurity type and / or a concentration of the semiconductor film obtained by mixing an N-type or P-type carrier impurity during the formation of the semiconductor are controlled. Production method. 88. A film made of amorphous silicon or polycrystalline silicon is formed by a low-temperature film forming technique, and the low-melting-point metal layer is provided above or below the film, or the low-melting-point metal containing the semiconductor is formed. 89. The method of manufacturing an electro-optical device according to claim 86, wherein a layer is provided, and thereafter, the heat treatment and the cooling treatment are performed. 89. The specific resistance of the single crystal semiconductor layer is adjusted by mixing an N-type or P-type carrier impurity into the single crystal semiconductor layer before performing the predetermined treatment on the single crystal semiconductor layer. A method for manufacturing an electro-optical device. 90. An insulating substrate as the first substrate, wherein the material layer is sapphire, spinel structure, calcium fluoride, strontium fluoride, barium fluoride,
89. The method of manufacturing an electro-optical device according to claim 86, wherein the method is formed of a material selected from the group consisting of boron phosphide, yttrium oxide, and zirconia. 91. The method according to claim 86, wherein a diffusion barrier layer is formed on the first substrate, and the single crystal semiconductor layer is formed thereon. 92. In the peripheral driver circuit portion, in addition to the first thin film transistor, a polycrystalline or amorphous silicon layer is used as a channel region, and a top gate type and a bottom type having a gate portion above and / or below the channel region. 91. The manufacturing of the electro-optical device according to claim 86, wherein a gate, a dual-gate thin film transistor, or a diode, a resistor, a capacitance, an inductance element, or the like using the single crystal silicon layer, the polycrystal silicon layer, or the amorphous silicon layer is provided. Method. 93. The method according to claim 86, wherein a switching element for switching the pixel electrode is provided on the first substrate in the display unit. 94. The electricity according to claim 93, wherein a second thin film transistor of a top gate type, a bottom gate type, or a dual gate type having a gate portion above and / or below a channel region is formed as the switching element. A method for manufacturing an optical device. 95. When the second thin film transistor is a bottom gate type or a dual gate type, a lower gate electrode made of a heat-resistant material is provided below the channel region, and a gate insulating film is formed on the gate electrode. 95. The method of manufacturing an electro-optical device according to claim 94, wherein after forming the lower gate portion, the second thin film transistor is formed through steps common to the first thin film transistor including the step of forming the material layer. 96. After forming the single-crystal semiconductor layer on the lower gate portion, an N-type or P-type carrier impurity is introduced into the single-crystal semiconductor layer to form source and drain regions, and then activated. The method for manufacturing an electro-optical device according to claim 95, wherein the process is performed. 97. After the formation of the single-crystal semiconductor layer, source and drain regions of the first and second thin film transistors are formed by ion implantation of the impurity using a resist as a mask, and the activation is performed after the ion implantation. The method of manufacturing an electro-optical device according to claim 96, wherein a gate electrode of the first thin film transistor is formed after forming the gate insulating film. 98. In the case where the second thin film transistor is a top gate type, after forming the single crystal semiconductor layer, each source and drain region of the second thin film transistor is formed by ion implantation of impurities using a resist as a mask. The method for manufacturing an electro-optical device according to claim 94, wherein an activation process is performed after the ion implantation, and thereafter, a gate portion including a gate insulating film and a gate electrode of the second thin film transistor is formed. 99. In the case where the second thin film transistor is a top gate type, after forming the single crystal semiconductor layer, a gate insulating film of each of the first and second thin film transistors and a gate electrode made of a heat-resistant material are formed. Forming respective gate portions by using the gate portions as masks, forming source and drain regions of the first and second thin film transistors by ion implantation of impurity elements, and performing an activation process after the ion implantation. Item 90. The method for manufacturing an electro-optical device according to Item 94. 100. The method of manufacturing an electro-optical device according to claim 94, wherein n-channel, p-channel, or complementary insulated gate field-effect transistors are configured as the thin film transistors of the peripheral driver circuit section and the display section. . 101. A pair of a complementary type and an n-channel type, and a complementary type and a p-type
A pair of channel type, or complementary type, n-channel type and p
The method for manufacturing an electro-optical device according to claim 100, wherein the electro-optical device is formed as a pair with a channel type. 102. At least a part of the thin film transistor in the peripheral driver circuit portion and / or the display portion has an LDD structure, and the LDD structure is a single type having an LDD portion between a gate and a source or a drain, or a gate and The method of manufacturing an electro-optical device according to claim 95, wherein the electro-optical device is of a double type having an LDD portion between the source and the drain. 103. The electro-optical device according to claim 102, wherein a resist mask used for forming the LDD structure is left, and ion implantation for forming a source region and a drain region is performed using a resist mask covering the resist mask. Manufacturing method. 104. A single crystal, polycrystal, or amorphous silicon layer is formed on one surface of the first substrate, and the single crystal, polycrystal, or amorphous silicon layer is used as a channel region, a source region, and a drain region. The method for manufacturing an electro-optical device according to claim 100, wherein the second thin film transistor having a gate portion above and / or below the second thin film transistor is formed. 105. When the thin film transistor of the peripheral driver circuit portion is the first thin film transistor of an n-channel type, a p-channel type, or a complementary type, and the thin film transistor of the display portion is a single-crystal silicon layer in a channel region, n A channel type, a p-channel type, or a complementary type; an n-channel type, a p-channel type, or a complementary type when a polycrystalline silicon layer is used as a channel region; and an n-channel type or a p-channel when an amorphous silicon layer is used as a channel region. 105. The method for manufacturing an electro-optical device according to claim 104, wherein the method is a mold or a complementary mold. 106. A step is formed on the first substrate and / or a film thereon, the material layer is formed on the first substrate having the step formed thereon, and the single crystal semiconductor is formed on the material layer. The method for manufacturing an electro-optical device according to claim 86, wherein the layer is formed. 107. The step is formed as a concave portion whose side surface is perpendicular to the bottom surface or inclined toward the lower end in the cross section, and the step is formed together with the material layer as a seed during epitaxial growth of the single crystal semiconductor layer. 107. The method of manufacturing an electro-optical device according to claim 106. 108. A step is formed on the first substrate and / or a film thereon, the material layer is formed on the first substrate having the step formed thereon, and the single crystal semiconductor is formed on the material layer. The method for manufacturing an electro-optical device according to claim 86, wherein the layer is formed. 109. The method according to claim 10, wherein the first thin film transistor is provided in and / or outside a substrate recess due to the step formed in the first substrate and / or a film thereon.
9. The method for manufacturing an electro-optical device according to item 8. 110. The method of manufacturing an electro-optical device according to claim 108, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the thin film transistor as the active element. Method. 111. The method of manufacturing an electro-optical device according to claim 86, wherein a step is formed in the material layer, and the single crystal semiconductor layer is formed on the material layer including the step. 112. The step is formed as a recess whose side surface is perpendicular to the bottom surface or inclined toward the lower end in the cross section, and the step is formed together with the material layer as a seed during epitaxial growth of the single crystal semiconductor layer. The method for manufacturing an electro-optical device according to claim 111, wherein 113. The method of manufacturing an electro-optical device according to claim 86, wherein a step is formed in the material layer, and the single crystal semiconductor layer is formed on the material layer including the step. 114. The first thin film transistor is provided inside and / or outside a substrate recess due to the step formed on the first substrate and / or a film thereon.
4. The method for manufacturing an electro-optical device according to item 3. 115. The method of manufacturing an electro-optical device according to claim 111, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the thin film transistor as the active element. Method. 116. A step is formed on the first substrate and / or a film thereon, and a single crystal, polycrystalline, or amorphous silicon layer is formed on the first substrate having the step formed thereon. 95. The electric device according to claim 94, wherein the second thin film transistor having a gate portion above and / or below the channel region is formed by using a crystal, polycrystalline, or amorphous silicon layer as a channel region, a source region, and a drain region. A method for manufacturing an optical device. 117. The step is formed as a concave portion whose side surface is perpendicular to the bottom surface or inclined toward the lower end in the cross section, and the step is formed together with the material layer as a seed during epitaxial growth of the single crystal semiconductor layer. 117. The method for manufacturing an electro-optical device according to claim 116, wherein 118. The method of manufacturing an electro-optical device according to claim 116, wherein a source or drain region of said first and / or second thin film transistor is formed on a region including said step. 119. The method according to claim 11, wherein the second thin film transistor is provided in and / or outside a substrate recess formed by the step formed on the first substrate and / or a film thereon.
7. The method for manufacturing an electro-optical device according to item 6. 120. The electro-optical device according to claim 116, wherein the step is formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor. Manufacturing method. 121. The method of manufacturing an electro-optical device according to claim 116, wherein the gate electrode under the single crystal, polycrystal, or amorphous silicon layer has a trapezoidal shape at a side end thereof. 122. The method of manufacturing an electro-optical device according to claim 116, wherein a diffusion barrier layer is provided between said first substrate and said single crystal, polycrystal or amorphous silicon layer. 123. The method according to claim 86, wherein the first substrate is a glass substrate or a heat-resistant resin substrate. 124. The method according to claim 86, wherein the first substrate is optically opaque or transparent. 125. The method of manufacturing an electro-optical device according to claim 86, wherein the pixel electrode is provided for a reflective or transmissive display unit. 126. The method of manufacturing an electro-optical device according to claim 86, wherein a laminated structure of the pixel electrode and a color filter layer is provided in the display unit. 127. When the pixel electrode is a reflective electrode, an unevenness is formed on a resin film, and a pixel electrode is provided thereon. When the pixel electrode is a transparent electrode, the surface is flattened by a transparent flattening film. 89. The method of manufacturing an electro-optical device according to claim 86, wherein the pixel electrode is provided on the flattened surface. 128. The method of manufacturing an electro-optical device according to claim 93, wherein said display section is configured to emit light or adjust light by being driven by said switching element. 129. The method according to claim 93, wherein the plurality of pixel electrodes are arranged in a matrix on the display section, and the switching element is connected to each of the pixel electrodes. 130. The method of manufacturing an electro-optical device according to claim 86, wherein the method is configured as a liquid crystal display device, an electroluminescence display device, a field emission display device, a light emitting polymer display device, a light emitting diode display device, or the like. 131. A step of performing a predetermined process on the single crystal semiconductor layer to form an element for constituting a control unit for controlling an operation of the peripheral driver circuit unit and / or the display unit. The manufacturing method of the electro-optical device according to the above. 132. An element for constituting the control unit is a cMOSTFT, an nMOSTFT, or a pMOSTF.
138. The method for manufacturing an electro-optical device according to claim 137, comprising an active element such as T and a diode, and a passive element such as a resistor, a capacitor, and an inductance. 133. A method of manufacturing a driving substrate for an electro-optical device, comprising: a display portion on which a pixel electrode is disposed; and a peripheral driving circuit portion disposed around the display portion on the substrate. Forming a gate portion comprising a gate electrode and a gate insulating film on one surface of the driving substrate; and forming a material layer having a good lattice match with a single crystal semiconductor on the one surface of the driving substrate for the substrate. And forming a semiconductor film made of a semiconductor and a low melting point metal layer made of tin or lead or an alloy of tin and lead on the material layer, or tin or lead containing a semiconductor. Forming a low-melting-point metal layer made of an alloy of tin and lead, dissolving the semiconductor in the low-melting-point metal layer by heat treatment, dissolving the semiconductor in the low-melting-point metal layer, and then cooling. The material layer A step of heteroepitaxially growing the semiconductor as a seed to deposit a single crystal semiconductor layer; a step of performing a predetermined treatment on the single crystal semiconductor layer to form a channel region, a source region and a drain region; Forming a first bottom-gate thin film transistor having the gate portion and constituting at least a part of the peripheral drive circuit portion, the method of manufacturing a drive substrate for an electro-optical device, the method comprising: . 134. The method of manufacturing a driving substrate for an electro-optical device according to claim 133, wherein the film made of the semiconductor is amorphous silicon or polycrystalline silicon, and the single crystal semiconductor layer is a single crystal silicon layer. 135. An impurity species and / or a concentration of the semiconductor film obtained by mixing an N-type or P-type carrier impurity during the formation of the semiconductor.
A method for manufacturing a drive substrate for an electro-optical device according to claim 134. 136. A film made of amorphous silicon or polycrystalline silicon is formed by a low-temperature film forming technique, and the low-melting-point metal layer is provided above or below the film, or the low-melting-point metal containing the semiconductor is formed. The method for manufacturing a driving substrate for an electro-optical device according to claim 134, wherein a layer is provided, and thereafter, the heat treatment and the cooling treatment are performed. 137. An N-type or P-type semiconductor layer is formed on the single crystal semiconductor layer before the predetermined treatment is performed on the single crystal semiconductor layer.
Adjust the specific resistance by mixing the carrier impurities of the mold,
A method for manufacturing a drive substrate for an electro-optical device according to claim 134. 138. An insulating substrate is used as a driving substrate for the substrate, and the material layer is made of sapphire, a spinel structure,
2. A material formed from a substance selected from the group consisting of calcium fluoride, strontium fluoride, barium fluoride, boron phosphide, yttrium oxide and zirconia.
35. The method for manufacturing a drive substrate for an electro-optical device according to claim 34. 139. The method for manufacturing a driving substrate for an electro-optical device according to claim 134, wherein a diffusion barrier layer is formed on the driving substrate for the substrate, and the single crystal semiconductor layer is formed thereon. 140. In the peripheral driver circuit portion, in addition to the first thin film transistor, a polycrystalline or amorphous silicon layer is used as a channel region, and a top gate type and a bottom portion having a gate portion above and / or below the channel region. 134. An electro-optical device according to claim 134, wherein a gate type or dual gate type thin film transistor, or a diode using the single crystal silicon layer or the polycrystalline silicon layer or the amorphous silicon layer, a resistor, a capacitance, an inductance element, or the like is provided. A method for manufacturing a drive substrate. 141. The method according to claim 134, wherein a switching element for switching the pixel electrode is provided on the driving substrate for the substrate in the display unit. 142. The electric device according to claim 141, wherein a second thin film transistor of a top gate type, a bottom gate type, or a dual gate type having a gate portion above and / or below a channel region is formed as the switching element. A method for manufacturing a drive substrate for an optical device. 143. When the second thin film transistor is a bottom gate type or a dual gate type, a lower gate electrode made of a heat-resistant material is provided below the channel region, and a gate insulating film is formed on the gate electrode. 142. The method of claim 142, wherein after forming the lower gate portion by performing a process common to the first thin film transistor including a process of forming the material layer, the second thin film transistor is formed.
A method for manufacturing a driving substrate for an electro-optical device according to the above. 144. After forming the single-crystal semiconductor layer on the lower gate portion, an N-type or P-type carrier impurity is introduced into the single-crystal semiconductor layer to form source and drain regions, and then activated. 143. Perform processing.
A method for manufacturing a driving substrate for an electro-optical device according to the above. 145. After the formation of the single crystal semiconductor layer, source and drain regions of the first and second thin film transistors are formed by ion implantation of the impurity using a resist as a mask, and the activation is performed after the ion implantation. 153. The method according to claim 144, wherein a gate electrode of the first thin film transistor is formed after forming the gate insulating film. 146. In the case where the second thin film transistor is a top gate type, after forming the single crystal semiconductor layer, each source and drain region of the second thin film transistor is formed by ion implantation of impurities using a resist as a mask. 142. The method of manufacturing a driving substrate for an electro-optical device according to claim 142, wherein an activation process is performed after the ion implantation, and thereafter, a gate portion including a gate insulating film and a gate electrode of the second thin film transistor is formed. 147. In the case where the second thin film transistor is a top-gate type, after forming the single crystal semiconductor layer, a gate insulating film of each of the first and second thin film transistors and a gate electrode made of a heat-resistant material are formed. Forming respective gate portions by using the gate portions as masks, forming source and drain regions of the first and second thin film transistors by ion implantation of impurity elements, and performing an activation process after the ion implantation. 142. A method for manufacturing a drive substrate for an electro-optical device according to item 142. 148. An electro-optical device drive according to claim 142, wherein an n-channel, p-channel, or complementary insulated gate field effect transistor is configured as the thin film transistor of the peripheral driver circuit portion and the display portion. Substrate manufacturing method. 149. The thin film transistor of the peripheral drive circuit section is a set of a complementary type and an n-channel type, and
A pair of channel type, or complementary type, n-channel type and p
149. The method for manufacturing a driving substrate for an electro-optical device according to claim 148, wherein the driving substrate is formed as a pair with a channel type. 150. At least a part of the thin film transistor of the peripheral driver circuit portion and / or the display portion has an LDD structure, and the LDD structure is a single type having an LDD portion between a gate and a source or a drain, or a gate type. 144. The method of manufacturing a drive substrate for an electro-optical device according to claim 143, wherein the drive substrate is a double type having an LDD portion between the source and the drain. 151. The electro-optical device according to claim 150, wherein a resist mask used for forming the LDD structure is left, and ion implantation for forming a source region and a drain region is performed using a resist mask covering the resist mask. Of manufacturing a driving substrate for a semiconductor device. 152. A single crystal, polycrystal, or amorphous silicon layer is formed on one surface of a driving substrate for the substrate, and the single crystal, polycrystal, or amorphous silicon layer is formed in a channel region, a source region, and a drain region. age,
148. The method for manufacturing a driving substrate for an electro-optical device according to claim 148, wherein the second thin film transistor having a gate portion at an upper portion and / or a lower portion thereof is formed. 153. The thin film transistor of the peripheral driver circuit portion is the n-channel, p-channel, or complementary first thin film transistor, and the thin film transistor of the display portion is n when a single crystal silicon layer is used as a channel region. A channel type, a p-channel type, or a complementary type; an n-channel type, a p-channel type, or a complementary type when a polycrystalline silicon layer is used as a channel region; and an n-channel type or a p-channel when an amorphous silicon layer is used as a channel region. 153. The method for manufacturing a drive substrate for an electro-optical device according to claim 152, wherein the drive substrate is a mold or a complementary mold. 154. A step is formed on the driving substrate for the substrate and / or a film thereon, the material layer is formed on the driving substrate for the substrate on which the step is formed, and the unit layer is formed on the material layer. The method for manufacturing a driving substrate for an electro-optical device according to claim 134, wherein a crystalline semiconductor layer is formed. 155. In the cross section, the step is formed as a concave portion such that the side surface is perpendicular to the bottom surface or inclined toward the lower end, and the step is formed together with the material layer as a seed during epitaxial growth of the single crystal semiconductor layer. 157. The method for manufacturing a drive substrate for an electro-optical device according to claim 154. 156. A step is formed in the driving substrate for the substrate and / or a film thereon, and the material layer is formed on the driving substrate for the substrate on which the step is formed, and the unit layer is formed on the material layer. The method for manufacturing a driving substrate for an electro-optical device according to claim 134, wherein a crystalline semiconductor layer is formed. 157. The electro-optical device according to claim 156, wherein the first thin film transistor is provided in and / or outside a substrate concave portion due to the step formed in the driving substrate for the substrate and / or a film thereon. Of manufacturing a driving substrate for a semiconductor device 158. The electro-optical device according to claim 156, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the thin film transistor as the active element. A method for manufacturing a drive substrate. 159. The method for manufacturing a driving substrate for an electro-optical device according to claim 134, wherein a step is formed in said material layer, and said single crystal semiconductor layer is formed on said material layer including said step. 160. The step is formed as a concave portion whose side surface is perpendicular to the bottom surface or inclined toward the lower end in the cross section, and the step is formed together with the material layer as a seed during epitaxial growth of the single crystal semiconductor layer. 160. The method for manufacturing a drive substrate for an electro-optical device according to claim 159. 161. The method for manufacturing a driving substrate for an electro-optical device according to claim 134, wherein a step is formed in said material layer, and said single crystal semiconductor layer is formed on said material layer including said step. 162. The electro-optical device according to claim 161, wherein the first thin film transistor is provided in and / or outside a substrate recess formed by the step formed on the driving substrate for the substrate and / or a film thereon. Of manufacturing a driving substrate for a semiconductor device. 163. The electro-optical device according to claim 159, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the thin film transistor as the active element. A method for manufacturing a drive substrate. 164. A step is formed on the driving substrate for the substrate and / or a film thereon, and a single crystal, polycrystalline, or amorphous silicon layer is formed on the driving substrate for the substrate having the step formed thereon. 144. The second thin film transistor having a gate portion above and / or below the channel region, wherein the single crystal, polycrystalline, or amorphous silicon layer is used as a channel region, a source region, and a drain region. A method for manufacturing a drive substrate for an electro-optical device. 165. In the cross section, the step is formed as a concave part whose side surface is perpendicular to the bottom surface or inclined toward the lower end, and the step is formed together with the material layer as a seed during epitaxial growth of the single crystal semiconductor layer. 164. The method for manufacturing a drive substrate for an electro-optical device according to claim 164. 166. The method of manufacturing a driving substrate for an electro-optical device according to claim 164, wherein a source or drain region of the first and / or second thin film transistor is formed on a region including the step. 167. The electro-optical device according to claim 164, wherein the second thin film transistor is provided in and / or outside a substrate recess formed by the step formed on the driving substrate for the substrate and / or a film thereon. Of manufacturing a driving substrate for a semiconductor device 168. The electro-optical device according to claim 164, wherein the step is formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor. Of manufacturing a driving substrate for a semiconductor device. 169. The method according to claim 164, wherein the gate electrode under the single crystal, polycrystal, or amorphous silicon layer is trapezoidal at a side end thereof. 170. The method for manufacturing a driving substrate for an electro-optical device according to claim 164, wherein a diffusion barrier layer is provided between the driving substrate for the substrate and the single crystal, polycrystalline, or amorphous silicon layer. 171. The method for manufacturing a driving substrate for an electro-optical device according to claim 134, wherein the driving substrate for the substrate is a glass substrate or a heat-resistant resin substrate. 172. The method for manufacturing a driving substrate for an electro-optical device according to claim 134, wherein the driving substrate for the substrate is made optically opaque or transparent. 173. The method for manufacturing a driving substrate for an electro-optical device according to claim 134, wherein said pixel electrode is provided for a reflective or transmissive display portion. 174. The method for manufacturing a driving substrate for an electro-optical device according to claim 134, wherein a laminated structure of said pixel electrode and a color filter layer is provided in said display section. 175. When the pixel electrode is a reflective electrode, an unevenness is formed on a resin film, and a pixel electrode is provided thereon. When the pixel electrode is a transparent electrode, the surface is flattened by a transparent flattening film. The method for manufacturing a driving substrate for an electro-optical device according to claim 134, wherein the pixel electrode is provided on the flattened surface. 176. The method of manufacturing a driving substrate for an electro-optical device according to claim 141, wherein said display unit is configured to emit light or adjust light by being driven by said switching element. 177. The method for manufacturing a driving substrate for an electro-optical device according to claim 141, wherein a plurality of said pixel electrodes are arranged in a matrix on said display section, and said switching element is connected to each of said pixel electrodes. . 178. The method for manufacturing a drive substrate for an electro-optical device according to claim 134, wherein the method is configured as a liquid crystal display, an electroluminescence display, a field emission display, a light emitting polymer display, a light emitting diode display, or the like. . 179. A step of performing a predetermined process on the single crystal semiconductor layer to form an element for constituting a control unit for controlling an operation of the peripheral driver circuit unit and / or the display unit. A method for manufacturing a driving substrate for an electro-optical device according to the above. 180. An element for forming the control unit is a cMOSTFT, an nMOSTFT, or a pMOSTF.
179. The method for manufacturing a drive substrate for an electro-optical device according to claim 179, comprising an active element such as T or a diode, or a passive element such as a resistor, a capacitor, or an inductance.