JP4366731B2 - Method for manufacturing electro-optical device and method for manufacturing drive substrate for electro-optical device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing an electro-optical device and a method of manufacturing a driving substrate for an electro-optical device, and more particularly, a top-gate thin-film insulating gate type using a single crystal silicon layer grown on a insulating substrate as a grapho-epitaxial film as an active region. The present invention relates to a method suitable for a field effect transistor (hereinafter referred to as a top gate type MOSTFT. Note that a top gate type includes a stagger type or a coplanar type) and a liquid crystal display device having a passive region.
[0002]
[Prior art]
As an active matrix type liquid crystal display device, a display unit using amorphous silicon as a TFT and an IC for an external drive circuit, or a display unit and a drive circuit using polycrystalline silicon by a solid phase growth method as a TFT Are known (Japanese Patent Laid-Open No. 6-242433), an integrated type of a display unit and a drive circuit using polycrystalline silicon subjected to excimer laser annealing in a TFT (Japanese Patent Laid-Open No. 7-13030), and the like. Yes.
[0003]
[Problems to be solved by the invention]
However, the above-described conventional amorphous silicon TFT has good productivity, but the electron mobility is 0.5 to 1.0 cm. ² Since it is as low as around / v · sec, a p-channel MOSTFT (hereinafter referred to as pMOSTFT) cannot be formed. Accordingly, since the peripheral driving unit using the pMOS TFT cannot be formed on the same glass substrate as the display unit, the driver IC is externally mounted and mounted by the TAB method, so that it is difficult to reduce the cost. For this reason, there is a limit to high definition. Furthermore, the electron mobility is 0.5 to 1.0 cm. ² Since it is as low as around / v · sec, sufficient on-current cannot be obtained, and when used in a display portion, the transistor size inevitably increases, which is disadvantageous for the high aperture ratio of the pixel.
[0004]
The electron mobility of the conventional polycrystalline silicon TFT described above is 70 to 100 cm. ² Since it can cope with high definition at / v · sec, LCD (Liquid Crystal Display) using a driver-integrated polycrystalline silicon TFT has recently attracted attention. However, in the case of a large LCD of 15 inches or more, the electron mobility of polycrystalline silicon is 70-100 cm. ² Since / v · sec, the drive capability is insufficient, and eventually an external drive circuit IC is required.
[0005]
In a TFT using polycrystalline silicon formed by solid phase growth, a gate SiO is formed by annealing at 600 ° C. or more for several tens of hours and thermal oxidation at about 1000 ° C. ₂ Therefore, it is necessary to employ a semiconductor manufacturing apparatus. Therefore, the wafer size of 8 to 12 inches φ is the limit, and it is necessary to employ high heat-resistant and expensive quartz glass, and it is difficult to reduce the cost. Therefore, it is limited to EVF and data / AV projector applications.
[0006]
Furthermore, in the conventional polycrystalline silicon TFT by excimer laser annealing described above, there are a number of problems such as excimer laser output stability, productivity, increase in device price due to increase in size, and yield / quality deterioration.
[0007]
In particular, when a large glass substrate of 1 m square or the like is used, the above-mentioned problems are expanded, and it is difficult to improve performance / quality and reduce costs.
[0008]
An object of the present invention is to form an active matrix substrate with a built-in high-performance driver by depositing a single crystal silicon thin film having a high electron / hole mobility at a relatively low temperature and uniformly, particularly in a peripheral drive circuit section. An electro-optical device such as a thin film semiconductor device for display used can be manufactured, and an n-channel MOS TFT (hereinafter referred to as an nMOS TFT) or an pMOS TFT having an LDD structure (Lightly doped drain structure) having high switching characteristics and low leakage current. Alternatively, a configuration in which a display unit of a complementary thin film insulated gate field effect transistor (hereinafter referred to as cMOSTFT) with high driving capability and a peripheral driving circuit made of cMOSTFT, nMOSTFT, pMOSTFT, or a mixture thereof is made possible. Realize high quality, high definition, narrow frame, high efficiency, large screen display panel It is possible to use even a large glass substrate with a relatively low strain point, high productivity, no need for expensive manufacturing equipment, cost reduction, and easy threshold adjustment. Therefore, it is to enable high speed operation and large screen by reducing resistance.
[0009]
[Means for Solving the Problems]
That is, according to the present invention, a display unit in which pixel electrodes (for example, a plurality of pixel electrodes arranged in a matrix: the same applies hereinafter) and a peripheral drive circuit unit disposed in the periphery of the display unit are provided in a first manner. A predetermined optical material such as a liquid crystal between the first substrate and the second substrate (i.e., the same applies hereinafter) between the first substrate and the second substrate (i.e., the same applies hereinafter). In each of the manufacturing methods of the electro-optical device and the driving substrate for the electro-optical device,
Forming a step on one surface of the first substrate;
The low melting point gold described later containing silicon on the first substrate including the recess due to the step.
Forming a melt layer of the genus by coating;
Next, the molten liquid layer is subjected to a cooling treatment (preferably a slow cooling treatment). silicon The above
Grapho-epitaxial growth using a step as a seed to deposit a single crystal silicon layer
Process,
This single crystal silicon At least one of active and passive elements by applying a predetermined treatment to the layer
Forming an active element (for example, the single crystal silicon layer is formed into a channel region, a source
A gate insulating film and a gate electrode on the channel region;
And a top gate type thin film transistor having a source and drain electrodes.
A step of forming a transistor (particularly MOSTFT: hereinafter the same) as an active element)
And an electro-optical device, and a method of manufacturing a drive substrate for the electro-optical device. In the present invention, the active element is a concept including an element such as a thin film transistor and other diodes, and the passive element is a concept including a resistor (hereinafter the same). Typical examples of the thin film transistor include a field effect transistor (FET) (which can be either a MOS type or a junction type), and a bipolar transistor, but the present invention is applicable to any transistor. Yes (hereinafter the same). The passive element is a concept including resistance, inductance, capacitance, and the like. For example, the passive element is a single crystal silicon layer (electrode) in which a high dielectric film such as silicon nitride (hereinafter referred to as SiN) is reduced in resistance. There is a capacitance formed by sandwiching.
[0010]
According to the present invention, silicon Such Dissolved Such as indium Low melting point metal melt Apply this melt Then, a single crystal semiconductor thin film such as a single crystal silicon thin film is formed by graphoepitaxial growth using the step formed on the substrate as a seed, and this is formed into a top gate type MOS TFT or a display of a peripheral drive circuit of a drive substrate such as an active matrix substrate. Since it is used for at least an active element such as an active element such as a top gate type MOSTFT of a peripheral driving circuit of an electro-optical device such as a part-peripheral driving circuit integrated type LCD, or a passive element such as resistance, inductance, capacitance, etc. The remarkable effects shown in the following (A) to (F) can be obtained.
[0011]
(A) A step having a predetermined shape / dimension is formed on the substrate, and the bottom corner of the step (bottom angle) is used as a seed for graphoepitaxy growth to be 540 cm. ² Since a single crystal semiconductor layer such as a single crystal silicon thin film having a high electron mobility of / v · sec or more can be obtained, an electro-optical device such as a display thin film semiconductor device with a built-in high performance driver can be manufactured. In this case, it is preferable that the step is formed as a concave portion whose side surface is perpendicular to the bottom surface in the cross section or is inclined so as to form a base angle of preferably 90 ° or less toward the lower end side.
[0012]
(B) In particular, this single crystal silicon thin film exhibits high electron and hole mobility comparable to that of a single crystal silicon substrate as compared with the conventional amorphous silicon thin film and polycrystalline silicon thin film. The MOSTFT has a display portion composed of an nMOS, pMOSTFT, or cMOSTFT having high switching characteristics (preferably, an LDD (Lightly doped drain) structure that reduces the electric field strength and reduces the leakage current), and a cMOS with high driving capability, or A configuration in which an nMOS, a pMOS TFT, or a peripheral driving circuit unit made of a mixture of these is integrated is possible, and a display panel with high image quality, high definition, narrow frame, high efficiency, and a large screen is realized. In particular, it is difficult to form a pMOS TFT with high hole mobility as a TFT for LCD with polycrystalline silicon, but the single crystal silicon thin film according to the present invention exhibits sufficiently high mobility even with holes. A peripheral drive circuit that can be driven alone or in combination with each other can be manufactured, and a panel in which this is integrated with an nMOS, pMOS, or cMOS LDD structure TFT for display can be realized. In the case of a small to medium panel, there is a possibility that one of a pair of peripheral vertical drive circuits can be omitted.
[0013]
(C) Since the low-melting-point metal melt is prepared at a low temperature (for example, 350 ° C.) and can be formed by coating on a substrate heated to a temperature slightly higher than that, it can be formed at a relatively low temperature (for example, 350 to 400 ° C.), a silicon single crystal film can be formed uniformly. Therefore, a glass substrate or a heat-resistant organic substrate having a relatively low strain point can be easily obtained, and a substrate having good physical properties at a low cost can be used, and the size of the substrate can be increased.
[0014]
(D) Since there is no need for long-term annealing (about 600 ° C., several tens of hours) or excimer laser annealing as in the case of the solid phase growth method, productivity is high and expensive manufacturing equipment is not required. Cost reduction is possible.
[0015]
(E) In this grapho epitaxial growth, a single crystal silicon thin film having a wide range of P-type impurity concentration and high mobility can be easily obtained by adjusting the heating temperature of the substrate, the composition ratio of the melt, the melt temperature, the cooling rate, etc. Therefore, Vth (threshold) adjustment is easy, and high-speed operation and a large screen can be achieved by reducing resistance.
[0016]
(F) When a silicon-containing low-melting-point metal melt layer is formed, growth can be achieved by doping a suitable amount of a Group 3 or Group 5 impurity element (boron, phosphorus, antimony, arsenic, bismuth, aluminum, etc.) separately. The impurity species and / or the concentration of the single crystal silicon epitaxial growth layer to be formed, that is, the P-type / N-type conductivity type and / or the carrier concentration can be arbitrarily controlled.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
In the present invention, the step is formed as a concave portion such that the side surface is perpendicular to the bottom surface in the cross section or is inclined so as to form a base angle of preferably 90 ° or less toward the lower end side. It is preferable that the barrier is formed on a film such as SiN (or both of them), and this step serves as a seed for grapho epitaxial growth of the single crystal silicon layer. The step is preferably formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the active element, for example, a thin film transistor. Further, it is preferable that the passive element, for example, it is formed along at least one side of an element region where a resistor is formed.
[0018]
In this case, the first thin film transistor such as the MOSTFT may be provided in the concave portion of the substrate due to the step, but may be provided on the substrate outside the concave portion or both of them.
[0019]
The step is formed by dry etching such as reactive ion etching, and a low-melting-point metal melt containing 2.0% to 0.005%, for example, 1% by weight of silicon is applied to a heated insulating substrate. Then, after holding for a predetermined time (several minutes to several tens of minutes), the cooling process is preferably performed. Thereby, a single crystal silicon film having a thickness of several μm to 0.005 μm, for example, 1 μm can be obtained.
[0020]
Further, an insulating substrate such as a glass substrate or a heat-resistant organic substrate is used as the substrate, and at least one selected from the group consisting of indium, gallium, tin, bismuth, lead, zinc, antimony and aluminum as the low melting point metal. Can be used.
[0021]
In this case, when using indium as the low melting point metal, the melt is applied to the insulating substrate heated to 850 to 1100 ° C., preferably 900 to 950 ° C., and indium gallium or gallium is used as the low melting point metal. When used, the melt can be applied to the insulating substrate heated to 300 to 1100 ° C., desirably 350 to 600 ° C. or 400 to 1100 ° C., desirably 420 to 600 ° C. In addition to a method of heating the entire substrate uniformly using an electric furnace, a lamp, or the like, the substrate can be heated by a method of locally heating only a predetermined place with an optical laser, an electron beam, or the like.
[0022]
As is apparent from the state diagram shown in FIG. 10, the melting point of the low melting point metal containing silicon is lowered according to the proportion of the low melting point metal. When indium is used, an indium melt layer containing silicon (for example, containing 1% by weight) is formed at a substrate temperature of 850 to 1100 ° C. Quartz plate glass can be used as the substrate up to about 1100 ° C. Up to 850 ° C., glass having lower heat resistance than that, for example, crystallized glass can be used. Even when gallium is used, a gallium melt layer containing silicon (for example, containing 1% by weight) can be formed at a substrate temperature of 400 to 1100 ° C. for the same reason as described above.
[0023]
In the latter case (indium gallium silicon or gallium silicon), a glass substrate or a heat-resistant organic substrate having a relatively low strain point can be used as the substrate. ² Although a semiconductor crystal layer can be formed on the above, such a substrate is inexpensive, can be easily thinned, and can produce a long rolled glass plate or a heat-resistant organic substrate. By using this, it is possible to continuously or discontinuously produce a single crystal silicon thin film by graphoepitaxial growth on a long rolled glass plate or a heat-resistant organic substrate by the above method.
[0024]
In the above-mentioned melt application method, the glass substrate is gradually cooled after being held for a certain time (several minutes to several tens of minutes). In addition, the glass substrate is immersed in the above solution and held for a certain time (several minutes to several tens of minutes). Then, a dipping method of gradually pulling up, or a floating method of slowly cooling by moving the molten liquid or the surface at an appropriate speed may be used. The thickness of the epitaxial growth layer and the carrier impurity concentration can be controlled by the composition, temperature, and pulling speed of the melt. The coating method, dipping method, floating method, etc. can process the substrate continuously or intermittently, so that mass productivity is improved.
[0025]
As described above, since the constituent elements easily diffuse into the upper layer of the glass having a low strain point from the inside of the glass, for the purpose of suppressing this, a thin film of the diffusion barrier layer (for example, silicon nitride: thickness 50 to About 200 nm) is preferable.
[0026]
After the single crystal silicon layer is deposited by graphoepitaxial growth using the step as a seed from the low melting point metal in which silicon is dissolved, the low melting point metal layer is dissolved and removed with hydrochloric acid or the like. After that, the single crystal silicon layer can be subjected to a predetermined treatment to produce an active element and a passive element.
[0027]
As described above, the low melting point metal thin film such as indium deposited on the single crystal silicon layer after cooling is dissolved and removed using hydrochloric acid or the like. ¹⁶ A semiconductor of a P-type single crystal silicon thin film is formed immediately after the production. This is therefore convenient for the fabrication of nMOS TFTs. However, since an N-type single crystal silicon thin film can be formed on the entire surface or selectively by ion-implanting an appropriate amount of N-type impurities such as phosphorus atoms, the pMOS TFT can also be formed. . For this reason, a cMOS TFT can also be produced. When forming a molten layer of a silicon-containing low-melting-point metal, if a suitable amount of a highly soluble group 3 or group 5 impurity element (boron, phosphorus, antimony, arsenic, gallium, bismuth, etc.) is doped separately, silicon grows. The impurity species and / or concentration of the epitaxial growth layer, that is, P-type / N-type and / or carrier concentration can be arbitrarily controlled.
[0028]
In this way, the single crystal silicon layer that is grapho epitaxially grown on the substrate is applied to the channel region, the source region, and the drain region of the top gate type MOS TFT constituting at least a part of the peripheral drive circuit, and the impurity species in each of these regions And / or its concentration can be controlled.
[0029]
The thin film transistors in the peripheral driver circuit portion and the display portion constitute an n-channel type, p-channel type or complementary type insulated gate field effect transistor. For example, a complementary type and an n-channel type, a complementary type and a p-channel type Or a pair of complementary type, n-channel type and p-channel type. Further, it is preferable that at least a part of the thin film transistor in the peripheral driver circuit portion and / or the display portion has an LDD (Lightly doped drain) structure. Note that the LDD structure may be provided not only between the gate and the drain but also between the gate and the source or between the gate and the source and between the gate and the drain (this is referred to as a double LDD).
[0030]
In particular, the MOSTFT preferably constitutes an nMOS, pMOS or cMOS LDD type TFT in the display section, and a cMOS, nMOS or pMOSTFT or a mixture thereof in the peripheral drive circuit section.
[0031]
The MOS TFT may be provided in the substrate recess due to the step and / or in the vicinity of the recess outside the substrate recess.
[0032]
In this case, a step is formed on one surface of the first substrate, a single crystal, polycrystalline, or amorphous silicon layer is formed on the substrate including the step, and the second thin film transistor is formed of the single crystal. Alternatively, a polycrystalline or amorphous silicon layer may be used as a channel region, a source region, and a drain region, and a top gate type, a bottom gate type, or a dual gate type having a gate portion above and / or below the channel region may be used. Also in this case, the step similar to the above is formed as a concave portion such that the side surface is perpendicular to the bottom surface in the cross section or is inclined so as to form a base angle of preferably 90 ° or less toward the lower end side. It becomes a seed for grapho epitaxial growth of the single crystal silicon layer.
[0033]
The second thin film transistor is provided in and / or outside the substrate recess due to the step formed on the first substrate and / or a film thereon. Similarly to the first thin film transistor, the second thin film transistor is simply formed by grapho epitaxial growth. The source, drain, and channel regions may be formed using a crystalline silicon layer.
[0034]
In the second thin film transistor, as described above, the group 3 or group 5 impurity species and / or the concentration of the single crystal, polycrystal, or amorphous silicon layer are controlled, or the step is the second step. The thin film transistor may be formed along at least one side of an element region formed by the channel region, the source region, and the drain region. The gate electrode under the single crystal, polycrystal or amorphous silicon layer is preferably trapezoidal at the side end. A diffusion barrier layer may be provided between the first substrate and the single crystal, polycrystalline or amorphous silicon layer.
[0035]
The source or drain electrode of the first and / or second thin film transistor may be formed on a region including the step.
[0036]
The first thin film transistor is at least a top gate type selected from a top gate type, a bottom gate type, and a dual gate type having a gate portion above and / or below a channel region, and a pixel in the display portion The switching element for switching the electrode may be the top gate type, the bottom gate type, or the dual gate type second thin film transistor.
[0037]
In this case, the gate electrode provided under the channel region is formed of a heat-resistant material, or the upper gate electrode of the second thin film transistor and the gate electrode of the first thin film transistor are formed of a common material. It's okay.
[0038]
In the peripheral driver circuit portion, in addition to the first thin film transistor, a polycrystalline or amorphous silicon layer is used as a channel region, and a top gate type, a bottom gate type or a dual gate having a gate portion above and / or below the channel region. A thin film transistor, or a diode, a resistor, a capacitance, an inductance element, or the like using the single crystal silicon layer, the polycrystalline silicon layer, or the amorphous silicon layer may be provided.
[0039]
The thin film transistors of the peripheral driver circuit unit and / or the display unit may be configured as a single gate or a multi gate.
[0040]
When the n or p channel type thin film transistor of the peripheral driving circuit unit and / or the display unit is a dual gate type, the upper or lower gate electrode is electrically opened or an arbitrary negative voltage (n channel type) Or a positive voltage (in the case of a p-channel type) is applied to operate as a bottom-gate or top-gate thin film transistor.
[0041]
The thin film transistor in the peripheral driver circuit portion is the first thin film transistor of n-channel type, p-channel type or complementary type, and the thin film transistor of the display portion is n-channel type, p. Channel type or complementary type, n channel type, p channel type or complementary type when the polycrystalline silicon layer is used as a channel region, n channel type, p channel type or complementary type when the amorphous silicon layer is used as a channel region It may be.
[0042]
In the present invention, after the single crystal silicon layer is deposited, an upper gate portion composed of a gate insulating film and a gate electrode is formed on the single crystal silicon layer, and the upper gate portion is used as a mask to form 3 The channel region, the source region, and the drain region may be formed by introducing a Group or Group 5 impurity element.
[0043]
Further, when the second thin film transistor is a bottom gate type or a dual gate type, a lower gate electrode made of a heat-resistant material is provided below the channel region, and a gate insulating film is formed on the gate electrode to form a lower portion. After the gate portion is formed, the second thin film transistor can be formed through a process common to the first thin film transistor including the step of forming the step. In this case, the upper gate electrode of the second thin film transistor and the gate electrode of the first thin film transistor can be formed of a common material.
[0044]
In addition, after the single crystal silicon layer is formed on the lower gate portion, a group 3 or group 5 impurity element is introduced into the single crystal silicon layer to form source and drain regions, and then an activation process is performed. be able to.
[0045]
Further, after the formation of the single crystal silicon layer, the source and drain regions of the first and second thin film transistors are formed by ion implantation of the impurity element using a resist as a mask, and the activation treatment is performed after the ion implantation, After forming the gate insulating film, a gate electrode of the first thin film transistor and, if necessary, an upper gate electrode of the second thin film transistor may be formed.
[0046]
When the thin film transistor is a top gate type, the source and drain regions of the first and second thin film transistors are formed by ion implantation of the impurity element using a resist as a mask after the formation of the single crystal silicon layer. An activation process is performed, and then each gate portion including the gate insulating film and the gate electrode of the first and second thin film transistors can be formed.
[0047]
Alternatively, when the thin film transistor is a top gate type, each gate insulating film of each of the first and second thin film transistors and each gate electrode made of a heat resistant material are formed after forming the single crystal silicon layer, and each gate portion is formed. The source and drain regions may be formed by ion implantation of the impurity element using these gate portions as a mask, and an activation process may be performed after the ion implantation.
[0048]
Further, the resist mask used when forming the LDD structure is left, and the ion implantation for forming the source region and the drain region can be performed using the resist mask covering the resist mask.
[0049]
Further, the substrate may be optically opaque or transparent, and a reflective or transmissive display unit pixel electrode may be provided.
[0050]
When the display unit has a laminated structure of the pixel electrode and the color filter layer, the color filter is formed on the display array unit, thereby improving the aperture ratio, luminance, and the like of the display panel. Cost reduction is realized by omitting substrates and improving productivity.
[0051]
In this case, when the pixel electrode is a reflective electrode, the resin film is provided with irregularities for obtaining optimum reflection characteristics and viewing angle characteristics, the pixel electrode is provided thereon, and the pixel electrode is a transparent electrode. In this case, the surface is flattened by the transparent flattening film, and the pixel electrode is preferably provided on the flattened surface.
[0052]
The display unit is configured to perform light emission or dimming by being driven by the MOSTFT. For example, a liquid crystal display (LCD), an electroluminescence display (EL), a field emission display (FED), a light emitting polymer display It may be configured as a device (LEPD), a light emitting diode display (LED) or the like. In this case, a plurality of the pixel electrodes may be arranged in a matrix on the display unit, and the switching element may be connected to each of the pixel electrodes.
[0053]
Next, the present invention will be described in more detail with respect to preferred embodiments.
[0054]
<First Embodiment>
1 to 13 show a first embodiment of the present invention.
[0055]
In the present embodiment, a single-crystal silicon layer is grown at a high temperature by graphoepitaxial growth from an indium-silicon melt using the step (concave portion) provided on the heat-resistant substrate as a seed, and a top gate type MOSTFT is formed using this. The present invention relates to a matrix reflection type liquid crystal display (LCD). First, the overall layout of the reflective LCD will be described with reference to FIGS.
[0056]
As shown in FIG. 11, this active matrix reflective LCD has a flat panel structure in which a main substrate 1 (which constitutes an active matrix substrate) and a counter substrate 32 are bonded together via a spacer (not shown). The liquid crystal (not shown here) is sealed between the substrates 1-32. On the surface of the main substrate 1, there are a display unit composed of pixel electrodes 29 (or 41) arranged in a matrix and switching elements for driving the pixel electrodes, and a peripheral drive circuit unit connected to the display unit. Is provided.
[0057]
The switching element of the display unit is an nMOS, pMOS or cMOS according to the present invention, and is composed of a top gate type MOS TFT having an LDD structure. Also, in the peripheral drive circuit section, cMOS, nMOS, pMOSTFT, or a mixture of these is formed as a circuit element of the top gate MOSTFT according to the present invention. One peripheral driving circuit unit is a horizontal driving circuit that supplies a data signal to drive the TFT of each pixel for each horizontal line, and the other peripheral driving circuit unit sets the gate of the TFT of each pixel for each scanning line. The vertical driving circuit is normally provided on both sides of the display portion. These drive circuits can be configured in either a dot sequential analog system or a line sequential digital system.
[0058]
As shown in FIG. 12, the above TFT is arranged at the intersection of the orthogonal gate bus line and the data bus line, and the liquid crystal capacitance (C _LC The image information is written in () and the electric charge is held until the next information comes. In this case, since it is not sufficient to hold only the channel resistance of the TFT, a storage capacitor (auxiliary capacitor) (C _S ) May be added to compensate for the decrease in the liquid crystal voltage due to the leakage current. Such LCD TFTs require different performance depending on the characteristics of TFTs used in the pixel portion (display portion) and TFTs used in the peripheral drive circuit. In particular, the TFTs in the pixel portion control off current and ensure on current. Is an important issue. For this reason, the display portion is provided with a TFT having an LDD structure as will be described later, thereby reducing the effective electric field applied to the channel region as a structure in which an electric field is unlikely to be applied between the gate and the drain, thereby reducing the off-current. The change of can be made small. However, since the process is complicated, the element size is increased, and problems such as a decrease in on-current occur, an optimum design that matches each purpose of use is required.
[0059]
As usable liquid crystal, TN liquid crystal (nematic liquid crystal used for TN mode of active matrix driving), STN (super twisted nematic), GH (guest / host), PC (phase change), FLC ( Liquid crystals for various modes such as ferroelectric liquid crystal), AFLC (antiferroelectric liquid crystal), and PDLC (polymer dispersed liquid crystal) may be used.
[0060]
Further, FIG. 13 outlines the circuit system of the peripheral driving circuit and the driving method thereof. The drive circuit is divided into a gate side drive circuit and a data side drive circuit, and it is necessary to configure a shift register on both the gate side and the data side. Generally, there are shift registers that use both pMOS TFT and nMOS TFT (so-called CMOS circuit) and those that use only one of the MOS TFTs. However, in terms of operation speed, reliability, and low power consumption, cMOS TFT or CMOS circuits are common.
[0061]
The scanning side driving circuit is composed of a shift register and a buffer, and sends a pulse synchronized with the horizontal scanning period from the shift register to each line. On the other hand, the data side drive circuit has two drive methods, a dot sequential method and a line sequential method, and the circuit configuration is relatively simple in the illustrated dot sequential method, and the display signal is controlled by a shift register through an analog switch. While writing directly to each pixel. Each pixel is sequentially written within one horizontal scanning time (R, G, and B in the figure schematically indicate the pixel for each color).
[0062]
Next, the active matrix reflective LCD according to the present embodiment will be described with reference to FIGS. 1 to 6, the left side of each figure shows the manufacturing process of the display unit, and the right side shows the manufacturing process of the peripheral drive circuit unit.
[0063]
First, as shown in FIG. 1A, a photoresist 2 is formed in a predetermined pattern on at least a TFT forming region on one main surface of an insulating substrate 1 such as quartz glass or crystallized glass, and this is used as a mask. For example, CF _Four F of plasma ⁺ Irradiation with ions 3 is performed to form a plurality of steps 4 with appropriate shapes and dimensions on the substrate 1 by general-purpose photolithography and etching (photoetching) such as reactive ion etching (RIE). In this case, the insulating substrate 1 is a high heat-resistant substrate (8-12 inches φ, 700-800 μm) such as quartz glass, crystallized glass, ceramic, etc. (however, an opaque ceramic substrate cannot be used in a transmissive LCD described later). Thickness) can be used. Further, the step 4 serves as a seed for grapho epitaxial growth of single crystal silicon, which will be described later, and may have a depth d of 0.1 μm, a width w of 5 to 10 μm, and a length (perpendicular to the paper surface) of 10 to 20 μm. The angle between the base and the side (base angle) is a right angle.
[0064]
Next, as shown in FIG. 1B, after removing the photoresist 2, a step 4 of the substrate 1 heated to 900 to 930 ° C. with a silicon-indium melt 6 containing about 1% by weight of silicon is formed. Apply to the entire surface. Alternatively, the substrate 1 can be dipped in the melt, or the surface of the melt can be gradually moved to float, the jet method, or the contact method under ultrasonic action.
[0065]
Next, after holding the substrate 1 for several minutes to several tens of minutes, it is gradually cooled (in the case of dipping, gradually pulled up), so that silicon dissolved in indium seeds the corners of the bottom of the step 4 ( As shown in FIG. 2 (3), grapho-epitaxial growth is performed as a seed, and a P-type single crystal silicon layer 7 having a thickness of, for example, about 0.1 μm is deposited. In the dipping method and the floating method, it is easy to manage the melt composition, temperature, pulling speed, etc., and the thickness of the epitaxial growth layer and the P-type carrier impurity concentration can be easily controlled.
[0066]
In this case, the (100) plane of the single crystal silicon layer 7 is epitaxially grown on the substrate, and this is due to a known phenomenon called grapho epitaxial growth. As shown in FIG. 8, when a vertical wall such as the step 4 is formed on the amorphous substrate (glass) 1 and an epitaxial growth layer is formed thereon, a random wall as shown in FIG. As shown in FIG. 8B, the (100) plane grows along the surface of the step 4 in the case of the plane orientation. The size of the single crystal grains increases in proportion to the temperature and time. However, when the temperature and time are reduced and shortened, the interval between the steps must be shortened. Further, the crystal orientation of the growth layer can be controlled by variously changing the shape of the step as shown in FIGS. When creating a MOS transistor, the (100) plane is most often used. In short, the cross-sectional shape of the step 4 is such that the angle of the base corner (bottom angle) may be inclined inward or outward from the upper end to the lower end, including a right angle, and a surface in a specific direction in which crystal growth is likely to occur. It only has to have. The base angle of the step 4 is usually preferably a right angle or 90 ° or less, and the corner of the bottom surface should have a slight curvature.
[0067]
Thus, after the single crystal silicon layer 7 is deposited on the substrate 1 by the grapho epitaxial growth, the indium film 6A deposited on the surface side is dissolved and removed by hydrochloric acid, sulfuric acid, etc. as shown in FIG. Then, post-processing is performed so that a lower silicon oxide film is not generated), and a top gate type MOS TFT having the single crystal silicon layer 7 as a channel region is manufactured.
[0068]
First, the single crystal silicon thin film 7 formed by the above-mentioned graphoepitaxial growth is made P-type by containing indium. However, since the P-type impurity concentration varies, the p-channel MOS TFT portion is masked with a photoresist (not shown). P-type impurity ions (for example, B ⁺ ) At 10 kV and 2.7 × 10 ¹¹ atoms / cm ² The specific resistance is adjusted by doping with a dose amount of. Further, as shown in FIG. 2 (5), in order to control the impurity concentration of the pMOS TFT formation region, the nMOS TFT portion is masked with a photoresist 60, and N-type impurity ions (for example, P ⁺ ) 65 x 1 kV at 10 kV ¹¹ atoms / cm ² The N-type well 7A is formed by doping with a dose amount of.
[0069]
Next, as shown in FIG. 3 (6), a silicon oxide film (hereinafter referred to as SiO 2) is formed on the entire surface of the single crystal silicon thin film layer 7 by plasma CVD, high density plasma CVD, catalytic CVD, or the like. ₂ Called membrane. ) (Approx. 200 nm thickness) and SiN film (approx. 100 nm thickness) are successively formed in this order to form the gate insulating film 8, and further, a sputtered film 9 (500 to 600 nm thickness) of molybdenum-tantalum (Mo · Ta) alloy Form.
[0070]
Next, as shown in (7) of FIG. 3, a photoresist pattern 10 is formed in each step region (inside the recess) between the TFT portion in the display region and the TFT portion in the peripheral drive region by a general-purpose photolithography technique. Then, the gate electrode 11 of the (Mo · Ta) alloy and the gate insulating film (SiN / SiO) are obtained by continuous etching. ₂ ) 12 and the single crystal silicon thin film layer 7 is exposed. (Mo · Ta) alloy film 9 is an acid-based etching solution, SiN is CF _Four Gas plasma etching, SiO ₂ Is treated with a hydrofluoric acid-based etching solution.
[0071]
Next, as shown in FIG. 3 (8), the nMOS and pMOS TFT in the peripheral drive region and the gate portion of the nMOS TFT in the display region are covered with a photoresist 13, and phosphorus ions 14 are applied to the exposed source / drain regions of the nMOS TFT. For example, 5 × 10 at 20 kV ¹³ atoms / cm ² Doping (ion implantation) with a dose amount of N ^- The LDD portion 15 made of a mold layer is formed in a self-aligned manner (self-alignment).
[0072]
Next, as shown in FIG. 4 (9), the entire pMOS TFT in the peripheral drive region, the gate portion of the nMOS TFT in the peripheral drive region, and the gate and LDD portion of the nMOS TFT in the display region are covered with photoresist 16 and exposed. For example, phosphorus or arsenic ions 17 are applied at 20 kV to 5 × 10 ¹⁵ atoms / cm ² Of the nMOS TFT by doping (ion implantation) with a dose of ⁺ A source part 18 and a drain part 19 and an LDD part 15 made of a mold layer are formed.
[0073]
Next, as shown in (10) of FIG. 4, the entire nMOS TFT in the peripheral drive region, the nMOS TFT in the display region, and the gate portion of the pMOS TFT are covered with a photoresist 20, and boron ions 21 are applied to the exposed region at, for example, 10 kV. × 10 ¹⁵ atoms / cm ² Of pMOS TFT by doping (ion implantation) at a dose of ⁺ The source part 22 and the drain part 23 of the layer are formed. This operation is unnecessary because there is no pMOS TFT in the case of an nMOS peripheral drive circuit.
[0074]
Next, as shown in (11) of FIG. 4, a photoresist 24 is provided for islanding active element portions such as TFTs and diodes and passive element portions such as resistors and inductances, and the peripheral drive region and display region are formed. The single crystal silicon thin film layers other than all the active element portions and passive element portions are removed by general photolithography and etching techniques. The etching solution is hydrofluoric acid.
[0075]
Next, as shown in FIG. 5 (12), by CVD, high density plasma CVD, catalytic CVD, etc., SiO 2 ₂ A protective film 25 is formed by continuously forming a film (about 200 nm thick) and a phosphorus silicate glass (PSG) film (about 300 nm thick) in this order on the entire surface.
[0076]
In this state, the single crystal silicon layer is activated. In this activation, lamp annealing conditions such as halogen are about 1000 ° C. and about 10 seconds, and a gate electrode material that can withstand this is necessary, but a high melting point Mo / Ta alloy is suitable. Therefore, the gate electrode material can be provided not only as a gate portion but also as a wiring over a wide range. Note that expensive excimer laser annealing is not used here, but if it is used, the condition is XeCl (308 nm wavelength), or the entire surface or selective overlap of 90% or more of only the active element portion and the passive element portion. Scanning is desirable.
[0077]
Next, as shown in (13) of FIG. 5, contact windows are opened in the source / drain portions of all TFTs of the peripheral drive circuit and the source portion of the display TFTs by general-purpose photolithography and etching techniques.
[0078]
Then, a sputtered film of 500 to 600 nm thick aluminum or aluminum alloy, for example, 1% Si-containing aluminum or 1-2% copper-containing aluminum, copper or the like is formed on the entire surface. At the same time as forming the source electrode 26 of all TFTs in the display portion and the drain electrode 27 of the peripheral driving circuit portion, the data line and the gate line are formed. After that, forming gas (N ₂ + H ₂ ) Is sintered at about 400 ° C./1 h.
[0079]
Next, as shown in FIG. 5 (14), an insulating film 36 composed of a PSG film (about 300 nm thick) and a SiN film (about 300 nm thick) is formed on the entire surface by plasma CVD, high density plasma CVD, catalytic CVD, or the like. Form. Next, a contact window is opened in the drain portion of the display TFT. Note that the SiO of the pixel portion ₂ It is not necessary to remove the PSG and SiN films.
[0080]
As a basic requirement of the reflection type liquid crystal display device, a function of reflecting incident light and a function of scattering incident light must be combined in the liquid crystal panel. This is because the direction of the observer with respect to the display is almost determined, but the direction of the incident light cannot be uniquely determined. For this reason, it is necessary to design the reflector assuming that a point light source exists in an arbitrary direction. Therefore, as shown in FIG. 6 (15), a photosensitive resin film 28 having a thickness of 2 to 3 μm is formed on the entire surface by spin coating or the like, and as shown in FIG. 6 (16), general-purpose photolithography and etching are performed. By using the technique, an uneven shape pattern for obtaining optimum reflection characteristics and viewing angle characteristics at least for the pixel portion is formed and reflowed to form a lower reflection surface composed of the uneven rough surface 28A. At the same time, a resin window for contact in the drain portion of the display TFT is opened.
[0081]
Next, as shown in FIG. 6 (17), a sputtered film such as aluminum having a thickness of 400 to 500 nm or aluminum containing 1% Si is formed on the entire surface, and an aluminum film other than the pixel portion is formed by general-purpose photolithography and etching techniques. Then, a reflective portion 29 made of uneven aluminum or the like connected to the drain portion 19 of the display TFT is formed. This is used as a pixel electrode for display. Thereafter, sintering is performed in forming gas at about 300 ° C./1 h to ensure sufficient contact. In order to increase the reflectance, silver or a silver alloy may be used instead of the aluminum series.
[0082]
As described above, the single crystal silicon layer 7 is formed using the step 4 as a seed for high temperature grapho epitaxial growth, and the top gate type nMOS LDD− is formed in the display unit and the peripheral drive circuit unit using the single crystal silicon layer 7 respectively. An active matrix substrate 30 integrated with a display unit-peripheral drive circuit unit in which a CMOS circuit composed of TFT, pMOSTFT and nMOSTFT is formed can be manufactured.
[0083]
Next, a method of manufacturing a reflective liquid crystal display device (LCD) using the active matrix substrate (drive substrate) 30 will be described with reference to FIG. Hereinafter, this active matrix substrate is referred to as a TFT substrate.
[0084]
When the liquid crystal cell of this LCD is fabricated by surface assembly (suitable for medium / large liquid crystal panels of 2 inches or more), first a TFT substrate 30 and a solid ITO (Indium tin oxide) electrode 31 are provided. Polyimide alignment films 33 and 34 are formed on the element formation surface of the counter substrate 32. This polyimide alignment film is formed to a thickness of 50 to 100 nm by roll coating, spin coating or the like, and cured and cured at 180 ° C./2 h.
[0085]
Next, the TFT substrate 30 and the counter substrate 32 are rubbed or subjected to photo-alignment treatment with polarized ultraviolet rays. The rubbing buff material includes cotton and rayon, but cotton is more stable in terms of buffing (dust) and retardation. Photo-alignment is a technique for aligning liquid crystal molecules by non-contact linearly polarized ultraviolet irradiation. For alignment, in addition to rubbing, a polymer alignment film can be formed by obliquely entering polarized light or non-polarized light (such a polymer compound is, for example, a polymethyl methacrylate polymer having azobenzene). Etc.).
[0086]
Next, after cleaning, a common agent is applied to the TFT substrate 30 side, and a sealing agent is applied to the counter substrate 32 side. Wash with water or IPA (isopropyl alcohol) to remove rubbing buff. The common agent may be an acrylic containing a conductive filler, or an epoxy acrylate, or an epoxy adhesive, and the sealant may be an acrylic, an epoxy acrylate, or an epoxy adhesive. Any of heat curing, ultraviolet radiation curing, ultraviolet radiation curing + heat curing can be used, but the ultraviolet radiation curing + heat curing type is preferable in terms of overlay accuracy and workability.
[0087]
Next, spacers for obtaining a predetermined gap are scattered on the counter substrate 32 side, and overlapped with the TFT substrate 30 at a predetermined position. After aligning the alignment mark on the counter substrate 32 side with the alignment mark on the TFT substrate 30 side with accuracy, the sealant is temporarily cured by irradiating with ultraviolet rays, and then heated and cured all at once.
[0088]
Next, a scribe break is performed to produce a single liquid crystal panel in which the TFT substrate 30 and the counter substrate 32 are overlapped.
[0089]
Next, the liquid crystal 35 is injected into the gap between the two substrates 30-32, and the injection port is sealed with an ultraviolet adhesive, followed by IPA cleaning. Any type of liquid crystal may be used, but for example, a fast response TN (twisted nematic) mode using a nematic liquid crystal is common.
[0090]
Next, the liquid crystal 35 is oriented by heating and quenching.
[0091]
Next, a flexible wiring is connected to the panel electrode extraction portion of the TFT substrate 30 by thermocompression bonding of an anisotropic conductive film, and a polarizing plate is bonded to the counter substrate 32.
[0092]
Further, in the case of a single surface assembly of a liquid crystal panel (suitable for a small liquid crystal panel having a size of 2 inches or less), polyimide orientations 33 and 34 are formed on the element formation surfaces of the TFT substrate 30 and the counter substrate 32 as described above. Then, both substrates are rubbed or subjected to alignment treatment of non-contact linearly polarized ultraviolet light.
[0093]
Next, the TFT substrate 30 and the counter substrate 32 are divided into single pieces by dicing or scribe break, and washed with water or IPA. A common agent is applied to the TFT substrate 30, and a sealant containing a spacer is applied to the counter substrate 32, and the two substrates are overlapped. The subsequent processes follow the above.
[0094]
In the reflective LCD described above, the counter substrate 32 is a CF (color filter) substrate, and a color filter layer 46 is provided under the ITO electrode 31. Incident light from the counter substrate 32 side is efficiently reflected by the reflective film 29 and is emitted from the counter substrate 32 side.
[0095]
On the other hand, when the TFT substrate 30 is a TFT substrate having an on-chip color filter (OCCF) structure in which a color filter is provided on the TFT substrate 30 in addition to the above-described substrate structure as shown in FIG. Is solid (or an ITO electrode with a black mask is solid).
[0096]
The auxiliary capacity C shown in FIG. _S Is incorporated into the pixel portion, a dielectric layer (not shown) provided on the substrate 1 may be connected to the drain region 19 of single crystal silicon.
[0097]
As described above, according to the present embodiment, the following significant operational effects can be obtained.
[0098]
(A) A step 4 having a predetermined shape / dimension is formed on the substrate 1, and high temperature grapho epitaxial growth is performed using the corner of the bottom of the step as a seed (however, the heating temperature during growth is relatively low, 900 to 930 ° C.). 540cm ² Since the single crystal silicon thin film 7 having a high electron mobility of / v · sec or more can be obtained, it is possible to manufacture an LCD with a high-performance driver.
[0099]
(B) This single crystal silicon thin film exhibits high electron and hole mobility comparable to that of a single crystal silicon substrate as compared with a conventional amorphous silicon thin film or polycrystalline silicon thin film. Has a structure in which an nMOS or pMOS or cMOS TFT display portion having an LDD structure with high switching characteristics and a low leakage current is integrated with a peripheral drive circuit portion made of cMOS, nMOS or pMOS TFT having a high driving capability or a mixture thereof. It becomes possible to realize a display panel with high image quality, high definition, narrow frame, large screen, and high efficiency. Since this single crystal silicon thin film 7 exhibits a sufficiently high hole mobility, a peripheral driving circuit for driving electrons and holes alone or in combination with each other can be produced, and this can be formed as an nMOS, pMOS or cMOS LDD. A panel integrated with a display TFT having a structure can be realized. In the case of a small to medium panel, there is a possibility that one of a pair of peripheral vertical drive circuits can be omitted.
[0100]
(C) Since the heat treatment temperature during grapho epitaxial growth described above can be 930 ° C. or lower, the single crystal silicon film 7 is uniformly formed on the insulating substrate at a relatively low temperature (eg 900 to 930 ° C. or lower). can do. As the substrate, quartz glass, crystallized glass, ceramic substrate, or the like can be used.
[0101]
(D) Since annealing at long temperatures and excimer laser annealing as in the case of the solid phase growth method are not required, productivity is high, expensive manufacturing equipment is not required, and cost can be reduced.
[0102]
(E) In this high temperature grapho epitaxial growth, a single crystal silicon thin film with a wide range of P-type impurity concentration and high mobility can be easily obtained by adjusting the indium / silicon composition ratio, substrate heating temperature, melt temperature, cooling rate, etc. Therefore, Vth (threshold) adjustment is easy, and high-speed operation is possible due to low resistance.
[0103]
(F) If a color filter is formed on the display array section, the cost can be reduced by improving the aperture ratio, luminance, etc. of the display panel, omitting the color filter substrate, and improving productivity.
[0104]
<Second Embodiment>
A second embodiment of the present invention will be described with reference to FIGS.
[0105]
This embodiment has the same top gate TFT as that in the first embodiment described above in the display unit and the peripheral drive circuit unit. However, unlike the first embodiment, the present embodiment relates to a transmissive LCD. Is. That is, the process from (1) in FIG. 1 to the process shown in (14) in FIG. 5 is the same, but after that process, as shown in (15) in FIG. Opening 19 for drain contact is performed, and at the same time, unnecessary SiO in the pixel opening is improved in order to improve the transmittance. ₂ , PSG and SiN films are removed. An opaque ceramic substrate cannot be used.
[0106]
Next, as shown in FIG. 14 (16), a planarizing film 28 B of a photosensitive acrylic transparent resin having a thickness of 2 to 3 μm is formed on the entire surface by spin coating or the like, and the drain side of the display TFT is formed by general-purpose photolithography. The transparent resin 28B is opened and cured under predetermined conditions.
[0107]
Next, as shown in FIG. 14 (17), an ITO sputtered film having a thickness of 130 to 150 nm is formed on the entire surface, and the ITO transparent electrode 41 in contact with the drain portion 19 of the display TFT is formed by general-purpose photolithography and etching techniques. Form. Then, the contact resistance between the drain of the display TFT and ITO and the transparency of the ITO are improved by heat treatment (in forming gas, 200 to 250 ° C./1 h).
[0108]
Then, as shown in FIG. 15, in combination with the counter substrate 32, a transmissive LCD is assembled in the same manner as in the first embodiment. However, a polarizing plate is also bonded to the TFT substrate side. In this transmissive LCD, transmitted light can be obtained as shown by a solid line, but transmitted light from the counter substrate 32 side can also be obtained as shown by a dashed line.
[0109]
In the case of this transmissive LCD, an on-chip color filter (OCCF) structure and an on-chip black (OCB) structure can be manufactured as follows.
[0110]
That is, the steps from (1) in FIG. 1 to (13) in FIG. 5 are performed in accordance with the above-described steps, and thereafter, as shown in (14) in FIG. ₂ The drain portion of the insulating film 25 is also opened to form the aluminum buried layer 41A for the drain electrode, and then the SiN / PSG insulating film 36 is formed.
[0111]
Next, as shown in FIG. 16 (15), a photoresist 61 in which each color of R, G, and B is pigment-dispersed for each segment is formed with a predetermined thickness (1 to 1.5 μm). As shown in (16), each color filter layer 61 (R), 61 (G), and 61 (B) is formed by patterning that leaves only a predetermined position (each pixel portion) by general-purpose photolithography technology (on-chip color). Filter structure). At this time, the window of the drain part is also opened. Note that an opaque ceramic substrate, low-transmittance glass, and a heat-resistant resin substrate cannot be used.
[0112]
Next, as shown in FIG. 16 (16), a light shielding layer 43 serving as a black mask layer is formed by metal patterning on the color filter layer in a contact hole communicating with the drain of the display TFT. For example, a film of molybdenum having a thickness of 200 to 250 nm is formed by sputtering and patterned into a predetermined shape that covers the display TFT and shields light (on-chip black structure).
[0113]
Next, as shown in FIG. 16 (17), a transparent resin flattening film 28 B is formed, and an ITO transparent electrode 41 is formed so as to be connected to the light shielding layer 43 in a through hole provided in the flattening film. .
[0114]
Thus, by forming the color filter 61 and the black mask 43 on the display array portion, the aperture ratio of the liquid crystal display panel can be improved and the power consumption of the display module including the backlight can be reduced.
[0115]
<Third Embodiment>
A third embodiment of the present invention will be described.
[0116]
In this embodiment, the above-described step (concave portion) is formed on a glass substrate having a low strain point, and this is used as a seed to grow a single crystal silicon layer from indium gallium silicon or a gallium silicon melt by low-temperature graphoepitaxy, The present invention relates to an active matrix reflective liquid crystal display device (LCD) in which a top gate type MOSTFT is formed using this.
[0117]
That is, in the present embodiment, compared with the first embodiment described above, in the step shown in FIG. 1 (1), as the substrate 1, a glass having a low strain point or maximum use temperature of about 600 ° C., for example, For example, a glass substrate such as borosilicate glass or aluminosilicate glass is used. This is inexpensive and easy to increase in size, and can be rolled / lengthened by increasing the size of the thin plate (for example, 500 × 600 × 0.1 to 1.1 mm thick). Of course, a quartz substrate or a crystallized glass substrate can also be employed.
[0118]
Then, after the step 4 is formed in the same manner as described above, a silicon / indium / gallium melt containing 1% by weight of silicon or a silicon / gallium melt containing the step 4 is formed in the step shown in FIG. Apply to. At this time, the substrate 1 is heated to about 300 to 600 ° C. or 420 to 600 ° C.
[0119]
Next, after the substrate 1 is held for several minutes to several tens of minutes, it is gradually cooled (in the case of dipping, it is gradually lifted, but in the case of floating, it is gradually moved along the melt surface) to thereby indium. Gallium or silicon dissolved in gallium is grapho epitaxially grown as shown in FIG. 2 (3) with the bottom corner of the step 4 as a seed, and is a P-type single layer having a thickness of about 0.1 μm, for example. A crystalline silicon layer 7 is deposited. In the dipping method and the floating method, management of the solution composition, temperature, pulling rate, etc. is easy, and the thickness of the epitaxial growth layer and the P-type impurity concentration can be easily controlled.
[0120]
In this case, the single crystal silicon layer 7 has the (100) plane epitaxially grown on the substrate in the same manner as described above, but the shape of the step is changed variously as shown in FIGS. Thus, the crystal orientation of the growth layer can be controlled.
[0121]
Thus, after depositing the single crystal silicon layer 7 on the substrate 1 by low temperature grapho epitaxial growth, indium gallium (or gallium) on the surface side is dissolved and removed with hydrochloric acid, sulfuric acid, etc. as shown in FIG. To do.
[0122]
Thereafter, using the single crystal silicon layer 7, a top gate type MOSTFT is manufactured in the display portion and the peripheral drive circuit portion in the same manner as in the first embodiment. Further, the structure shown in FIG. 7 may be similarly applied to this embodiment.
[0123]
According to the present embodiment, in addition to the operational effects described in the first embodiment, the following significant operational effects can be obtained.
[0124]
(A) The silicon single crystal thin film 7 can be uniformly formed on the glass substrate 1 by grapho epitaxial growth at a temperature as low as about 300 to 600 ° C. or 420 to 600 ° C.
[0125]
(B) Therefore, since a silicon single crystal thin film can be formed not only on a glass substrate but also on an insulating substrate such as an organic substrate, a substrate material having a low strain point, low cost and good physical properties can be arbitrarily selected. Also, the substrate can be enlarged. Glass substrates and organic substrates can be made cheaper than quartz substrates and ceramic substrates, and can be made thinner / longer / rolled. A large / rolled large glass substrate or the like can be manufactured with good productivity and at low cost. When glass with a low glass strain point (or maximum operating temperature) (for example, 500 ° C.) is used as the glass substrate, the constituent elements diffuse from the inside of the glass into this upper layer, and this affects transistor characteristics. For the purpose of suppression, a barrier layer thin film (for example, silicon nitride: about 50 to 200 nm thick) may be formed.
[0126]
(C) In this low temperature grapho epitaxial growth, a wide range of P-type impurity concentration and high mobility single crystal silicon can be obtained by adjusting the indium / gallium composition ratio, substrate heating temperature, melt temperature, cooling rate, etc. of the indium / gallium film. Since a thin film can be easily obtained, Vth adjustment is easy and high-speed operation with low resistance is possible.
[0127]
<Fourth embodiment>
A fourth embodiment of the present invention will be described.
[0128]
This embodiment relates to a transmissive LCD as compared with the above-described third embodiment, and the manufacturing process thereof uses an indium gallium melt as described in the above-described third embodiment. A single crystal silicon thin film can be formed by low temperature grapho epitaxial growth.
[0129]
Then, using this single crystal silicon thin film, a transmissive LCD can be manufactured by the steps shown in FIGS. 14 to 16 as described in the fourth embodiment. However, opaque ceramic substrates and organic substrates with opaque or low transmittance are not suitable.
[0130]
Therefore, in this embodiment, it is possible to have both the excellent effects of both the first embodiment and the third embodiment described above. That is, in addition to the functions and effects of the first embodiment described above, it is possible to use a substrate 1 that can be made thin and long at low cost, such as an organic substrate such as borosilicate glass or heat-resistant polyimide, indium The aperture ratio of the liquid crystal display panel is improved by making it easy to adjust the conductivity type and Vth of the single crystal silicon thin film 7 by the / gallium composition ratio, and by forming the color filter 42 and the black mask 43 on the display array portion. In addition, low power consumption of the display module including the backlight is realized.
[0131]
<Fifth embodiment>
17 to 25 show a fifth embodiment of the present invention.
[0132]
In the present embodiment, the peripheral drive circuit section is constituted by a cMOS drive circuit composed of a top gate type pMOS TFT and an nMOS TFT similar to the first embodiment described above. Although the display unit is of a reflective type, the TFTs have various gate structures and are variously combined.
[0133]
That is, in FIG. 17A, a top gate type nMOS LDD-TFT similar to that of the first embodiment described above is provided in the display portion, but the bottom gate type is provided in the display portion shown in FIG. In the display portion shown in FIG. 17C, dual-gate nMOSLDD-TFTs are provided. Both of these bottom gate type and dual gate type MOSTFTs can be manufactured in the same process as the top gate type MOSTFT of the peripheral drive circuit section as will be described later. The driving capability is improved by the portion, which is suitable for high-speed switching, and can be operated as a top gate type or a bottom gate type depending on the case by selectively using either the upper or lower gate portion.
[0134]
In the bottom gate type MOSTFT of FIG. 17B, 71 in the figure is a gate electrode such as Mo / Ta, 72 is a SiN film, and 73 is a SiON film. ₂ A gate insulating film is formed, and a channel region or the like using a single crystal silicon layer similar to the top gate type MOS TFT is formed on the gate insulating film. In the dual gate type MOSTFT of FIG. 17C, the lower gate part is the same as the bottom gate type MOSTFT, but the upper gate part has the gate insulating film 73 formed of SiO2. ₂ The upper gate electrode 74 is provided thereon. However, in any case, each gate portion is formed outside the step 4 which becomes a seed for grapho epitaxial growth.
[0135]
Next, the manufacturing method of the bottom gate type MOSTFT will be described with reference to FIGS. 18 to 22, and the manufacturing method of the dual gate type MOSTFT will be described with reference to FIGS. Since the manufacturing method of the top gate type MOSTFT of the peripheral drive circuit section is the same as that described in FIGS. 1 to 6, the illustration is omitted here.
[0136]
In order to manufacture a bottom gate type MOSTFT in the display section, first, as shown in FIG. 18 (1), a sputtered film 71 (500 to 600 nm thick) of a molybdenum / tantalum (Mo · Ta) alloy is formed on the substrate 1. ).
[0137]
Next, as shown in FIG. 18 (2), a photoresist 70 is formed in a predetermined pattern, and using this as a mask, the Mo / Ta film 9 is taper-etched, and the side end 71 a has a trapezoidal shape at 20 to 45 degrees. A gently inclined gate electrode 71 is formed.
[0138]
Next, as shown in FIG. 18 (3), after removing the photoresist 71, an SiN film (about 100 nm thick) 72 and SiO 2 are deposited on the substrate 1 including the molybdenum / tantalum alloy film 71 by plasma CVD or the like. ₂ A gate insulating film is formed by laminating a film (about 200 nm thick) 73 in this order.
[0139]
Next, as shown in FIG. 18 (4), in the same process as in FIG. 1 (1), a photoresist 2 is formed in a predetermined pattern at least in the TFT formation region, and this is used as a mask in the same manner as described above. A plurality of steps 4 are formed in an appropriate shape and size on the gate insulating film on 1 (and also on the substrate 1). This step 4 serves as a seed for grapho epitaxial growth of single crystal silicon, which will be described later, and has a depth d = 0.3 to 0.4 μm, a width w = 2 to 3 μm, and a length (perpendicular to the paper surface). = 10 to 20 μm, and the angle between the base and the side surface (base angle) is a right angle.
[0140]
Next, as shown in FIG. 19 (5), after removing the photoresist 2, in the same process as (2) in FIG. 1, the indium containing silicon (or indium gallium or gallium) is melted in the same manner as described above. The liquid 6 is applied onto the substrate 1 at the same substrate temperature as described above. Hereinafter, indium will be described as an example.
[0141]
Next, as shown in FIG. 19 (6), in the same process as FIG. 2 (3), by gradually cooling, silicon dissolved in indium is seeded at the bottom corner of the step 4. Is grown as a P-type single crystal silicon layer 7 having a thickness of, for example, about 0.1 μm. At this time, since the side end portion 71a of the underlying gate electrode 71 is a gently inclined surface, the epitaxial growth due to the step 4 is not hindered on this surface, and the single crystal silicon layer 7 is grown without step breakage. Will do.
[0142]
Next, as shown in FIG. 19 (7), indium 6A adhering to the surface side may be dissolved and removed with hydrochloric acid, sulfuric acid, or the like, and then an appropriate amount of impurity ions may be doped to adjust the specific resistance.
[0143]
Next, as shown in FIG. 19 (8), in the same step as FIG. 3 (8), the gate portion of the nMOS TFT of the display portion is covered with a photoresist 13, and phosphorus ions 14 are formed in the exposed source / drain regions of the nMOS TFT. Is doped (ion implantation) to form N ^- An LDD portion 15 made of a mold layer is formed in a self-aligning manner. At this time, the difference in surface height (or pattern) is easily recognized due to the presence of the bottom gate electrode 71, alignment (mask alignment) of the photoresist 13 is easily performed, and misalignment hardly occurs.
[0144]
Next, as shown in FIG. 20 (9), in the same step as (9) of FIG. 4, the gate portion and LDD portion of the nMOS TFT are covered with the photoresist 16, and the exposed region is doped with phosphorus or arsenic ions 17 ( Ion implantation) and NMOS TFT N ⁺ A source part 18 and a drain part 19 made of a mold layer are formed.
[0145]
Next, as shown in FIG. 20 (10), in the same process as (10) in FIG. 4, the entire nMOS TFT is covered with a photoresist 20, and boron ions 21 are doped (ion implantation) to produce a peripheral drive circuit section. PMOSTFT of P ⁺ A source part and a drain part of the layer are formed.
[0146]
Next, as shown in FIG. 20 (11), in the same process as (11) in FIG. 4, a photoresist 24 is provided to make the active element portion and the passive element portion into an island, and the single crystal silicon thin film layer is used as a general purpose. It is selectively removed by photolithography and etching techniques.
[0147]
Next, as shown in (12) of FIG. 20, in the same process as (12) of FIG. 4, SiO, high density plasma CVD, catalytic CVD, etc. ₂ A film 53 (about 300 nm thick) and a phosphorous silicate glass (PSG) film 54 (about 300 nm thick) are formed on the entire surface in this order. In addition, SiO ₂ The film 53 and the PSG film 54 correspond to the protective film 25 described above. In this state, the single crystal silicon film is activated in the same manner as described above.
[0148]
Next, as shown in (13) of FIG. 21, in the same process as (13) of FIG. 5, a contact window is opened in the source portion by general-purpose photolithography and etching techniques. Then, a sputtered film of aluminum or the like having a thickness of 400 to 500 nm is formed on the entire surface, and the data electrode and the gate line are formed simultaneously with the formation of the source electrode 26 of the TFT by general-purpose photolithography and etching techniques. Thereafter, sintering is performed in forming gas at about 400 ° C./1 h.
[0149]
Next, as shown in (14) of FIG. 21, in the same process as (14) of FIG. 5, a PSG film (about 300 nm thick) and a SiN film (about 300 nm thick) are formed by high-density plasma CVD, catalytic CVD, or the like. An insulating film 36 is formed on the entire surface, and a contact window is opened in the drain portion of the display TFT.
[0150]
Next, as shown in FIG. 21 (15), in the same step as FIG. 6 (15), a photosensitive resin film 28 having a thickness of 2 to 3 μm is formed by spin coating or the like, and shown in FIG. 21 (16). As described above, by using general-purpose photolithography and etching techniques, an uneven shape pattern that obtains optimum reflection characteristics and viewing angle characteristics is formed at least in the pixel portion, and reflowed to form a lower reflective surface composed of the uneven rough surface 28A. . At the same time, a resin window for contact in the drain portion of the display TFT is opened.
[0151]
Next, as shown in FIG. 21 (16), in the same process as (16) of FIG. 6, a sputtered film of 400 to 500 nm thick aluminum or the like is formed on the entire surface, and display is performed using general-purpose photolithography and etching techniques. A reflection part 29 made of uneven aluminum or the like connected to the drain part 19 of the TFT is formed.
[0152]
As described above, a bottom gate type nMOS LDD-TFT (in the peripheral circuit portion, a CMOS driving circuit composed of a pMOS TFT and an nMOS TFT is used for the display portion using the single crystal silicon layer 7 formed with the step 4 as a seed for high temperature grapho epitaxial growth. ), An active matrix substrate 30 integrated with a display unit-peripheral drive circuit unit can be manufactured.
[0153]
FIG. 22 shows an example in which the gate insulating film of the bottom gate type MOSTFT provided in the display portion is formed by the Mo / Ta anodic oxidation method.
[0154]
That is, after the step (2) in FIG. 18, the molybdenum / tantalum alloy film 71 is subjected to a known anodic oxidation treatment as shown in FIG. ₂ O _Five A gate insulating film 74 made of is formed to a thickness of 100 to 200 nm.
[0155]
In the subsequent process, as shown in FIG. 22 (4), the step 4 is formed in the same manner as in the process of FIG. 18 (4), and after applying the indium melt 6 containing silicon, FIG. As shown in (5) of FIG. 22, the active matrix substrate 30 is fabricated in the same manner as the steps (5) to (16) of FIG.
[0156]
Next, in order to manufacture a dual gate type MOS TFT in the display portion, first, the steps from (1) to FIG. 19 (7) are performed in the same manner as described above.
[0157]
That is, as shown in FIG. 23 (8), the step 4 is formed in the insulating films 72 and 73 and the substrate 1, and the single crystal silicon layer 7 is grapho epitaxially grown using the step 4 as a seed. Next, in the same process as (6) of FIG. 3, the entire surface of the single crystal silicon thin film 7 is formed on the entire surface by SiO, catalytic CVD or the like. ₂ A film (about 200 nm thick) and a SiN film (about 100 nm thick) are successively formed in this order to form an insulating film 80 (which corresponds to the above-described insulating film 8), and a Mo / Ta alloy sputtered film 81 (500) (This is equivalent to the above-mentioned sputtered film 9).
[0158]
Next, as shown in (9) of FIG. 23, in the same process as (7) of FIG. 3, a photoresist pattern 10 is formed, and Mo / Ta alloy top gate electrode 82 (this is described above) by continuous etching. Gate electrode 12) and a gate insulating film 83 (which corresponds to the gate insulating film 11 described above) are formed, and the single crystal silicon thin film layer 7 is exposed.
[0159]
Next, as shown in (10) of FIG. 23, in the same process as (8) of FIG. 3, the top gate portion of the nMOS TFT is covered with a photoresist 13, and phosphorus ions are exposed in the exposed source / drain regions of the nMOS TFT for display. 14 is doped (ion implantation), and N ^- The LDD portion 15 of the mold layer is formed.
[0160]
Next, as shown in FIG. 23 (11), in the same step as (9) of FIG. 4, the gate portion and LDD portion of the nMOS TFT are covered with the photoresist 16, and the exposed region is doped with phosphorus or arsenic ions 17 ( Ion implantation) and NMOS TFT N ⁺ A source part 18 and a drain part 19 made of a mold layer are formed.
[0161]
Next, as shown in (12) of FIG. 24, in the same process as (10) of FIG. 4, the gate portion of the pMOS TFT is covered with a photoresist 20, and boron ions 21 are doped (ion implantation) in the exposed region. P of the pMOS TFT in the peripheral drive circuit section ⁺ A source part and a drain part of the layer are formed.
[0162]
Next, as shown in (13) of FIG. 24, in the same process as (11) of FIG. 4, in order to island the active element portion and the passive element portion, a photoresist 24 is provided, and the active element portion and the passive element portion. The single crystal silicon thin film layer other than the above is selectively removed by general-purpose photolithography and etching techniques.
[0163]
Next, as shown in (14) of FIG. 24, in the same process as (12) of FIG. 5, SiO, high density plasma CVD, catalytic CVD method, etc. are used. ₂ A film 53 (about 200 nm thick) and a phosphorus silicate glass (PSG) film 54 (about 300 nm thick) are formed on the entire surface. These films 53 and 54 correspond to the protective film 25 described above. Then, the single crystal silicon layer 7 is activated.
[0164]
Next, as shown in (15) of FIG. 24, in the same process as (13) of FIG. 5, a contact window is opened in the source portion. Then, a sputtered film of aluminum having a thickness of 400 to 500 nm is formed on the entire surface, and the source electrode 26 is formed at the same time as the data line and the gate line by general-purpose photolithography and etching techniques.
[0165]
Next, as shown in FIG. 25 (16), an insulating film 36 composed of a PSG film (about 300 nm thick) and a SiN film (about 300 nm thick) is formed on the entire surface in the same process as (14) of FIG. A contact window is opened in the drain portion of the TFT.
[0166]
Next, as shown in (17) of FIG. 25, a photosensitive resin film 28 having a thickness of 2 to 3 μm is formed on the entire surface by spin coating or the like. As shown in (18) of FIG. 25, (17) of FIG. ), (18) In the same manner as in the step (18), at least the pixel part is formed with a lower reflection surface composed of the rough surface 28A, and at the same time, a resin window is opened for contact in the drain part of the display TFT. An uneven aluminum reflecting portion 29 connected to the drain portion 19 so as to obtain optimum reflection characteristics and viewing angle characteristics is formed.
[0167]
As described above, using the single crystal silicon layer 7 formed with the step 4 as a seed for high-temperature grapho epitaxial growth, a dual-gate nMOS LDDTFT is formed in the display portion, and a CMOS driving circuit composed of pMOS TFT and nMOS TFT in the peripheral portion. The integrated display portion-peripheral drive circuit portion-integrated active matrix substrate 30 can be manufactured.
[0168]
<Sixth Embodiment>
26 to 31 show a sixth embodiment of the present invention.
[0169]
In this embodiment, unlike the above-described embodiment, the gate electrode of the top gate portion is made of aluminum, an aluminum alloy, for example, 1% Si-containing aluminum, 1 to 2% copper-containing aluminum, copper or the like. It is made of a low material.
[0170]
First, when the top gate type MOS TFT is provided for both the display portion and the peripheral drive circuit portion, the steps from (1) in FIG. 1 to (5) in FIG. Then, as shown in (5) of FIG. 26, an N-type well 7A is formed in the pMOS TFT portion of the peripheral drive circuit portion.
[0171]
Next, as shown in FIG. 26 (6), the nMOS and pMOS TFT in the peripheral drive region and the gate portion of the nMOS TFT in the display region are covered with a photoresist 13, and phosphorus ions 14 are applied to the exposed source / drain regions of the nMOS TFT. For example, 5 × 10 at 20 kV ¹³ atoms / cm ² Doping (ion implantation) with a dose amount of N ^- An LDD portion 15 made of a mold layer is formed in a self-aligning manner.
[0172]
Next, as shown in FIG. 27 (7), the entire pMOS TFT in the peripheral drive region, the gate portion of the nMOS TFT in the peripheral drive region, and the gate and LDD portion of the nMOS TFT in the display region are covered with photoresist 16 and exposed. For example, phosphorus or arsenic ions 17 are applied at 20 kV to 5 × 10 ¹⁵ atoms / cm ² Of the nMOS TFT by doping (ion implantation) with a dose of ⁺ A source part 18 and a drain part 19 and an LDD part 15 made of a mold layer are formed. In this case, if the resist 13 is left like an imaginary line and the resist 16 is provided so as to cover the resist 13, the alignment of the mask at the time of forming the resist 16 can be used as a guide, the mask alignment becomes easy, and the alignment shifts. Less.
[0173]
Next, as shown in (8) of FIG. 27, the entire nMOS TFT in the peripheral drive region, the nMOS TFT in the display region, and the gate portion of the pMOS TFT are covered with a photoresist 20, and boron ions 21 are exposed to, for example, 10 kV at 5 kV. × 10 ¹⁵ atoms / cm ² Of pMOS TFT by doping (ion implantation) at a dose of ⁺ The source part 22 and the drain part 23 of the layer are formed.
[0174]
Next, after removing the resist 20, as shown in FIG. 27 (9), the single crystal silicon layers 7 and 7 A are activated in the same manner as described above, and the surface is further subjected to the gate insulating film 12 and the gate electrode material (aluminum). Alternatively, aluminum containing 1% Si or the like) 11 is formed. The gate electrode material layer 11 can be formed by vacuum deposition or sputtering.
[0175]
Next, in the same manner as described above, after patterning each gate portion, the active element portion and the passive element portion are formed into islands. Further, as shown in FIG. ₂ A protective film 25 is formed by continuously forming a film (about 200 nm thick) and a phosphorus silicate glass (PSG) film (about 300 nm thick) in this order on the entire surface.
[0176]
Next, as shown in (11) of FIG. 28, contact windows are opened in the source / drain portions of all TFTs of the peripheral drive circuit and the source portion of the display TFTs by general-purpose photolithography and etching techniques.
[0177]
Then, a sputtered film such as aluminum having a thickness of 500 to 600 nm or aluminum containing 1% Si is formed on the entire surface, and the peripheral drive circuit and the source electrode 26 and the peripheral drive circuit of all TFTs in the display unit are formed by general-purpose photolithography and etching techniques. At the same time as forming the drain electrode 27, the data line and the gate line are formed. After that, forming gas (N ₂ + H ₂ ) Is sintered at about 400 ° C./1 h.
[0178]
Next, similarly to (14) to (17) of FIG. 5, aluminum, 1% Si-containing aluminum, or the like is used as a gate electrode for the display portion and the peripheral driver circuit portion using the single crystal silicon layer 7, respectively. An active matrix substrate 30 integrated with a display portion-peripheral drive circuit portion in which a CMOS drive circuit composed of a top gate type nMOS LDD-TFT, pMOS TFT and nMOS TFT is formed can be produced.
[0179]
In this embodiment, since the gate electrode 11 such as aluminum or aluminum containing 1% Si is formed after the activation process of the single crystal silicon layer 7, the influence of heat during the activation process is affected by the heat resistance of the gate electrode material. Therefore, the gate electrode material has a relatively low heat resistance, and low-cost aluminum or aluminum containing 1% Si can be used. The same applies to the case where the display unit is a bottom gate type MOSTFT.
[0180]
Next, in the case where a dual gate type MOSTFT is provided in the display portion and the peripheral drive circuit is provided with a top gate type MOSTFT, the steps from (1) in FIG. 18 to (7) in FIG. In the same manner, as shown in FIG. 29 (7), an N-type well 7A is formed in the pMOS TFT portion of the peripheral drive circuit portion.
[0181]
Next, as shown in (8) of FIG. 29, in the same manner as in (6) of FIG. 26, the TFT portion of the display portion is doped with phosphorus ions 14 to form the LDD portion 15.
[0182]
Next, as shown in (9) of FIG. 30, the nMOS TFT portion of the display portion and the peripheral drive circuit portion is doped with phosphorus ions 17 in the same manner as (7) of FIG. ⁺ A type source region 18 and a drain region 19 are formed.
[0183]
Next, as shown in (10) of FIG. 30, boron ions 21 are doped into the pMOS TFT portion of the peripheral drive circuit portion in the same manner as (8) of FIG. ⁺ A type source region 22 and a drain region 23 are formed.
[0184]
Next, after removing the resist 20, as shown in (11) of FIG. 30, the single crystal silicon layer 7 is patterned to form islands of the active element portion and the passive element portion, and then as shown in (12) of FIG. Further, the single crystal silicon layers 7 and 7A are activated in the same manner as described above, and the gate insulating film 80 is formed on the surface in the display portion, and the gate insulating film 12 is formed on the surface in the peripheral driver circuit portion.
[0185]
Next, as shown in (13) of FIG. 31, aluminum formed by sputtering is patterned on the entire surface to form each upper gate electrode 83 in the display portion and each gate electrode 11 in the peripheral drive circuit portion.
[0186]
Next, as shown in FIG. ₂ A protective film 25 is formed by continuously forming a film (about 200 nm thick) and a phosphorus silicate glass (PSG) film (about 300 nm thick) in this order on the entire surface.
[0187]
Next, in the same manner as described above, the source electrode 26 of all the TFTs in the peripheral drive circuit and the display unit and the drain electrode 27 of the peripheral drive circuit unit are formed, and the display unit and the peripheral drive circuit using the single crystal silicon layer 7 are formed. A display unit-peripheral drive circuit unit integrated active matrix substrate 30 in which a CMOS drive circuit composed of dual gate nMOSLDD-TFT, pMOSTFT, and nMOSTFT using aluminum as a gate electrode is formed in each unit. it can.
[0188]
Also in this embodiment, since the gate electrodes 11 and 83 such as aluminum are formed after the activation process of the single crystal silicon layer 7, the influence of heat during the activation process is independent of the heat resistance of the gate electrode material. Therefore, heat resistance is relatively low as the gate electrode material, and low-cost aluminum, aluminum alloy, copper, or the like can be used, and the range of selection of the electrode material is widened. In addition, although the source electrode 26 (and also the drain electrode) can be formed at the same time in the step (13) of FIG. 31, there is a manufacturing advantage in this case.
[0189]
In any of the above-described embodiments, for example, when fabricating a bottom gate type or top gate type MOS TFT, as shown schematically in FIG. Since the crystalline silicon film 7 is thin, disconnection (connection failure) or thinning (increase in resistance) may occur. Therefore, in order to reliably connect the source electrode 26 (or drain electrode), FIG. As shown in B) and (C), it is desirable to deposit the electrode on the region including the step 4.
[0190]
Note that in the step of FIG. 26 (6) or the step of FIG. 29 (8), after the top gate insulating film is formed on the single crystal silicon layer 7, ion implantation and activation treatment are performed, and then the top gate electrode, The source and drain electrodes may be formed simultaneously with aluminum.
[0191]
Further, as shown in FIG. 33A, the above-described step 4 is formed on the substrate 1 (and also on a film such as SiN thereon) in the above-described example. For example, as shown in FIG. Thus, the SiN film 51 on the substrate 1 (which has a function of diffusing ions from the glass substrate 1) can also be formed. Instead of the SiN film 51 or on the SiN film, the gate insulating films 72 and 73 described above may be provided, and the step 4 may be formed thereon.
[0192]
<Seventh embodiment>
34 to 36 show a seventh embodiment of the present invention.
[0193]
In the present embodiment, various examples in which each TFT is formed outside the step 4 described above (that is, on the substrate 1 other than the step) will be described. Note that the single crystal silicon layer 7 and the gate / source / drain electrodes 26 and 27 are simply illustrated.
[0194]
First, FIG. 34 shows a top gate type MOS TFT. FIG. 34A shows a step 4 where a recess 4 is formed on one side of the source side along the source region, and on the single crystal silicon layer 7 on the substrate flat surface other than the recess. A gate insulating film 12 and a gate electrode 11 are formed. Similarly, (b) shows an example in which the concave portion 4 due to the step is formed in an L-shaped pattern over not only the source region but also the drain region end in the channel length direction, and (c) shows the same concave portion 4. An example is shown in which a rectangular shape is formed over four sides so as to surround the TFT active region. Moreover, (d) is an example in which the same concave portion 4 is formed over three sides, and (e) is an example in which the same concave portion 4 is formed in an L-shaped pattern over two sides. The recesses 4-4 are not continuous.
[0195]
As described above, the recesses 4 of various patterns can be formed, and the TFTs are provided on a flat surface other than the recesses 4, so that the TFTs can be easily manufactured.
[0196]
FIG. 35 shows the case of the bottom gate type MOSTFT, but the steps (or recesses) 4 of various patterns shown in FIG. 34 can be formed similarly. That is, FIG. 35A is an example corresponding to FIG. 34A, in which a bottom gate type MOS TFT is formed on a flat surface other than the recess 4 due to a step. Similarly, FIG. 35 (b) shows an example corresponding to FIG. 34 (b), and FIG. 35 (c) shows an example corresponding to FIGS. 34 (c) and (d).
[0197]
FIG. 36 shows a case of a dual gate type MOSTFT, but this can also form the step (or recess) 4 of various patterns shown in FIG. 34, for example, the step 4 shown in FIG. 34 (c). A dual gate type MOSTFT can be fabricated on the flat surface of the inner region of.
[0198]
<Eighth Embodiment>
37 to 39 show an eighth embodiment of the present invention.
[0199]
The example of FIG. 37 relates to a double gate type MOS TFT in which a plurality of TFTs having a self-aligned LDD structure, for example, a top gate type MOS LDD-TFT are connected.
[0200]
According to this, the gate electrode 11 is branched into two, and one is used for the first LDD-TFT as the first gate and the other is used for the second LDD-TFT as the second gate (however, N between the gate electrodes in the center of the single crystal silicon layer ⁺ A mold region 100 is provided to reduce resistance). In this case, a different voltage may be applied to each gate, and even if one of the gates becomes inoperable for some reason, the remaining gate can be used to move carriers between the source / drain. Therefore, a highly reliable device can be provided. In addition, since the thin film transistor for driving each pixel is formed by connecting the first LDD-TFT and the second LDD-TFT in series, the source of each thin film transistor is turned off. The voltage applied between the drains can be greatly reduced. Therefore, the leakage current that flows when turned off can be reduced, and the contrast and image quality of the liquid crystal display can be improved satisfactorily. Further, since the two LDD transistors are connected using only the same semiconductor layer as the lightly doped drain region in the LDD transistor, the connection distance between the transistors can be shortened. Even if two are connected, the required area can be prevented from becoming large. Note that the first and second gates described above can be completely separated from each other and operated independently.
[0201]
The example of FIG. 38 includes a bottom gate type MOSTFT having a double gate structure (A) and a dual gate type MOSTFT having a double gate structure (B).
[0202]
These double gate type MOSTFTs also have the same advantages as the top gate type described above, but in the case of the dual gate type, even if one of the upper and lower gate parts becomes inoperable, It is also an advantage that it can be used.
[0203]
FIG. 39 shows an equivalent circuit diagram of each of the double gate type MOS TFTs. In the above description, the gate is divided into two. However, the gate may be branched or divided into three or more. In these double gate or multi-gate structures, two or more branched gate electrodes having the same potential may be provided in the channel region, or divided gate electrodes having different potentials or the same potential may be provided.
[0204]
<Ninth embodiment>
FIG. 40 shows a ninth embodiment of the present invention. In a dual-gate TFT of nMOS TFT, one of the upper and lower gate portions is operated as a transistor, and the other gate portion is It works like this.
[0205]
That is, in FIG. 40A, in the nMOS TFT, an arbitrary negative voltage is always applied to the gate electrode on the top gate side to reduce the back channel leakage current. When the top gate electrode is opened, it is used as a bottom gate type. In FIG. 40B, an arbitrary negative voltage is always applied to the gate electrode on the bottom gate side to reduce the back channel leakage current. Also in this case, if the bottom gate electrode is opened, it can be used as a top gate type. In the case of a pMOS TFT, the back channel leakage current can be reduced by always applying an arbitrary positive voltage to the gate electrode.
[0206]
In either case, the interface between the single crystal silicon layer 7 and the insulating film has poor crystallinity and a leak current easily flows, but the leak current can be cut off by applying a negative voltage to the electrode as described above. This is advantageous in combination with the effect of the LDD structure. In addition, a leak current may flow due to light incident from the glass substrate 1 side, but since the light is blocked by the bottom gate electrode, the leak current can be reduced.
[0207]
<Tenth Embodiment>
41 to 49 show a tenth embodiment of the present invention.
[0208]
As described above, each of the top gate type, the bottom gate type, and the dual gate type TFT has a difference in structure or function or a feature, so when adopting them in the display unit and the peripheral drive circuit unit, It may be advantageous to provide various combinations of TFTs between these parts.
[0209]
For example, as shown in FIG. 41, when a top gate type, bottom gate type, or dual gate type MOSTFT is adopted for the display portion, the peripheral gate drive circuit has a top gate type MOSTFT, bottom gate type MOSTFT, dual gate type. Among the type MOS TFTs, at least the top gate type can be adopted, or they can be mixed. There are 12 combinations (No. 1 to No. 12). In particular, when a dual gate structure is used for the MOSTFT of the peripheral drive circuit, such a dual gate structure can be easily changed to a top gate type or a bottom gate type by selecting the upper and lower gate portions, When a TFT having a large driving capability is necessary for a part of the peripheral driving circuit, a dual gate type may be necessary. For example, it is considered necessary when the present invention is applied to an organic EL or FED as an electro-optical device other than an LCD.
[0210]
42 and 43 show the case where the MOST TFT of the display portion has no LDD structure, FIGS. 44 and 45 show the case where the MOS TFT of the display portion has an LDD structure, and FIGS. 48 and 49 show combinations of MOSTFTs of the peripheral drive circuit unit and the display unit according to the channel conductivity types in the case where both the peripheral drive circuit unit and the display unit include the MOSD of the LDD structure. Various examples (No. 1 to No. 216) are shown.
[0211]
Thus, the combinations according to gate structures shown in FIG. 41 are specifically as shown in FIGS. The same combination is possible even when the peripheral drive circuit section is composed of a MOSTFT in which a top gate type and other gate types are mixed. The various combinations of TFTs shown in FIGS. 41 to 49 are not limited to the case where the TFT channel region is formed of single crystal silicon, but are formed of polycrystalline silicon or amorphous silicon (however, only the display portion). The same applies to the case.
[0212]
<Eleventh embodiment>
50 to 51 show an eleventh embodiment of the present invention.
[0213]
In the present embodiment, in the active matrix drive LCD, the peripheral drive circuit portion is provided with the above-described TFT using the single crystal silicon layer based on the present invention from the viewpoint of improving the drive capability. However, this is not limited to the top gate type, and other gate types may be mixed, channel conductivity types may be various, and MOSTFTs using a polycrystalline silicon layer other than a single crystal silicon layer are included. It may be. On the other hand, it is desirable to use a monocrystalline silicon layer for the MOSTFT of the display portion, but the present invention is not limited to this, and a polycrystalline silicon or an amorphous silicon layer may be used, or at least three types of silicon layers may be used. Two types may be mixed. However, when the display portion is formed by an nMOS TFT, a practical switching speed can be obtained even if an amorphous silicon layer is used. However, a single crystal silicon or a polycrystalline silicon layer can reduce the TFT area and reduce pixel defects. This is also advantageous over amorphous silicon. In addition, not only single crystal silicon but also polycrystalline silicon is generated at the same time as the above-described grapho epitaxial growth, and so-called CGS (Continuous Grain Silicon) structure may be included, which is also used for forming active and passive elements. it can.
[0214]
FIG. 50 shows various combinations (A), (B), and (C) of MOSTFTs between the respective parts, and FIG. 51 illustrates specific examples thereof. When single crystal silicon is used, the current driving capability is improved, so that the element can be made smaller, the screen can be enlarged, and the aperture ratio is improved in the display portion.
[0215]
In the peripheral drive circuit section, it is needless to say that not only the above-mentioned MOS TFT but also an electronic circuit in which a diode, capacitance, resistance, inductance, etc. are integrated may be integrally formed on an insulating substrate (glass substrate or the like).
[0216]
<Twelfth embodiment>
FIG. 52 shows a twelfth embodiment of the present invention.
[0217]
In the present embodiment, each of the above-described embodiments is an example of active matrix driving, whereas the present invention is applied to passive matrix driving.
[0218]
That is, the display unit is not provided with a switching element such as the above-described MOSTFT, and incident light or reflected light of the display unit is dimmed only by a potential difference caused by a voltage applied between a pair of electrodes formed on the opposing substrate. Such light control elements include reflective and transmissive LCDs, organic EL (electroluminescence display elements), FED (field emission display elements), LEPD (light emitting polymer display elements), LEDs (light emitting diode display elements). ) Etc. are also included.
[0219]
<Thirteenth embodiment>
FIG. 53 shows a thirteenth embodiment of the present invention.
[0220]
In this embodiment, the present invention is an organic or inorganic EL (electroluminescence display element), FED (field emission display element), LEPD (generated polymer display element), LED (light emitting diode) which is an electro-optical device other than an LCD. Display element).
[0221]
That is, FIG. 53A shows an active matrix driving EL element, for example, an organic EL layer using an amorphous organic compound (or an inorganic EL layer using ZnS: Mn) 90 is provided on the substrate 1, The transparent electrode (ITO) 41 described above is formed in the lower part, the cathode 91 is formed in the upper part, and light emission of a predetermined color is obtained through the filter 61 by applying a voltage between these two electrodes.
[0222]
At this time, in order to apply a data voltage to the transparent electrode 41 by active matrix driving, a single crystal silicon MOSTFT according to the present invention using a single crystal silicon layer that is grapho epitaxially grown using the step 4 on the substrate 1 as a seed (that is, nMOSLDD-TFT) is formed on the substrate 1. Similar TFTs are also provided in the peripheral drive circuit. Since this EL element is driven by a MOSLDD-TFT using a single crystal silicon layer, the switching speed is high and the leakage current is small. The filter 61 can be omitted if the EL layer 90 emits a specific color.
[0223]
In the case of an EL element, since the drive voltage is high, it is advantageous to provide a high-breakdown-voltage driver element (such as a high-breakdown-voltage cMOS TFT and a bipolar element) in the peripheral drive circuit unit in addition to the above-described MOSTFT.
[0224]
FIG. 53B shows a passive matrix drive FED. In a vacuum portion between opposing glass substrates 1-32, electrons emitted from the cold cathode 94 by a voltage applied between both electrodes 92-93 are gate lines. By entering 95, the light is made incident on the facing phosphor layer 96 to obtain light emission of a predetermined color.
[0225]
Here, the emitter line 92 is guided to a peripheral drive circuit and driven by a data voltage. The peripheral drive circuit is provided with a MOS TFT using a single crystal silicon layer according to the present invention. This contributes to high-speed driving. The FED can be driven in an active matrix by connecting the above-described MOS TFT to each pixel.
[0226]
Note that in the element of FIG. 53A, when a known light-emitting polymer is used instead of the EL layer 90, a light-emitting polymer display device (LEPD) driven by a passive matrix or an active matrix can be formed. In addition, in the element of FIG. 53B, a device similar to an FED using a diamond thin film on the cathode side can be configured. In a light emitting diode, a light emitting part made of, for example, a gallium-based (gallium, aluminum, arsenic, etc.) film can be driven by a single crystal silicon MOS TFT epitaxially grown on the light emitting part according to the present invention. Alternatively, it is conceivable to grow a single crystal of the light emitting portion film by the epitaxial growth method of the present invention.
[0227]
The embodiment of the present invention described above can be variously modified based on the technical idea of the present invention.
[0228]
For example, a low-melting-point metal melt, such as boron, phosphorus, antimony, arsenic, aluminum, gallium, indium, or bismuth, is used as a trivalent or pentavalent element having high solubility when the above-described low-melting-point metal melt 6 is applied. If a suitable amount is doped to 6, the P-type or N-type channel conductivity type of the silicon epitaxial growth layer 7 to be grown and its carrier concentration can be arbitrarily controlled.
[0229]
In addition, in order to prevent diffusion of ions from the glass substrate, a SiN film (for example, 50 to 200 nm thick) is formed on the substrate surface, and further, if necessary SiO ₂ Films (for example, 100 nm thick) may be provided, and the step 4 as described above may be formed in these films. The steps described above can be formed by ion milling or the like other than RIE.
[0230]
In addition, the present invention is suitable for a peripheral drive circuit TFT, but other than that, an active region of an element such as a diode and a passive region such as a resistor, a capacitance, and an inductance are formed of a single crystal silicon layer according to the present invention. It is also possible to do.
[0231]
[Effects of the invention]
According to the present invention, a low-melting-point metal melt in which silicon is dissolved using the step formed on the substrate as a seed. Apply this melt A single crystal semiconductor layer such as a single crystal silicon thin film layer formed by silicon epitaxial growth is formed by deposition of single crystal silicon from the substrate, and this is formed on the top of the peripheral drive circuit portion of an electro-optical device such as a display-peripheral drive circuit integrated LCD. Since it is used for at least an active element such as an active element such as a gate type MOSTFT and a passive element, the following significant effects (A) to (F) can be obtained.
[0232]
(A) A step having a predetermined shape / dimension is formed on the substrate, and the bottom corner of the step is used as a seed to perform graphoepitaxial growth, thereby 540 cm. ² Since a single crystal semiconductor layer such as a single crystal silicon thin film having a high electron mobility of / v · sec or more can be obtained, an electro-optical device such as a display thin film semiconductor device with a built-in high performance driver can be manufactured.
[0233]
(B) In particular, the single crystal silicon top gate type MOS TFT with the single crystal silicon thin film has a high switching characteristic, an nMOS or pMOS or cMOS TFT display portion having an LDD structure, and a high driving capacity cMOS, nMOS or pMOS TFT. Alternatively, a configuration in which a peripheral driving circuit made of a mixture of these can be integrated, and a display panel with high image quality, high definition, a narrow frame, high efficiency, and a large screen is realized.
[0234]
(C) Since the above-described melt layer of low melting point metal is prepared at a low temperature and can be formed by coating on a substrate heated to a temperature slightly higher than this, a silicon single crystal film is uniformly formed at a relatively low temperature. be able to.
[0235]
(D) Since long-term annealing at high temperatures and excimer laser annealing as in the case of the solid phase growth method are not required, productivity is high, expensive manufacturing equipment is not required, and cost can be reduced.
[0236]
(E) In this grapho epitaxial growth, the composition ratio of the low melting point metal melt (especially silicon / indium / gallium composition ratio, silicon / indium composition ratio), substrate heating temperature, melt temperature, cooling rate, etc. can be adjusted to adjust the wide range. Since a single crystal silicon thin film having a high P-type impurity concentration and high mobility can be easily obtained, Vth adjustment is easy, and high-speed operation is possible due to low resistance.
[0237]
(F) Further, when a silicon-containing low-melting-point metal layer is formed, if an appropriate amount of a highly soluble Group 3 or Group 5 impurity element (boron, phosphorus, antimony, arsenic, bismuth, aluminum, etc.) is doped, It is possible to arbitrarily control the impurity species and / or the concentration of the single crystal silicon thin film by grapho epitaxial growth, that is, the P-type / N-type conductivity type and / or the carrier concentration.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a manufacturing process of an LCD (liquid crystal display device) according to a first embodiment of the present invention in the order of steps.
FIG. 2 is a sectional view showing the manufacturing process of the LCD in the order of steps.
FIG. 3 is a cross-sectional view showing the manufacturing process of the LCD in the order of steps.
FIG. 4 is a cross-sectional view showing the manufacturing process of the LCD in the order of steps.
FIG. 5 is a sectional view showing the manufacturing process of the LCD in the order of steps.
6 is a cross-sectional view showing the manufacturing process of the LCD in the order of steps. FIG.
FIG. 7 is a cross-sectional view of the main part of the LCD.
FIG. 8 is a schematic perspective view for explaining a situation of silicon crystal growth on an amorphous substrate.
FIG. 9 is a schematic cross-sectional view showing various step shapes and silicon growth crystal orientations in the grapho epitaxial growth technique.
FIG. 10 is a Si—In phase diagram (A) and a Si—Ga phase diagram (B).
FIG. 11 is a perspective view showing an overall schematic layout of the LCD according to the first embodiment of the present invention.
FIG. 12 is an equivalent circuit diagram of the LCD.
FIG. 13 is a schematic configuration diagram of the LCD.
FIG. 14 is a cross-sectional view showing a manufacturing process of the LCD according to the second embodiment of the present invention in the order of steps.
FIG. 15 is a sectional view of the principal part of the LCD.
FIG. 16 is a cross-sectional view showing the manufacturing process of the LCD in the order of steps.
FIG. 17 is a cross-sectional view of main parts of an LCD according to a fifth embodiment of the present invention.
FIG. 18 is a cross-sectional view showing the manufacturing process of the LCD in the order of steps.
FIG. 19 is a cross-sectional view showing the manufacturing process of the LCD in the order of steps.
FIG. 20 is a cross-sectional view showing the manufacturing process of the LCD in the order of steps.
FIG. 21 is a cross-sectional view showing the manufacturing process of the LCD in the order of steps.
FIG. 22 is a cross-sectional view showing the manufacturing process of the LCD in the order of steps.
FIG. 23 is a cross-sectional view showing the manufacturing process of the LCD in the order of steps.
FIG. 24 is a cross-sectional view showing the manufacturing process of the LCD in the order of steps.
FIG. 25 is a cross-sectional view showing the manufacturing process of the LCD in the order of steps.
FIG. 26 is a cross-sectional view showing the manufacturing process of the LCD according to the sixth embodiment of the present invention in the order of steps.
FIG. 27 is a cross-sectional view showing the manufacturing process of the LCD in the order of steps.
FIG. 28 is a cross-sectional view showing the manufacturing process of the LCD in the order of steps.
FIG. 29 is a cross-sectional view showing the manufacturing process of the LCD in the order of steps.
FIG. 30 is a cross-sectional view showing the manufacturing process of the LCD in the order of steps.
FIG. 31 is a cross-sectional view showing the manufacturing process of the LCD in the order of steps.
FIG. 32 is a cross-sectional view of the principal part at the time of manufacturing the LCD in the same case.
FIG. 33 is a cross-sectional view of the principal part at the time of manufacturing the LCD of the same.
FIG. 34 is a plan view or a cross-sectional view showing various TFTs of an LCD according to a seventh embodiment of the present invention.
FIG. 35 is a cross-sectional view showing various TFTs of the LCD.
FIG. 36 is a cross-sectional view of the principal part of the LCD.
FIG. 37 is a cross-sectional view or plan view of main parts of an LCD according to an eighth embodiment of the present invention.
FIG. 38 is a cross-sectional view of main parts of various TFTs of the LCD.
FIG. 39 is an equivalent circuit diagram of the TFT of the LCD.
FIG. 40 is a cross-sectional view of the principal part of the TFT of the LCD according to the ninth embodiment of the present invention.
FIG. 41 is a diagram showing combinations of TFTs of respective parts of the LCD according to the tenth embodiment of the present invention.
FIG. 42 is a diagram showing combinations of TFTs of each part of the LCD.
FIG. 43 is a diagram showing a combination of TFTs of each part of the LCD.
44 is a diagram showing a combination of TFTs of each part of the LCD. FIG.
45 is a diagram showing a combination of TFTs of each part of the LCD. FIG.
FIG. 46 is a diagram showing combinations of TFTs in each part of the LCD.
47 is a diagram showing a combination of TFTs of each part of the LCD. FIG.
FIG. 48 is a diagram showing a combination of TFTs of each part of the LCD.
FIG. 49 is a diagram showing a combination of TFTs of each part of the LCD.
FIG. 50 is a schematic layout diagram of an LCD according to an eleventh embodiment of the present invention.
FIG. 51 is a diagram showing a combination of TFTs of each part of the LCD.
FIG. 52 is a schematic layout diagram of a device according to a twelfth embodiment of the present invention.
FIG. 53 is a sectional view showing the main parts of an EL and an FED according to a thirteenth embodiment of the present invention.
[Explanation of symbols]
1 ... Glass (or quartz) substrate, 4 ... Step,
6: Indium (or indium gallium or gallium) melt,
6A: Indium (or indium gallium or gallium),
7 ... single crystal silicon layer, 9 ... Mo-Ta layer, 11 ... gate electrode,
12 ... Gate oxide film, 14, 17 ... N-type impurity ions, 15 ... LDD portion,
18, 19 ... N ⁺ Type source or drain region, 21... P type impurity ions,
22, 23 ... P ⁺ Type source or drain region, 25, 36 ... insulating film,
26, 27, 31, 41 ... electrode, 28 ... flattened film, 28A ... rough surface (unevenness),
29 ... reflective film (or electrode), 30 ... LCD (TFT) substrate,
33, 34 ... alignment film, 35 ... liquid crystal, 37, 46 ... color filter layer,
43 ... Black mask layer

Claims (5)

A display unit on which pixel electrodes are arranged and a peripheral drive circuit unit arranged on the periphery of the display unit are provided on a first substrate, and a predetermined region is provided between the first substrate and the second substrate. In a method of manufacturing an electro-optical device that includes an optical material,
Forming a step on one surface of the first substrate;
On the first substrate including the recess due to the step, silicon is contained and indium,
Forming a melt layer of a low-melting-point metal composed of at least one selected from the group consisting of gallium, tin, bismuth, lead, zinc, antimony and aluminum by coating;
Then, the silicon of the melt layer is subjected to a graphoepitaxial growth with the step as a seed by a cooling process to deposit a single crystal silicon layer;
A method of manufacturing an electro-optical device, comprising: performing a predetermined process on the single crystal silicon layer to form at least an active element among active elements and passive elements. After deposition of the single crystal silicon layer,
Applying a predetermined treatment to the single crystal silicon layer to form a channel region, a source region, and a drain region;
2. The electro-optical device according to claim 1, further comprising: forming a top gate-type first thin film transistor that forms at least a part of the peripheral drive circuit portion by forming a gate portion above the channel region. Manufacturing method.   The method of manufacturing an electro-optical device according to claim 2, wherein a switching element for switching the pixel electrode in the display unit is provided on the first substrate. The first thin film transistor is at least a top gate type selected from a top gate type, a bottom gate type, or a dual gate type having a gate portion above and / or below a channel region, and as the switching element, 4. The method of manufacturing an electro-optical device according to claim 3 , wherein the top gate type, the bottom gate type, or the dual gate type second thin film transistor is formed. In a method for manufacturing a drive substrate for an electro-optical device having a display unit on which a pixel electrode is disposed and a peripheral drive circuit unit disposed on the periphery of the display unit on the substrate,
Forming a step on one surface of the substrate;
On the substrate including the concave portion by the step, containing silicon and indium, Gallium, tin, bismuth, lead, zinc, the melt of the low melting point metal consisting of at least one selected from the group consisting of antimony and aluminum Forming a layer by coating;
Then, the silicon of the melt layer is subjected to a graphoepitaxial growth with the step as a seed by a cooling process to deposit a single crystal silicon layer;
A method of manufacturing a drive substrate for an electro-optical device, comprising: performing a predetermined treatment on the single crystal silicon layer to form at least an active element among active elements and passive elements.

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