JP2002203972A - Thin film transistor array and liquid crystal display comprising it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor array, and a liquid crystal display comprising it, in which reliability of an n-channel thin film transistor is enhanced under a voltage stress by preventing generation of movable ions in the gate electrode and the lifetime can be prolonged by enhancing reliability of a peripheral drive circuit formed on a substrate. SOLUTION: The n-channel thin film transistor has a lightly doped (LDD) region 13b between a channel region 13a and a source 13c or drain region 13d. A gate electrode formed on the n-channel thin film transistor contains no boron nor phosphorus whereas a gate electrode formed on a p-channel thin film transistor does not contain phosphorus but contains boron.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a polycrystalline silicon thin film transistor (hereinafter abbreviated as TFT) and a liquid crystal display device using the same.

[0002]

2. Description of the Related Art FIGS. 6A to 6D and FIGS.
(G) As a conventional example, an example of a method of manufacturing a complementary metal oxide semiconductor (C-MOS) active matrix array for a liquid crystal display device using polycrystalline silicon for an active layer will be described. FIGS. 6A to 7G show a series of steps.

[0003] As shown in FIG.
An amorphous silicon thin film 10 is formed on a (high heat resistant glass substrate) by a plasma vapor deposition method (PCVD method), and is subjected to a heat treatment at 450 ° C. in a nitrogen atmosphere to reduce the hydrogen concentration in the amorphous silicon thin film. I do. Thereafter, the amorphous silicon thin film is crystallized by excimer laser irradiation to form a polycrystalline silicon thin film 13 serving as an active layer. Next, as shown in FIG. 6B, the polycrystalline silicon thin film is processed into an island shape to form a silicon oxide thin film to be the gate insulating film 14. A gate electrode 15 made of a Mo—W alloy is formed on the silicon oxide thin film 14. After the formation of the gate electrode, first impurity implantation is performed by ion implantation using the gate electrode as a mask to form a low-concentration impurity implantation region (n ⁻ region) 13b. Phosphorus (P) ions are implanted as a first impurity implantation at an accelerating voltage of 80
KV is implanted at a dose of 3 × 10 ¹³ / cm ² . After the first impurity implantation, as shown in FIG. 6C, after an implantation mask using a photoresist 25 is formed on the n-channel thin film transistor, boron ions are increased to form source and drain regions of the p-channel thin film transistor. Implanted to a concentration (p ⁺ region): 13d is formed. Boron (B) ions are implanted at an acceleration voltage of 70 KV and a dose of 8 × 10 ¹⁴ / cm ² . Thereafter, as shown in FIG. 6D, the photoresist 25 is applied to the n-channel LDD region of the thin film transistor and the p-channel thin film transistor by the photoresist 25.
After forming an implantation mask using No. 5, phosphorus ions are implanted at a high concentration to form the source and drain regions of the n-channel thin film transistor (n ⁺ region) 13c. Phosphorus (P) ion has an acceleration voltage of 80 KV and a dose of 1 × 1
Inject at 0 ¹⁵ / cm ² .

After ion implantation, the photoresist mask is removed, and the implanted impurities are activated. The activation treatment is performed at 600 ° C. for 2 hours. After the activation process, FIG.
The interlayer insulating film 16 is formed as shown in FIG. After forming an interlayer insulating film made of silicon oxide, a contact hole is opened, and then source / drain electrodes 20 and 21 are formed. After forming the source and drain electrodes, a protective insulating film made of the silicon nitride thin film 23 is formed. Finally, a heat treatment is performed at 400 ° C. for 2 hours in a hydrogen atmosphere to diffuse hydrogen in the silicon nitride thin film into the polycrystalline silicon film and compensate (crystallize) crystal defects in the film, thereby completing the thin film transistor. 7 (f)). Thereafter, a contact hole is opened in the silicon nitride thin film on the storage capacitor portion, and a light transmitting film 24 made of an organic material is applied to flatten the thin film transistor array. After the flattening film is applied, the display electrode 26 made of ITO is used.
Is formed to complete an active matrix array for a liquid crystal display device (FIG. 7 (g)).

[0005]

A thin film transistor using polycrystalline silicon as an active layer has a high electron mobility and can form a part or all of a peripheral driving circuit on the same substrate. Development is active. However, since the peripheral driver circuit section has a function realized by a conventional LSI on a glass substrate, a polycrystalline silicon thin film transistor is required to have high reliability equivalent to that of the LSI. However, the reliability of the polycrystalline silicon thin film transistor is still not enough to be comparable to that of an LSI, and securing the reliability of the peripheral drive circuit is a major issue. As a cause of the reliability deterioration of the n-channel thin film transistor, there is a problem that movable ions in the gate electrode move into the gate insulating film under bias stress and cause a threshold shift. As shown in the conventional example, three times of impurity implantation (ion doping) steps are generally used in the process of manufacturing an active matrix array used for a liquid crystal display device with a built-in drive circuit using polycrystalline silicon for an active layer. Aluminum (Al), chromium (Cr), molybdenum (Mo),
Generally, a metal material having a crystal structure such as tungsten (W), copper (Cu), or an alloy thereof is used. By implanting ions at a high energy into the metal material having such a crystal structure, the crystal structure in the metal material is broken, and mobile (metal) ions are generated in the gate electrode material. In particular, when these mobile ions are formed on the n-channel thin film transistor, the reliability of the thin film transistor under bias stress is greatly reduced.

The present invention solves the above-mentioned conventional problems by preventing the generation of mobile ions in a gate electrode, thereby improving the reliability of an n-channel thin film transistor under voltage stress, and forming the n-channel thin film transistor on a substrate. It is another object of the present invention to provide a thin film transistor array capable of improving the reliability of a peripheral drive circuit and having a longer life, and a liquid crystal display device using the same.

[0007]

In order to achieve the above object, an active matrix array for a liquid crystal display device according to the present invention comprises an n-type thin film transistor and a p-type thin film transistor using a polycrystalline silicon thin film as an active layer on a light-transmitting substrate. In a thin film transistor array integrated on the same substrate,
The n-channel thin film transistor includes a low-concentration impurity implantation (LDD) region in which a low-concentration impurity is introduced between a channel region and a source or drain region, and a gate electrode formed on the n-channel thin film transistor includes boron and phosphorus. It does not contain, and the gate electrode formed on the p-channel thin film transistor contains boron without containing phosphorus.

The liquid crystal display device of the present invention uses a complementary metal oxide semiconductor (C-MOS) using polycrystalline silicon for an active layer.
In a liquid crystal display device with a built-in drive circuit in which a drive circuit having the above configuration is integrated on the same substrate, the active matrix array is used.

[0009]

In the present invention, the thin film transistor has a top gate structure, and contains phosphorus in the source and drain regions and the low concentration impurity implantation (LDD) region of the n-channel thin film transistor. The source and drain regions preferably contain phosphorus and boron. This is because a circuit having a complementary metal oxide semiconductor (C-MOS) configuration is formed. Here, the low concentration impurity implantation (LDD) region refers to a region having a sheet resistance of 5 to 100 kΩ / □.

It is preferable that the gate electrode of the active matrix array is made of a metal material having a crystal structure. This is for reducing the wiring resistance.

It is preferable that the gate electrode material is made of a material containing molybdenum as a main component. High heat resistance,
This is because the resistance is low.

Further, the concentration of boron contained in the gate electrode of the p-channel thin film transistor is 5 × 10 ¹³ / cm ²
It is preferably in the range of 1 × 10 ¹⁶ / cm ² or less.
This is because the p-channel thin film transistor uses the gate electrode as a mask to form source / drain regions in a self-aligned manner.

Preferably, the concentration of hydrogen contained in the gate electrode of the p-channel thin film transistor is at least five times the concentration of hydrogen contained in the gate electrode of the n-channel thin film transistor. This is because ions generated by plasma decomposition of the B ₂ H ₆ / H ₂ gas are implanted without mass separation using an ion doping method.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) An example of a method of manufacturing an active matrix array for a liquid crystal display device having a C-MOS structure according to the present invention will be described with reference to FIGS. 1 (a) to 1 (d) and 2 (e). ~ (G)
This will be described with reference to FIG. FIGS. 1A to 2G show a series of steps.

As shown in FIG. 1A, an amorphous silicon thin film 10 is formed on a light-transmitting substrate 11 (high heat-resistant glass substrate) by a plasma vapor deposition method (PCVD method). Heat treatment at 450 ° C was performed to reduce the hydrogen concentration in the amorphous silicon thin film. Thereafter, the amorphous silicon thin film was crystallized by excimer laser irradiation to form a polycrystalline silicon thin film 13 serving as an active layer. The polycrystalline silicon thin film was processed into an island shape to form a silicon oxide thin film serving as a gate insulating film: 14. Next, a gate electrode is formed on the silicon oxide thin film. The gate electrode is formed by processing a Mo-W alloy (W ratio: 35%) by dry etching, and comprises SF ₆ (sulfur hexafluoride) and O _2. (Induced Coup) using mixed gas of
led Plasma) dry etching SF ₆ / O ₂ = 300/1
Etching was performed at 0 ccm, a pressure of 9.3 Pa (70 mTorr), an ICP power of 1.5 W / cm ² , and a bias power of 0.2 W / cm ² . After the etching, as shown in FIG. 1B, a first impurity implantation was performed by ion doping while leaving the photoresist, thereby forming a low-concentration impurity implantation region (n ⁻ region): 13b. In the first impurity implantation, phosphorus (P) ions were implanted at an acceleration voltage of 80 KV and a dose of 3 × 10 ¹³ / cm ² . In the present invention, since the first phosphorous ion implantation is performed with the photoresist left on the gate electrode, it is possible to prevent phosphorous ions from being implanted into the gate electrode. Further, since dry etching is used for processing the gate electrode, an undercut in which the gate electrode enters under the photoresist during the processing of the gate electrode can be prevented. Therefore, it is possible to prevent the formation of an offset region in which impurities are not implanted into the thin film transistor even when the photoresist is implanted while the photoresist is left during ion doping. After the first impurity (phosphorus) implantation, as shown in FIG.
An implantation mask using a photoresist was formed on the n-channel thin film transistor, and boron ions were implanted at a high concentration for forming source and drain regions of the p-channel thin film transistor (p ⁺ region): 13d. Boron (B) ions have an acceleration voltage of 70 KV and a dose of 8 × 10 ¹⁴ / cm
Injected at ² . At this time, since a resist mask was not formed on the p-channel thin film transistor and boron ions were implanted in a self-alignment manner using the gate electrode, boron and hydrogen ions were implanted into the gate electrode on the p-channel thin film transistor. After that, as shown in FIG.
After an implantation mask using a photoresist was formed on the D region and on the p-channel thin film transistor, phosphorus ions were implanted at a high concentration (n ⁺ region): 13c to form the source and drain regions of the n-channel thin film transistor. Phosphorus (P) ions were implanted at an acceleration voltage of 80 KV and a dose of 1 × 10 ¹⁵ / cm ² . After the ion implantation, the photoresist mask was removed, and the implanted impurities were activated. The activation treatment was performed by a heat treatment in a hydrogen atmosphere at 600 ° C. for 1 hour. This activation treatment was performed using a batch-type heat treatment furnace. When the temperature in the furnace reached 300 ° C. in the temperature decreasing process after the treatment, high-frequency power was applied and hydrogen plasma was generated for one hour, and then taken out. . After the activation process, an interlayer insulating film 16 was formed as shown in FIG. Silicon oxide formed by a plasma CVD method was used for the interlayer insulating film of this example. The silicon oxide film was formed by using a mixed gas of TEOS and oxygen at a flow ratio of 1:50, a substrate temperature of 300 ° C., and a discharge power of 1 W / cm ² . After forming the interlayer insulating film, a contact hole was opened by dry etching. The contact hole uses a mixed gas of carbon tetrafluoride (CF ₄ ) and carbon trifluoride (CHF ₃ ), CF ₄ / CHF ₃ = 100/400 ccm, degree of vacuum 13.3 Pa (100 mTorr), discharge power 1.2 W / cm. Etched with ² . After the opening of the contact hole, the source / drain electrodes 20, 2 in which aluminum (Al) is laminated
1 was formed (FIG. 2F). After the formation of the source and drain electrodes, a protective insulating film made of a silicon nitride thin film (400 nm) is formed by a plasma CVD method, and heated at 350 ° C. in a hydrogen atmosphere at 1 ° C.
Heat treatment was performed for a long time to complete the thin film transistor (FIG. 2 (g)). Thereafter, a contact hole was opened in the silicon nitride thin film on the storage capacitor portion, and a light transmitting film 24 made of an organic material was applied to flatten the thin film transistor array.
After the flattening film was applied, a display electrode 26 made of an indium tin oxide alloy (ITO) was formed to complete an active matrix array for a liquid crystal display device.

As shown in the present invention, the manufacturing process of the active matrix array has three impurity implantation steps. In these three impurity implantation steps, the gate electrode on the p-channel thin film transistor is formed by forming the n-channel thin film transistor. At this time, the phosphorus ions are masked, but boron ions are implanted when the p-channel thin film transistor is formed. On the other hand, the gate electrode on the n-channel thin film transistor is covered with a photoresist mask in all the implantation steps. As a result, the gate electrode is not only implanted with ions such as phosphorus or boron, but also has a sufficient blocking ability against hydrogen implanted by the ion doping process if the photoresist film thickness is 1 μm or more. Can be prevented from being injected. As a result, no impurity was implanted into the gate electrode on the n-channel thin film transistor, and the crystal structure of the gate electrode was not changed by the impurity implantation, thereby preventing the reliability of the n-channel thin film transistor from being adversely affected.

(Embodiment 2) Next, another example of a method of manufacturing an active matrix array for a C-MOS liquid crystal display device of the present invention will be described with reference to FIGS. 3 (a) to 4 (g).

As shown in FIG. 3A, the transparent substrate 11
Plas amorphous silicon thin film on (high heat resistant glass substrate)
Formed by vapor phase epitaxy (PCVD)
In amorphous silicon thin film by heat treatment at 450 ℃
The concentration was reduced. After that, by excimer laser irradiation
Polycrystalline silicon which crystallizes amorphous silicon thin film and becomes active layer
A thin film 13 was formed. Converting the polycrystalline silicon thin film to an island
After processing into the shape, as shown in FIG.
DD and channel region and p-channel thin film transformer
An injection mask using photoresist was formed on the resister.
After that, the source and drain of the n-channel thin film transistor
Phosphorous ions are implanted at a high concentration to form an⁺Territory
Region 13c was formed. Phosphorus (P) ion has an accelerating voltage of 15 KV,
Dose 5 × 10¹⁴/cm^TwoWas injected. Phosphorus ion implantation
After that, the photoresist mask is removed and the gate insulating film 14 is removed.
Silicon oxide thin film formed by plasma CVD
did. A gate made of a Mo-W alloy on the silicon oxide thin film
The electrode 15 was formed. Gate electrode is dry-etched
Mo-W is processed and formed by SF.₆(Sulfur hexafluoride)
And O _Two(Induced Coupled Plasma) using mixed gas of
SF by dry etching method ₆/ O_Two= 300 / 10ccm, pressure 93mP
a (70mTorr), ICP power 1.5W / cm^Two, Bias power 0.2W / cm ^Two
Ion with the photoresist etched and left
Phosphorus ions are implanted by the doping method to form LDD regions (n^-region)
13b was formed (FIG. 3 (c)). Phosphorus for LDD region formation
(P) ions at an accelerating voltage of 80 KV and a dose of 3 × 10¹³/cm^Two
Was injected. In the present invention, phosphorus for forming LDD regions is used.
Leave the photoresist on the gate electrode during ion implantation
Impurities, such as phosphorus ions and water
Element ions) can be prevented from being implanted. Again
Since dry etching is used to process the gate electrode,
The gate electrode is under the photoresist when processing the gate electrode
Since the undercut that enters can be prevented,
Even if the photoresist is injected while leaving the photoresist at the time of
Offset regions where impurities are not implanted into transistors
It is not formed, and the deterioration of the characteristics of the thin film transistor can be prevented.
You. After phosphorus ion implantation for the purpose of LDD region formation, Fig. 3 (d)
As shown in FIG.
An implantation mask using photoresist on the transistor
Forming the source and drain of the p-channel thin film transistor.
Boron ions are implanted at a high concentration to form a rain region.⁺
Region 13d was formed. Boron (B) ion is accelerating voltage
70KV, dose 8 × 10¹⁴/cm^TwoWas injected. At this time
Form a resist mask on p-channel thin film transistor
Without implanting boron ions in a self-aligned manner using the gate electrode.
The gate on the p-channel thin film transistor.
The electrodes were implanted with boron and hydrogen ions.

After boron ion implantation, the photoresist
The impurities were removed, and the implanted impurities were activated. Activity
Treatment is performed in a hydrogen atmosphere by heat treatment at 600 ° C for 1 hour.
Was. This activation treatment uses a batch type heat treatment furnace.
When the furnace temperature reaches 300 ° C during the cooling process,
For 1 hour in a state where hydrogen plasma is generated by applying microwave power
After holding it, I took it out. After the activation process, as shown in FIG.
As described above, the interlayer insulating film 16 was formed. In this embodiment
Silicon oxide formed by plasma CVD is used for the edge film
Was. Silicon oxide film is formed by tetraethoxyoxysilicon.
Flow rate ratio of mixed gas of TEOS and oxygen 1:50, substrate
Temperature 300 ° C, discharge power 1W / cm^TwoFormed. Interlayer insulating film
After formation, open contact holes by dry etching
did. Dry etching is carbon tetrafluoride (CF_Four) And carbon trifluoride
Raw (CHF_Three), CF_Four/ CHF_Three= 100 /
400 ccm, vacuum degree 0.75 Pa (100 mTorr), discharge power 1.2 W
/cm ^TwoEtched. After opening the contact hole,
Aluminum (Al) on source (Ti) thin film
Rain electrodes 20 and 21 were formed (FIG. 4F). Sauce
After the formation of the drain and drain electrodes, the silicon nitride
Form a protective insulating film consisting of a capacitor thin film (400 nm)
Heat treatment at 350 ° C for 1 hour in ambient air
Completed. Then, the silicon nitride thin film on the storage capacitor
The contact hole is opened in the transparent material made of organic material
Apply film 24 to flatten thin film transistor array
Was. After the flattening film is applied, the display electrode 26 made of ITO is formed.
To form an active matrix array for a liquid crystal display.
It was completed (FIG. 4 (g)).

As shown in the present invention, the manufacturing process of the active matrix array has three impurity implantation steps. Among them, the phosphorus ion implantation for forming the n ⁺ region is performed before the formation of the gate electrode. Subsequent to the formation of the electrode, impurity implantation is substantially performed twice. In the two impurity implantation steps, the gate electrode on the n-channel thin film transistor is entirely covered with the photoresist mask, so that no impurity is implanted into the gate electrode. Phosphorous ions for the purpose of formation are masked with a photoresist, but when forming a p-channel thin film transistor, boron ions are implanted into the gate electrode because boron ions are implanted in a self-aligned manner using the gate electrode as a mask. Is done. As a result, the impurity was not implanted into the gate electrode on the n-channel thin film transistor, and the crystal structure of the gate electrode material was not changed by the impurity implantation, thereby preventing the reliability of the n-channel thin film transistor from being adversely affected.

(Embodiment 3) FIG. 5 is an example of a sectional view of a liquid crystal display device using an active matrix array according to the present invention, in which a pixel portion is enlarged and displayed. Active matrix formed on translucent substrate 11 and counter substrate 4
3, a liquid crystal 47 is held via an alignment film 46, and the pixel electrode 1 is formed by using a thin film transistor as a switching element.
7 is driven to charge the liquid crystal and display an image. The reliability of the n-channel thin film transistor under the voltage stress is greatly improved in the thin film transistor array of the present invention as compared with the thin film transistor array manufactured by the conventional manufacturing method, and the operation reliability of the peripheral drive circuit using the thin film transistor is improved. Has been greatly improved, and a long-life liquid crystal display device has been realized.

[0023]

As shown in the present invention, in the impurity implantation step used for the liquid crystal display device, the impurity is not implanted into the gate electrode on the n-channel thin film transistor. The crystal structure is not destroyed by ion damage, and as a result, generation of mobile ions in the gate electrode can be prevented. As a result, the reliability of the n-channel thin film transistor under voltage stress is improved, and the reliability of the peripheral driving circuit formed on the same substrate of the liquid crystal display device is improved by using the thin film transistor, and the life of the liquid crystal display device can be extended.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views showing the steps of a first embodiment of the thin film transistor array of the present invention.

FIGS. 2 (e) to 2 (g) are cross-sectional views showing the steps of a first embodiment of the thin film transistor array of the present invention.

FIGS. 3A to 3D are cross-sectional views showing the steps of a second embodiment of the thin film transistor array of the present invention.

FIGS. 4 (e) to 4 (g) are cross-sectional views showing the steps of a second embodiment of the thin film transistor array of the present invention.

FIG. 5 is a sectional configuration view of a liquid crystal display device according to a third embodiment of the present invention.

6 (a) to 6 (d) are cross-sectional views showing steps of a conventional thin film transistor array.

FIGS. 7 (e) to 7 (g) are cross-sectional views showing steps of a conventional thin film transistor array.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Amorphous silicon 11 Glass substrate 13 Polycrystalline silicon 13a Channel region 13b Low concentration impurity implantation region (LDD region) 13c High concentration impurity implantation region (source and drain regions) 13d Drain region 14a Silicon oxide thin film 14b Tantalum oxide thin film 15 Gate Electrodes 16, 17 Interlayer insulating film 18 Pixel electrode 21, 22 Source and drain electrode 23 Protective insulating film (silicon nitride) 24 Flattening film 25 Photoresist 26 Display electrode (ITO) 41 Black matrix 42 Polarizing plate 43 Counter substrate 44 Color filter 45 transparent conductive layer 46 alignment film 47 liquid crystal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/43 H01L 29/62 G 21/336 29/78 612B H04N 5/66 102 613A 616A 616V F term ( Reference) 2H092 JA24 JA37 JA41 JB58 KA10 MA27 NA25 PA08 PA09 4M104 AA09 BB13 BB14 BB38 BB40 CC05 DD08 DD26 DD65 DD78 FF13 FF22 GG09 GG10 HH16 5C058 AA06 AB01 BA35 5F048 AA07 AB10 AC04 BA16 BB02 A02 BB02A02 BB02A02 EE02 EE03 EE04 EE06 EE12 EE28 EE50 FF02 GG02 GG13 GG45 HJ01 HJ04 HJ12 HJ23 HL03 HL04 HL07 HL11 HM15 NN03 NN23 NN24 NN35 NN72 NN78 PP03 PP35 QQ04 QQ11

Claims (7)

[Claims] 1. A thin film transistor array in which an n-type thin film transistor and a p-type thin film transistor are integrated on the same substrate using a polycrystalline silicon thin film as an active layer on a light-transmitting substrate, wherein the n-channel thin film transistor has a channel region and a source or drain region. A low-concentration impurity-implanted region into which a low-concentration impurity is introduced, wherein the gate electrode formed on the n-channel thin film transistor does not contain boron and phosphorus, and is formed on the p-channel thin film transistor. An active matrix array for a liquid crystal display device, characterized by containing boron without containing phosphorus. 2. The thin film transistor has a top gate structure, contains phosphorus in the source and drain regions of the n-channel thin film transistor and the lightly doped region, and contains phosphorus and boron in the source and drain regions of the p-channel thin film transistor. The active matrix array according to claim 1, comprising: 3. The active matrix array according to claim 1, wherein a gate electrode of the active matrix array is made of a metal material having a crystal structure. 4. The active matrix array according to claim 3, wherein said gate electrode material is made of a material containing molybdenum as a main component. 5. The method according to claim 1, wherein the concentration of boron contained in the gate electrode of the p-channel thin film transistor is 5 × 10 ¹³ / cm ² or more.
The active matrix array according to claim 1, wherein the active matrix array has a size of × 10 ¹⁶ / cm ² or less. 6. The active according to claim 1, wherein the concentration of hydrogen contained in the gate electrode of the p-channel thin film transistor is at least five times the concentration of hydrogen contained in the gate electrode of the n-channel thin film transistor. Matrix array. 7. A driving circuit built-in liquid crystal display device in which a driving circuit having a complementary metal oxide semiconductor (C-MOS) structure is integrated on the same substrate using polycrystalline silicon for an active layer.
A liquid crystal display device using the active matrix array according to claim 1.