JP2001250777A - Method for creating semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for creating a semiconductor device with improved gettering efficiency. SOLUTION: When phosphor is added into a poly-Si film crystallized by adding metal, and heat treatment is made for gettering, the shape of an island- shaped insulation film on the poly-Si film used when implanting phosphor is carefully designed, thus increasing the area of the boundary surface between a region where phosphor is added and a region where no phosphors are added, and improving gettering efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technique for manufacturing a semiconductor device using a crystalline semiconductor thin film containing silicon as a main component. In particular, the present invention relates to a method for manufacturing a thin film transistor (hereinafter, referred to as a TFT) using a substrate having a crystalline semiconductor thin film containing silicon as a main component over an insulating substrate.

[0002] In this specification, a semiconductor device generally refers to a device that functions using a semiconductor, and includes a TFT.
Not only a single element as described above, but also an electronic device and the like equipped with it, such as an arithmetic processing unit, a storage processing unit, and an electro-optical device, are included in the category of the semiconductor device.

[0003]

2. Description of the Related Art An active matrix type liquid crystal display device is a monolithic type display device in which a pixel matrix circuit and a driver circuit are provided on the same substrate. In a monolithic display device, a thin film transistor (TFT) is mainly used. The thin film transistor is a glass substrate,
An active layer is formed by forming an amorphous silicon film (amorphous silicon film) on an insulating substrate such as a quartz substrate. Development of a system-on-panel using a TFT and incorporating a logic circuit such as a memory circuit or a clock generation circuit has been advanced.

Since such driver circuits and logic circuits need to operate at high speed, it is inappropriate to form an amorphous silicon film as an active layer on a quartz substrate or a glass substrate and use it as an element. . For this reason, TFTs using a polycrystalline silicon film as an active layer are currently being manufactured.

There are several techniques for obtaining a polycrystalline silicon film by crystallization after forming an amorphous silicon film on a quartz substrate or a glass substrate. Among them, there is known a technique in which excellent element electrical characteristics are obtained when an element is formed, a catalytic metal element that promotes crystallization of an amorphous silicon film is added, and crystallization is performed by heat treatment. I have. Hereinafter, this technique will be described in more detail.

On an insulating substrate such as a quartz substrate or a glass substrate, a semiconductor thin film having an amorphous structure containing silicon as a main component and having a thickness of about 50 nm to 100 nm is formed by an LPCVD apparatus or a PECVD apparatus. The semiconductor thin film having the amorphous structure is solid-phase crystallized by adding a metal to the surface and in the film of the semiconductor thin film having the amorphous structure and performing heat treatment. By solid-phase crystallization of the semiconductor thin film having the amorphous structure, a crystalline semiconductor thin film containing silicon as a main component is obtained. It has been confirmed by the present inventors that the solid phase crystallization is promoted by the addition of the metal, and it can be said that the metal functions as a catalyst during the solid phase crystallization. The metal is herein referred to as a catalyst metal.

The phenomenon in which the semiconductor thin film having an amorphous structure is crystallized by heat treatment using a metal as a catalyst is described in Me.
tal Induced Lateral crystal
Many have been reported as allization (MILC). Typical examples include transition metal elements such as nickel (Ni), cobalt (Co), palladium (Pd), platinum (Pt), and copper (Cu). Due to the presence of the catalyst metal, the semiconductor thin film having the amorphous structure is more advantageous in terms of the temperature and time required for solid-phase crystallization than when the catalyst metal is not added. According to experiments, Ni element is very excellent as a catalyst metal. Hereinafter, it is assumed that Ni element is used as the catalyst metal.

The heat treatment required for solid-phase crystallization of the semiconductor thin film having an amorphous structure is performed at 400 ° C. by an electric furnace or the like.
It is several hours or more at ~ 700 ° C.

In this specification, a semiconductor thin film having an amorphous structure containing silicon as a main component is referred to as a silicon thin film having an amorphous structure.
Also includes a Ge thin film having a Ge component ratio of less than 50%.

[0010]

The catalyst metals for promoting the crystallization of the semiconductor thin film having an amorphous structure include nickel (Ni), cobalt (Co), palladium (Pd), and platinum.
Transition metal elements such as (Pt) and copper (Cu) are used. As is generally well known, metals such as Ni, when present in crystalline silicon, form deep levels and adversely affect the electrical characteristics and reliability of the device. Therefore, from the region where the element is formed and used as the element (the element active area), N
It is necessary to remove metals such as i element. Also in the case of the crystalline semiconductor thin film, there is a concern that the catalytic metal may adversely affect the device characteristics.

[0011]

Therefore, it is necessary to remove metals such as Ni from the active region of the element to such an extent that the electrical characteristics are not affected. The removal of a metal such as a Ni element from an element active region in crystalline silicon is generally called gettering. Hereinafter, a gettering method confirmed by the present inventors will be described.

An insulating film is formed on the crystalline semiconductor thin film. As the insulating film, a silicon oxide film, a silicon nitride film, or the like is formed by a CVD device or a sputtering device. Next, the insulating film is formed in an island shape. The islands of the insulating film can be formed by photolithography and etching common in semiconductor technology.

Using the insulating film as a mask, a non-metallic element or ions of the non-metallic element are added to the crystalline semiconductor thin film, and a region where the non-metallic element or the non-metallic element ion is added to the crystalline semiconductor thin film. To form In other words, the region where the islands of the insulating film exist on the crystalline semiconductor thin film is added to the region where the islands do not exist without the non-metal element or the non-metal element ion being added. . The non-metallic element or the non-metallic element ion is added by thermal diffusion from a gas phase or an ion implantation device.

The non-metallic element or the non-metallic element ion includes boron (B), silicon (Si), phosphorus (P), arsenic (A
s), helium (He), neon (Ne), argon (Ar), Kr (krypton), and xenon (Xe).

The mechanism and phenomenon of gettering of transition metal elements in single crystal silicon have been actively studied, and a considerable portion has been clarified. Although there is no detailed information about gettering in polycrystalline silicon, the case of single crystal silicon can be referred to. Damage introduced into the polycrystalline silicon by the ion implantation method (ion implantation method) is effective gettering. Traces of atoms bounced off by ion implantation become locally amorphous,
When the amorphous portion is recrystallized by the subsequent heat treatment, high-density crystal defects and the like are introduced. Therefore, the non-metallic element or the non-metallic element ion to be added by ion implantation at the time of gettering can be ion-implanted, has a smaller diffusion coefficient than the metal to be gettered, and almost reaches the element active region even by heat treatment. It does not matter if it does not diffuse or is electrically inactive and does not affect the device characteristics.

Elements satisfying the above conditions include B, Si,
There is one or more selected from P, As, He, Ne, Ar, Kr, and Xe. However, it is conceivable that damages such as grain boundaries, fine twins, stacking faults, dislocation loops, and dislocation networks are different depending on differences in ion species, dose, and acceleration energy. Even when phosphorus (P) or the like is diffused from the gas phase, when it is added to crystalline silicon, it forms a misfit transition and becomes a gettering source. The present inventors have confirmed that adding phosphorus (P) to the crystalline semiconductor thin film is effective for gettering the catalyst metal.

Next, the crystalline semiconductor thin film is subjected to a heat treatment at 400 ° C. or more and 1000 ° C. or less to getter the metal in the region to which the nonmetallic element or the ion of the nonmetallic element is added. Experiments by the inventors have confirmed that phosphorus (P) has a particularly remarkable gettering effect.

In general, gettering is achieved by forming a gettering site outside the element active region and segregating a metal on the gettering site by heat treatment. In the semiconductor element formation technique including the above-described thin film formation, heat treatment is indispensable, but the smaller the amount of heat supply = temperature × time, the more desirable. Reducing the amount of heat supply is economically advantageous and can reduce the time. In addition, the warpage and shrinkage of the semiconductor substrate can be reduced, and the generation of extra stress near the element active region can be prevented. In addition, after the gettering step, the smaller the metal remaining without being getterable in the element active region, the better.

A semiconductor thin film 10 having an amorphous structure containing silicon as a main component is formed on a glass substrate or a quartz substrate 10101.
102 is formed. A metal is added to the semiconductor thin film 102 having the amorphous structure. Nickel (N
i), cobalt (Co), palladium (Pd), platinum (P
t), copper (Cu) and the like are conceivable, but in the section of means for solving the problem, it is assumed that Ni is used and a Ni acetate acetate salt solution 10103 is applied.

Semiconductor thin film 101 having the amorphous structure
02, 400 ° C. or more and 700 ° C. using the metal as a catalyst
By the following heat treatment, solid phase crystallization is performed to obtain a crystalline semiconductor thin film containing silicon as a main component (FIG. 1A). Ni is a very effective metal for promoting solid-phase crystallization,
It has been confirmed by the inventors' experiments.

After an insulating film is formed on the crystalline semiconductor thin film 10107, the insulating film is finely processed into an island-shaped object 10104. Using the insulating film islands 10104 as a mask,
A nonmetal element or ions of the nonmetal element are added to the crystalline semiconductor thin film (FIG. 1B). In the section for solving the problems, it is assumed that phosphorus (P) is used as the nonmetallic element.

In addition to phosphorus (P), B, Si, As, H
e, Ne, Ar, Kr, Xe, etc. are considered effective for gettering. These elements are capable of introducing damage to the poly-Si film by ion implantation and subsequent heat treatment, are harder to diffuse than the gettering metal, or are inactive and do not affect the device characteristics.
Regions 10106 and 10109 to which a nonmetallic element or ions of the nonmetallic element are added are formed in the crystalline semiconductor thin film. 400 ° C. or higher for the crystalline semiconductor thin film
The metal is subjected to a heat treatment at a temperature of 00 ° C. or lower to getter the metal in the region to which the nonmetallic element or the ion of the nonmetallic element is added. (FIG. 1 (C)) In FIG. 1 (C),
Reference numeral 10110 denotes a direction in which Ni moves.

One of the features of the present invention includes a process of forming a gettering site by adding a nonmetallic element or ions of the nonmetallic element to a crystalline semiconductor thin film, and a heat treatment process. By the heat treatment, the metal contained in the crystalline semiconductor thin film moves and is captured at a gettering site (a region to which a nonmetallic element or an ion of the nonmetallic element is added), and the metal is removed from the crystalline semiconductor thin film other than the gettering site. Is to eliminate or reduce.

The main configuration of the present invention is that the island-shaped insulating film shapes 10301 and 10201 with respect to a plane parallel to the surface 10203 of the crystalline semiconductor thin film 10206 are polygons having the number of vertices n (n> 20). And the number m (m> m) of the vertices whose inner angles are 180 degrees or more among the vertices
8) It is a polygon having three pieces.

As described above, the regions 10106 and 1010 to which the non-metallic element or ions of the non-metallic element are added
The area of the interface 10108 between the region 9 and the region not added is increased, and at least one of the efficiency and the effect of gettering is improved.

In general, the progress of gettering includes a step of releasing a metal from the active region of the element, a step of diffusion, and a step of capture at a gettering site. It is intended to increase the efficiency or effect of gettering by increasing the area of the boundary surface and promoting the diffusion phenomenon of the metal.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A quartz substrate 10101 has an LPCV
D device, an amorphous silicon film (a-S
An i-film) 10102 is formed.

Spin-coat Ni acetate acetate solution 10103
Drop by the method. Ni concentration of Ni acetate acetate solution is weight conversion
It is about 10 ppm in calculation. Ni acetate acetate solution is dropped
Prior to irradiation with UV light in an oxygen atmosphere
And an ultra-thin silicon oxide film (SiO _TwoFilm), and a-S
It is necessary to make it easy to wet the Ni acetate solution on the surface of the i-film.
You.

As a method for adding a metal such as Ni, besides adding from a liquid phase, a method using an ion implant device,
There is a method of forming a metal deposition film on the a-Si film.

A quartz substrate (having an a-Si film) is subjected to a heat treatment at 600 ° C. for several hours or more in a nitrogen atmosphere. N
It has been confirmed that the addition of the i element causes solid phase crystallization of the entire a-Si film in a much shorter time than the case where Ni is not added. The solid-phase crystallization results in a polycrystalline silicon film (poly-Si). It has been confirmed by the inventors that Ni is involved in both the generation of initial nuclei in the a-Si film and the crystallization of the entire a-Si film.

The phenomenon in which crystallization is promoted when a catalytic metal is added to an a-Si film is described in Metal Induced La.
teral crystallization (MIL
C), many of which have been reported as nickel (Ni), cobalt (Co), palladium (Pd), platinum (Pt), and copper (Cu).
Transition metal elements. According to experiments by the inventors, Ni
The elements have been found to be very good as catalytic metals.

As is generally well known, metals such as Ni, when present in crystalline silicon, form deep levels and adversely affect the electrical characteristics and reliability of the device. Therefore, it is necessary to remove a metal such as Ni from a region where the element is formed and used as an element (an element active area).
The poly-Si film crystallized with the catalyst metal also has a concern that the catalyst metal may adversely affect the device characteristics.

Therefore, it is necessary to remove metals such as Ni elements from the element active region to such an extent that the electric characteristics are not affected. The removal of a metal such as a Ni element from an element active region in crystalline silicon is generally called gettering.

On the poly-Si film, 150 nm
A silicon oxide film of a degree is formed. The silicon oxide film is LTO
(Low temperature oxide) film. The insulating film to be formed may be a silicon nitride film or the like in addition to the silicon oxide film.
There are a VD device, a sputtering device, and the like.

The formed poly-Si film has an island shape 101
Fine processing is carried out by photolithography and etching so as to obtain 04. Surface of poly-Si film 10203
Consider a cross-sectional shape 10208 formed when the island is cut off on a plane 10202 that is parallel to. The main configuration of the present invention is that the cross-sectional shape is a polygon having the number n of vertices (n> 20), and the inner angle of the vertices is 18
It is to be a polygon having the number m (m> 8) of vertices that are 0 degrees or more. In the first embodiment, the cross-sectional shape of the island-shaped object is shown in FIG. 2B with reference to the Koch curve. The Koch curve is a figure that is famous for fractal geometry.

Using islands of the silicon oxide film as a mask, phosphorus (P) is converted into poly-Si using a plasma doping apparatus.
It is added to the film (FIG. 1 (B)). Ion implantation amount 1E15a
toms / cm ² and an acceleration voltage of 10 kV. In consideration of the thickness of the silicon oxide film,
4 should be an accelerating voltage and an ion implantation amount such that P ions do not penetrate. In addition to phosphorus (P), B, Si, H
e, As, Ne, Ar, Kr, Xe, etc. are considered effective for gettering. These elements are capable of introducing damage to the poly-Si film by ion implantation and subsequent heat treatment, are harder to diffuse than the gettering metal, or are inactive and do not affect the device characteristics.

The plasma doping apparatus, unlike the ion implant apparatus used for LSI manufacturing, has no mechanism for mass separation when implanting ions. For this reason, there is also a point that the accuracy of controlling the implantation amount and the implantation depth is inferior to that of the ion implant device. However, they can be efficiently implanted into a large area, and thus are often used in TFT manufacturing.

After the phosphorus (P) ion implantation, heat treatment was performed at 600 ° C. for about 5 hours in a nitrogen atmosphere (FIG. 1C), and phosphorus (P) in the poly-Si film was added. The regions 10106 and 10109 are gettered with Ni serving as a catalyst metal during crystallization. It has already been confirmed by the inventors that remarkable gettering effect is obtained by adding phosphorus (P). The heat treatment at the time of gettering is performed at 400 ° C. or higher to 1000 ° C. or lower.

The reason why the shape of the islands of the silicon oxide film is the complicated polygon 10208 as described above is that the surface 101 where the phosphorus (P) added region and the non-added region in the poly-Si film are in contact with each other.
08 to increase the area. It is intended to increase the efficiency of gettering or its effect by increasing the area where the added region and the non-added region are in contact with each other and promoting the diffusion phenomenon of the metal.

By the gettering, the concentration of the metal to be gettered in the element active region is reduced to such an extent that the element characteristics are not affected.

After the solid-phase crystallization and gettering of the a-Si film are completed, a normal TFT array substrate is manufactured.
Manufacturing even liquid crystal devices and organic EL devices.

[0042]

[Embodiment 1] In this embodiment, a process for manufacturing a display device will be described. A method for simultaneously manufacturing a pixel TFT and a storage capacitor in a pixel portion and a TFT of a driving circuit provided in the periphery of a display region is described. 4 will be described in detail with reference to FIGS.

In FIG. 4A, a substrate 101 is made of a glass substrate such as barium borosilicate glass or aluminoborosilicate glass typified by Corning's # 7059 glass or # 1737 glass, and polyethylene terephthalate (PET). ), Polyethylene naphthalate (P
EN), a plastic substrate having no optical anisotropy such as polyethersulfone (PES) can be used. When a glass substrate is used, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. Then, a base film 102 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface of the substrate 101 where a TFT is to be formed, in order to prevent impurity diffusion from the substrate 101. For example, SiH ₄ in plasma CVD, NH _3, the N ₂ O silicon oxynitride film 102a made from 10 to 200 nm (preferably 50 to 100 nm), as well oxynitride made from SiH _4, N ₂ O The hydrogenated silicon film 102b is
The layer is formed to a thickness of 00 nm (preferably 100 to 150 nm).

The silicon oxynitride film is formed by using a parallel plate type plasma CVD method. Silicon oxynitride film 10
2a is SiH ₄ at 10 SCCM, NH ₃ at 100 SCCM, N ₂
O was introduced into the reaction chamber at 20 SCCM, and the substrate temperature was 325.
° C, a reaction pressure of 40 Pa, a discharge power density of 0.41 W / cm ² , and a discharge frequency of 60 MHz. On the other hand, the hydrogenated silicon oxynitride film 102b is made of ₅ SCCM of SiH ₄ and 120 SCC of N ₂ O.
M and H ₂ were introduced into the reaction chamber at 125 SCCM, and the substrate temperature was 4
00 ° C, reaction pressure 20 Pa, discharge power density 0.41 W / c
m ² , and the discharge frequency is 60 MHz. These films can be continuously formed only by changing the substrate temperature and changing the reaction gas.

The silicon oxynitride film 102a manufactured under the above conditions has a density of 9.28 × 10 ²² / cm ³ , 7.13% of ammonium hydrogen fluoride (NH ₄ HF ₂ ) and ammonium fluoride. Of a mixed solution (trade name: LAL500, manufactured by Stella Chemifa) containing 15.4% (NH ₄ F)
The etching rate at a temperature of ° C. is as low as about 63 nm / min, and the film is dense and hard. The use of such a film as a base film is effective in preventing an alkali metal element from a glass substrate from diffusing into a semiconductor film formed thereover.

Next, 25 to 80 nm (preferably 30 to 80 nm)
Semiconductor film 103 having a thickness of 60 nm and having an amorphous structure.
a is formed by a known method such as a plasma CVD method or a sputtering method. For example, an amorphous silicon film is formed to a thickness of 55 nm by a plasma CVD method. The semiconductor film having an amorphous structure includes an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used. Further, both the base film 102 and the amorphous semiconductor film 103a can be formed continuously. For example, as described above, the silicon oxynitride film 102a and the hydrogenated silicon oxynitride film 102b
Is continuously formed by a plasma CVD method, and then the reaction gas is Si.
H _4, N ₂ O, be switched from H ₂ only SiH ₄ and H ₂ or SiH _4, once can be continuously formed without exposure to the atmosphere. As a result, the hydrogenated silicon oxynitride film 102b
To prevent contamination of the surface of the TFT
And variations in threshold voltage can be reduced.

As in Embodiment 1 of this specification, crystallization using a metal catalyst and gettering of the metal are performed. The islands of the silicon oxide film used for gettering are removed by wet etching.

Then, as shown in FIG. 4C, using a photomask 1 (PM1) on the crystalline semiconductor film 103b,
A resist pattern is formed using a photolithography technique, and the crystalline semiconductor film is divided into islands by dry etching, so that island-shaped semiconductor films 104 to 108 are formed. For dry etching, a mixed gas of CF ₄ and O ₂ is used. After that, a mask layer 194 of a silicon oxide film having a thickness of 50 to 100 nm is formed by a plasma CVD method or a sputtering method.

In this state, for the purpose of controlling the threshold voltage (Vth) of the TFT, an impurity element imparting a p-type is added to the island-like semiconductor film in an amount of about 1 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / cm ³ . The concentration may be added to the entire surface of the island-shaped semiconductor film. The impurity element imparting p-type to the semiconductor includes boron (B),
Elements of Group 13 of the periodic table, such as aluminum (Al) and gallium (Ga), are known. As the method, an ion implantation method or an ion doping method can be used, but the ion doping method is suitable for treating a large-area substrate.
In the ion doping method, diborane (B ₂ H ₆ ) is used as a source gas and boron (B) is added. The implantation of such an impurity element is not always necessary and may be omitted. However, it is a method preferably used for keeping the threshold voltage of the n-channel TFT within a predetermined range.

In order to form an LDD region of an n-channel TFT of a driver circuit, an impurity element imparting n-type is selectively added to the island-shaped semiconductor films 105 and 107. The resist masks 195a to 195e are formed in advance. As an impurity element imparting n-type, phosphorus (P) or arsenic (A
s) may be used. Here, an ion doping method using phosphine (PH ₃ ) is applied to add phosphorus (P). The formed impurity regions are low-concentration n-type impurity regions 196 and 197, and the phosphorus (P) concentration is 2 × 1
The range may be from 0 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ . In this specification, the impurity regions 196, 1
97, the concentration of the impurity element imparting n-type
-). The impurity region 198 is a semiconductor film for forming a storage capacitor of the pixel matrix circuit, and phosphorus (P) is added to this region at the same concentration (FIG. 4).
(D)).

Thereafter, a process for activating the added impurity element is performed. The activation process is performed by the heat treatment using laser light described in the seventh embodiment. An example of the heat treatment conditions is a laser pulse oscillation frequency of 1 kHz and a laser energy density of 100 to 300 mJ / cm ² (typically, 15
0 to 250 mJ / cm ² ). Then, the linear beam is irradiated over the entire surface of the substrate, and the overlapping ratio (overlap ratio) of the linear beam at this time is 80 to 99% (preferably 9%).
5-99%).

The gate insulating film 109 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by a plasma CVD method or a sputtering method. For example, 120 nm
Of a silicon oxynitride film. A silicon oxynitride film formed by adding O ₂ to SiH ₄ and N ₂ O is a preferable material for this application because the fixed charge density in the film is reduced. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure (FIG. 4E).

Then, as shown in FIG. 4E, a heat-resistant conductive layer for forming a gate electrode is formed over the gate insulating film 109. The heat-resistant conductive layer may be formed as a single layer, or may be formed as a multilayer structure including a plurality of layers such as two layers or three layers as necessary. Using such a heat-resistant conductive material, for example, a conductive layer (A) 110 made of a conductive nitride metal film and a conductive layer (B) 111 made of a metal film
Are preferably laminated. The conductive layer (B) 111 is made of tantalum (Ta), titanium (Ti), molybdenum (M
o), an element selected from tungsten (W), an alloy containing the above element as a main component, or an alloy film (typically, a Mo—W alloy film or a Mo—Ta alloy film) that combines the above elements. The conductive layer (A) 110 may be formed using tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), molybdenum nitride (MoN), or the like. The conductive layer (A) 110 may be formed using tungsten silicide, titanium silicide, or molybdenum silicide. The conductive layer (B) 111 preferably has a reduced impurity concentration in order to reduce the resistance. In particular, the oxygen concentration is preferably 30 ppm or less. For example, tungsten (W) has an oxygen concentration of 30 pp.
m or less, a specific resistance of 20 μΩcm or less can be realized.

The conductive layer (A) 110 has a thickness of 10 to 50 nm (preferably 20 to 30 nm), and the conductive layer (B) 111 has a thickness of 200 to 400 nm (preferably 250 to 350 nm).
It is good. When W is used as a gate electrode, argon (Ar) gas and nitrogen (N2) gas are introduced by sputtering using W as a target, and the conductive layer (A) 111 is made of tungsten nitride (WN) to a thickness of 50 nm. The conductive layer (B) 110 is formed with W to a thickness of 250 nm. As another method, the W film is made of tungsten hexafluoride (WF6)
Can also be formed by a thermal CVD method. In any case, in order to use it as a gate electrode, it is necessary to reduce the resistance, and it is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is inhibited and the resistance is increased. From this, when the sputtering method is used, the purity is 99.999.
A 9% to 20 μΩcm resistivity can be achieved by using a 9% W target and forming the W film with sufficient care so as not to mix impurities from the gas phase during film formation.

On the other hand, a TaN film is formed on the conductive layer (A) 110.
When a Ta film is used for the conductive layer (B) 111, it can be formed by a sputtering method in the same manner. TaN film is T
The target film a is formed using a mixed gas of Ar and nitrogen as a sputtering gas, and the Ta film uses Ar as a sputtering gas. When an appropriate amount of Xe or Kr is added to these sputter gases, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. The α-phase Ta film has a resistivity of about 20 μΩcm and can be used as a gate electrode, but the β-phase Ta film has a resistivity of about 180 μΩcm and is not suitable for a gate electrode. TaN film is α
Since it has a crystal structure close to that of a phase, an α-phase Ta film was easily obtained by forming a Ta film thereon. Although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm under the conductive layer (A) 110. Thus, the adhesion of the conductive film formed thereover is improved and oxidation is prevented, and at the same time, a small amount of an alkali metal element contained in the conductive layer (A) 110 or the conductive layer (B) 111 is added to the gate insulating film 109. Spreading can be prevented. In any case, the conductive layer (B) 1
11 preferably has a resistivity in the range of 10 to 50 μΩcm.

Next, using the photomask 2 (PM2),
The resist masks 112 to 117 are formed by using a photolithography technique, and the conductive layer (A) 110 and the conductive layer (B) 111 are collectively etched to form the gate electrode 11.
8 to 122 and the capacitor wiring 123 are formed. Gate electrode 1
18 to 122 and the capacitor wiring 123 are made of conductive layers (A) 118 a to 122 a and conductive layers (B) 118
b to 122b are integrally formed (FIG. 5).
(A)).

The method of etching the conductive layer (A) and the conductive layer (B) may be appropriately selected by a practitioner. However, when the conductive layer (A) and the conductive layer (B) are formed of a material containing W as a main component as described above, It is desirable to apply a dry etching method using high-density plasma in order to perform etching at high speed and with high accuracy. One of the techniques for obtaining high-density plasma is inductively coupled plasma (Inductively Coupled Plasma:
It is preferable to use an ICP) etching apparatus. In the method of etching W using an ICP etching apparatus, two kinds of gases, CF ₄ and Cl ₂ , are introduced into a reaction chamber as an etching gas, and the pressure is set to 0.5 to 1.5 Pa (preferably 1 Pa). 200-1000W high frequency (13.56MHZ)
z) Apply power. At this time, a high frequency power of 20 W is applied to the stage on which the substrate is placed, and the stage is charged to a negative potential by a self-bias, so that positive ions are accelerated and anisotropic etching can be performed. By using ICP etching equipment, hard metal film such as W
An etching rate of 5 nm / sec can be obtained. Also,
In order to perform etching without leaving a residue, 10 to 2
It is preferable to increase the etching time at a rate of about 0% and perform overetching. At this time, however, it is necessary to pay attention to the etching selectivity with the base. For example, since the selectivity of the silicon oxynitride film (gate insulating film 109) to the W film is 2.5 to 3, the surface where the silicon oxynitride film is exposed by such an over-etching process is 20%.
It is etched to about 50 nm and becomes substantially thin.

Then, the n-channel TFT of the pixel TFT is used.
In order to form an LDD region, a step of adding an impurity element for imparting n-type (n-doping step) is performed. Using the gate electrodes 118 to 122 as a mask, an impurity element imparting n-type in a self-aligned manner was added by an ion doping method. The concentration of phosphorus (P) added as an impurity element imparting n-type is 1
It is added in a concentration range of × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ . In this way, low-concentration n-type impurity regions 124 to 129 are formed in the island-shaped semiconductor film as shown in FIG.

Next, a high-concentration n-type impurity region functioning as a source region or a drain region is formed in the n-channel TFT (n + doping step). First, using a photomask 3 (PM3), a resist mask 130 is used.
To 134, and an n-type impurity element is added to form high-concentration n-type impurity regions 135 to 140. n
Phosphorus (P) is used as an impurity element for imparting a mold, and an ion doping method using phosphine (PH ₃ ) is performed so that the concentration becomes 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ^3. (FIG. 5C).

Then, high-concentration p-type impurity regions 144 and 145 serving as a source region and a drain region are formed in the island-shaped semiconductor films 104 and 106 forming the p-channel TFT. Here, a p-type impurity element is added using the gate electrodes 118 and 120 as a mask to form a high-concentration p-type impurity region in a self-aligned manner. At this time, the island-shaped semiconductor films 105, 107, and 10 forming an n-channel TFT are formed.
8 is to form resist masks 141 to 143 using the photomask 4 (PM4) and cover the entire surface. The high-concentration p-type impurity regions 144 and 145 are formed by an ion doping method using diborane (B ₂ H ₆ ). The boron (B) concentration in this region is set to 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ (FIG. 5D).

The high-concentration p-type impurity regions 144 and 145
Has phosphorus (P) added in the previous step, and 1 × 10 ²⁰ is added to the high-concentration p-type impurity regions 144a and 145a.
At a concentration of about 1 × 10 ²¹ atoms / cm ³ , the high concentration p-type impurity regions 144b and 145b have 1 × 10 ^{16 to} 5 × 10 ¹⁹ atoms.
Although it is contained at a concentration of s / cm ³ , by increasing the concentration of boron (B) added in this step from 1.5 to 3 times,
There is no problem in functioning as the source and drain regions of the p-channel TFT.

After that, as shown in FIG. 6A, a protective insulating film 146 is formed over the gate electrode and the gate insulating film. The protective insulating film may be formed using a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a stacked film including a combination thereof. In any case, the protective insulating film 146
Is formed from an inorganic insulating material. The thickness of the protective insulating film 146 is 100 to 200 nm. Here, in the case of using a silicon oxide film, TEOS is performed by a plasma CVD method.
(Tetraethyl OrthoSilicate) and O ₂ are mixed, the reaction pressure is set to 40 Pa, the substrate temperature is set to 300 to 400 ° C., and discharge is performed at a high frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm ² . In the case of using a silicon oxynitride film, a silicon oxynitride film formed from SiH ₄ , N ₂ O, and NH ₃ by a plasma CVD method or a silicon oxynitride film formed from SiH ₄ and N ₂ O is used. Good. The manufacturing conditions in this case are a reaction pressure of 20 to 200 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (60 MHz) power density of 0.1 to 1.0 W / cm ² . Also,
A silicon oxynitride hydride film formed from SiH ₄ , N ₂ O, and H ₂ may be used. Similarly, a silicon nitride film can be formed from SiH ₄ and NH ₃ by a plasma CVD method.

Thereafter, a step of activating the impurity elements imparting n-type or p-type added at the respective concentrations is performed. This step can be performed by a thermal annealing method using a furnace annealing furnace, or may be activated by a heat treatment method using laser light. The heat treatment conditions in this case are the same as those described above. On the other hand, when performing the thermal annealing method, the oxygen concentration is 1 ppm or less, preferably 0.1 ppm.
The heat treatment is performed at 400 to 700 ° C., typically 500 to 600 ° C. in a nitrogen atmosphere of ppm or less. In this embodiment, the heat treatment is performed at 550 ° C. for 4 hours. Also, the substrate 101
When using a plastic substrate with low heat resistance temperature,
It is preferable to apply the heat treatment method using laser light of the present invention (FIG. 6B).

After the heat treatment, 3 to 100%
1 to 12 at 300 to 450 ° C. in an atmosphere containing hydrogen
Heat treatment was performed for a long time to perform a step of hydrogenating the island-shaped semiconductor film. This step is to terminate dangling bonds of 10 @ 16 to 10 @ 18 / cm @ 3 in the island-shaped semiconductor film by thermally excited hydrogen. Plasma hydrogenation (using hydrogen excited by plasma) as another means of hydrogenation
May be performed.

When the heat treatment method using laser light of the present invention is combined with the plasma hydrogenation treatment, it can be carried out by using an apparatus having the structure shown in FIG. Specifically, heat treatment using laser light is performed in the processing chamber 818, and then the substrate is moved to the processing chamber 816 by the transfer unit 820 to perform plasma hydrogenation processing. If hydrogen gas, ammonia gas, or the like is introduced into the processing chamber 816, plasma hydrogenation can be easily performed. As described above, the substrate is held in the apparatus, and the substrate is continuously processed without being exposed to the air, whereby contamination of the substrate surface can be prevented, and the throughput can be improved.

Then, an interlayer insulating film 147 made of an organic insulating material is formed with an average thickness of 1.0 to 2.0 μm. As the organic resin material, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. For example, when using polyimide of the type that thermally polymerizes after coating on the substrate,
It is formed by firing at 300 ° C. in a clean oven. Also, when using acrylic, use a two-liquid type,
After mixing the main material and the curing agent, the entire surface of the substrate is applied using a spinner, and then pre-heated at 80 ° C. for 60 seconds on a hot plate, and further heated at 250 ° C. for 60 seconds in a clean oven.
It can be formed by firing separately.

As described above, the surface can be satisfactorily flattened by forming the interlayer insulating film with the organic insulating material. In addition, since organic resin materials generally have a low dielectric constant, parasitic capacitance can be reduced. However, since it has hygroscopicity and is not suitable as a protective film, it must be used in combination with a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like formed as the protective insulating film 146 as in this embodiment.

Thereafter, a resist mask having a predetermined pattern is formed using the photomask 5 (PM5), and a contact hole reaching the source region or the drain region formed in each of the island-shaped semiconductor films is formed. The formation of the contact hole is performed by a dry etching method. In this case, an interlayer insulating film made of an organic resin material is first etched using a mixed gas of CF ₄ , O ₂ , and He as an etching gas, and then, the protective insulating film 146 is etched using CF ₄ and O ₂ as an etching gas. I do. Further, in order to increase the selectivity with the island-like semiconductor film, the etching gas is CH
By etching the gate insulating film is switched to F _3, can satisfactorily form a contact hole.

Then, a conductive metal film is formed by a sputtering method or a vacuum evaporation method, a resist mask pattern is formed by a photomask 6 (PM6), and the source wirings 148 to 152 and the drain wirings 153 to 157 are etched.
To form Here, the drain wiring 157 functions as a pixel electrode. Although not shown, in this embodiment, this electrode is formed by forming a Ti film with a thickness of 50 to 150 nm, forming a contact with the semiconductor film forming the source or drain region of the island-like semiconductor film, and forming the Ti film. Aluminum (Al) is formed in a thickness of 300 to 400 nm on the upper portion to form a wiring.

When hydrogenation is performed in this state, favorable results can be obtained for improving the characteristics of the TFT. For example, 3 ~
Heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 100% hydrogen, or the same effect can be obtained by using a plasma hydrogenation method. Further, by such a heat treatment, the protective insulating film 146 and the base film 102 are formed.
Can be diffused into the island-shaped semiconductor films 104 to 108 for hydrogenation. In any case, the defect density in the island-shaped semiconductor films 104 to 108 is desirably 10 16 / cm ³ or less.
What is necessary is just to give about 0.1 atomic% (FIG. 6 (C)).

In this way, a substrate having a driving circuit TFT and a pixel TFT of a pixel portion on the same substrate can be completed using the seven photomasks. The driving circuit includes a first p-channel TFT 200, a first n-channel TFT 201, a second p-channel TFT 202, and a second p-channel TFT 202.
N-channel type TFT 203, and the pixel portion has a pixel TFT 2
04, a storage capacitor 205 is formed. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

First p-channel TFT 20 of drive circuit
0, the channel forming region 20 in the island-shaped semiconductor film 104
6. Source region 207 made of high-concentration p-type impurity region
a, 207b and a single drain structure having drain regions 208a, 208b. The first n-channel TFT 201 includes a channel formation region 209, an LDD region 210 overlapping with the gate electrode 119, a source region 212, and a drain region 211 in the island-shaped semiconductor film 105. In this LDD region, the gate electrode 119
If the LDD region that overlaps with Lov is Lov, the length in the channel length direction is 0.5 to 3.0 μm, preferably 1.0 to 2.0 μm.
It was set to 0 μm. By setting the length of the LDD region in the n-channel TFT in this way, a high electric field generated near the drain region can be reduced, hot carriers can be prevented from being generated, and deterioration of the TFT can be prevented. Similarly, the second p-channel type TFT 202 of the driver circuit is a single drain type in which the island-shaped semiconductor film 106 has a channel formation region 213, source regions 214a and 214b made of high-concentration p-type impurity regions, and drain regions 215a and 215b. It has a structure. In the second n-channel TFT 203, the LDD regions 217 and 21 partially overlapping the channel formation region 216 and the gate electrode 121 on the island-shaped semiconductor film 107.
8, a source region 220 and a drain region 219 are formed. The length of Lov overlapping the gate electrode of this TFT is also 0.5 to 3.0 μm, preferably 1.0 to 2.0 μm. The LDD region that does not overlap with the gate electrode is Lof.
As f, the length in the channel length direction is 0.5 to 4.0.
μm, preferably 1.0 to 2.0 μm. Pixel TF
At T204, the island-shaped semiconductor film 108 includes channel formation regions 221 and 222, LDD regions 223 to 225, and source or drain regions 226 to 228. LDD
The length of the region (Loff) in the channel length direction is 0.5 to 4.
0 μm, preferably 1.5 to 2.5 μm. Further, a storage capacitor 205 is formed by the capacitor wiring 123, an insulating film made of the same material as the gate insulating film, and a semiconductor film 229 connected to the drain region 228 of the pixel TFT 204. In FIG. 6C, the pixel TFT 204 has a double gate structure, but may have a single gate structure or a multi-gate structure in which a plurality of gate electrodes are provided.

FIG. 16 is a top view showing almost one pixel of the pixel portion. The cross section AA ′ shown in the drawing corresponds to the cross-sectional view of the pixel portion shown in FIG. The gate electrode 122 of the pixel TFT 204 intersects with the underlying island-shaped semiconductor film 108 via a gate insulating film (not shown). Further, the gate electrode 122 is made of a low-resistance conductive material formed using a material such as Al or Cu.
Is in contact with the outside of the island-shaped semiconductor film 108 without a contact hole. Although not shown, the island-shaped semiconductor film 1
In 08, a source region, a drain region, and an LDD region are formed. Reference numeral 256 denotes a contact portion between the source wiring 152 and the source region 226, and reference numeral 257 denotes a contact portion between the drain wiring 157 and the drain region 228.
The storage capacitor 205 is connected to the drain region 2 of the pixel TFT 204.
The capacitor wiring 123 is formed in a region where the capacitor wiring 123 overlaps with the semiconductor film 229 extending from the gate insulating film and the gate insulating film. In this structure, an impurity element for controlling valence electrons is not added to the semiconductor film 229.

The above-described configuration makes it possible to optimize the structure of the TFT constituting each circuit in accordance with the specifications required by the pixel TFT and the driving circuit, thereby improving the operation performance and reliability of the semiconductor device. . Further, the gate electrode is formed of a conductive material having heat resistance, thereby facilitating activation of the LDD region, the source region, and the drain region. When a heat treatment method using a laser beam and a laser apparatus according to the present invention are applied to manufacture an active matrix substrate provided with such a TFT, a TFT having good characteristics can be obtained.
An FT can be manufactured, and an improvement in productivity can be achieved. A liquid crystal display device or an EL display device can be manufactured using such an active matrix substrate.

[Embodiment 2] Embodiment 1 shows an example in which a heat-resistant conductive material such as W or Ta is used as a material of a gate electrode of a TFT. The reason for using such a material is that the impurity element added to the semiconductor film for the purpose of controlling valence electrons after the formation of the gate electrode is mainly activated by thermal annealing at 400 to 700 ° C., prevention of electromigration, corrosion resistance Due to several factors, such as improvement in However, such a heat-resistant conductive material has a sheet resistance of about 10Ω and is not suitable for a liquid crystal display device or an EL display device having a screen size of 4 inches or more. This is because if the gate wiring connected to the gate electrode is formed of the same material, the length of the wiring on the substrate surface is inevitably increased, and the delay time due to the wiring resistance cannot be ignored.

For example, when the pixel density is VGA, 480
Gate wirings and 640 source wirings are formed.
In the case of GA, 768 gate wirings and 1024 source wirings are formed. The screen size of the display area is 13
In the case of inch class, the length of the diagonal is 340 mm,
In the case of the 18-inch class, it is 460 mm. In this embodiment, as a means for realizing such a liquid crystal display device,
A method for forming a gate wiring using a low-resistance conductive material such as Al or copper (Cu) will be described with reference to FIGS.

First, in the same manner as in Embodiment 1, FIGS.
The step shown in FIG. 5D is performed. Then, a process for activating the impurity element added to each island-shaped semiconductor film is performed for the purpose of controlling valence electrons. This activation treatment is most preferably performed by a heat treatment method using laser light.
Further, in an atmosphere containing 3 to 100% hydrogen, 300
Heat treatment is performed at 450 ° C. for 1 to 12 hours to hydrogenate the island-shaped semiconductor film. In this step, dangling bonds in the semiconductor film are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed (FIG. 7A).

When the activation and hydrogenation processes are completed,
The gate wiring is formed of a low resistance conductive material. This low-resistance conductive layer is formed of a conductive layer (D) containing Al or Cu as a main component. For example, an Al film containing 0.1 to 2% by weight of Ti is formed on the entire surface as a conductive layer (D) (not shown). The conductive layer (D) 145 has a thickness of 200 to 400 nm (preferably 25 to 400 nm).
(0 to 350 nm). Then, a predetermined resist pattern is formed using a photomask, and an etching process is performed thereon, so that the gate wirings 163 and 164 and the capacitor wiring 165 are formed.
To form In the etching treatment, the conductive layer (D) is removed by wet etching using a phosphoric acid-based etching solution, so that the gate wiring can be formed while maintaining the selectivity with the base. Then, a protective insulating film 146 is formed (FIG. 7B).

Thereafter, in the same manner as in the first embodiment, the interlayer insulating film 147 made of an organic insulating material and the source wirings 148 to 1
51, 167 and drain wirings 153 to 156, 168 can be formed to complete the active matrix substrate. FIGS. 8A and 8B are top views of this state. FIG. 8A is a cross-sectional view taken along the line BB ′ of FIG. 8A and FIG.
The cross section C ′ corresponds to AA ′ and CC ′ in FIG. 7C. 8A and 8B, the gate insulating film, the protective insulating film, and the interlayer insulating film are omitted, but the source and drain regions (not shown) of the island-shaped semiconductor films 104, 105, and 108 are provided. Wiring 148, 149, 167
And drain wirings 153, 154, 168 are connected via contact holes. Further, D- in FIG.
FIGS. 9A and 9B show a D ′ cross section and an EE ′ cross section of FIG. 8B, respectively. The gate wiring 163 is formed so as to overlap with the gate electrodes 118 and 119, and the gate wiring 164 is formed so as to overlap with the gate electrode 122 outside the island-shaped semiconductor films 104, 105 and 108, and the conductive layer (C) and the conductive layer (D) are formed. Electrically conductive upon contact. By forming the gate wiring from a low-resistance conductive material, the wiring resistance can be sufficiently reduced. Therefore, the present invention can be applied to a liquid crystal display device or an EL display device having a pixel portion (screen size) of 4 inches or more.

[Embodiment 3] The active matrix substrate manufactured in Embodiment 1 can be applied to a reflection type liquid crystal display device as it is. On the other hand, in the case of a transmissive liquid crystal display device, a pixel electrode provided for each pixel in the pixel portion may be formed of a transparent electrode. In this embodiment, a method for manufacturing an active matrix substrate corresponding to a transmission type liquid crystal display device will be described with reference to FIGS.

An active matrix substrate is manufactured in the same manner as in the first embodiment. In FIG. 11A, a conductive metal film is formed for a source wiring and a drain wiring by a sputtering method or a vacuum evaporation method. In this method, a Ti film is formed to a thickness of 50 to 150 nm, a contact is formed with a semiconductor film forming a source or drain region of an island-shaped semiconductor film, and aluminum (Al) is formed on the Ti film by a thickness of 300 to 150 nm. It is formed to a thickness of 400 nm, and a Ti film or a titanium nitride (TiN) film is
It was formed to a thickness of 00 to 200 nm to form a three-layer structure. After that, a transparent conductive film is formed over the entire surface, and a pixel electrode 171 is formed by a patterning process using a photomask and an etching process. The pixel electrode 171 is formed of the interlayer insulating film 14.
7 and the drain wiring 16 of the pixel TFT 204.
9 is provided to form a connection structure.

In FIG. 11B, first, an interlayer insulating film 147 is formed.
This is an example in which a transparent conductive film is formed thereon, a patterning process and an etching process are performed to form a pixel electrode 171, and then a drain wiring 169 is formed by providing a portion overlapping the pixel electrode 171. The drain wiring 169 has a thickness of 50 to
A contact is formed with the semiconductor film forming the source or drain region of the island-shaped semiconductor film, and aluminum (Al) is formed on the Ti film so as to have a thickness of 30 nm.
It is formed and provided with a thickness of 0 to 400 nm. With this configuration, the pixel electrode 171 is connected to the T
It comes into contact with only the i film. As a result, it is possible to prevent the reaction between the transparent conductive film material and Al.

The material of the transparent conductive film is indium oxide (I
n ₂ O ₃ ) and indium tin oxide alloy (In ₂ O ₃ —S
nO ₂ ; ITO) or the like can be formed by a sputtering method, a vacuum evaporation method, or the like. The etching of such a material is performed using a hydrochloric acid-based solution. However, in particular, since etching of ITO easily generates residues, an indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO) may be used in order to improve the etching processability. Since the indium oxide zinc oxide alloy has excellent surface smoothness and excellent thermal stability with respect to ITO, it is possible to prevent a corrosion reaction with Al contacting at the end face of the drain wiring 169. Similarly,
Zinc oxide (ZnO) is also a suitable material, and zinc oxide (ZnO: Ga) to which gallium (Ga) is added to increase the transmittance and conductivity of visible light can be used.

Thus, an active matrix substrate corresponding to a transmission type liquid crystal display device can be completed. In this embodiment, the same steps as those in the first embodiment have been described. However, such a configuration can be applied to the active matrix substrate described in the second embodiment.

[Embodiment 4] In this embodiment, a process of manufacturing an active matrix type liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described. First, as shown in FIG. 12A, a spacer including a columnar spacer is formed on the active matrix substrate in the state of FIG. 6C. The spacer may be provided by scattering particles of several μm, but here, a method of forming a resin film over the entire surface of the substrate and then patterning the resin film is adopted. Although there is no limitation on the material of such a spacer, for example, NN700 manufactured by JSR Corporation is applied by a spinner and then formed into a predetermined pattern by exposure and development processing. Further, it is cured by heating at 150 to 200 ° C. in a clean oven or the like. The shape of the spacer manufactured in this manner can be varied depending on the conditions of the exposure and the development processing. When the substrates are combined, mechanical strength as a liquid crystal display panel can be secured. The shape is not particularly limited, such as a cone, a pyramid, but specifically, for example, when it is a cone,
The height is set to 1.2 to 5 μm, and the average radius is set to 5 to 7 μm.
m, the ratio of the average radius to the bottom radius is about 1: 1.5. At this time, the taper angle viewed from the cross section is preferably set to ± 15 ° or less.

The arrangement of the columnar spacers may be determined arbitrarily. Preferably, as shown in FIG. 12A, in the pixel portion, the portion overlaps with the contact portion 235 of the drain wiring 161 (pixel electrode) and the portion is overlapped. It is preferable to form the columnar spacer 168 so as to cover it. Since the flatness of the contact portion 235 is impaired and the liquid crystal is not well aligned in this portion, the columnar spacer 168 is formed in such a manner that the contact portion 235 is filled with the resin for the spacer, so that disclination and the like can be performed. Can be prevented.

After that, an alignment film 174 is formed. Usually, a polyimide resin is used for the alignment film of the liquid crystal display element. After forming the alignment film, a rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. The area not rubbed in the rubbing direction from the end of the columnar spacer 173 provided in the pixel portion was set to 2 μm or less. In the rubbing process, the generation of static electricity often poses a problem.
In this case, it is possible to obtain the original role as a spacer and the effect of protecting the TFT from static electricity.

The opposing substrate 175 on the opposing side has a light shielding film 17
6, a transparent conductive film 177 and an alignment film 178 are formed.
The light shielding film 176 is made of Ti, Cr, Al,
It is formed with a thickness of nm. Then, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are bonded with a sealant 179. A filler 180 is mixed in the sealant 179, and the two substrates are bonded at a uniform interval by the filler 180 and the spacers 172 and 173. Thereafter, a liquid crystal material 606 is injected between the two substrates, and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material.
Thus, an active matrix liquid crystal display device shown in FIG. 12B is completed.

In FIG. 12, the spacer 172 is connected to the T of the driving circuit.
Although an example in which the spacer is formed on the entire surface on the FT is shown, as shown in FIG.
To 172e. The spacer provided in the portion where the driving circuit is formed may be formed so as to cover at least the source wiring and the drain wiring of the driving circuit. With such a configuration,
Each TFT of the drive circuit includes a protective insulating film 146, an interlayer insulating film 147, a spacer 172 or spacers 172a to 172a.
2e will be completely covered and protected.

FIG. 14 is a top view of an active matrix substrate on which spacers and a sealant are formed, and is a top view showing the positional relationship between the pixel portion and the drive circuit portion, the spacers, and the sealant. A scanning signal side driving circuit 185 and an image signal side driving circuit 186 are provided around the pixel portion 188 as driving circuits. Further, a signal processing circuit 187 such as a CPU or a memory may be added. And
These drive circuits are connected to an external input / output terminal 182 by connection wiring 183. In the pixel portion 188, the gate wiring group 189 extending from the scanning signal driving circuit 185 and the source wiring group 1 extending from the image signal driving circuit 186 are provided.
90 intersect in a matrix to form pixels, and each pixel is provided with a pixel TFT 204 and a storage capacitor 205.

The columnar spacer 1 provided in the pixel portion
73 may be provided for all the pixels, or may be provided every several to several tens of pixels arranged in a matrix. That is, the ratio of the number of spacers to the total number of pixels constituting the pixel portion is preferably 20 to 100%. Also,
Spacers 172, 172 ', 17 provided in the drive circuit section
2 ″ may be provided so as to cover the entire surface, or may be provided in a plurality as shown in FIG. 13 in accordance with the positions of the source and drain wirings of each TFT. The sealant 179 is formed outside the pixel portion 188 and the scan signal side drive circuit 185, the image signal side drive circuit 186, and other signal processing circuits 187 on the substrate 101 and inside the external input / output terminal 182. .

The structure of such an active matrix type liquid crystal display device will be described with reference to the perspective view of FIG. FIG.
In 5, the active matrix substrate is a glass substrate 1
The pixel section 188, the scanning signal side driving circuit 185, the image signal side driving circuit 186, and other signal processing circuits 187 are formed on the pixel section 901. The pixel portion 188 is provided with a pixel TFT 204 and a storage capacitor 205, and a driving circuit provided around the pixel portion is basically configured by a CMOS circuit. The scanning signal side driving circuit 185 and the image signal side driving circuit 186 are connected to the pixel TFT 204 by the gate wiring 122 and the source wiring 152, respectively. In addition, Flexible Printed C
An ircuit (FPC) 191 is connected to the external input terminal 182 and used to input image signals and the like. Then, it is connected to each drive circuit by a connection wiring 183. Although not shown, the opposing substrate 175 is provided with a light-shielding film and a transparent electrode.

The liquid crystal display device having such a configuration can be formed using the active matrix substrates shown in Embodiments 1 to 3. A reflective liquid crystal display device can be obtained by using the active matrix substrates described in Embodiments 1 and 2, and a transmissive liquid crystal display device can be obtained by using the active matrix substrate described in Embodiment 3.

[Embodiment 5] In this embodiment, a self-luminous display panel (hereinafter, referred to as an EL display device) using an electroluminescent (EL) material by using the active matrix substrate of the embodiment 1 will be described. ) Will be described. Note that luminescence includes light emission due to fluorescence and phosphorescence, but electroluminescence referred to in this specification includes light emission due to one or both of them. FIG. 17A is a top view of an EL display panel using the present invention. FIG.
10A, reference numeral 10 denotes a substrate, 11 denotes a pixel portion, 12 denotes a source side driving circuit, 13 denotes a gate side driving circuit, and each driving circuit reaches the FPC 17 via wirings 14 to 16 and is connected to an external device. Is done.

FIG. 17B is a cross-sectional view taken along the line AA ′ of FIG. 17A. At this time, the opposing plate 80 is provided at least over the pixel portion, preferably over the driving circuit and the pixel portion. The opposing plate 80 is bonded to the active matrix substrate on which a light emitting layer using a TFT and an EL material is formed by a sealing material 19. A filler (not shown) is mixed in the sealant 19, and the two substrates are bonded with a substantially uniform interval by the filler. Further, the outside of the seal member 19 and the upper surface and the periphery of the FPC 17 are sealed with a sealant 81. The sealant 81 uses a material such as a silicone resin, an epoxy resin, a phenol resin, and butyl rubber.

As described above, when the active matrix substrate 10 and the counter substrate 80 are bonded together by the sealant 19, a space is formed therebetween. The space is filled with a filler 83. The filler 83 also has the effect of bonding the opposing plate 80. Filler 83 is made of PVC (polyvinyl chloride), epoxy resin, silicone resin, P
VB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. Further, since the light emitting layer is weak to moisture including water and easily deteriorated, it is desirable to mix a desiccant such as barium oxide in the filler 83 because the moisture absorbing effect can be maintained. Also,
A passivation film 82 formed of a silicon nitride film, a silicon oxynitride film, or the like is formed over the light emitting layer, and a filler 83
It has a structure to prevent corrosion due to alkali elements and the like contained in.

A glass plate, an aluminum plate, a stainless steel plate, FRP (Fiberglass-Reinforced Pl)
astics) plate, PVF (polyvinyl fluoride) film, mylar film (trade name of DuPont), polyester film, acrylic film or acrylic plate. Further, moisture resistance can be enhanced by using a sheet having a structure in which an aluminum foil of several tens of μm is sandwiched between PVF films or mylar films. In this way, the EL element is in a sealed state and is isolated from the outside air.

In FIG. 17B, a TFT for a drive circuit (here, a C-type TFT combining an n-channel TFT and a p-channel TFT) is formed on the substrate 10 and the base film 21.
2 illustrates a MOS circuit. 22) and TFT for pixel portion
23 (however, here, TF for controlling the current to the EL element)
Only T is shown. ) Is formed. These T
Among the FTs, an n-channel TFT, in particular, is provided with an LDD region having the structure shown in this embodiment in order to prevent a decrease in on-current due to the hot carrier effect and a decrease in characteristics due to Vth shift and bias stress.

For example, the driving circuit TFT 22 is formed as shown in FIG.
The p-channel TFTs 200 and 202 and the n-channel TFTs 201 and 203 shown in FIG. Also,
The pixel TFT 2 shown in FIG.
04 or p-channel type TF having a structure similar thereto
T may be used.

In order to manufacture an EL display device from the active matrix substrate in the state shown in FIG. 6C or FIG. Is formed, and a T for pixel portion is formed thereon.
A pixel electrode 27 made of a transparent conductive film electrically connected to the drain of the FT 23 is formed. For the transparent conductive film, a compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used. After the pixel electrode 27 is formed, the insulating film 28 is formed.
Is formed, and an opening is formed on the pixel electrode 27.

Next, the light emitting layer 29 is formed. Light emitting layer 29
Are known EL materials (a hole injection layer, a hole transport layer, a light emitting layer,
An electron transport layer or an electron injection layer) may be freely combined to form a stacked structure or a single-layer structure. A known technique may be used to determine the structure. EL materials include low molecular weight materials and high molecular weight (polymer) materials.
When a low molecular material is used, an evaporation method is used. When a high molecular material is used, a simple method such as a spin coating method, a printing method, or an ink jet method can be used.

The light emitting layer is formed by a vapor deposition method using a shadow mask,
Alternatively, it is formed by an inkjet method, a dispenser method, or the like. In any case, light emitting layers capable of emitting light of different wavelengths for each pixel (red light emitting layer, green light emitting layer, and blue light emitting layer)
Is formed, color display becomes possible. In addition, there are a method in which a color conversion layer (CCM) and a color filter are combined, and a method in which a white light emitting layer and a color filter are combined, and any method may be used. Needless to say, a monochromatic EL display device can be used.

After the light emitting layer 29 is formed, the cathode 3
0 is formed. It is desirable to remove moisture and oxygen existing at the interface between the cathode 30 and the light emitting layer 29 as much as possible. Therefore, it is necessary to devise a method of continuously forming the light emitting layer 29 and the cathode 30 in a vacuum or forming the light emitting layer 29 in an inert atmosphere and forming the cathode 30 in a vacuum without opening to the atmosphere. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

In this embodiment, the cathode 30 is made of Li
A laminated structure of an F (lithium fluoride) film and an Al (aluminum) film is used. Specifically, 1 is formed on the light emitting layer 29 by the vapor deposition method.
A LiF (lithium fluoride) film having a thickness of nm is formed, and an aluminum film having a thickness of 300 nm is formed thereon. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 30 is connected to the wiring 16 in a region indicated by 31. The wiring 16 is a power supply line for applying a predetermined voltage to the cathode 30, and is connected to the FPC 17 via an anisotropic conductive paste material 32. A resin layer 80 is further formed on the FPC 17 to increase the adhesive strength at this portion.

In order to electrically connect the cathode 30 and the wiring 16 in the region indicated by 31, it is necessary to form contact holes in the interlayer insulating film 26 and the insulating film 28. These may be formed at the time of etching the interlayer insulating film 26 (at the time of forming a contact hole for a pixel electrode) or at the time of etching the insulating film 28 (at the time of forming an opening before forming a light emitting layer). Further, when the insulating film 28 is etched, the etching may be performed all at once up to the interlayer insulating film 26. In this case, if the interlayer insulating film 26 and the insulating film 28 are made of the same resin material, the shape of the contact hole can be made good.

The wiring 16 is composed of a seal 19 and the substrate 10.
Is electrically connected to the FPC 17 through a gap (but closed with a sealant 81). Although the wiring 16 has been described here, the other wirings 14 and 15 are also electrically connected to the FPC 17 under the sealing material 18 in the same manner.

FIG. 18 shows a more detailed sectional structure of the pixel portion, FIG. 19A shows a top structure thereof, and FIG.
It is shown in (B). In FIG. 18A, a switching TFT 2402 provided on a substrate 2401 is the same as that of the first embodiment.
6C is formed with the same structure as the pixel TFT 204 shown in FIG. With a double gate structure, substantially two TFs
There is an advantage that the structure is such that T is connected in series, and the off-current value can be reduced. In this embodiment, a double gate structure is used, but a triple gate structure or a multi-gate structure having more gates may be used.

The current controlling TFT 2403 is the same as that shown in FIG.
It is formed using an n-channel TFT 201 shown in FIG. At this time, the drain line 35 of the switching TFT 2402 is electrically connected to the gate electrode 37 of the current controlling TFT by the wiring 36. A wiring indicated by 38 is a gate line that electrically connects the gate electrodes 39a and 39b of the switching TFT 2402.

At this time, it is very important that the current control TFT 2403 has the structure of the present invention. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows and the element has a high risk of deterioration due to heat or hot carriers. Therefore, by providing the current control TFT with an LDD region that partially overlaps the gate electrode, deterioration of the TFT is prevented,
Operation stability can be improved.

In this embodiment, the current controlling TFT 24 is used.
03 is shown with a single gate structure.
A multi-gate structure in which FTs are connected in series may be used.
Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

Further, as shown in FIG. 19A, the wiring to be the gate electrode 37 of the current controlling TFT 2403 has 24 wirings.
In a region indicated by 04, the region overlaps with the drain line 40 of the current control TFT 2403 via an insulating film. At this time, 24
In a region indicated by 04, a capacitor is formed. The capacitor 2404 functions as a capacitor for holding a voltage applied to the gate of the current control TFT 2403. The drain line 40 is a current supply line (power supply line) 2
501, a constant voltage is always applied.

The first passivation film 4 is formed on the switching TFT 2402 and the current control TFT 2403.
And a planarizing film 42 made of a resin insulating film thereon.
Is formed. It is very important to flatten the steps due to the TFT using the flattening film 42. Since a light-emitting layer formed later is very thin, light emission failure may occur due to the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming it so that the light emitting layer can be formed as flat as possible.

Reference numeral 43 denotes a pixel electrode (cathode of an EL element) made of a conductive film having high reflectivity.
403 is electrically connected to the drain. Pixel electrode 43
It is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof. Of course, a stacked structure with another conductive film may be employed. A groove (corresponding to a pixel) formed by banks 44a and 44b formed of an insulating film (preferably resin).
The light emitting layer 44 is formed in the inside. Although only one pixel is shown here, R (red), G (green), B (blue)
The light emitting layers corresponding to the respective colors may be separately formed. As the organic EL material for the light emitting layer, a π-conjugated polymer material is used. Typical polymer-based materials include polyparaphenylenevinylene (PPV), polyvinylcarbazole (PVK), and polyfluorene.
There are various types of PPV-based organic EL materials, for example, "H. Shenk, H. Becker, O. Gelsen, E. Kluge,
W. Kreuder, and H. Spreitzer, “Polymers for Light Emi
tting Diodes ”, Euro Display, Proceedings, 1999, p.33-
37 "or a material described in JP-A-10-92576.

As a specific light emitting layer, cyanopolyphenylene vinylene is used for a light emitting layer emitting red light, polyphenylene vinylene is used for a light emitting layer emitting green light, and polyphenylene vinylene or polyalkylphenylene is used for a light emitting layer emitting blue light. Good. Thickness is 30-150nm
(Preferably 40 to 100 nm). However, the above example is an example of an organic EL material that can be used as a light emitting layer, and there is no need to limit the invention to this.
A light-emitting layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light-emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, an example in which a polymer material is used as the light emitting layer has been described.
A low molecular organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

In this embodiment, PEDOT is formed on the light emitting layer 45.
The light emitting layer has a laminated structure in which a hole injection layer 46 made of (polythiophene) or PANi (polyaniline) is provided. An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of this embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (toward the upper side of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, it is possible to form after forming a light-emitting layer or a hole-injecting layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

When the anode 47 is formed, the self-luminous element 2405 is completed. The EL element 240 referred to here
Reference numeral 5 denotes a capacitor formed by the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 46, and the anode 47. FIG.
As shown in FIG. 9A, the pixel electrode 43 substantially matches the area of the pixel, so that the entire pixel functions as an EL element. Therefore, the efficiency of light emission is extremely high, and a bright image can be displayed.

In the present embodiment, a second passivation film 48 is further provided on the anode 47. Second
As the passivation film 48, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated due to oxidation and the effect of suppressing outgassing from the organic EL material. Thereby, the reliability of the EL display device is improved.

As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. 19, and a switching TFT having a sufficiently low off-state current value and a current controlling portion which is resistant to hot carrier injection. And a TFT. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.

FIG. 18B shows an example in which the structure of the light emitting layer is inverted. The current controlling TFT 2601 corresponds to p
It is formed using a channel type TFT 200. Embodiment 1 can be referred to for the manufacturing process. In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

The banks 51a and 51b made of an insulating film are used.
Is formed, a light emitting layer 52 made of polyvinyl carbazole is formed by applying a solution. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, an EL element 2602 is formed. In the case of this embodiment, the light generated in the light emitting layer 53 is emitted toward the substrate on which the TFT is formed as indicated by the arrow. In the case of the structure as in this embodiment, it is preferable that the current control TFT 2601 be formed of a p-channel TFT.

The structure of this embodiment is different from that of the first and second embodiments in that
FT configurations can be implemented in any combination. In addition, it is effective to use the EL display panel of this embodiment as the display unit of the electronic device of the eighth embodiment.

[Embodiment 6] In this embodiment, FIG. 20 shows an example in which a pixel having a structure different from that of the circuit diagram shown in FIG. 19B is used. In this embodiment, 2701
270 is the source wiring of the switching TFT 2702, 270
3 is a gate wiring of the switching TFT 2702, 27
04 is a current control TFT, 2705 is a capacitor, 27
Reference numerals 06 and 2708 denote current supply lines, and 2707 denotes an EL element.

FIG. 20A shows an example in which the current supply line 2706 is shared between two pixels. That is, it is characterized in that the two pixels are formed to be line-symmetric with respect to the current supply line 2706. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 20B shows a current supply line 270.
8 is provided in parallel with the gate wiring 2703. Note that in FIG. 20B, the current supply line 2708 and the gate wiring 2703 are provided so as not to overlap with each other; however, if the wirings are formed in different layers, they overlap with each other via an insulating film. It can also be provided as follows. In this case, since the power supply line 2708 and the gate wiring 2703 can share an occupied area, the pixel portion can have higher definition.

FIG. 20C shows that a current supply line 2708 is provided in parallel with the gate wiring 2703 and two pixels are connected to the current supply line 2708 similarly to the structure of FIG. 20B.
It is characterized in that it is formed so as to be line-symmetric with respect to.
It is also effective to provide the current supply line 2708 so as to overlap with one of the gate wirings 2703. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition. FIG.
20A and FIG. 20B, a capacitor 240 is used to hold the voltage applied to the gate of the current control TFT 2403.
4, but the capacitor 2404 can be omitted.

As the current controlling TFT 2403, FIG.
Since the n-channel TFT of the present invention as shown in FIG. 1A is used, an LDD region is provided so as to overlap with a gate electrode via a gate insulating film. Although a parasitic capacitance generally called a gate capacitance is formed, this embodiment is characterized in that this parasitic capacitance is actively used instead of the capacitor 2404. The capacitance of the parasitic capacitance is determined by the gate electrode and the LDD region. And changes in the area that overlaps,
It is determined by the length of the LDD region included in the overlapping region. In the structures of FIGS. 20A, 20B, and 20C, the capacitor 2705 can be omitted.

The configuration of this embodiment is different from that of the first and second embodiments in that
FT configurations can be implemented in any combination. In addition, it is effective to use the EL display panel of this embodiment as the display unit of the electronic device of the eighth embodiment.

[Embodiment 7] In this embodiment, the TFT of the present invention is used.
A semiconductor device incorporating an active matrix liquid crystal display device using circuits will be described with reference to FIGS. 21, 22, and 23. FIG.

Such semiconductor devices include portable information terminals (electronic notebooks, mobile computers, mobile phones, etc.), video cameras, still cameras, personal computers,
TV and the like. Examples of these are shown in FIGS. 21 and 22.
Shown in

FIG. 21A shows a portable telephone, and a main body 90.
01, audio output unit 9002, audio input unit 9003, display device 9004, operation switch 9005, antenna 900
6. The present invention is an audio output unit 900
2. The present invention can be applied to a display device 9004 including an audio input unit 9003 and an active matrix substrate.

FIG. 21B shows a video camera, which includes a main body 9101, a display device 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 91.
06. The present invention can be applied to the display device 9102 and the image receiving unit 9106 each including the active matrix substrate.

FIG. 21C shows a mobile computer or a portable information terminal.
02, an image receiving section 9203, operation switches 9204, and a display device 9205. The present invention relates to an image receiving unit 920.
3 and display device 9 including active matrix substrate
205 can be applied.

FIG. 21D shows a head-mounted display, which comprises a main body 9301, a display device 9302, and an arm portion 9303. The present invention can be applied to the display device 9302. Although not shown, it can be used for other driving circuits.

FIG. 21E shows a television set having a main body 940.
1, a speaker 9402, a display device 9403, a receiving device 9404, an amplifying device 9405, and the like. Example 5
The liquid crystal display device shown by, and the EL display device shown by Embodiment 6 or 7 can be applied to the display device 9403.

FIG. 21F shows a portable book, and a main body 95.
01, display devices 9502 and 9503, storage medium 950
4, comprising an operation switch 9505 and an antenna 9506 for displaying data stored on a mini disk (MD) or a DVD or data received by the antenna. The display devices 9502 and 9503 are direct-view display devices, and the present invention can be applied to this.

FIG. 22A shows a personal computer, which includes a main body 9601, an image input section 9602, and a display device 9.
603 and a keyboard 9604.

FIG. 22B shows a player using a recording medium on which a program is recorded (hereinafter, referred to as a recording medium). The main body 9701, the display device 9702, and the speaker 97
03, a recording medium 9704, and operation switches 9705. This device uses a DVD (Di) as a recording medium.
It is possible to watch music, watch a movie, play a game, or use the Internet by using a CD (g. Versatile Disc) or a CD.

FIG. 22C shows a digital camera, which includes a main body 9801, a display device 9802, an eyepiece 9803, operation switches 9804, and an image receiving unit (not shown).

FIG. 23A shows a front type projector, which comprises a display device 3601 and a screen 3602. The present invention can be applied to a display device and other driving circuits.

FIG. 23B shows a rear type projector, which includes a main body 3701, a projection device 3702, and a mirror 370.
3. It is composed of a screen 3704. The present invention can be applied to a display device and other driving circuits.

FIG. 23C is a diagram showing an example of the structure of the projection devices 3601 and 3702 in FIGS. 23A and 23B. Projection devices 3601, 37
02 denotes a light source optical system 3801, mirrors 3802, 380
4 to 3806, dichroic mirror 3803, prism 3807, liquid crystal display device 3808, retardation plate 380
9. It is composed of a projection optical system 3810. Projection optical system 38
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 23D is a diagram showing an example of the structure of the light source optical system 3801 in FIG. 23C. In this embodiment, the light source optical system 3801 includes a reflector 3811, a light source 3812, a lens array 3813,
814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system shown in FIG. 23D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

In addition, the present invention can be applied to an image sensor and an EL display device. As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields.

Example 8 In order to confirm the effectiveness of the present invention, nonmetallic elements (B, Si, P, As, He, Ne, A
The following experiment was performed using argon (Ar) among one or more selected from r, Kr, and Xe).

The semiconductor film is formed on a 50 nm amorphous silicon film by one step.
After applying an aqueous solution containing 0 ppm nickel acetate, 500 ppm
A crystalline semiconductor film crystallized by a dehydrogenation treatment at 1 ° C. for 1 hour and a heat treatment at 550 ° C. for 4 hours was used. After patterning this crystallized semiconductor film, a 90 nm silicon oxide film was formed. Then, a sample in which phosphorus was injected into the gettering site by the ion doping method, a sample in which argon was injected after phosphorus was injected, and a sample in which only argon was injected were prepared, and these were comparatively evaluated. At this time,
The phosphorus implantation conditions were 5% PH ₃ diluted with hydrogen, an acceleration voltage of 80 keV, and a dose of 1.5 × 10 ¹⁵ / cm ² . The time required for the implantation is about 8 minutes, and phosphorus having an average concentration of 2 × 10 ²⁰ / cm ³ can be implanted into the crystalline semiconductor film. On the other hand, argon is 90 keV acceleration voltage and 2
The implantation was performed at a dose of × 10 ¹⁵ or 4 × 10 ¹⁵ / cm ² .
Argon used was 99.9999% or more, and the time required for the injection was preferably 1 to 2 minutes.

The gettering was performed by heat treatment at 550 ° C. for 4 hours in a nitrogen atmosphere. After gettering,
After removing the silicon oxide film, the substrate was treated with FPM. The gettering effect was confirmed by the number of etch pits in the gettering region of the crystalline semiconductor film. That is, it is known that most of the added nickel remains in the crystalline semiconductor film as nickel silicide, but this is etched by FPM (a mixed solution of hydrofluoric acid, hydrogen peroxide, and pure water). Therefore, the effect of gettering can be confirmed by processing the gettered region with FPM and confirming the presence or absence of an etch pit. in this case,
The smaller the number of etch pits, the higher the gettering effect. FIG. 25 shows a simplified view of a sample in which an etch pit has been formed. In FIG. 25, the doped region 10
Reference numeral 401 denotes a region to which argon or phosphorus is added. The number of etch pits 10403 present in the gettered region (gettered region) 10402 was counted while observing with an optical microscope to obtain an etch pit density.

FIG. 24 shows the result. FIG. 24
The sample indicated by P is a sample to which only phosphorus was added.
Therefore, the phosphorus injection condition of this sample was 5 μl diluted with hydrogen.
% PH_ThreeUsing an acceleration voltage of 80 keV and a dose of 1.5 ×
10^Fifteen/cm^TwoAnd In FIG. 24, P + Ar
For the sample indicated as (1 min), phosphorus and argon were added.
The phosphorus injection condition for this sample was hydrogen
5% PH diluted_ThreeAt an accelerating voltage of 80 keV
1.5 × 10^Fifteen/cm^TwoAnd argon injection conditions are:
2 × 10 at 90 keV accelerating voltage^Fifteen/cm^TwoDose and
The time required for argon injection was set to 1 minute. Also,
In FIG. 24, a sample indicated as P + Ar (2 min)
Is a sample to which phosphorus and argon are added.
Phosphorus injection conditions are 5% PH diluted with hydrogen_ThreeTo
Used, acceleration voltage 80 keV, dose 1.5 × 10^Fifteen/cm^Two
The argon injection conditions were 90 keV acceleration voltage,
4 × 10^Fifteen/cm ^TwoDose required for argon injection
The time taken was 2 minutes. Also, in FIG.
Where Ar is a sample to which only argon is added.
The argon injection condition of this sample was 90 keV
2 × 10 at accelerating voltage^Fifteen/cm^TwoDose.

According to the experimental results shown in FIG. 24, the sample to which only phosphorus was added had an etch pit density of 3.5 × 10 ⁻³ / μm ² , whereas the sample to which gettering was performed by adding argon was used. Is less than 5 × 10 ⁻⁴ / μm ² , and it can be seen that the number is extremely reduced. This result means that the effect of gettering is extremely enhanced by injecting argon, and the nonmetallic elements (B, Si, P, As, He, Ne, Ar, Kr, and Xe) of the present invention are obtained.
Gettering using one or more kinds selected from (1) is extremely effective.

[0149]

According to the present invention, when gettering a metal contained in a crystalline semiconductor thin film containing silicon as a main component,
Improve at least one of gettering efficiency and effectiveness. In this specification, improving the gettering efficiency means reducing the heat supply amount (= temperature × time) for reducing the amount of metal contained in the element active region. In this specification, improving the effect of gettering means reducing the remaining amount of the gettering metal in the element active region even when the heat supply amount is the same.

[0150]

[Brief description of the drawings]

FIG. 1 is a schematic view of crystallization and gettering of a semiconductor thin film of the present invention.

FIG. 2 is a schematic view of an island-like object of a semiconductor thin film and a silicon oxide film formed at the time of gettering of the present invention.

FIG. 3 is a schematic view of islands of a semiconductor thin film and a silicon oxide film formed during gettering of the present invention.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 8 is a top view illustrating a structure of a driving circuit TFT and a pixel TFT.

FIG. 9 is a cross-sectional view illustrating a structure of a TFT and a pixel TFT of a driving circuit.

FIG. 10 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 11 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 12 is a cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.

FIG. 13 is a cross-sectional view illustrating a configuration of an active matrix liquid crystal display device.

FIG. 14 is a top view illustrating input terminals, wiring, circuit arrangement, spacers, and sealants of a liquid crystal display device.

FIG. 15 is a perspective view illustrating a structure of a liquid crystal display device.

FIG. 16 is a top view illustrating a pixel in a pixel portion.

17A and 17B are a top view and a cross-sectional view illustrating a structure of an EL display device.

FIG. 18 is a cross-sectional view of a pixel portion of an EL display device.

FIG. 19 is a top view and a circuit diagram of a pixel portion of an EL display device.

FIG. 20 is an example of a circuit diagram of a pixel portion of an EL display device.

FIG. 21 illustrates an example of a semiconductor device.

FIG. 22 illustrates an example of a semiconductor device.

FIG. 23 illustrates an example of a projector.

FIG. 24 is a graph showing etch pit density (pieces / μm ² ) observed by FPM processing after gettering.

FIG. 25 is a simplified diagram showing etch pits observed by FPM processing after gettering.

[Explanation of symbols]

10101: insulating film substrate. Glass substrate, quartz substrate, etc. Reference numeral 10102: a semiconductor thin film having an amorphous structure containing silicon as a main component 10103: an aqueous solution of Ni acetate 10104: an island-like insulating film 10106: a non-metal element or a region to which ions of the non-metal element are added 10107: silicon as a main component A crystalline semiconductor thin film 10108: a boundary surface between a region to which a nonmetallic element or ions of a nonmetallic element is added and a region to which no ion is added. Reference numeral 10109: a region to which a nonmetal element or ions of the nonmetal element are added 10110: a direction in which Ni moves 10201: an island-shaped insulating film 10202: a surface parallel to the surface of the crystalline semiconductor thin film containing silicon as a main component 10203: Surface of a crystalline semiconductor thin film containing silicon as a main component 10204: A region to which a nonmetallic element or ions of the nonmetallic element is added 10205: A region to which a nonmetallic element or ions of the nonmetallic element is added 10206: Silicon as a main component A crystalline semiconductor thin film 10207: an insulating film substrate. Glass substrate, quartz substrate, etc. 10208: The shape of the island-shaped insulating film with respect to a plane parallel to the surface of the crystalline semiconductor thin film containing silicon as a main component. 10301: island-shaped insulating film 10302: crystalline semiconductor thin film containing silicon as a main component 10303: insulating film substrate. Glass substrate, quartz substrate, etc.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 21/336 H01L 29/78 627G

Claims (9)

[Claims] 1. A step of forming a semiconductor thin film having an amorphous structure containing silicon as a main component, a step of adding a metal to the semiconductor thin film having an amorphous structure, and a step of forming a semiconductor having the amorphous structure. Forming a crystalline semiconductor thin film containing silicon as a main component by a first heat treatment, forming an island-shaped insulating film, and using the island-shaped insulating film as a mask to form a non-metallic element or Adding the ions of the non-metallic element to the crystalline semiconductor thin film to form a non-metallic element or a region to which the ions of the non-metallic element are added in the crystalline semiconductor thin film; Heat-treating to getter the metal in a region to which the non-metallic element or the ion of the non-metallic element is added, wherein the island-like shape with respect to a plane parallel to the surface of the crystalline semiconductor thin film is provided. Insulation film Shape is a polygonal shape having a number n (n> 20) number of vertices, and the interior angle of the apex 18
A method for manufacturing a semiconductor device, which is a polygon having a number m (m> 8) of vertices of 0 ° or more. 2. The method according to claim 1, wherein the metal is nickel.
(Ni), cobalt (Co), palladium (Pd), platinum (P
t) copper (Cu). 3. The method for manufacturing a semiconductor device according to claim 1, wherein the first heat treatment is performed at a temperature higher than or equal to 400.degree. 4. The method according to claim 1, wherein said non-metallic element or non-metallic element ion is boron (B), silicon (Si), phosphorus (P), arsenic (As), helium (He), neon (N
e) one or more selected from argon (Ar), krypton (Kr), and xenon (Xe). 5. The method for manufacturing a semiconductor device according to claim 1, wherein the second heat treatment is performed at a temperature higher than or equal to 400 ° C. and lower than or equal to 1000 ° C. 6. A step of forming a semiconductor thin film having an amorphous structure containing silicon as a main component, a step of adding a metal to the semiconductor thin film having the amorphous structure, and a step of forming a semiconductor having the amorphous structure. Forming a crystalline semiconductor thin film containing silicon as a main component by a first heat treatment, forming an island-shaped insulating film, and using the island-shaped insulating film as a mask to form a non-metallic element or Adding the ions of the non-metallic element to the crystalline semiconductor thin film to form a non-metallic element or a region to which the ions of the non-metallic element are added in the crystalline semiconductor thin film; And b. Heat-treating the metal to getter the metal in a region to which the non-metallic element or ions of the non-metallic element are added. 7. The method according to claim 6, wherein the metal is nickel.
(Ni), cobalt (Co), palladium (Pd), platinum (P
t) copper (Cu). 8. The method according to claim 6, wherein said non-metallic element or non-metallic element ion is boron (B), silicon (Si), phosphorus (P), arsenic (As), helium (He), neon (N
e) one or more selected from argon (Ar), krypton (Kr), and xenon (Xe). 9. The method according to claim 8, wherein said argon is applied to said crystalline semiconductor thin film at an acceleration voltage of 90 keV and 2 × 10
^A method for manufacturing a semiconductor device, which is added at a dose of ¹⁵ / cm ² .