JP2001274405A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the gettering technology which can increase the throughput by shortening the heat treatment time and thereby improving the gettering efficiency, for gettering in a process of removing impurity elements such as heavy metal elements mixed in semiconductor manufacturing processes, possibly shortening the life of the carrier of silicon to cause a defective gate oxide film and decline in reliability. SOLUTION: The grain boundaries in a semiconductor region in the vicinity of a channel formed region are used in a gettering site and, at the same time, gettering using ion implantation is conducted. Due to this method, a plurality of kinds of impurity elements such as heavy metal elements can be removed, and depletion layers in the channel formed region 407 and PN junctions of a TFT can be efficiently applied getting.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a circuit including an active matrix type field effect thin film transistor (hereinafter, referred to as a TFT) on a substrate having an insulating surface, and a method for manufacturing the same. A semiconductor device in this specification refers to all devices that function by utilizing semiconductor characteristics. In particular, the present invention can be suitably used for an electro-optical device typified by a liquid crystal display device provided with an image display area and a driving circuit for displaying an image on the same substrate, and an electronic device equipped with the electro-optical device. The semiconductor device includes the electro-optical device and an electronic device including the electro-optical device in its category.

[0002]

2. Description of the Related Art A TFT having a crystalline silicon semiconductor layer typified by polycrystalline silicon (polysilicon), microcrystalline silicon and single crystal silicon (hereinafter referred to as crystalline silicon T).
FT) has a higher field-effect mobility than a TFT having an amorphous silicon semiconductor layer (hereinafter, referred to as amorphous silicon TFT) and can operate at high speed. For this reason, it was inappropriate to use an amorphous silicon TFT for manufacturing a drive circuit for an image area requiring high-speed operation, but using a crystalline silicon TFT makes it possible to manufacture it on the same substrate as the image display area. became.

[0003] However, the problem of impurity elements such as heavy metals mixed during the manufacturing process of semiconductor devices has not been sufficiently solved. In particular, when a heavy metal element forms a solid solution in silicon, a deep level is formed in a band gap, and the lifetime of silicon carriers is reduced. Further, it precipitates as silicide during heat treatment, causing dielectric breakdown of the gate oxide film and poor reliability, thereby lowering the yield of the device.

Therefore, in order to obtain a device having good characteristics and high reliability, a method of removing impurity elements such as heavy metals,
That is, gettering technology is important. As one of the gettering techniques, there is a technique described in JP-A-10-303430. The technology disclosed in the publication discloses a method of performing crystal growth by introducing a metal that promotes crystallization, moving the metal that promotes crystallization to a region doped with an element represented by P, and performing gettering. It is. This technique lowers the crystallization temperature by the action of a metal that promotes crystallization, reduces the time required for crystallization, and reduces the electric power of the semiconductor device after crystallization is completed. The metal which promotes crystallization is reduced from the crystalline film to such an extent that it is not removed or adversely affected so that the characteristics are not deteriorated or the reliability is not reduced. By using this technique, a metal that promotes crystallization by low-temperature heat treatment can be gettered, and the characteristics of a low-temperature process can be utilized in manufacturing a semiconductor device.

[0005]

The gettering needs to be performed completely. If the incomplete gettering portion remains on the substrate surface, each transistor will have variations in electrical characteristics. sell. In order to perform the gettering completely, the heat treatment time at the time of gettering may be lengthened,
From the viewpoint of throughput, the heat treatment time is preferably as short as possible. An object of the present invention is to improve gettering efficiency and perform gettering completely in a short time.

[0006]

Means for Solving the Problems In order to solve the above problems, the present inventors have paid attention to a mechanism for controlling the rate of gettering. FIG. 1 is an SEM photograph of a crystalline silicon semiconductor layer formed on an insulating substrate after FPM (dilute hydrofluoric acid) treatment.
This crystalline silicon semiconductor layer is disclosed in
According to the technique described in Japanese Patent Application Laid-open No. 2 (1994) -2002, it is formed by using a metal element Ni and further subjected to laser annealing. Therefore, Ni silicide exists in this semiconductor layer. In the FPM process, a dangling bond such as a crystal grain boundary and a metal or a silicide are selectively etched. Therefore, by observing a hole formed by the etching, a region where the metal or the silicide is segregated can be known. FIG. 1 shows a large number of etched holes formed by the FPM process, and the holes are most often found at boundaries between crystal grains, that is, at grain boundaries. That is, impurity elements such as heavy metals such as Ni are easily segregated at crystal defects, particularly at crystal grain boundaries in the crystalline silicon semiconductor layer, and this segregation governs gettering. Therefore, if the crystal grain boundaries in the semiconductor layer can be eliminated, gettering can be performed efficiently and in a short time. However, it is not easy to completely eliminate grain boundaries. Therefore, the present inventors have considered a method of reversing the idea and actively utilizing the crystal grain boundaries for gettering.

That is, the present inventors have considered a method of using a region having a large number of crystal grain boundaries as a gettering site. In the gettering of a silicon wafer, a PBS (Polysilicon Back Seal) method in which a crystalline silicon film is deposited on the back surface and used as a gettering site is known. A gettering site is formed to enhance the gettering effect. Since the gettering site is formed close to the element formation region, the gettering ability is increased and the time required for gettering can be reduced.

Usually, a plurality of types of impurity elements such as heavy metals are present in a semiconductor layer, and it is known that the gettering method is compatible with impurity elements such as heavy metals. For example, gettering using P has a large effect on Ni, and gettering using B has a large effect on Fe. That is, in order to remove a plurality of types of impurity elements such as heavy metals, it is effective to combine a plurality of gettering methods. In this specification, gettering is performed by giving a gradient to the concentration of a metal element such as P described in Japanese Patent Application No. 11-372214 to remove impurity elements such as heavy metals near the junction, The method of using the world as a gettering site is combined to enhance the gettering effect.

The essence of the present technology is to make the density of the crystal grain boundary at the gettering site higher than the density of the crystal grain boundary in the region where the gettering is to be performed. The density of the grain boundary is defined by the length of the grain boundary per unit area. The length of the crystal grain boundary is a quantity that can be measured by an SEM photograph or AFM after secoetch. By increasing the density of the crystal grain boundary of the gettering site, the same effect as in the case of reducing the density of the crystal grain boundary in a region close to the gettering site can be obtained. By increasing the density of the crystal grain boundaries at the gettering sites, impurity elements such as heavy metals can be segregated at the crystal grain boundaries at the gettering sites.

[0010] Since the crystal grain boundaries are often curved,
It is difficult to determine its length. Therefore, in this specification, a parameter that can be easily measured corresponding to the density of the crystal grain boundary is used. This focuses on the number of intersecting points of the crystal grain boundaries, and utilizes that the density of the intersecting points of the crystal grain boundaries is large and the density of the crystal grain boundaries is large. FIG. 2 shows a model in which each crystal grain is modeled as a square having a side length of a. The intersection of each crystal grain boundary is often a triple point (FIG. 2 (a)), but a quadruple point may be formed as shown in FIG. 2 (b). Since the frequency at which five or more crystal grain boundaries intersect at one point is extremely small, it is not considered after the five-point. Here, paying attention to the number of intersections on the line c in FIG. 2 (c) representing a set of triple points and FIG. 2 (d) representing a set of quadruples, Is twice as high as the density at the intersection of the crystal grain boundaries in FIG. 2 (d). Therefore, considering that the density of grain boundaries (line length per unit area) is the same in Figs. 2 (c) and 2 (d), the number of intersections is doubled at the quadruple point. I do. Thereby, the density of the crystal grain boundary and the density of the intersection of the crystal grain boundary can be made to correspond, and the gettering ability can be defined by the density of the intersection of the crystal grain boundary.

The average area of crystal grains can also be used as a method for defining the gettering ability so as to be easily understood visually. That is, each crystal grain is approximated by a circle (the diameter of a circle having the same area is obtained), and the diameter of this circle is defined as the particle size of each crystal grain. The value obtained by averaging the grain sizes of the respective crystal grains in the region of interest is defined as the crystal grain size. The smaller the average particle size, the higher the density of the crystal grain boundaries, so that impurity elements such as heavy metals are easily segregated and can be used as gettering sites.

The configuration of the present invention will be described with reference to FIG.
The substrate 403 is a glass substrate or a quartz substrate. On the substrate 403, a channel forming region 407, first impurity regions 401 and 411 outside the channel forming region 407, and second impurity regions 402 and 412 outside the channel forming region 407 are further formed. An impurity element of one conductivity type is introduced into the first impurity regions 401 and 411 at a first concentration, and an impurity element of the same type as the conductivity type is introduced into the second impurity regions 402 and 412 at a second concentration. The channel forming region 407 is formed of a metal (Ni
, Etc.). An insulating film 404 is formed on the channel forming region 407, and a gate electrode 405 is formed facing the channel forming region 407 via the insulating film 404. A region in which the first impurity regions 401 and 411 and the second impurity regions 402 and 412 are combined becomes the whole or a part of the source / drain regions. The insulating film 404 may be formed on the source / drain regions. When an LDD region or an offset region is formed, the first impurity regions 401 and 411 and the second impurity region are interposed between the channel forming region and the impurity region so as to sandwich the LDD region or the offset region.
Impurity regions 402 and 412 are formed.

The present invention relates to the first impurity regions 401 and 411.
Than the first concentration in the second impurity region 402,
412 is characterized in that the second density is higher. Further, the density of the intersection of the crystal grain boundaries in the second impurity regions 402 and 412 is larger than the density of the intersection of the crystal grain boundaries in the channel formation region 407, or the crystal grain size in the second impurity regions 402 and 412 is The diameter is smaller than the particle diameter in the channel forming region 407. Specifically, the invention of the present application is characterized in that the first concentration is 1
× 10 ¹⁹ / cm ^{3 to} 5 × 10 ²¹ / cm ³ , and the second concentration is
The first concentration is 1.2 to 1000 times the first concentration. The configuration of the present invention may be configured on both sides of the channel forming region as shown in FIG. 4, or may be configured on only one side. That is, for example, when it is desired to getter impurities near the junction of the drain region, the first impurity region and the second impurity region may be formed only on the drain side.

The above structure describes a case where impurity elements which give the same conductivity at the first concentration and the second concentration are introduced into the first impurity region and the second impurity region, respectively. Next, the structure of the present invention in the case of introducing impurity elements that give opposite conductivity at the first concentration and the second concentration to the first impurity region and the second impurity region, respectively, will be described with reference to FIG. explain. The structure is similar to that of the first impurity region 40.
1,411 is doped with an impurity element of one conductivity type at a first concentration, and the second impurity regions 402 and 412 are doped with an impurity element imparting the same conductivity type as the impurity element introduced into the first impurity region. The impurity element is introduced at the first concentration and an impurity element having a conductivity type opposite to the one conductivity type is introduced at a second concentration. This configuration is characterized in that the first density is higher than the second density. In addition, the density of the intersection of the crystal grain boundaries in the second impurity regions 402 and 412 is larger than the density of the intersection of the crystal grain boundaries in the channel formation region 407, or the crystal grain size in the second impurity regions 402 and 412 is , The channel forming region 4
It is smaller than the particle size in 07. Specifically, the present invention is characterized in that the second concentration is 1 × 10 ¹⁹ / cm ³ to 1 × 1
0 ²² / cm ³ . For example, P-type TF
In T, Ni is effectively gettered from the vicinity of the junction region by introducing P having a large effect of gettering Ni into the second impurity region. Another example is N-type T
In FT, if B having a large effect of gettering Fe is introduced into the second impurity region, Fe can be effectively gettered from the vicinity of the junction region.

It is not necessary that the region into which the impurity imparting one conductivity type is implanted and the region forming the gettering site completely match the second impurity region. That is, the first impurity region may be formed outside the channel formation region.

In this specification, the concentration is defined as follows. Generally, when impurities are introduced by thermal diffusion or ion implantation of impurities, the impurity concentration in the semiconductor layer varies depending on the depth in the semiconductor layer, and has an uneven concentration distribution. Therefore, the concentration here means a value obtained by averaging the concentration distribution in the depth direction in the semiconductor layer.

In this specification, the impurity elements such as heavy metals include alkali metal elements and nonmetal elements. That is, it indicates an element that lowers the characteristics of the device.

By using the above method, impurity elements such as heavy metals (3d transition metals, Fe, Co, Ru, Rh, Pd, Os, Ir, P
t, Cu, Au, etc.) can be effectively removed or reduced from the channel formation region of the transistor. In addition, by using the technique described in Japanese Patent Application No. 11-372214, an impurity element such as heavy metal can be removed or reduced from the PN junction near the boundary between the channel formation region and the source and drain regions. . That is, by increasing the concentration of the element represented by P in the second impurity region with respect to the concentration of the element represented by P in the first impurity region, the impurity element such as a heavy metal can be removed from the second impurity region. Then, impurities such as heavy metals in the junction region can be gettered.

The present invention is particularly effective when a metal that promotes crystallization (mainly a 3d transition metal) is used in forming a crystalline silicon thin film. A method of performing crystallization using a metal that promotes crystallization is disclosed in JP-A-10-303430.
No., published in Japanese Unexamined Patent Publication No.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention can be applied to an element forming technique of a semiconductor thin film device. In order to implement the present invention, it is necessary to form a region serving as a gettering site in the semiconductor layer, that is, a region having a high density of intersections of crystal grain boundaries or a small crystal grain size. As a method for selectively forming a region serving as a gettering site in the semiconductor layer, there are a method using a laser, a method using a heat treatment, a method of applying physical damage, and the like. A method using a laser will be described in Embodiment 1, and other methods will be described in Examples.

[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. Here, a method of gettering an impurity element such as a heavy metal using the present invention will be described in the order of steps, taking as an example a case where TFTs of a driver portion provided in a pixel portion and a peripheral portion thereof are simultaneously manufactured. In the present embodiment, a technique described in Japanese Patent Application No. 11-372214 for performing gettering by giving a gradient to the P concentration to remove impurity elements such as heavy metals near the junction is described in this specification. Next, a method will be described in which the technique of using an impurity element such as a heavy metal at the crystal grain boundary is also used. However, for the sake of simplicity, in the driving circuit, a CMOS circuit which is a basic circuit such as a shift register circuit and a buffer circuit, and an n-channel TFT forming a sampling circuit are illustrated.

In FIG. 5A, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass represented by Corning # 7059 glass or # 1737 glass, a quartz substrate, or the like is used as the substrate 101.
In the case of using a glass substrate, the glass strain point should be 10
The heat treatment may be performed in advance at a temperature lower by about 20 ° C. On the surface of the substrate 101 where the TFT is to be formed, the substrate 10
In order to prevent impurity diffusion from above, a base film 102 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. For example, plasma CV
The silicon oxynitride film 102a formed from SiH ₄ , NH ₃ , and N ₂ O by the method D is formed to a thickness of 10 to 200 nm (preferably 50 nm).
~ 100 nm), as well SiH _4, N ₂ O hydrogenated silicon oxynitride film 102b made from 50 to 200 nm (preferably laminated in a thickness of 100 to 150 nm). Here, the base film 102 has a two-layer structure; however, the base film 102 may be a single-layer film of the insulating film or a stack of two or more layers.

Next, 25 to 80 nm (preferably 30 to 6 nm)
Semiconductor layer 103a having a thickness of 0 nm) and having an amorphous structure.
Is formed by a method such as a plasma CVD method or a sputtering method. The semiconductor film having an amorphous structure includes an amorphous semiconductor layer and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used. In the case where an amorphous silicon film is formed by a plasma CVD method, both the base film 102 and the amorphous semiconductor layer 103a can be formed continuously. For example, the silicon oxynitride film 102a and the hydrogenated silicon oxynitride film 1
02b is continuously formed by a plasma CVD method, and then the reaction gas is changed from SiH ₄ , N ₂ O, and H ₂ to SiH ₄ and H ₂ or SiH _4.
By switching only to the above, continuous formation can be performed without once exposing to the atmosphere. As a result, the hydrogenated silicon oxynitride film 1
02b can be prevented from being contaminated, and variations in the characteristics of the TFT to be manufactured and fluctuations in the threshold voltage can be reduced.

Next, a crystallization step is performed to form a crystalline semiconductor layer 103b from the amorphous semiconductor layer 103a. Here, the crystallization method will be described with reference to FIG. The substrate 6003 corresponds to the substrate 101 in FIG. 5A, and the base film 6008 is the base film 10 in FIG.
It corresponds to 2. The amorphous semiconductor layer 103a in FIG. 5 corresponds to the semiconductor layer in FIG. Three types of regions are formed in the amorphous silicon semiconductor thin film by the following method. First, using a mask layer 100 (FIG. 5) of a silicon oxide film, a metal for promoting crystallization is selectively introduced into the channel formation region 6007 (FIG. 6).
The crystal is grown toward 01,6011 (FIG. 6). At this time, the amorphous regions 6002 and 6012 are added to the island-shaped semiconductor formation region 6004 (FIG. 6).
The distance for crystal growth is controlled appropriately so that (FIG. 6) remains. This crystal growth distance can be controlled by changing the amount of the metal to promote crystallization, the heat treatment temperature during crystallization, and the heat treatment time. Therefore crystalline silicon film
103b is composed of a crystalline region and an amorphous region. Next, after removing the mask layer 100 made of the silicon oxide film, the crystalline silicon film 103b is crystallized again by using a laser crystallization method. By optimally selecting the laser power, regions having different particle sizes can be formed.

FIG. 7 shows that an amorphous film formed on an insulating substrate is subjected to lateral crystal growth by the above-mentioned method using Ni as a metal for promoting crystallization, and then a XeCl excimer laser (wavelength 308 nm, It is a SEM photograph of the sample surface which performed laser crystallization using pulse width 30ns). FIG. 7A shows the channel formation region 6007 (FIG. 6), and FIG.
001, 6011 (FIG. 6), and FIG. 7 (c) shows the amorphous regions 6002, 6012 (FIG.
FIG. 6 is an SEM photograph of (6), which shows that the amorphous region portions 6002 and 6012 have the smallest crystal grain size and the highest density of crystal grain boundaries. Therefore, Ni is most easily segregated in the amorphous region portions 6002 and 6012 (FIG. 6), and Ni in the channel forming region 6007 (FIG. 6).
Is reduced by a subsequent heat treatment such as activation.

Then, a first layer is formed on the crystalline semiconductor layer 103b.
Lithography using a photomask (PM1)
A resist pattern is formed using the
The crystalline semiconductor layer is divided into islands by etching,
Forming island-shaped semiconductor layers 104 to 108 as shown in FIG.
I do. CF for dry etching of crystalline silicon film _Four
And O_TwoIs used.

For the purpose of controlling the threshold voltage (Vth) of the TFT, an impurity element imparting p-type is added to such an island-like semiconductor layer in an amount of about 1 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / cm ³ . The concentration may be added to the entire surface of the island-shaped semiconductor layer. The impurity element imparting p-type to the semiconductor includes boron (B),
Elements of Group 13 of the periodic table, such as aluminum (Al) and gallium (Ga), are known. As the method, an ion implantation method or an ion doping method (or an ion shower doping method) can be used, but the ion doping method is suitable for treating a large-area substrate. In the ion doping method, diborane (B ₂ H ₆ ) is used as a source gas and boron (B) is added. The implantation of such an impurity element is not always necessary and may be omitted. However, it is a method preferably used for keeping the threshold voltage of the n-channel TFT within a predetermined range.

The gate insulating film 109 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. In this embodiment, 120
It is formed from a silicon oxynitride film with a thickness of nm. Also, S
A silicon oxynitride film formed by adding O ₂ to iH ₄ and N ₂ O is a preferable material for this application because the fixed charge density in the film is reduced. In addition, SiH ₄
A silicon oxynitride film formed from N ₂ O and H ₂ is preferable because the density of interface defects with the gate insulating film can be reduced.
Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TE
Mix OS (Tetraethyl Orthosilicate) and O ₂ ,
It can be formed by discharging at a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm ² . The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.

Then, as shown in FIG. 5D, a heat-resistant conductive layer 111 for forming a gate electrode on the gate insulating film 109 of the first shape has a thickness of 200 to 400 nm (preferably 250 to 350 nm). It is formed with a thickness. The heat-resistant conductive layer may be formed as a single layer, or may have a laminated structure including a plurality of layers such as two layers or three layers as necessary.
The heat-resistant conductive layer referred to in this specification is a conductive material having a selectivity obtained by etching, such as a conductive nitride, a conductive oxide, or a conductive carbide. These heat-resistant conductive layers are formed by a sputtering method or a CVD method, and it is preferable to reduce the concentration of impurities contained therein in order to reduce the resistance. In particular, the oxygen concentration is preferably 30 ppm or less. In this embodiment, a W film is formed to a thickness of 300 nm. The W film may be formed by sputtering using W as a target, or may be formed by thermal CVD using tungsten hexafluoride (WF ₆ ). In any case, in order to use it as a gate electrode, it is necessary to reduce the resistance, and it is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is inhibited and the resistance is increased. From this, when the sputtering method is used, W of 99.9999% purity is obtained.
By using a target and forming the W film with sufficient care so as not to mix impurities from the gas phase during film formation, a resistivity of 9 to 20 μΩcm can be realized.

On the other hand, when a Ta film is used for the heat-resistant conductive layer 111, it can be similarly formed by a sputtering method. The Ta film uses Ar as a sputtering gas. Also, if an appropriate amount of Xe or Kr is added to the gas during sputtering,
The internal stress of the film to be formed can be relaxed to prevent the film from peeling. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used for the gate electrode.
The resistivity of the film was about 180 μΩcm, and was not suitable for use as a gate electrode. Since the TaN film has a crystal structure close to the α-phase, an α-phase Ta film can be easily obtained by forming a TaN film under the Ta film. Although not shown, phosphorus (P) having a thickness of about 2 to 20 nm is formed under the heat-resistant conductive layer 111.
It is effective to form a silicon film doped with a. Thereby, the adhesion of the conductive film formed thereon is improved and oxidation is prevented, and at the same time, a small amount of the alkali metal element contained in the heat-resistant conductive layer 111 diffuses into the gate insulating film 109 of the first shape. Can be prevented. In any case, the heat-resistant conductive layer 111 has a resistivity of 10 to 50 μΩ.
It is preferable to set it in the range of cm.

Next, as shown in FIG. 8A, using a second photomask (PM2), masks 112 to 117 made of resist are formed by photolithography. Then, a first etching process is performed. In this embodiment, an ICP etching apparatus is used, Cl ₂ and CF ₄ are used as etching gases, and RF of 3.2 W / cm ^{2 is} applied at a pressure of 1 Pa.
(13.56 MHz) Power is supplied to form plasma.
224 mW / cm ² RF (13.5
6 MHz), which applies a substantially negative self-bias voltage. Under these conditions, the etching rate of the W film is about 100 nm / min. In the first etching process, the time when the W film was just etched was estimated based on this etching rate, and the time obtained by increasing the etching time by 20% was set as the etching time.

The conductive layers 118 to 123 having the first tapered shape are formed by the first etching process. The angle of the tapered portion is 15 to 30 degrees. In order to perform etching without leaving a residue, over-etching is performed to increase the etching time at a rate of about 10 to 20%. The selectivity of the silicon oxynitride film (the first shape gate insulating film 109) to the W film is 2 to 4.
(Typically 3), the surface of the silicon oxynitride film exposed by the over-etching process is 20 to 50
A gate insulating film 170a having a second shape in which a tapered shape is formed in the vicinity of an end portion of the conductive layer having the first tapered shape by being etched by about nm is formed.

Then, a first doping process is performed to add an impurity element of one conductivity type to the island-shaped semiconductor layer. Here, a step of adding an n-type impurity element is performed. First
The masks 112 to 117 on which the conductive layers having the shapes shown in FIGS.
Using 123 as a mask, an impurity element imparting n-type in a self-aligned manner is added by an ion doping method. In order to add the impurity element imparting n-type through the tapered portion at the end of the gate electrode and the gate insulating film so as to reach the semiconductor layer located thereunder, the dose is set to 1 × 10 ^{13 to} 5 × 1.
This is performed at 0 ¹⁴ atoms / cm ² and an acceleration voltage of 80 to 160 keV. As an impurity element imparting n-type, an element belonging to Group 15 of the periodic table, typically, phosphorus (P) or arsenic (As) is used. Here, phosphorus (P) is used. By such an ion doping method, an impurity element imparting n-type is added to the third impurity regions 124 to 128 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ atomic / cm ³ , and the third impurity regions 124 to 128 are formed below the tapered portion. The fourth impurity region (A) to be formed is not necessarily uniform within the same region, but is 1 × 10 ¹⁷ to 1 × 10 ²⁰ atomic / cm ^3.
Is added within the concentration range of n.

In this step, at least the first shape conductive layer 118 is formed in the fourth impurity region (A).
The change in the concentration of the impurity element imparting n-type contained in the portion overlapping with the region 123 reflects the change in the thickness of the tapered portion. That is, the concentration of phosphorus (P) added to the fourth impurity regions (A) 129 to 132 gradually increases inward from the end of the conductive layer in the region overlapping the conductive layer having the first shape. The concentration will be lower. This is because the concentration of phosphorus (P) reaching the semiconductor layer changes depending on the difference in the thickness of the tapered portion.

Next, a second etching process is performed as shown in FIG. The etching process is similarly performed by an ICP etching apparatus, and CF ₄ and Cl ₂ are used as etching gases.
RF power 3.2W / cm ² (13.56MHz)
Etching is performed at a bias power of 45 mW / cm ² (13.56 MHz) and a pressure of 1.0 Pa. Conductive layers 140 to 145 having the second shape formed under these conditions are formed. A tapered portion is formed at the end, and the tapered shape gradually increases inward from the end. As compared with the first etching process, the ratio of the isotropic etching is increased by the lower bias power applied to the substrate side, and the angle of the tapered portion is 30 to 60 °. Further, the surface of the second shape gate insulating film 170a is etched by about 40 nm, and a third shape gate insulating film 170b is newly formed.

Then, an impurity element imparting n-type is doped under a condition of a higher acceleration voltage with a lower dose than in the first doping process. For example, when the accelerating voltage is 70 to 120
KeV, and a dose of 1 × 10 ¹³ / cm ² , so that the impurity concentration in a region overlapping with the conductive layers 140 to 145 having the second shape is 1 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ^3. To Thus, the fourth impurity region (B) 14
6 to 150 are formed.

Then, impurity regions 156 and 157 having a conductivity type opposite to one conductivity type are formed in the island-shaped semiconductor layers 104 and 106 forming the p-channel TFT. In this case also the second
An impurity element imparting p-type is added by using the conductive layers 140 and 142 having the above shape as a mask to form an impurity region in a self-aligned manner. At this time, the island-shaped semiconductor layers 105, 107, and 108 forming the n-channel TFT are formed by using resist masks 151 to 15 using a third photomask (PM3).
3 is formed and the entire surface is covered. The impurity regions 156 and 157 formed here are formed by an ion doping method using diborane (B ₂ H ₆ ). The concentration of the impurity element imparting p-type in impurity regions 156 and 157 is 2 × 10 ²⁰ to 2 ×
It is set to 10 ²¹ atoms / cm ³ .

However, the impurity regions 156, 1
Numeral 57 designates 3 containing an impurity element imparting n-type.
It can be divided into two areas. The third impurity regions 156a and 157a are 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm.
The fourth impurity regions (A) 156b and 157b include an impurity element that imparts n-type at a concentration of ^{3 and have} a concentration of 1 × 10 ¹⁷ to 1 ×
10 at a concentration of ²⁰ atoms / cm ³⁶ includes an impurity element imparting n-type, the fourth impurity regions (B) 156c, 157c is an n-type at a concentration of ^{1 × 10 16 ~5 × 10 18} atoms / cm 3 Contains an impurity element to be provided. However, the concentration of the impurity element imparting p-type in these impurity regions 156b, 156c, 157b and 157c is set to 1 × 10 ¹⁹ atoms / cm ³ or more, and the third impurity regions 156a and 157a
, The concentration of the impurity element imparting p-type is set to 1.5
When the third impurity region is used, the third impurity region functions as a source region and a drain region of the p-channel type TFT, so that no problem occurs. Also,
The fourth impurity regions (B) 156c and 157c are formed so as to partially overlap with the conductive layer 140 or 142 having the second tapered shape.

Thereafter, as shown in FIG. 9A, a first interlayer insulating film 158 is formed on the gate electrode and the gate insulating film.
To form The first interlayer insulating film may be formed using a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a stacked film combining these. In any case, the first
Is formed from an inorganic insulating material. The thickness of the first interlayer insulating film 158 is 100 to 200 nm. Here, when a silicon oxide film is used, TEOS and O ₂ are mixed by a plasma CVD method, and a reaction pressure of 40 P
a, a substrate temperature of 300 to 400 ° C., and a high frequency (13.5
6 MHz) It can be formed by discharging at a power density of 0.5 to 0.8 W / cm ² . When a silicon oxynitride film is used, SiH ₄ , N ₂ O, NH ₃
A silicon oxynitride film made from SiH ₄ ,
N ₂ O may be formed by a silicon oxynitride film made from. The production conditions in this case are a reaction pressure of 20 to 200 Pa,
The substrate can be formed at a substrate temperature of 300 to 400 ° C. and a high frequency (60 MHz) power density of 0.1 to 1.0 W / cm ² .
Alternatively, a hydrogenated silicon oxynitride film formed from SiH ₄ , N ₂ O, and H ₂ may be used. Similarly, a silicon nitride film can be formed from SiH ₄ and NH ₃ by a plasma CVD method.

As described above, the surface can be satisfactorily planarized by forming the second interlayer insulating film with the organic insulating material. In addition, since organic resin materials generally have a low dielectric constant, parasitic capacitance can be reduced. However, since it is hygroscopic and not suitable as a protective film, it is preferable to use it in combination with a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like formed as the first interlayer insulating film 158 as in this embodiment. .

Thereafter, a resist mask having a predetermined pattern is formed using the fourth photomask (PM4), and a contact hole is formed in each island-shaped semiconductor layer and reaches an impurity region serving as a source region or a drain region. I do. The contact hole is formed by a dry etching method. In this case, the second interlayer insulating film 159 made of organic resin material using a mixed gas of CF _4, O _2, He as an etching gas is first etched, then followed by the first etching gas as CF _4, O ₂ Is etched. Further, in order to increase the selectivity with respect to the island-shaped semiconductor layer, a contact hole can be formed by switching the etching gas to CHF ₃ and etching the third shape gate insulating film 170b.

Next, P is added to a part of the source region or the drain region exposed by the formation of the contact hole. P is added by an ion doping method using phosphine (PH ₃ ), and the P concentration in this region is set to 1 × 10 ²⁰ to
1 × 10 ²¹ / cm ³ . P ion doping is performed in order to reduce or reduce the metal that promotes crystallization from near the junction. In order to perform gettering efficiently, it is better that the position of the contact hole is closer to the junction and that the area of the contact hole is larger.

Then, a step of activating the impurity elements imparting n-type or p-type added at the respective concentrations is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In the thermal annealing method, the oxygen concentration is 40 ppm in a nitrogen atmosphere of 1 ppm or less, preferably 0.1 ppm or less.
The reaction is performed at 0 to 700 ° C, typically 500 to 600 ° C. By this heat treatment, a metal which promotes crystallization and other impurity elements such as heavy metals existing in the channel formation region move to the source region or the drain region. This movement is more efficient than before because there are two types of gettering sites. In other words, impurity elements such as heavy metals are gettered in regions where the crystal grain size is small and the density of the crystal grain boundaries is high (the amorphous regions 6002 and 6012 (Fig. 6) are laser-crystallized) and in the regions where P is doped. Let it. In addition, since the P-doped region and the high-density region of the crystal grain boundary are separated from the junction region of the TFT through the contact hole, an impurity element such as metal or other heavy metal that promotes crystallization is effectively removed from the junction region. It is also possible to remove it.

Following the activation step, the atmosphere gas is changed
And in an atmosphere containing 3 to 100% hydrogen,
Heat treatment at 450 ° C. for 1 to 12 hours to form an island-shaped semiconductor layer
Is carried out. This process was thermally excited
10 in the island-like semiconductor layer due to hydrogen¹⁶-10¹⁸/cm^ThreeNo da
This is a step of terminating the ringing bond. Other hydrogenation
As a means, plasma hydrogenation (excited by plasma
Using hydrogen). In any case, the island
Defect density in the semiconductor layers 104 to 108 is 10 ¹⁶/cm^ThreeLess than
It is preferable to set the hydrogen content to 0.01 to
What is necessary is just to give about 0.1 atomic%.

Then, a conductive metal film is formed by a sputtering method or a vacuum evaporation method, a resist mask pattern is formed by a fifth photomask (PM5), and the source lines 160 to 164 and the drain lines 165 to 168 are etched.
To form The pixel electrode 169 is formed together with the drain line. The pixel electrode 171 represents a pixel electrode belonging to an adjacent pixel. Although not shown, in this embodiment, this wiring is formed by forming a Ti film with a thickness of 50 to 150 nm, forming a contact with an impurity region forming a source or drain region of the island-shaped semiconductor layer, and forming the Ti film. Aluminum (Al) is formed in a thickness of 300 to 400 nm on top of this (FIG. 9
(Shown by 160a to 169a in (C)), and a transparent conductive film is formed thereon with a thickness of 80 to 120 nm (FIG.
9 (C), indicated by 160b to 169b). Indium oxide zinc oxide alloy (In ₂ O _3-
ZnO) and zinc oxide (ZnO) are also suitable materials. Further, zinc oxide (ZnO: Ga) to which gallium (Ga) is added in order to increase the transmittance and conductivity of visible light can be preferably used. .

In this way, a substrate having a TFT of a driving circuit and a pixel TFT of a pixel portion on the same substrate can be completed by using five photomasks. The driving circuit includes a first p-channel TFT 200, a first n-channel TFT 20, a second p-channel TFT 202, a second n-channel TFT 203, and a pixel portion including a pixel TFT 20.
4. A storage capacitor 205 is formed. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

First p-channel TFT 20 of drive circuit
0, a conductive layer having a second tapered shape has a function as a gate electrode 220, and a third impurity region 207a functioning as a channel formation region 206, a source region or a drain region in the island-shaped semiconductor layer 104; Fourth impurity region (A) 207b forming an LDD region not overlapping gate electrode 220, and fourth impurity region (B) 207c forming an LDD region partially overlapping gate electrode 220
It has a structure having.

In the first n-channel TFT 201, a conductive layer having a second tapered shape has a function as a gate electrode 221, and the island-shaped semiconductor layer 105 serves as a channel forming region 208, a source region or a drain region. A functioning third impurity region 209a and a fourth impurity region (A) forming an LDD region that does not overlap with the gate electrode 221
(A) 209 b, LD partially overlapping gate electrode 221
The structure has a fourth impurity region (B) 209c that forms the D region. For a channel length of 2 to 7 μm, a fourth impurity region (B) 209 c
The length of the portion overlapping 1 is 0.1 to 0.3 μm. The length of Lov is controlled from the thickness of the gate electrode 221 and the angle of the tapered portion. By forming such an LDD region in an n-channel TFT, a high electric field generated in the vicinity of the drain region can be relaxed, hot carriers can be prevented from being generated, and deterioration of the TFT can be prevented.

Second p-channel TFT 20 of drive circuit
Similarly, the island-shaped semiconductor layer 106 has a second tapered conductive layer serving as the gate electrode 222.
A channel formation region 210, a third impurity region 211 a functioning as a source region or a drain region, a fourth impurity region (A) 211 b forming an LDD region which does not overlap with the gate electrode 222, part of which overlaps with the gate electrode 222. Fourth impurity region (B) 21 forming LDD region
1c.

The second n-channel type TFT 20 of the driving circuit
3, a conductive layer having a second tapered shape has a function as a gate electrode 223, and a third impurity region 213 a functioning as a channel formation region 212, a source region or a drain region in the island-shaped semiconductor layer 107. Fourth impurity region (A) 213b forming an LDD region that does not overlap with gate electrode 223, and fourth impurity region (B) 213c forming an LDD region that partially overlaps with gate electrode 223
It has a structure having. Second n-channel TFT
Similarly to 201, the length of the portion where the fourth impurity region (B) 213c overlaps the gate electrode 223 is 0.1 to 0.3 μm.
And

The driving circuit is formed by a logic circuit such as a shift register circuit or a buffer circuit, or a sampling circuit formed by analog switches. In FIG. 9B, the TFTs forming them have a single-gate structure in which one gate electrode is provided between a pair of sources and drains. A gate structure may be used.

In the pixel TFT 204, a conductive layer having a second tapered shape has a function as a gate electrode 224, and a channel forming region 214 a is formed in the island-shaped semiconductor layer 108.
214b, third impurity regions 215a and 217 functioning as source or drain regions, and gate electrode 22
A fourth impurity region (A) 215b forming an LDD region that does not overlap with the gate electrode 224;
The structure has a fourth impurity region (B) 215c that forms the D region. Fourth impurity region (B) 213
The length of the portion where c overlaps with the gate electrode 224 is 0.1 to
0.3 μm. Further, a semiconductor extending from the third impurity region 217 and including a fourth impurity region (A) 219b, a fourth impurity region (B) 219c, and a region 218 to which an impurity element which determines a conductivity type is not added. A storage capacitor is formed from the layer, an insulating layer formed using the same layer as the gate insulating film having the third shape, and a capacitor wiring 225 formed using a conductive layer having a second tapered shape.

FIG. 10 is a top view showing almost one pixel of the pixel portion. The cross section AA ′ shown in the drawing corresponds to the cross section of the pixel portion shown in FIG. In the pixel TFT 204, the gate electrode 224 intersects the island-like semiconductor layer 108 thereunder via a gate insulating film (not shown), and further extends over a plurality of island-like semiconductor layers to serve also as a gate wiring. .
Although not shown, the source region, the drain region, and the LDD region described with reference to FIG. 9B are formed in the island-shaped semiconductor layer. Reference numeral 230 denotes a contact portion between the source wiring 164 and the source region 215a, and reference numeral 231 denotes a pixel electrode 16
9 and a contact portion between the drain region 227. The storage capacitor 205 is connected to the drain region 227 of the pixel TFT 204.
The capacitor wiring 225 is formed in a region where the capacitor wiring 225 overlaps with a semiconductor layer extending from the gate insulating film via a gate insulating film. In this structure, an impurity element for controlling valence electrons is not added to the semiconductor layer 218.

The above configuration enables the structure of the TFT constituting each circuit to be optimized according to the specifications required by the pixel TFT and the driving circuit, thereby improving the operation performance and reliability of the semiconductor device. . Further, the activation of the LDD region, the source region, and the drain region is facilitated by forming the gate electrode with a conductive material having heat resistance. Further, when forming the LDD region overlapping with the gate electrode via the gate insulating film, the LDD region is formed by giving a concentration gradient to the impurity element added for the purpose of controlling the conductivity type, particularly in the vicinity of the drain region. Can be expected to increase the electric field relaxation effect.

In the case of an active matrix type liquid crystal display device, the first p-channel TFT 200 and the first n-channel TFT 201 are used for forming a shift register circuit, a buffer circuit, a level shifter circuit, etc. which emphasize high-speed operation. . FIG. 9B illustrates these circuits as logic circuit units. First n-channel type TFT2
The fourth impurity region (B) 209c of No. 01 has a structure emphasizing measures against hot carriers. Further, in order to increase the withstand voltage and stabilize the operation, as shown in FIG.
T280 and the first n-channel TFT 281 may be used. This TFT has a structure in which two transistors
It has a double gate structure provided with two gate electrodes, and such a TFT can be similarly manufactured using the steps of this embodiment. In the first p-channel TFT 280, channel formation regions 236 a and 236 b and a third impurity region 238 functioning as a source or drain region are formed in the island-shaped semiconductor layer.
a, 239a, 240a, a fourth impurity region (A) 238b, 239b, 240b serving as an LDD region and a fourth impurity region (B) 238c, 239c, 240c, which partially overlaps the gate electrode 237 and serves as an LDD region. It has a structure having. In the first n-channel TFT 281, channel formation regions 241 a and 241 are formed in the island-shaped semiconductor layer.
b, third impurity regions 243a, 244a, 245a functioning as source or drain regions and fourth impurity regions (A) 243b, 244b, 24 serving as LDD regions
5b and the fourth impurity regions (B) 243c, 244c, and 24 which partly overlap with the gate electrode 242 and serve as LDD regions.
5c. The channel length is 3 to 7 μm, the LDD region overlapping with the gate electrode is Lov, and the length in the channel length direction is 0.1 to 0.3 μm.

Further, a second p-channel type TFT 202 and a second n-channel type TFT 203 having the same configuration can be applied to a sampling circuit composed of analog switches. The sampling circuit places importance on measures against hot carriers and low off-current operation. Therefore, as shown in FIG. 10B, the TFT of this circuit is replaced with a second p-channel type TF.
T282 and the second n-channel TFT 283 may be used. The second p-channel type TFT 282 has a triple gate structure in which three gate electrodes are provided between a pair of sources and drains. Such a TFT can be manufactured in the same manner by using the steps of this embodiment. Second p-channel type TF
In T282, a channel formation region 246 is formed in the island-shaped semiconductor layer.
a, 234b, 246c Third impurity regions 249a, 250a, 25 functioning as source or drain regions
1a, 252a, the fourth impurity regions (A) 249b, 250b, 251b, 252b serving as LDD regions and the fourth impurity regions (B) 249c, 250c, 251c which partially overlap the gate electrode 247 and serve as LDD regions. 25
2c. Second n-channel type T
The FT 283 includes a channel forming region 25 in the island-shaped semiconductor layer.
3a, 253b, third impurity regions 255a, 256a, 257a functioning as source or drain regions and a fourth impurity region (A) 255b,
56b, 257b and the fourth impurity region (B) 255c, which partly overlaps with the gate electrode 254 and becomes an LDD region.
56c and 257c. Channel length is 3-7μ
m, the LDD region overlapping the gate electrode is Lov, and the length in the channel length direction is 0.1 to 0.3 μm.

As described above, whether a TFT has a single gate structure or a multi-gate structure in which a plurality of gate electrodes are provided between a source region and a drain region depends on the characteristics of a circuit. The practitioner may select it appropriately. Then, by using the active matrix substrate completed in this embodiment, a reflective liquid crystal display device can be manufactured.

In the following, the first to third embodiments only describe a method for forming a region serving as a gettering site in a semiconductor film, that is, a region having a small crystal grain size or a high density of intersections of crystal grain boundaries. Do. Using these methods, an active matrix substrate can be manufactured as described in Embodiment 1. In the first embodiment, a method is used in which a high concentration of P is doped into the contact region to effectively remove impurity elements such as heavy metals in the junction region. However, the method described in Japanese Patent Application No. 11-372214 is used. May be used in combination with the above method.

[0059]

[Example 1] In Example 1, a method of forming a gettering site by controlling the generation density of crystal nuclei will be described (FIG. 11). The substrate 1103 is a glass or quartz substrate. A base 1108 made of an insulating film containing silicon is formed on the surface of the substrate 1103 where the TFT is to be formed. Further, an amorphous semiconductor thin film or a crystalline semiconductor thin film having a thickness of 20 to 100 nm is formed on the base film 1108 by a known film forming method.

A mask layer 1130 of a silicon oxide film is formed on the channel forming region 1107 of the semiconductor film. It is preferable that this mask protrudes from the channel formation region to a region to be a source / drain region later. Next, metal Ni for promoting crystallization is added to the entire surface of the substrate using a spin coater or the like, and heat treatment is performed at 400 to 700 ° C. At this time, since the diffusion coefficient of Ni is small in the oxide film, the concentration of Ni in the semiconductor thin film under the mask layer 1130 of the silicon oxide film is small. Since the nucleation density decreases as the concentration of Ni in the film decreases, the crystal grain size of the crystalline semiconductor under the mask layer 1130 of the silicon oxide film increases, and the intersection points of the crystal grain boundaries that make a tolerance also decrease. Therefore, the semiconductor regions 1101 and 1111 become gettering sites.

Embodiment 2 In Embodiment 2, a porous film is used as a gettering site. The substrate 1203 is a glass or quartz substrate. A base 1208 made of an insulating film containing silicon is formed on the surface of the substrate 1203 where the TFT is formed. In addition, 20
An amorphous semiconductor thin film having a thickness of about 100 nm is formed by a known film forming method.

The porous film can be formed by anodization in an HF solution, and a sufficient growth rate can be obtained without irradiating the p-type substrate with light. Therefore, in FIG. 12, the semiconductor regions 1201 and 1211 are doped with an impurity element imparting p-type in order to make the semiconductor regions 1201 and 1211 p-type. At this time, anodization is performed such that all the p-type-provided semiconductor regions in the substrate are connected. By the anodization method, the semiconductor regions 1201 and 1211 become porous films. The porous film has many crystal defects and high gettering ability. Further, since the surface area is large, diffusion of impurity atoms is promoted. Generally, the diffusion coefficient at the surface of an impurity atom and the diffusion coefficient in a grain boundary are several orders of magnitude higher than the diffusion coefficient in a bulk. Therefore, it can be used as a gettering site.

Example 3 Generally, the crystal grain size is determined by the frequency of nucleation of crystal nuclei. One of the parameters that determines this frequency is temperature. That is, depending on the temperature (degree of subcooling),
The critical radius of growth from embryo to solid crystal differs. (FIG. 13) FIG. 13 is “FIG. 5.1” described in “Solidification Engineering; Hideo Nakae, published by Agne, pp. 58”. Therefore, in crystallization using laser or lamp annealing, a region where a gettering site is to be formed may be set to a temperature at which the number of generated nuclei increases. To achieve this, annealing is performed, for example, via an appropriate oxide film mask.

[Embodiment 4] In this embodiment, a process of manufacturing an active matrix type liquid crystal display device from the active matrix substrate manufactured in the embodiment mode and Examples 1 to 3 will be described. First, as shown in FIG.
Is formed on the active matrix substrate in the state described above. The spacer may be provided by scattering particles of several μm, but here, a method of forming a resin film over the entire surface of the substrate and then patterning the resin film is adopted. There is no limitation on the material of such a spacer,
For example, using NN700 manufactured by JSR Co., it is applied with a spinner and then formed into a predetermined pattern by exposure and development. 150 to 200 in a clean oven
Heat at ℃ to cure. The shape of the spacer manufactured in this manner can be varied depending on the conditions of the exposure and the development processing. When combined, the mechanical strength of the liquid crystal display panel can be secured. The shape is not particularly limited, such as a conical shape or a pyramid shape. For example, when the shape is a conical shape, specifically, the height is 1.2 to 5 μm, and the average radius is 5 to 7 μm.
m, the ratio of the average radius to the bottom radius is 1: 1.5.
At this time, the taper angle of the side surface is set to ± 15 ° or less.

The arrangement of the spacers may be arbitrarily determined, but preferably, as shown in FIG. 14A, in the pixel portion, the columnar spacer is overlapped with the contact portion 231 of the pixel electrode 169 so as to cover that portion. 406 may be formed. Since the flatness of the contact portion 231 is impaired and the liquid crystal is not well aligned in this portion, the columnar spacer 406 is formed in such a manner that the contact portion 231 is filled with the resin for the spacer, so that disclination or the like is performed. Can be prevented. In addition, the driving circuit T
Spacers 405a to 405e are also formed on the FT. This spacer may be formed over the entire surface of the drive circuit portion, or may be provided so as to cover the source line and the drain line as shown in FIG.

After that, an alignment film 407 is formed. Usually, a polyimide resin is used for the alignment film of the liquid crystal display element. After forming the alignment film, a rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. The area not rubbed in the rubbing direction from the end of the columnar spacer 406 provided in the pixel portion was set to 2 μm or less. In the rubbing treatment, generation of static electricity often poses a problem, but the effect of protecting the TFT from static electricity can be obtained by the spacers 405a to 405e formed on the TFT of the driving circuit. Although not explained in the figure,
After forming the alignment film 407 first, the spacers 406, 4
05a to 405e may be formed.

The opposing substrate 401 on the opposing side has a light shielding film 40
2. A transparent conductive film 403 and an alignment film 404 are formed.
The light-shielding film 402 includes a Ti film, a Cr film, an Al film,
It is formed with a thickness of 300 nm. Then, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are attached with a sealant 408. A filler (not shown) is mixed in the sealant 408, and the two substrates are bonded at a uniform interval by the filler and the spacers 406 and 405a to 405e. After that, a liquid crystal material 409 is injected between the two substrates. A known liquid crystal material may be used as the liquid crystal material. For example, in addition to the TN liquid crystal, a thresholdless antiferroelectric mixed liquid crystal exhibiting electro-optical response in which the transmittance continuously changes with respect to an electric field can be used. In this thresholdless antiferroelectric mixed liquid crystal,
Some exhibit a V-shaped electro-optical response characteristic. Thus, the active matrix liquid crystal display device shown in FIG. 14B is completed.

FIG. 15 is a top view of such an active matrix substrate, and is a top view showing a positional relationship between a pixel portion and a drive circuit portion, a spacer, and a sealant. A scan signal driver circuit 605 and an image signal driver circuit 606 are provided as driver circuits around the pixel portion 604 over the glass substrate 101 described in the embodiment mode. In addition, other CP
A signal processing circuit 607 such as a U or a memory may be added. These drive circuits are connected to an external input / output terminal 602 by a connection wiring 603. In the pixel portion 604, a gate wiring group 608 extending from the scanning signal driving circuit 605 and a source wiring group 609 extending from the image signal driving circuit 606 intersect in a matrix to form a pixel. And holding capacity 2
05 is provided.

In FIG. 14, the columnar spacer 406 provided in the pixel portion may be provided for every pixel, but is provided every several to several tens of pixels arranged in a matrix as shown in FIG. May be. That is, the ratio of the number of spacers to the total number of pixels constituting the pixel portion is 20 to
It can be 100%. Further, the spacers 405a to 405e provided in the drive circuit portion may be provided so as to cover the entire surface or may be provided in accordance with the positions of the source and drain wirings of each TFT. In FIG. 15, the arrangement of the spacers provided in the drive circuit portion is indicated by 610 to 612. Then, the sealing agent 613 shown in FIG. 15 is outside the pixel portion 604 and the scanning signal driving circuit 605, the image signal driving circuit 606, and other signal processing circuits 607 on the substrate 101 and inside the external input / output terminal 602 Formed.

The structure of such an active matrix type liquid crystal display device will be described with reference to the perspective view of FIG. FIG.
6, the active matrix substrate is a glass substrate 1
01, a pixel portion 604, a scanning signal driving circuit 605, an image signal driving circuit 606, and another signal processing circuit 607. The pixel portion 604 includes a pixel T
An FT 204 and a storage capacitor 205 are provided, and a driving circuit provided around the pixel portion is configured based on a CMOS circuit. From the scanning signal driver circuit 605 and the image signal driver circuit 606, a gate line (equivalent to 224 in FIG. 9B when formed continuously with the gate electrode) and a source line 164 are connected to the pixel portion 604. Extend, the pixel T
Connected to FT204. Also, a flexible printed circuit (FPC) 613 is used.
Are connected to the external input terminal 602 and are used to input image signals and the like. The FPC 613 is firmly bonded by a reinforcing resin 614. The connection wiring 603 is connected to each drive circuit. Also, the counter substrate 40
1, a light shielding film and a transparent electrode, not shown, are provided.

[Embodiment 5] FIG. 17 shows an embodiment and an embodiment 1.
FIG. 4 is a diagram illustrating an example of a circuit configuration of an active matrix substrate illustrated in FIGS. This active matrix substrate includes an image signal driving circuit 606, scanning signal driving circuits (A) and (B) 605, and a pixel portion 604. Note that the driving circuit described in this specification is a general term including the image signal driving circuit 606 and the scanning signal driving circuit 605.

The image signal driving circuit 606 includes a shift register circuit 501a, a level shifter circuit 502a, a buffer circuit 503a, and a sampling circuit 504.
Each of the scanning signal driving circuits (A) and (B) 185 includes a shift register circuit 501b, a level shifter circuit 502b, and a buffer circuit 503b.

The shift register circuits 501a and 501b have a drive voltage of 5 to 16 V (typically 10 V).
Of the first p-channel TFT 200 and the first n-channel TFT 201. Alternatively, a first p-channel TFT 280 and a first n-channel TFT 281 illustrated in FIG. 9A may be used. Further, the level shifter circuits 502a and 502b and the buffer circuits 503a and 503
b has a multi-gate TFT structure because the drive voltage is as high as 14 to 16 V. Forming a TFT with a multi-gate structure increases the breakdown voltage, which is effective in improving the reliability of the circuit.

The sampling circuit 504 is composed of an analog switch, and has a drive voltage of 14 to 16 V. However, since the polarity is alternately inverted and the off-current value needs to be reduced, the sampling circuit 504 shown in FIG. It is desirable to form the second p-channel type TFT 202 and the second n-channel type TFT 203 shown by.

The driving voltage of the pixel portion is 14 to 16 V, and it is required to further reduce the off-current value as compared with the sampling circuit from the viewpoint of low power consumption.
A multi-gate structure is basically used like the pixel TFT 204 shown in FIG.

The structure of this embodiment can be easily realized by manufacturing a TFT according to the steps described in the embodiment mode. In this embodiment, only the configuration of the pixel portion and the driving circuit is shown. However, according to the steps of the embodiment, other components such as a signal dividing circuit, a frequency dividing circuit, a D / A converter, a γ correcting circuit, and an operational amplifier circuit Further, a signal processing circuit such as a memory circuit or an arithmetic processing circuit, or a logic circuit can be formed over the same substrate. As described above, the present invention can realize a semiconductor device including a pixel portion and a driver circuit over the same substrate, for example, a liquid crystal display device including a signal control circuit and a pixel portion.

[Embodiment 6] In this embodiment, a self-luminous display panel (hereinafter, referred to as an EL display device) using an electroluminescent (EL) material by using the active matrix substrate as in the third embodiment. ) Will be described. FIG. 18A is a top view of an EL display panel using the present invention. In FIG. 18A, 10 is a substrate, 11 is a pixel portion, 12 is a source side drive circuit, 13 is a gate side drive circuit, and each drive circuit reaches the FPC 17 via wirings 14 to 16 and is connected to an external device. Connected to

FIG. 18B is a cross-sectional view taken along the line AA ′ of FIG. 18A. At this time, the opposing plate 80 is provided at least over the pixel portion, preferably over the driving circuit and the pixel portion. The opposing plate 80 is bonded to the active matrix substrate on which the TFT and the EL layer are formed with the sealing material 19.
A filler (not shown) is mixed in the sealant 19, and the two substrates are bonded with a substantially uniform interval by the filler. Further, the outside of the seal member 19 and the upper surface and the periphery of the FPC 17 are sealed with a sealant 81. The sealant 81 uses a material such as a silicone resin, an epoxy resin, a phenol resin, and butyl rubber.

As described above, when the active matrix substrate 10 and the counter substrate 80 are bonded together by the sealant 19, a space is formed therebetween. The space is filled with a filler 83. The filler 83 also has the effect of bonding the opposing plate 80. Filler 83 is made of PVC (polyvinyl chloride), epoxy resin, silicone resin, P
VB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. Also, E
The L layer is susceptible to moisture and moisture and easily deteriorates. Therefore, it is desirable to mix a desiccant such as barium oxide into the filler 83 because a moisture absorbing effect can be maintained. Also,
A passivation film 82 formed of a silicon nitride film, a silicon oxynitride film, or the like is formed over the EL layer, and a filler 83
It has a structure to prevent corrosion due to alkali elements and the like contained in.

A glass plate, an aluminum plate, a stainless steel plate, FRP (Fiberglass-Reinforced Pl)
astics) plate, PVF (polyvinyl fluoride) film, mylar film (trade name of DuPont), polyester film, acrylic film or acrylic plate. Further, moisture resistance can be enhanced by using a sheet having a structure in which an aluminum foil of several tens of μm is sandwiched between PVF films or mylar films. In this way, the EL element is in a sealed state and is isolated from the outside air.

In FIG. 18B, a TFT for a driving circuit (here, a C-type TFT combining an n-channel TFT and a p-channel TFT) is formed on the substrate 10 and the base film 21.
2 illustrates a MOS circuit. 22) and TFT for pixel portion
23 (however, here, TF for controlling the current to the EL element)
Only T is shown. ) Is formed. These T
Among the FTs, an n-channel TFT, in particular, is provided with an LDD region having the structure shown in this embodiment in order to prevent a decrease in on-current due to the hot carrier effect and a decrease in characteristics due to Vth shift and bias stress.

For example, the driving circuit TFT 22 is used as shown in FIG.
The p-channel TFTs 200 and 202 and the n-channel TFTs 201 and 203 shown in FIG. Also,
A pixel TFT 2 shown in FIG.
04 or p-channel type TF having a structure similar thereto
T may be used.

In order to manufacture an EL display device from the active matrix substrate in the state shown in FIG. 9B or FIG. 6B, an interlayer insulating film (flattening film) 26 made of a resin material is formed on source lines and drain lines. Formed, and a TFT for pixel section
A pixel electrode 27 made of a transparent conductive film electrically connected to the drain of the pixel 23 is formed. As the transparent conductive film, a compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used. When the pixel electrode 27 is formed, the insulating film 2 is formed.
8 is formed, and an opening is formed on the pixel electrode 27.

Next, an EL layer 29 is formed. EL layer 29
Are known EL materials (a hole injection layer, a hole transport layer, a light emitting layer,
An electron transport layer or an electron injection layer) may be freely combined to form a stacked structure or a single-layer structure. A known technique may be used to determine the structure. EL materials include low molecular weight materials and high molecular weight (polymer) materials.
When a low molecular material is used, an evaporation method is used. When a high molecular material is used, a simple method such as a spin coating method, a printing method, or an ink jet method can be used.

The EL layer is formed by a vapor deposition method using a shadow mask,
Alternatively, it is formed by an inkjet method, a dispenser method, or the like. In any case, light emitting layers capable of emitting light of different wavelengths for each pixel (red light emitting layer, green light emitting layer, and blue light emitting layer)
Is formed, color display becomes possible. In addition, there are a method in which a color conversion layer (CCM) and a color filter are combined, and a method in which a white light emitting layer and a color filter are combined, and any method may be used. Needless to say, a monochromatic EL display device can be used.

After the EL layer 29 is formed, the cathode 3
0 is formed. It is desirable to remove moisture and oxygen existing at the interface between the cathode 30 and the EL layer 29 as much as possible. Therefore, it is necessary to devise a method of continuously forming the EL layer 29 and the cathode 30 in a vacuum, or forming the EL layer 29 in an inert atmosphere and forming the cathode 30 in a vacuum without opening to the atmosphere. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

In this embodiment, the cathode 30 is made of Li
A laminated structure of an F (lithium fluoride) film and an Al (aluminum) film is used. Specifically, one layer is formed on the EL layer 29 by vapor deposition.
A LiF (lithium fluoride) film having a thickness of nm is formed, and an aluminum film having a thickness of 300 nm is formed thereon. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 30 is connected to the wiring 16 in a region indicated by 31. The wiring 16 is a power supply line for applying a predetermined voltage to the cathode 30, and is connected to the FPC 17 via an anisotropic conductive paste material 32. A resin layer 80 is further formed on the FPC 17 to increase the adhesive strength at this portion.

In order to electrically connect the cathode 30 and the wiring 16 in the region 31, it is necessary to form contact holes in the interlayer insulating film 26 and the insulating film 28. These may be formed at the time of etching the interlayer insulating film 26 (at the time of forming a contact hole for a pixel electrode) or at the time of etching the insulating film 28 (at the time of forming an opening before forming an EL layer). Further, when the insulating film 28 is etched, the etching may be performed all at once up to the interlayer insulating film 26. In this case, if the interlayer insulating film 26 and the insulating film 28 are made of the same resin material, the shape of the contact hole can be made good.

The wiring 16 is composed of a seal 19 and the substrate 10.
Is electrically connected to the FPC 17 through a gap (but closed with a sealant 81). Although the wiring 16 has been described here, the other wirings 14 and 15 are also electrically connected to the FPC 17 under the sealing material 18 in the same manner.

FIG. 19 shows a more detailed sectional structure of the pixel portion, FIG. 20A shows a top structure thereof, and FIG.
It is shown in (B). In FIG. 19A, the switching TFT 2402 provided on the substrate 2401 is the same as that of the first embodiment.
9 (B) of FIG. 9B. With a double gate structure, substantially two TFs
There is an advantage that the structure is such that T is connected in series, and the off-current value can be reduced. In this embodiment, a double gate structure is used, but a triple gate structure or a multi-gate structure having more gates may be used.

The current controlling TFT 2403 is the same as that of FIG.
It is formed using an n-channel TFT 201 shown in FIG. At this time, the drain line 35 of the switching TFT 2402 is electrically connected to the gate electrode 37 of the current controlling TFT by the wiring 36. A wiring indicated by 38 is a gate line that electrically connects the gate electrodes 39a and 39b of the switching TFT 2402.

At this time, it is very important that the current control TFT 2403 has the structure of the present invention. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows and the element has a high risk of deterioration due to heat or hot carriers. Therefore, by providing the current control TFT with an LDD region that partially overlaps the gate electrode, deterioration of the TFT is prevented,
Operation stability can be improved.

In this embodiment, the current controlling TFT 24 is used.
03 is shown with a single gate structure.
A multi-gate structure in which FTs are connected in series may be used.
Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

Further, as shown in FIG. 20A, the wiring to be the gate electrode 37 of the current controlling TFT 2403 has 24 wirings.
In a region indicated by 04, the region overlaps with the drain line 40 of the current control TFT 2403 via an insulating film. At this time, 24
In a region indicated by 04, a capacitor is formed. The capacitor 2404 functions as a capacitor for holding a voltage applied to the gate of the current control TFT 2403. The drain line 40 is a current supply line (power supply line) 2
501, a constant voltage is always applied.

The first passivation film 4 is formed on the switching TFT 2402 and the current control TFT 2403.
And a planarizing film 42 made of a resin insulating film thereon.
Is formed. It is very important to flatten the steps due to the TFT using the flattening film 42. Since an EL layer formed later is extremely thin, poor light emission may be caused by the presence of a step. Therefore, it is desirable that the EL layer be flattened before forming the pixel electrode so that the EL layer can be formed as flat as possible.

Reference numeral 43 denotes a pixel electrode (cathode of an EL element) made of a conductive film having high reflectivity.
403 is electrically connected to the drain. Pixel electrode 43
It is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof. Of course, a stacked structure with another conductive film may be employed. A groove (corresponding to a pixel) formed by banks 44a and 44b formed of an insulating film (preferably resin).
The light emitting layer 45 is formed in the inside. Although only one pixel is shown here, R (red), G (green), B (blue)
The light emitting layers corresponding to the respective colors may be separately formed. As the organic EL material for the light emitting layer, a π-conjugated polymer material is used. Typical polymer-based materials include polyparaphenylenevinylene (PPV), polyvinylcarbazole (PVK), and polyfluorene.

There are various types of PPV-based organic EL materials, for example, “H. Shenk, H. Becker, O. Ge.
lsen, E. Kluge, W. Kreuder, and H. Spreitzer, “Polymers
for Light Emitting Diodes ”, Euro Display, Proceedin
gs, 1999, p.33-37 ”and JP-A-10-92576.

As a specific light emitting layer, cyanopolyphenylenevinylene is used for a red light emitting layer, polyphenylenevinylene is used for a green light emitting layer, and polyphenylenevinylene or polyalkylphenylene is used for a blue light emitting layer. Good. Thickness is 30-150nm
(Preferably 40 to 100 nm). However, the above example is an example of an organic EL material that can be used as a light emitting layer, and there is no need to limit the invention to this.
An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, an example in which a polymer material is used as the light emitting layer has been described.
A low molecular organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

In this embodiment, PEDOT is formed on the light emitting layer 45.
The EL layer has a laminated structure in which a hole injection layer 46 made of (polythiophene) or PAni (polyaniline) is provided. An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of this embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (toward the upper side of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, it is possible to form after forming a light-emitting layer or a hole-injecting layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

When the anode 47 is formed, the EL element 2
405 is completed. Note that the EL element 2405 referred to here
Are the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 4
6 and the anode 47. FIG.
As shown in (A), the pixel electrode 43 substantially matches the area of the pixel, and the entire pixel functions as an EL element. Therefore, the efficiency of light emission is extremely high, and a bright image can be displayed.

In the present embodiment, a second passivation film 48 is further provided on the anode 47. Second
As the passivation film 48, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated due to oxidation and the effect of suppressing outgassing from the organic EL material. Thereby, the reliability of the EL display device is improved.

As described above, the EL display panel of the present invention has the pixel portion composed of the pixels having the structure as shown in FIG. And a TFT. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.

FIG. 19B shows an example in which the structure of the EL layer is inverted. The current control TFT 2601 corresponds to the p of FIG. 9B.
It is formed using a channel type TFT 200. Embodiment 1 can be referred to for the manufacturing process. In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

The banks 51a and 51b made of an insulating film
Is formed, a light emitting layer 52 made of polyvinyl carbazole is formed by applying a solution. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, an EL element 2602 is formed. In the case of this embodiment, the light generated in the light emitting layer 53 is emitted toward the substrate on which the TFT is formed as indicated by the arrow. In the case of the structure as in this embodiment, it is preferable that the current control TFT 2601 be formed of a p-channel TFT.

The structure of this embodiment can be implemented by freely combining the structures of the TFTs of the embodiment mode and Embodiments 1 to 3. In addition, it is effective to use the EL display panel of this embodiment as the display unit of the electronic device of the eighth embodiment.

[Embodiment 7] In this embodiment, FIG. 21 shows an example in which a pixel having a structure different from that of the circuit diagram shown in FIG. 20B is used. In this embodiment, 2701
270 is the source wiring of the switching TFT 2702, 270
3 is a gate wiring of the switching TFT 2702, 27
04 is a current control TFT, 2705 is a capacitor, 27
Reference numerals 06 and 2708 denote current supply lines, and 2707 denotes an EL element.

FIG. 21A shows an example in which the current supply line 2706 is shared between two pixels. That is, it is characterized in that the two pixels are formed to be line-symmetric with respect to the current supply line 2706. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 21B shows the current supply line 270.
8 is provided in parallel with the gate wiring 2703. Note that in FIG. 21B, the current supply line 2708 and the gate wiring 2703 are provided so as not to overlap with each other.
They can be provided so as to overlap with each other via an insulating film. In this case, since the power supply line 2708 and the gate wiring 2703 can share an occupied area, the pixel portion can have higher definition.

FIG. 21C shows that the current supply line 2708 is provided in parallel with the gate wiring 2703 as in the structure of FIG.
It is characterized in that it is formed so as to be line-symmetric with respect to.
It is also effective to provide the current supply line 2708 so as to overlap with one of the gate wirings 2703. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition. FIG.
21A and 21B, a capacitor 240 is used to hold the voltage applied to the gate of the current controlling TFT 2403.
4, but the capacitor 2404 can be omitted.

As the current controlling TFT 2403, FIG.
Since the n-channel TFT of the present invention as shown in FIG. 1A is used, an LDD region is provided so as to overlap with a gate electrode via a gate insulating film. Although a parasitic capacitance generally called a gate capacitance is formed, this embodiment is characterized in that this parasitic capacitance is actively used instead of the capacitor 2404. The capacitance of the parasitic capacitance is determined by the gate electrode and the LDD region. And changes in the area that overlaps,
It is determined by the length of the LDD region included in the overlapping region. In the structure of FIGS. 21A, 21B, and 21C, the capacitor 2705 can be omitted in the same manner.

The structure of this embodiment can be implemented by freely combining the structures of the TFTs of the embodiment mode and Embodiments 1 to 3. In addition, it is effective to use the EL display panel of this embodiment as the display unit of the electronic device of the eighth embodiment.

[Embodiment 8] A CMOS circuit and a pixel portion formed by implementing the present invention are used for various electro-optical devices (active matrix liquid crystal display, active matrix EL display, active matrix EC display). Can be. That is, the invention of the present application can be applied to all electronic devices in which these electro-optical devices are incorporated in a display unit.

Such electronic devices include a video camera, digital camera, projector (rear or front type), head mounted display (goggle type display), car navigation, car stereo,
Examples include a personal computer and a portable information terminal (a mobile computer, a mobile phone, an electronic book, or the like). Examples of these are shown in FIG. 22, FIG. 23 and FIG.

FIG. 22A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like. The present invention can be applied to the image input unit 2002, the display unit 2003, and other signal driving circuits.

FIG. 22B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, an operation switch 2104, a battery 2105, and an image receiving portion 210.
6 and so on. The present invention can be applied to the display portion 2102 and other signal driver circuits.

FIG. 22C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like. The present invention can be applied to the display portion 2205 and other signal driving circuits.

FIG. 22D shows a goggle type display, which includes a main body 2301, a display section 2302, and an arm section 230.
3 and so on. The present invention can be applied to the display portion 2302 and other signal driver circuits.

FIG. 22E shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402 and other signal driver circuits.

FIG. 22F shows a digital camera, which includes a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, an image receiving section (not shown), and the like. The present invention can be applied to the display portion 2502 and other signal driver circuits.

FIG. 23A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 forming a part of the projection device 2601 and other signal driving circuits.

FIG. 23B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like. The present invention relates to a projection device 2
The present invention can be applied to a liquid crystal display device 2808 which forms a part of the pixel 702 and other signal driving circuits.

FIG. 23C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 23A and 23B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 23D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 23D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 23, a case where a transmissive electro-optical device is used is shown, and examples of application to a reflective electro-optical device and an EL display device are not shown.

FIG. 24A shows a portable telephone, and a main body 29.
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on. The present invention can be applied to the audio output unit 2902, the audio input unit 2903, the display unit 2904, and other signal driving circuits.

FIG. 24B shows a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on. The present invention can be applied to the display units 3002 and 3003 and other signal circuits.

FIG. 24C shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

The electronic apparatus of this embodiment is described in the embodiment mode and the embodiment.
The present invention can be realized by using a configuration composed of any combination of 1 to 3. In addition, the present invention can be applied to an image sensor and an EL display device. As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields.

[0129]

By using the present invention, a plurality of types of impurity elements such as heavy metals can be gettered, and a channel forming region of a TFT and a depletion layer region in a PN junction can be efficiently gettered. Impurities near the boundary between the channel formation region and the source and drain regions of the transistor can be removed or reduced, and the operation performance and reliability of the semiconductor device (specifically, an electro-optical device in this case) can be significantly improved.

[Brief description of the drawings]

FIG. 1 is an SEM photograph showing the segregation of Ni at crystal grain boundaries.

FIG. 2 is a schematic diagram showing intersections of crystal grain boundaries.

FIG. 3 is a view showing a crystal grain size.

FIG. 4 is a diagram showing a configuration of the present invention.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a pixel portion and a driver circuit.

FIG. 6 is a diagram showing a method for forming a gettering site.

FIG. 7 is an SEM photograph showing a crystal grain boundary.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of a pixel portion and a driver circuit.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of a pixel portion and a driver circuit.

FIG. 10 is a cross-sectional view illustrating a manufacturing process of a pixel portion and a driver circuit.

FIG. 11 is a view showing a method for forming a gettering site.

FIG. 12 is a diagram showing a method for forming a gettering site.

FIG. 13 is a diagram showing a relationship between free energy and critical nuclear radius.

FIG. 14 is a cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.

FIG. 15 is a top view illustrating input / output terminals, wiring, circuit arrangement, spacers, and sealants of a liquid crystal display device.

FIG. 16 is a perspective view illustrating a structure of a liquid crystal display device.

FIG. 17 is a block diagram illustrating a circuit configuration of an active matrix display device.

18A and 18B are a top view and a cross-sectional view illustrating a structure of an EL display device.

FIG. 19 is a cross-sectional view of a pixel portion of an EL display device.

FIG. 20 is a top view and a circuit diagram of a pixel portion of an EL display device.

FIG. 21 is an example of a circuit diagram of a pixel portion of an EL display device.

FIG. 22 illustrates an example of a semiconductor device.

FIG. 23 illustrates a configuration of a projection type liquid crystal display device.

FIG 24 illustrates an example of a semiconductor device.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) H01L 21/322 H01L 29/78 627Z G02F 1/136 500 H01L 29/78 616S 618Z 627G F term (reference) 2H092 GA59 HA28 JA25 JA33 JA39 JA43 JA44 JB33 JB51 JB58 KA12 KA18 KB04 KB25 MA05 MA08 MA13 MA27 MA29 MA30 MA37 MA41 PA02 PA03 PA06 PA08 PA09 5F110 AA14 AA30 BB02 BB04 CC02 DD02 DD03 DD13 DD14 DD15 DD17 DD25 EE01 EE04 EE11 EE14 EE14 EE14 EE14 EE14 EE12 FF28 FF30 FF36 GG02 GG13 GG25 GG28 GG32 GG34 GG43 GG45 GG51 HJ01 HJ04 HJ07 HJ12 HJ23 HL03 HL04 HL07 HL11 HL23 HM07 HM15 NN03 NN04 NN22 NN23 NN24 NN27 QNN QNN NN46

Claims (15)

[Claims] A channel forming region in the semiconductor layer; a first impurity region outside the channel forming region;
A second impurity region outside the impurity region, the first impurity region includes an impurity element imparting one conductivity type at the first concentration, and the second impurity region includes the second impurity region. An impurity element imparting the same type as the type is included at the second concentration, wherein the second concentration is higher than the first concentration, and a crystal grain size on a surface of the second impurity region is: A semiconductor device having a crystal grain size smaller than a crystal grain size on a surface of the channel formation region. 2. A semiconductor device comprising: a channel formation region in a semiconductor layer; a first impurity region outside the channel formation region; a second impurity region outside the first impurity region; The impurity region includes an impurity element imparting one conductivity type at the first concentration, the second impurity region includes the impurity element imparting one conductivity type at the first concentration, and A second concentration of an impurity element imparting a conductivity type opposite to the conductivity type, wherein the first concentration is higher than the second concentration; and a crystal on a surface of the second impurity region is provided. A semiconductor device having a grain size smaller than a crystal grain size on a surface of the channel formation region. 3. A semiconductor device comprising: a channel formation region in a semiconductor layer; a first impurity region outside the channel formation region; and a second impurity region outside the first impurity region. The impurity region includes an impurity element imparting one conductivity type at a first concentration, the second impurity region includes an impurity element imparting the same type as the one conductivity type at a second concentration, and the second concentration Is characterized by being higher than the first concentration, wherein the density of the intersection of the crystal grain boundaries in the second impurity region is larger than the density of the intersection of the crystal grain boundaries in the channel formation region. Semiconductor device. 4. A semiconductor device comprising: a channel formation region in a semiconductor layer; a first impurity region outside the channel formation region; and a second impurity region outside the first impurity region. The impurity region includes an impurity element imparting one conductivity type at a first concentration, the second impurity region includes the impurity element imparting one conductivity type at the first concentration, and An impurity element imparting a conductivity type opposite to that of the second impurity region at a second concentration, wherein the first concentration is higher than the second concentration; A semiconductor device, wherein the density of intersections is higher than the density of intersections of crystal grain boundaries in the channel formation region. 5. The Ni concentration in the channel formation region,
5. The semiconductor device according to claim 1, wherein the Ni concentration in the second impurity region is 1/5 or less. 6. The semiconductor device according to claim 1, wherein an LDD region is formed between said channel formation region and said first impurity region. 7. The semiconductor device according to claim 1, wherein an offset region is formed between said channel formation region and said first impurity region. 8. The method according to claim 1, wherein the first concentration is 1 × 10 ¹⁹ / cm ^{3 to} 5 × 10 ²¹ / cm ^3.
cm ^3, and the second concentration semiconductor device according to any one of claims 1 to 4, characterized in that it is 1000 times 1.2 times the first density. 9. The method according to claim 1, wherein the channel forming region is formed using a metal that promotes crystallization.
5. The semiconductor device according to any one of claims 4 to 4. 10. The semiconductor device according to claim 9, wherein the channel formation region is formed using Ni as a metal for promoting crystallization. 11. The impurity element imparting one conductivity type is P
5. The semiconductor device according to claim 1, wherein: 12. The method according to claim 1, wherein:
The semiconductor device is a liquid crystal display device, an EL display device, or an image sensor. 13. The semiconductor device according to claim 1, wherein the semiconductor device is a mobile phone, a video camera, a digital camera, a projector, a goggle type display, a personal computer, a DVD player, an electronic dictionary, or a mobile phone. A semiconductor device, which is one selected from a type information terminal. 14. A step of forming a semiconductor layer including a channel formation region, and introducing a first conductivity type impurity element at a first concentration to form a first layer outside the channel formation region in the semiconductor layer. Forming an impurity region, and introducing an impurity element imparting the same conductivity type as the one conductivity type at a second concentration higher than the first concentration to form a second impurity outside the first impurity region. Forming a region, and reducing a crystal grain size on a surface of the second semiconductor region to be smaller than a crystal grain size on a surface of the channel formation region. . 15. A step of forming a semiconductor layer including a channel formation region, and introducing a first conductivity type impurity element at a first concentration to form a first layer outside the channel formation region in the semiconductor layer. Forming an impurity region, introducing the impurity element imparting one conductivity type at the first concentration, and adding the impurity element imparting a conductivity type opposite to the one conductivity type to the first concentration. Introduced at a higher second concentration,
Forming a second impurity region outside the first impurity region; and reducing a crystal grain size on a surface of the second semiconductor region to be smaller than a crystal grain size on a surface of the channel formation region. A method for manufacturing a semiconductor device, comprising: