JP5244274B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device having a circuit including thin film transistors (hereinafter referred to as TFTs). For example, the present invention relates to an electro-optical device typified by a liquid crystal display device and a configuration of an electric apparatus in which the electro-optical device is mounted as a component. Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and the electro-optical device and the electric appliance are also included in the category.

In recent years, a technique for crystallizing an amorphous semiconductor film formed on an insulating substrate such as glass by laser annealing to improve crystallinity has been widely studied. Silicon is often used for the amorphous semiconductor film.

  A glass substrate is inexpensive and rich in workability compared to a quartz substrate that has been frequently used in the past, and has an advantage that a large-area substrate can be easily manufactured. This is the reason for the above research. In addition, the reason why lasers are used favorably for crystallization is that the melting point of the glass substrate is low. The laser can give high energy only to the amorphous semiconductor film without significantly increasing the temperature of the substrate.

  Since a crystalline semiconductor is made of many crystal grains, it is also called a polycrystalline semiconductor film. Since the crystalline semiconductor film formed by laser annealing has high mobility, a thin film transistor (TFT) is formed using this crystalline semiconductor film, for example, on a single glass substrate for pixel driving. It is actively used in monolithic liquid crystal electro-optical devices and the like for producing TFTs for driving circuits.

  Also, a pulse laser beam such as an excimer laser having a large output is processed by an optical system so as to form a square spot of several centimeters square or a linear shape having a length of 10 cm or more on the irradiated surface or in the vicinity thereof. The method of performing laser annealing by scanning the beam (or moving the irradiation position of the laser beam relative to the irradiated surface) is preferred because it is highly productive and industrially superior. .

  In particular, when a linear beam is used, the laser beam is scanned over the entire irradiated surface by scanning only in the direction perpendicular to the longitudinal direction of the linear beam, unlike the case of using a spot laser beam that requires front-rear and left-right scanning. Productivity is high because irradiation can be performed. The reason for scanning in the direction perpendicular to the longitudinal direction is that it is the most efficient scanning direction. Due to this high productivity, at present, it is becoming mainstream to use a linear beam obtained by processing a pulsed excimer laser beam with an appropriate optical system for laser annealing.

  FIG. 1 shows an example of the configuration of an optical system for processing the shape of a laser beam into a linear shape at or near the irradiation surface. This configuration is very general, and all the optical systems conform to the configuration shown in FIG. This configuration not only converts the shape of the laser beam into a linear shape, but also achieves homogenization of the energy of the laser beam on the irradiated surface. In general, an optical system for homogenizing beam energy is called a beam homogenizer.

  If an excimer laser, which is ultraviolet light, is used as a light source, all of the base material of the optical system is preferably quartz. This is because high transmittance can be obtained. Moreover, it is preferable to use a coating having a transmittance of 99% or more with respect to the wavelength of the excimer laser to be used.

  First, the side view of FIG. 1 will be described. The laser beam emitted from the laser oscillator 61 is split in a direction perpendicular to the traveling direction of the laser beam by the cylindrical array lenses 62a and 62b. The direction is referred to as the vertical direction in the present specification. The vertical direction is bent in the direction of light bent by the mirror when the mirror enters the middle of the optical system. In this configuration, there are four divisions. These divided laser beams are once combined into one laser beam by the cylindrical array lens 64. After being reflected by the mirror 67, the laser beam is condensed again into one laser beam on the irradiation surface 69 by the doublet cylindrical lens 68. A doublet cylindrical lens refers to a lens composed of two cylindrical lenses. Thereby, the energy homogenization in the width direction of the linear beam and the length in the width direction are determined.

  Next, a top view will be described. The laser beam emitted from the laser oscillator 61 is split by the cylindrical array lens 63 in a direction perpendicular to the traveling direction of the laser beam and perpendicular to the longitudinal direction. This direction is referred to as a lateral direction in this specification. The horizontal direction is bent in the direction of light bent by the mirror when the mirror enters the middle of the optical system. In this configuration, there are seven divisions. Thereafter, the laser beam is combined into one at the irradiation surface 69 by the cylindrical lens 64. This determines the homogenization and length of the energy in the longitudinal direction of the linear beam.

  The above lenses are made of synthetic quartz for use with excimer lasers. In addition, the surface is coated so that it can pass through the excimer laser well. As a result, the transmittance of the excimer laser with one lens was 99% or more.

  By irradiating the linear beam processed in the above configuration while being gradually shifted in the width direction of the laser beam, laser annealing is performed on the entire surface of the amorphous semiconductor to cause crystallization or crystallinity. Can be improved.

Next, a typical method for manufacturing a semiconductor film to be irradiated will be described. First, a Corning 1737 substrate having a thickness of 0.7 mm and a 5-inch square was prepared as a substrate. Substrate by using a plasma CVD device, a SiO2 film having a thickness of 200nm was deposited (oxide silicon film), (referred to as hereinafter a-Si film) amorphous silicon film with a thickness of 50nm on the SiO ₂ film surface A film was formed. The substrate was exposed to an atmosphere of nitrogen gas and a temperature of 500 ° C. for 1 hour to reduce the hydrogen concentration in the film. This significantly improved the laser resistance of the film.

  The laser device used was a Lambda XeCl excimer laser (wavelength 308 nm, pulse width 30 ns) L3308. This laser device emits a pulsed laser and has the ability to emit energy of 500 mJ / pulse. The size of the laser beam is 10 mm × 30 mm at the exit of the laser beam (both half-value width in the beam profile). In this specification, the exit of the laser beam is a plane perpendicular to the traveling direction of the laser beam immediately after the laser beam is emitted from the laser irradiation apparatus.

  The shape of the laser beam generated by the excimer laser is generally rectangular and falls within the range of about 3 to 5 when expressed in terms of aspect ratio. The intensity of the laser beam shows a Gaussian distribution that is stronger toward the center of the laser beam. The size of the laser beam was converted into a linear beam with a uniform energy distribution of 125 mm × 0.4 mm by an optical system having the configuration shown in FIG.

FIG. 2 shows a state where two pulses of the linear beam are irradiated as seen from above, and FIGS. 2A to 2D show the superposition in the beam width (half width in the beam profile) of the linear beam. The pitch is changed. When irradiating the above-described semiconductor film with laser, the overlapping pitch in the beam width is most suitable around 1/10 of the beam width of the linear beam as shown in FIG. Thereby, the uniformity of the crystallinity within the semiconductor film was improved. In the above example, since the half width was 0.4 mm, the pulse frequency of the excimer laser was 30 Hz, the scanning speed was 1.0 mm / s, and the laser beam was irradiated. At this time, the energy density on the laser beam irradiation surface was set to 420 mJ / cm ² . The method described so far is a very general method used for crystallizing a semiconductor film using a linear beam.

Problems to be solved by the invention

When laser annealing is performed, the laser beam is processed into a linear beam having a linear shape at or near the irradiated surface using an optical system as shown in FIG. As shown in FIG. 2A, the overlapping pitch in the beam width of the linear beam is about 1/10 of the beam width.

As shown in FIG. 3, since the wavelength of the excimer laser is 308 nm, the absorption coefficient at this wavelength is 1.38 × 10 ⁶ cm ⁻¹ for the amorphous silicon film, and the polycrystalline silicon film Is 1.56 × 10 ⁶ cm ⁻¹ , and the absorption coefficients for the amorphous silicon film and the polycrystalline silicon film are substantially the same.

From the above, when laser annealing is performed with an excimer laser, recrystallization is repeatedly performed on a region once crystallized. For this reason, variation in grain size has occurred.

At present, the long length of the linear beam is about 100 mm. Even when the length of the linear beam is extended using a beam expander, about 150 mm is a limit in consideration of the uniformity and energy density of the linear beam.

On the other hand, the substrate to be used has been increased in area, and as the large-area substrate, for example, a 600 mm × 720 mm substrate, a 320 mm × 400 mm substrate, a circular 8-inch substrate (diameter of about 200 mm), etc. have come to be used. ing. An example of a method of irradiating such a large area substrate with the linear beam is shown in FIG.

4 and 27, a 320 mm × 400 mm substrate on which an amorphous semiconductor film is formed is scanned with the linear beam having a long length of the linear beam of 150 mm (or the linear shape). In this example, irradiation is performed by moving the irradiation position of the beam relative to the irradiated surface. In the irradiation method as shown in FIGS. 4 and 27, the area scanned by the linear beam overlaps the central portion of the substrate (FIGS. 4A and 27A), or the central portion of the substrate is irradiated. (FIG. 4 (b), FIG. 27 (b)). Further, as shown in FIGS. 4C and 27C, there is an irradiation method in which the ends of irradiation with a linear beam are in contact with each other at the center of the substrate.

When irradiation is performed as shown in FIGS. 4A and 27A, the excimer laser has substantially the same absorption coefficient for the amorphous silicon film and the polycrystalline silicon film, as described above. In the central portion of the substrate, which is the overlapping portion of the region scanned by the beam, recrystallization was performed many times, resulting in variations in grain size. Therefore, good characteristics were not obtained even when a TFT was fabricated using the central portion of the substrate and the electrical characteristics were measured.

When irradiation is performed as shown in FIGS. 4B and 27B, since the laser annealing is not performed on the central portion of the substrate, the amorphous silicon film is not crystallized, and is obtained by laser annealing. The crystallinity is different from the crystalline silicon film. Even when a TFT was fabricated using such a silicon film and the electrical characteristics were measured, the characteristics of the central portion of the substrate were extremely poor.

When irradiation is performed as shown in FIG. 4C and FIG. 27C, the energy density at both ends of the linear beam is considerably lower than that near the center of the linear beam. The central portion of the substrate where the ends of irradiation are present has poor crystallinity. Even when a TFT was fabricated using such a silicon film and the electrical characteristics were measured, the characteristics varied within the substrate.

That is, as shown in FIGS. 4A to 4C and FIGS. 27A to 27C, in any case, laser annealing is performed by scanning the linear beam on a large area substrate. A region having poor crystallinity was generated, and even when a TFT was fabricated using the region as an active layer, the electrical characteristics of the TFT could not be obtained.

The present invention provides a first crystalline region obtained by performing laser annealing by using a laser beam having a wavelength in a range of 370 to 650 nm and irradiating the amorphous semiconductor film while moving the laser beam; An object of the present invention is to obtain a crystalline semiconductor film having good crystallinity by forming a region obtained by performing laser annealing by irradiating the laser beam while moving it to a region including a part of the first crystalline region. And Note that in this specification, the crystalline region refers to a region crystallized by irradiation while moving the linear beam. However, the shape of the laser beam at or near the irradiation surface is not limited to a linear shape, and may be a rectangular shape. As already described, the use of a linear beam is particularly desirable because of its high productivity. In addition, the present invention is particularly effective when performing laser annealing on a large area substrate, since it is not necessary to expand the length of the linear beam in accordance with the size of the large area substrate. It is economical because it is not necessary to prepare a new optical system to match the size of the large area substrate.

Means for solving the problem

FIG. 3 shows the absorption coefficient with respect to wavelength in the amorphous silicon film and the polycrystalline silicon film. Since the wavelength of the excimer laser is 308 nm, it can be seen from FIG. 3 that the absorption coefficient of the amorphous silicon film is 1.38 × 10 ⁶ cm ⁻¹ and the absorption coefficient of the polycrystalline silicon film is 1.56 × 10 ⁶ cm ^−1. It becomes. On the other hand, since the wavelength of the second harmonic of the YAG laser is 532 nm, the absorption coefficient of the amorphous silicon film is 9.31 × 10 ⁴ cm ⁻¹ , and the absorption coefficient of the polycrystalline silicon film is 2.74 × 10 ^4. cm ⁻¹ .

From the above, the absorption of the excimer laser to the amorphous silicon film and the polycrystalline silicon film is comparable, but the second harmonic of the YAG laser is more easily absorbed by the amorphous silicon film than the polycrystalline silicon film. I understand. That is, when laser annealing is performed on the amorphous silicon film using the second harmonic of the YAG laser, the crystalline silicon film crystallized by the laser annealing is again laser-annealed by the second harmonic of the YAG laser. But it hardly changes.

An excimer laser has a high output and can oscillate a pulse having a high repetition rate of about 300 Hz at present. In recent years, an excimer laser is used in a crystallization process of a semiconductor film for manufacturing a liquid crystal display of a low-temperature polysilicon TFT which has been commercialized. In addition to the excimer laser, an Ar laser, a YAG laser, a YVO ₄ laser, a YLF laser, or the like can be used.

Here, a method of laser annealing the amorphous silicon film using the second harmonic of the YAG laser will be described. As in the prior art, an optical system as shown in FIG. 1 is used to process a second harmonic laser beam of a YAG laser into a linear beam whose shape on the irradiation surface is linear. The amorphous silicon film is irradiated with the linear beam while moving the stage in a direction perpendicular to the longitudinal direction of the linear beam to obtain a crystalline silicon film.

As described above, the absorption coefficient of the second harmonic of the YAG laser with respect to the amorphous silicon film is 9.31 × 10 ⁴ cm ⁻¹ , and the absorption coefficient of the polycrystalline silicon film is 2.74 × 10 ⁴ cm ^−1. It is. Therefore, the second harmonic of the YAG laser is absorbed more in the amorphous silicon film than in the polycrystalline silicon film. In other words, when laser annealing is performed using the second harmonic of the YAG laser, an amorphous region can be crystallized without affecting the already crystallized region, and a crystalline semiconductor film with good uniformity can be obtained. Can be obtained.

Here, a case will be described in which laser annealing is performed on an amorphous silicon film formed on a large-area substrate as shown in FIGS. 4A and 27A using the second harmonic of a YAG laser. As already described, the second harmonic of the YAG laser is absorbed more in the amorphous silicon film than in the polycrystalline silicon film. Therefore, the central part of the substrate shown in FIGS. 4A and 27A scans the linear beam (or moves the irradiation position of the linear beam relative to the irradiated surface). Although annealing is performed twice, the crystallinity formed at the first time hardly changes even if the second irradiation is performed. For this reason, the laser beam is irradiated only once even in a region where the laser beam is irradiated a plurality of times as in the central portion of the substrate in FIGS. 4A and 27A. Even in the region, a crystalline silicon film having good crystallinity can be obtained. When a TFT is manufactured using the crystalline silicon film and the electrical characteristics are measured, good characteristics can be obtained even in the central portion of the substrate.

Next, the overlapping pitch in the beam width of the linear beam will be described. The second harmonic of the YAG laser is processed into a linear beam having a linear shape at or near the irradiated surface using an optical system as shown in FIG. 1, and the laser is applied to the amorphous silicon film. Irradiate. At this time, the optimum value of the superposition pitch in the beam width of the linear beam differs depending on the film thickness of the amorphous silicon film. For example, as shown in FIG. 2 (b), the overlapping pitch in the beam width of the linear beam is about 1/3 of the beam width of the linear beam, or 1 as shown in FIG. 2 (c). There is also a method of setting to about / 2.

On the other hand, the YAG laser is highly coherent and it is difficult to form a beam, and it is difficult to process it into a linear beam. However, as already described, since the second harmonic of the YAG laser is more easily absorbed by the amorphous silicon film than the polycrystalline silicon film, the region once crystallized into the polycrystalline silicon film is again the YAG laser. Even if laser annealing is performed with the second harmonic of the laser, it hardly changes. From the above, the shape of the laser beam at or near the irradiated surface is not necessarily linear. However, the energy of the laser beam on the irradiated surface is preferably uniform.

The laser used in the present invention is not limited to the second harmonic of the YAG laser. As shown in FIG. 3, the wavelength of the laser beam to be irradiated may be in the range of 370 to 650 nm where the amorphous silicon film is better absorbed than the polycrystalline silicon film.

Furthermore, there are amorphous semiconductor films and microcrystalline semiconductor films as amorphous semiconductor films. In addition to amorphous silicon films, compound semiconductor films having an amorphous structure such as amorphous silicon germanium films are applied. May be.

[Example 1]
In this embodiment, an amorphous silicon film is formed by a sputtering apparatus and laser annealing is performed using the second harmonic (wavelength 532 nm) of a YAG laser whose rod shape is cylindrical.

As a substrate, a Corning 1737 substrate having a thickness of 0.7 mm and 320 mm × 400 mm was prepared. A silicon nitride oxide film having a thickness of 200 nm was formed on the substrate using a plasma CVD apparatus, and an amorphous silicon film having a thickness of 50 nm was formed on the surface of the silicon nitride oxide film using a sputtering apparatus.

Thereafter, laser annealing is performed using the second harmonic of the YAG laser to crystallize the amorphous semiconductor film. If the rod shape of the YAG laser used at this time is cylindrical, the beam shape is a circle. Therefore, as shown in FIG. 5, if a beam expander composed of two cylindrical lenses 71 and 72 is first inserted after the laser oscillator of FIG. 1, and the beam is shaped into an ellipse, it is processed into a linear beam. It's easy to do.

As shown in FIG. 3, in the second harmonic (wavelength 532 nm) of the YAG laser, amorphous silicon has a higher absorption rate than polycrystalline silicon. Therefore, also in the first region irradiated with the linear beam moving and the second region including a part of the first region irradiated with the linear beam moving, the first region is The amorphous region can be crystallized without breaking the shape of the continuous crystal region, and a crystalline silicon film with good crystallinity can be obtained.

Using the crystalline silicon film thus produced, a TFT is produced by, for example, a known method or a method shown in a later example. The TFT has good electrical characteristics and has characteristics with little variation.

[Example 2]
In this embodiment, an amorphous silicon film is formed by a sputtering apparatus and laser annealing is performed using a second harmonic (wavelength: 532 nm) of a YAG laser whose rod shape is a slab shape.

As a substrate, a Corning 1737 substrate having a thickness of 0.7 mm and 320 mm × 400 mm was prepared. A silicon nitride oxide film having a thickness of 200 nm was formed on the substrate using a plasma CVD apparatus, and an amorphous silicon film having a thickness of 50 nm was formed on the surface of the silicon nitride oxide film using a sputtering apparatus.

Thereafter, laser annealing is performed using the second harmonic of the YAG laser to crystallize the amorphous semiconductor film. If the rod shape of the YAG laser used at this time is a slab shape, the obtained beam shape is a rectangle, so that it can be processed into a linear beam using the optical system of FIG. 1 as it is.

As shown in FIG. 3, in the second harmonic (wavelength 532 nm) of the YAG laser, amorphous silicon has a higher absorption rate than polycrystalline silicon. Therefore, also in the first region irradiated with the linear beam moving and the second region including a part of the first region irradiated with the linear beam moving, the first region is The amorphous region can be crystallized without breaking the shape of the continuous crystal region, and a crystalline silicon film with good crystallinity can be obtained.

Using the crystalline silicon film thus produced, a TFT is produced by, for example, a known method or a method shown in a later example. The TFT has good electrical characteristics and has characteristics with little variation.

[Example 3]
In this embodiment, an amorphous silicon film is formed by a CVD apparatus, heat-treated and partially crystallized, and then laser annealing is performed using the second harmonic (wavelength 532 nm) of a YAG laser. The case will be described.

As a substrate, a Corning 1737 substrate having a thickness of 0.7 mm and 320 mm × 400 mm was prepared. A silicon nitride oxide film having a thickness of 200 nm was formed on the substrate using a plasma CVD apparatus, and then an amorphous silicon film having a thickness of 50 nm was formed on the surface of the silicon nitride oxide film using the plasma CVD apparatus. A solution containing an element that promotes crystallization is applied onto the amorphous silicon film. For example, when a nickel acetate solution is used as the solution, the nickel acetate solution (weight conversion concentration: 10 ppm) is applied to the entire surface of the film by spin coating.

Next, the substrate was heated in a nitrogen atmosphere at a temperature of 500 ° C. for 1 hour and further in a nitrogen atmosphere at a temperature of 550 ° C. for 4 hours. Thereafter, laser annealing is performed using the second harmonic of the YAG laser to crystallize the amorphous semiconductor film. If the rod shape of the YAG laser used at this time is cylindrical, the beam shape is a circle. Therefore, as shown in FIG. 5, if a beam expander composed of two cylindrical lenses 71 and 72 is first inserted after the laser oscillator of FIG. 1, and the beam is shaped into an ellipse, it is processed into a linear beam. It's easy to do. Further, if the rod shape of the YAG laser used at this time is a slab shape, the obtained beam shape is a rectangle, so that it can be processed into a linear beam using the optical system of FIG. 1 as it is.

As shown in FIG. 3, in the second harmonic (wavelength 532 nm) of the YAG laser, amorphous silicon has a higher absorption rate than polycrystalline silicon. Therefore, also in the first region irradiated with the linear beam moving and the second region including a part of the first region irradiated with the linear beam moving, the first region is The amorphous region can be crystallized without breaking the shape of the continuous crystal region, and a crystalline silicon film with good crystallinity can be obtained.

Using the crystalline silicon film thus produced, a TFT is produced by, for example, a known method or a method shown in a later example. The TFT has good electrical characteristics and has characteristics with little variation.

[Example 4]
In this embodiment, an example in which laser annealing is performed using the second harmonic (wavelength 532 nm) of a YVO ₄ laser will be described.

The YVO ₄ laser is characterized by the high quality of the laser beam, and M ^2, which is one index representing the quality of the laser beam, is very close to 1.

As in Example 1, a Corning 1737 substrate having a thickness of 0.7 mm and 320 mm × 400 mm was prepared, and a silicon nitride oxide film having a thickness of 200 nm was formed on the substrate by using a plasma CVD apparatus. An amorphous silicon film having a thickness of 50 nm is formed on the surface of the silicon nitride oxide film. The amorphous silicon film is irradiated with the second harmonic laser beam of the YVO ₄ laser and laser annealing is performed. First, an example in which the second harmonic laser beam of the YVO ₄ laser is processed into a linear beam. A description will be given with reference to FIG.

  In FIG. 6, first, the beam is expanded in one direction by a beam expander composed of cylindrical lenses 301 and 302, then the beam is divided by a cylindrical array lens 303, and further, an irradiation surface having a length of 5 mm is formed by a condensing cylindrical lens 304. Form a beam. A cylindrical lens 305 is disposed at a right angle to the cylindrical lens 304 so that the beam width is 0.1 mm. However, although the mirror 306 is disposed immediately after the beam expander, the mirror 306 is not necessarily required. In this way, the beam is processed into a linear beam having a linear shape at or near the irradiated surface, and the linear beam is scanned on the amorphous silicon film to be crystallized.

As shown in FIG. 3, in the second harmonic (wavelength 532 nm) of the YVO ₄ laser, the absorption rate of amorphous silicon is sufficiently higher than that of polycrystalline silicon. Therefore, also in the first region irradiated with the linear beam moving and the second region including a part of the first region irradiated with the linear beam moving, the first region is The amorphous region can be crystallized without breaking the shape of the continuous crystal region, and a crystalline silicon film with good crystallinity can be obtained.

Using the crystalline silicon film thus produced, a TFT is produced by, for example, a known method or a method shown in a later example. The TFT has good electrical characteristics and has characteristics with little variation.

[Example 5]
In this embodiment, an example in which laser annealing is performed using the second harmonic (wavelength 527 nm) of a YLF laser will be described.

The second harmonic of the YLF laser can be made about 5 mm in diameter at the exit of the laser beam. Therefore, it is much easier to adjust the shape and energy density of the laser beam compared to laser beams close to other point light sources.

As shown in Example 1, a Corning 1737 substrate having a thickness of 0.7 mm and 320 mm × 400 mm was prepared, and a silicon nitride oxide film having a thickness of 200 nm was grown on the substrate using a plasma CVD apparatus, and sputtering was performed. An amorphous silicon film having a thickness of 50 nm is formed on the surface of the silicon nitride oxide film using an apparatus. Thereafter, similarly to Example 4, the laser beam is processed into a linear beam using the optical system shown in FIG. 6, and the amorphous silicon film is irradiated with the linear beam.

As shown in FIG. 3, in the second harmonic (wavelength 527 nm) of the YLF laser, the absorption rate of amorphous silicon is higher than that of polycrystalline silicon. Therefore, also in the first region irradiated with the linear beam moving and the second region including a part of the first region irradiated with the linear beam moving, the first region is The amorphous region can be crystallized without breaking the shape of the continuous crystal region, and a crystalline silicon film with good crystallinity can be obtained.

Using the crystalline silicon film thus produced, a TFT is produced by, for example, a known method or a method shown in a later example. The TFT has good electrical characteristics and has characteristics with little variation.

[Example 6]
An embodiment of the present invention will be described with reference to FIGS. Here, a method for simultaneously manufacturing the pixel TFT and the storage capacitor of the pixel portion and the TFT of the driver circuit provided around the pixel portion will be described in detail according to the process.

In FIG. 7A, a glass substrate such as barium borosilicate glass or alumino borosilicate glass represented by Corning # 7059 glass or # 1737 glass, a quartz substrate, or the like is used for the substrate 101. When a glass substrate is used, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. Then, in order to prevent impurity diffusion from the substrate 101, a base film 102 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface of the substrate 101 where the TFT is formed. For example, a silicon oxynitride film 102a formed from SiH ₄ , NH ₃ , and N ₂ O by plasma CVD is 10 to 200 nm (preferably 50 to 100 nm), and similarly, oxynitride that is formed from SiH ₄ and N ₂ O. A silicon hydride film 102b is formed to a thickness of 50 to 200 nm (preferably 100 to 150 nm). Although the base film 102 is shown here as a two-layer structure, it may be formed by laminating a single layer film or two or more layers of the insulating film.

The silicon oxynitride film is formed using a parallel plate type plasma CVD method. The silicon oxynitride film 102a is introduced into the reaction chamber with SiH ₄ as 10 SCCM, NH ₃ as 100 SCCM, and N ₂ O as 20 SCCM. The substrate temperature is 325 ° C., the reaction pressure is 40 Pa, the discharge power density is 0.41 W / cm ² , and the discharge frequency. It was set to 60 MHz. On the other hand, the silicon oxynitride nitride film 102b is introduced into the reaction chamber with SiH ₄ as 5 SCCM, N ₂ O as 120 SCCM, and H ₂ as 125 SCCM. The substrate temperature is 400 ° C., the reaction pressure is 20 Pa, and the discharge power density is 0.41 W / cm. ^{2. The} discharge frequency was 60 MHz. These films can be formed continuously only by changing the substrate temperature and switching the reaction gas.

The silicon oxynitride film 102a manufactured in this way has a total number of atoms per unit volume of 9.28 × 10 ²² / cm ³ and is fluorinated with ammonium hydrogen fluoride (NH ₄ HF ₂ ) at 7.13%. This is a dense and hard film having a slow etching rate of about 63 nm / min at 20 ° C. for a mixed solution containing 15.4% ammonium fluoride (NH ₄ F) (product name: LAL500, manufactured by Stella Chemifa Corporation). When such a film is used for the base film, it is effective to prevent the alkali metal element from the glass substrate from diffusing into the semiconductor layer formed thereon.

Next, a semiconductor layer 103a having an amorphous structure with a thickness of 25 to 100 nm (preferably 30 to 70 nm) is formed by a method such as plasma CVD or sputtering. The semiconductor film having an amorphous structure includes an amorphous semiconductor layer and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied. In the case where an amorphous silicon film is formed by a plasma CVD method, the base film 102 and the amorphous semiconductor layer 103a can be formed continuously. For example, as described above, after the silicon oxynitride film 102a and the silicon oxynitride nitride film 102b are continuously formed by the plasma CVD method, the reaction gas is changed from SiH ₄ , N ₂ O, H ₂ to SiH ₄ and H ₂ or By switching to only SiH _4, continuous formation can be achieved without being exposed to the air atmosphere once. As a result, contamination of the surface of the silicon oxynitride silicon film 102b can be prevented, and variation in characteristics and threshold voltage of the manufactured TFT can be reduced.

  Then, a crystallization step is performed to form a crystalline semiconductor layer 103b from the amorphous semiconductor layer 103a. As the method, a laser annealing method, a thermal annealing method (solid phase growth method), or a rapid thermal annealing method (RTA method) can be applied. When using a glass substrate or a plastic substrate having poor heat resistance as described above, it is particularly preferable to apply the laser annealing method of the present invention. In the RTA method, an infrared lamp, a halogen lamp, a metal halide lamp, a xenon lamp, or the like is used as a light source. Alternatively, the crystalline semiconductor layer 103b can be formed by a crystallization method using a metal element in accordance with the technique disclosed in Japanese Patent Application Laid-Open No. 7-130652. Alternatively, the crystalline semiconductor layer 103b can be formed by performing both a laser annealing method and a crystallization method using a metal element. In the crystallization step, first, it is preferable to release hydrogen contained in the amorphous semiconductor layer, and heat treatment is performed at 400 to 500 ° C. for about 1 hour to include the amount of hydrogen contained in the amorphous semiconductor layer. If the crystallization is performed after setting the number of atoms to 5% or less of the total number of atoms, roughening of the film surface can be prevented.

Further, in the step of forming the amorphous silicon film by the plasma CVD method, if SiH ₄ and argon (Ar) are used as the reaction gas and the substrate temperature during film formation is 400 to 450 ° C., the amorphous silicon layer The hydrogen concentration can be made 5% or less of the total number of atoms contained in the amorphous silicon layer. In such a case, heat treatment for releasing hydrogen is not necessary.

  For crystallization, any of the methods shown in Examples 1 to 5 may be applied. In this way, a crystalline semiconductor layer 103b as shown in FIG. 7B can be obtained.

Then, using the first photomask (PM1) over the crystalline semiconductor layer 103b, a resist pattern is formed using a photolithography technique, the crystalline semiconductor layer is divided into islands by dry etching, and FIG. As shown in (C), island-like semiconductor layers 104 to 108 are formed. A mixed gas of CF ₄ and O ₂ is used for dry etching of the crystalline silicon film.

In order to control the threshold voltage (Vth) of the TFT, such an island-shaped semiconductor layer is doped with an impurity element imparting p-type at a concentration of about 1 × 10 ^{16 to} 5 × 10 ¹⁷ / cm ^3. You may add to the whole surface of a semiconductor layer. As an impurity element imparting p-type to a semiconductor, elements of Group 13 of the periodic table such as boron (B), aluminum (Al), and gallium (Ga) are known. As the method, an ion implantation method or an ion doping method (or an ion shower doping method) can be used, but the ion doping method is suitable for processing a large area substrate. In the ion doping method, diborane (B ₂ H ₆ ) is used as a source gas and boron (B) is added. Such implantation of the impurity element is not always necessary and may be omitted. However, this is a technique that is particularly suitable for keeping the threshold voltage of the n-channel TFT within a predetermined range.

The gate insulating film 109a is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. In this embodiment, the silicon oxynitride film is formed with a thickness of 120 nm. In addition, a silicon oxynitride film manufactured by adding O ₂ to SiH ₄ and N ₂ O is a preferable material for this application because the fixed charge density in the film is reduced. A silicon oxynitride film formed from SiH ₄ , N ₂ O, and H ₂ is preferable because the interface defect density with the gate insulating film can be reduced. Of course, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a laminated structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ are mixed by a plasma CVD method to a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (13.56 MHz) power density of 0. It can be formed by discharging at 5 to 0.8 W / cm ² . The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by thermal annealing at 400 to 500 ° C. thereafter.

Then, as shown in FIG. 7D, a heat-resistant conductive layer 111 for forming a gate electrode over the first shape gate insulating film 109a is formed to a thickness of 200 to 400 nm (preferably 250 to 350 nm). Form. The heat-resistant conductive layer may be formed as a single layer, or may have a laminated structure including a plurality of layers such as two layers or three layers as necessary. The heat-resistant conductive layer referred to in this specification includes an element selected from Ta, Ti, and W, an alloy containing the element as a component, or an alloy film combining the elements. These heat-resistant conductive layers are formed by a sputtering method or a CVD method, and it is preferable to reduce the concentration of impurities contained in order to reduce the resistance. Particularly, the oxygen concentration is preferably 30 ppm or less. In this embodiment, the W film is formed with a thickness of 300 nm. The W film may be formed by sputtering using W as a target, or may be formed by thermal CVD using tungsten hexafluoride (WF ₆ ). In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and the resistivity of the W film is desirably 20 μΩcm or less. Although the resistivity of the W film can be reduced by increasing the crystal grains, if the impurity element such as oxygen is large in W, the crystallization is hindered and the resistance is increased. Therefore, in the case of sputtering, the resistivity is obtained by using a W target with a purity of 99.9999% and forming a W film with sufficient consideration so that impurities are not mixed in the gas phase during film formation. 9-20 μΩcm can be realized.

  On the other hand, when a Ta film is used for the heat-resistant conductive layer 111, it can be similarly formed by sputtering. The Ta film uses Ar as a sputtering gas. In addition, if an appropriate amount of Xe or Kr is added to the gas during sputtering, the internal stress of the film to be formed can be relieved and peeling of the film can be prevented. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used as a gate electrode, but the resistivity of the β-phase Ta film is about 180 μΩcm and is not suitable for a gate electrode. Since the conductive nitride has a crystal structure close to the α phase, for example, if a TaN film is formed on the base of the Ta film, an α phase Ta film can be easily obtained. Although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm under the heat resistant conductive layer 111. This improves the adhesion of the conductive film formed thereon and prevents oxidation, and at the same time, the alkali metal element contained in a trace amount in the heat-resistant conductive layer 111 diffuses into the first shape gate insulating film 109a. Can be prevented. In any case, the heat resistant conductive layer 111 preferably has a resistivity in the range of 10 to 50 μΩcm.

Next, resist masks 112 to 117 are formed using a second photomask (PM2) by using a photolithography technique. Then, a first etching process is performed. In this embodiment, an ICP etching apparatus is used, Cl ₂ and CF ₄ are used as etching gases, and plasma is formed by applying RF (13.56 MHz) power of 3.2 W / cm ² at a pressure of 1 Pa. 224 mW / cm ² of RF (13.56 MHz) power is also applied to the substrate side (sample stage), thereby applying a substantially negative self-bias voltage. Under this condition, the etching rate of the W film is about 100 nm / min. In the first etching process, the time during which the W film was just etched was estimated based on this etching rate, and the time when the etching time was increased by 20% was used as the etching time.

  Conductive layers 118 to 123 having a first tapered shape are formed by the first etching process. The angle of the tapered portion is 15 to 30 °. In order to perform etching without leaving a residue, overetching that increases the etching time at a rate of about 10 to 20% is performed. Since the selection ratio of the silicon oxynitride film (first shape gate insulating film 109a) to the W film is 2 to 4 (typically 3), the surface on which the silicon oxynitride film is exposed by the over-etching process is A second shape gate insulating film 109b having a tapered shape is formed in the vicinity of the end of the conductive layer having the first tapered shape, which is etched by about 20 to 50 nm.

Then, a first doping process is performed, and an impurity element of one conductivity type is added to the island-shaped semiconductor layer. Here, a step of adding an impurity element imparting n-type is performed. The mask 112 to 117 on which the first shape conductive layer is formed is left as it is, and an impurity element imparting n-type is added by ion doping in a self-aligning manner using the first taper shape of the conductive layers 118 to 123 as a mask. To do. In order to add the impurity element imparting n-type through the tapered portion at the end of the gate electrode and the gate insulating film so as to reach the semiconductor layer located thereunder, the dose is set to 1 × 10 ^{13 to} 5 × 10 ^14. / Cm ² and an acceleration voltage of 80 to 160 kV. As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but phosphorus (P) is used. By such an ion doping method, an impurity element imparting n-type is added to the first impurity regions 124 to 128 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ , and formed below the tapered portion. An impurity element imparting n-type is added to the second impurity region (A), which is not necessarily uniform in the region, but in a concentration range of 1 × 10 ¹⁷ to 1 × 10 ²⁰ / cm ³ .

  In this step, in the second impurity regions (A) 129 to 133, the concentration change of the impurity element imparting n-type contained in at least the portion overlapping with the first shape conductive layers 118 to 123 is changed in the tapered portion. Reflects changes in film thickness. That is, the concentration of phosphorus (P) added to the second impurity regions (A) 129 to 132 is gradually increased inward from the end of the conductive layer in the region overlapping the first shape conductive layer. The concentration is lowered. This is because the concentration of phosphorus (P) reaching the semiconductor layer changes due to the difference in film thickness of the tapered portion.

Next, a second etching process is performed as shown in FIG. The etching process is similarly performed by an ICP etching apparatus, using a mixed gas of CF ₄ and Cl ₂ as an etching gas, RF power 3.2 W / cm ² (13.56 MHz), bias power 452 mW / cm ² (13.56 MHz), pressure Etching is performed at 1.0 Pa. Conductive layers 140 to 145 having the second shape formed under these conditions are formed. A tapered portion is formed at the end, and a taper shape is formed in which the thickness gradually increases from the end toward the inside. Compared to the first etching process, the ratio of isotropic etching is increased by reducing the bias power applied to the substrate side, and the angle of the tapered portion is 30 to 60 °. Further, the surface of the second shape gate insulating film 109b is etched by about 40 nm, and a third shape gate insulating film 109c is newly formed.

Then, an impurity element imparting n-type conductivity is doped under a condition of a high acceleration voltage with a dose amount lower than that in the first doping treatment. For example, the acceleration voltage is set to 70 to 120 kV and the dose is 1 × 10 ¹³ / cm ² , and the impurity concentration in the region overlapping with the conductive layers 140 to 145 having the second shape is set to 1 × 10 ¹⁶ to 1 × 10 ^18. / cm ³ In this manner, second impurity regions (B) 146 to 150 are formed.

Then, impurity regions 156 and 157 having a conductivity type opposite to the one conductivity type are formed in the island-like semiconductor layers 104 and 106 forming the p-channel TFT. Also in this case, an impurity element imparting p-type conductivity is added using the second shape conductive layers 140 and 142 as a mask to form impurity regions in a self-aligning manner. At this time, the island-like semiconductor layers 105, 107, and 108 forming the n-channel TFT are covered with a resist mask 151 to 153 using a third photomask (PM3). The impurity regions 156 and 157 formed here are formed by an ion doping method using diborane (B ₂ H ₆ ). The concentration of the impurity element imparting p-type in the impurity regions 156 and 157 is set to 2 × 10 ²⁰ to 2 × 10 ²¹ / cm ³ .

The impurity regions 156 and 157 can be divided into three regions containing an impurity element imparting n-type. The third impurity regions 156a and 157a include an impurity element imparting n-type at a concentration of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ , and the fourth impurity regions (A) 156b and 157b are 1 × 10 ¹⁷ The fourth impurity regions (B) 156c and 157c contain an impurity element imparting n-type at a concentration of ˜1 × 10 ²⁰ / cm ³ , and the fourth impurity regions (B) 156c and 157c are n-type at a concentration of 1 × 10 ^{16 to} 5 × 10 ¹⁸ / cm ³ It contains an impurity element that imparts. However, the concentration of the impurity element imparting p-type in these impurity regions 156b, 156c, 157b, and 157c is set to 1 × 10 ¹⁹ / cm ³ or more, and in the third impurity regions 156a and 157a, p-type is used. The third impurity region functions as a source region and a drain region of the p-channel TFT by increasing the concentration of the impurity element imparting ˜1.5 to 3 times. In addition, the fourth impurity regions (B) 156c and 157c are formed so as to partially overlap with the conductive layer 140 or 142 having the second tapered shape.

Thereafter, as shown in FIG. 9A, a first interlayer insulating film 158 is formed over the gate electrode and the gate insulating film. The first interlayer insulating film may be formed using a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a stacked film including a combination thereof. In any case, the first interlayer insulating film 158 is formed of an inorganic insulating material. The film thickness of the first interlayer insulating film 158 is 100 to 200 nm. Here, when a silicon oxide film is used, TEOS and O ₂ are mixed by a plasma CVD method, the reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0. It can be formed by discharging at 8 W / cm ² . In the case of using a silicon oxynitride film, a silicon oxynitride film manufactured from SiH ₄ , N ₂ O, and NH ₃ by a plasma CVD method or a silicon oxynitride film manufactured from SiH ₄ and N ₂ O is used. What is necessary is just to form. The production conditions in this case are a reaction pressure of 20 to 200 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (60 MHz) power density of 0.1 to 1.0 w / cm ² . Alternatively, a silicon oxynitride silicon film formed from SiH ₄ , N ₂ O, and H ₂ may be used. Similarly, the silicon nitride film can be formed from SiH ₄ and NH ₃ by plasma CVD.

  Then, a step of activating the impurity element imparting n-type or p-type added at each concentration is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 1 ppm or less, preferably 0.1 ppm or less in a nitrogen atmosphere at 400 to 700 ° C., typically 500 to 600 ° C. In this example, the temperature is 550 ° C. for 4 hours. Heat treatment was performed. Further, when a plastic substrate having a low heat resistant temperature is used for the substrate 101, it is preferable to apply a laser annealing method.

Subsequent to the activation step, the step of hydrogenating the island-like semiconductor layer by changing the atmospheric gas and performing heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen. Do. This step is a step of terminating dangling bonds of 10 ¹⁶ to 10 ¹⁸ / cm ^{3 in} the island-like semiconductor layer by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed. In any case, it is desirable that the defect density in the island-shaped semiconductor layers 104 to 108 is 10 ¹⁶ / cm ³ or less, and for this reason, about 0.01 to 0.1% of the total number of atoms included in the island-shaped semiconductor layers. Of hydrogen may be added.

Thereafter, a second interlayer insulating film 159 made of an organic resin is formed to a thickness of 1.0 to 1.5 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Here, it was formed by baking at 300 ° C. using a type of polyimide that is thermally polymerized after being applied to the substrate.

  Thus, the surface can be satisfactorily flattened by forming the second interlayer insulating film with an organic insulating material. Moreover, since an organic resin material generally has a low dielectric constant, parasitic capacitance can be reduced. However, since it is hygroscopic and not suitable as a protective film, it is preferably used in combination with a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like formed as the first interlayer insulating film 158 as in this embodiment. .

Thereafter, a resist mask having a predetermined pattern is formed using a fourth photomask (PM4), and contact holes reaching impurity regions which are formed in the respective island-like semiconductor layers and serve as source regions or drain regions are formed. The contact hole is formed by a dry etching method. In this case, the second interlayer insulating film 159 made of an organic resin material is first etched using a mixed gas of CF ₄ , O ₂ , and He as an etching gas, and then the etching gas is first changed to CF ₄ and O ₂ as the first gas. The interlayer insulating film 158 is etched. Further, in order to increase the selection ratio with the island-shaped semiconductor layer, the contact hole can be formed by etching the third shape gate insulating film 109c by switching the etching gas to CHF ₃ .

Then, a conductive metal film is formed by sputtering or vacuum evaporation, a resist mask pattern is formed by a fifth photomask (PM5), and source lines 160 to 164 and drain lines 165 to 168 are formed by etching. . The pixel electrode 169 is formed together with the drain line. A pixel electrode 171 represents a pixel electrode belonging to an adjacent pixel. Although not shown, in this embodiment, this wiring is formed by forming a Ti film with a thickness of 50 to 150 nm, forming a contact with an impurity region that forms a source or drain region of the island-like semiconductor layer, and the Ti film. Overlaid on top, aluminum (Al) is formed to a thickness of 300 to 400 nm (indicated by 160a to 169a in FIG. 9B), and a transparent conductive film is formed thereon to a thickness of 80 to 120 nm (FIG. 9 (B) indicated by 160b to 169b). Indium zinc oxide alloy (In ₂ O ₃ —ZnO) and zinc oxide (ZnO) are also suitable materials for the transparent conductive film, and gallium (Ga) is added to increase the transmittance and conductivity of visible light. Zinc oxide (ZnO: Ga) or the like can be preferably used.

  In this way, a substrate having the TFT of the driving circuit and the pixel TFT of the pixel portion can be completed on the same substrate by using five photomasks. A first p-channel TFT 200, a first n-channel TFT 201, a second p-channel TFT 202, and a second n-channel TFT 203 are formed in the driver circuit, and a pixel TFT 204 and a storage capacitor 205 are formed in the pixel portion. Yes. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

  In the first p-channel TFT 200 of the driver circuit, a conductive layer having a second taper shape functions as the gate electrode 220, and the island-shaped semiconductor layer 104 has a channel formation region 206, a source region, or a drain region. A third impurity region 207 a that functions, a fourth impurity region (A) 207 b that forms an LDD region that does not overlap the gate electrode 220, and a fourth impurity region (B that forms an LDD region that partially overlaps the gate electrode 220 ) 207c.

  In the first n-channel TFT 201, a conductive layer having a second taper shape functions as the gate electrode 221, and the island-shaped semiconductor layer 105 functions as a channel formation region 208, a source region, or a drain region. 1 impurity region 209a, a second impurity region (A) 209b that forms an LDD region that does not overlap with the gate electrode 221, and a second impurity region (B) 209c that forms an LDD region that partially overlaps the gate electrode 221. It has a structure. For the channel length of 2 to 7 μm, the length of the portion where the second impurity region (B) 209 c overlaps with the gate electrode 221 is 0.1 to 0.3 μm. The length is controlled from the thickness of the gate electrode 221 and the angle of the tapered portion. By forming such an LDD region in an n-channel TFT, a high electric field generated in the vicinity of the drain region can be relaxed, hot carrier generation can be prevented, and deterioration of the TFT can be prevented.

  Similarly, in the second p-channel TFT 202 of the driver circuit, the conductive layer having the second taper shape functions as the gate electrode 222, and the channel formation region 210, the source region or the drain region is formed in the island-shaped semiconductor layer 106. A third impurity region 211 a that functions as a fourth impurity region (A) 211 b that forms an LDD region that does not overlap the gate electrode 222, and a fourth impurity region that forms an LDD region that partially overlaps the gate electrode 222 ( B) It has a structure having 211c.

  In the second n-channel TFT 203 of the driver circuit, a conductive layer having a second taper shape functions as the gate electrode 223, and the island-shaped semiconductor layer 107 has a channel formation region 212, a source region, or a drain region. A first impurity region 213a that functions, a second impurity region (A) 213b that forms an LDD region that does not overlap with the gate electrode 223, and a second impurity region that forms an LDD region that partially overlaps the gate electrode 223 (B ) 213c. Similar to the second n-channel TFT 201, the length of the portion where the second impurity region (B) 213 c overlaps with the gate electrode 223 is 0.1 to 0.3 μm.

  The drive circuit is formed by a logic circuit such as a shift register circuit or a buffer circuit, a sampling circuit formed by an analog switch, or the like. In FIG. 9B, the TFT for forming these is shown as a single gate structure in which one gate electrode is provided between a pair of sources and drains, but a multi-gate in which a plurality of gate electrodes are provided between a pair of sources and drains. A gate structure is also acceptable.

  In the pixel TFT 204, a conductive layer having a second taper shape functions as the gate electrode 224, and the first impurity functions as the channel formation regions 214 a and 214 b and the source region or the drain region in the island-shaped semiconductor layer 108. Regions 215a and 217; a second impurity region (A) 215b that forms an LDD region that does not overlap with the gate electrode 224; and a second impurity region (B) 215c that forms an LDD region that partially overlaps the gate electrode 224. It has a structure. The length of the portion where the second impurity region (B) 215 c overlaps with the gate electrode 224 is 0.1 to 0.3 μm. In addition, the semiconductor includes a second impurity region (A) 219b, a second impurity region (B) 219c, and a region 218 to which an impurity element that determines a conductivity type is not added, which extends from the first impurity region 217. A storage capacitor is formed from a layer, an insulating layer formed in the same layer as the gate insulating film having a third shape, and a capacitor wiring 225 formed from a conductive layer having a second tapered shape.

  FIG. 15 is a top view showing almost one pixel in the pixel portion. A cross section AA ′ shown in the drawing corresponds to the cross sectional view of the pixel portion shown in FIG. In the pixel TFT 204, the gate electrode 224 intersects the island-like semiconductor layer 108 through a gate insulating film (not shown), and further extends over a plurality of island-like semiconductor layers to serve as a gate wiring. . Although not shown, the island region, the drain region, and the LDD region described in FIG. 9B are formed in the island-shaped semiconductor layer. Reference numeral 230 denotes a contact portion between the source wiring 164 and the source region 215a, and reference numeral 231 denotes a contact portion between the pixel electrode 169 and the drain region 217. The storage capacitor 205 is formed in a region where the capacitor wiring 225 overlaps with the semiconductor layer extending from the drain region 217 of the pixel TFT 204 and the gate insulating film. In this structure, no impurity element for the purpose of valence electron control is added to the semiconductor layer 218.

  The configuration as described above makes it possible to optimize the structure of the TFT constituting each circuit according to the specifications required by the pixel TFT and the drive circuit, and to improve the operation performance and reliability of the semiconductor device. Furthermore, activation of the LDD region, the source region, and the drain region is facilitated by forming the gate electrode with a heat-resistant conductive material. Further, when forming the LDD region overlapping the gate electrode through the gate insulating film, the impurity element added for the purpose of controlling the conductivity type is provided with a concentration gradient to form the LDD region, particularly in the vicinity of the drain region. It can be expected that the electric field relaxation effect will increase.

  In the case of an active matrix liquid crystal display device, the first p-channel TFT 200 and the first n-channel TFT 201 are used to form a shift register circuit, a buffer circuit, a level shifter circuit, etc. that place importance on high-speed operation. In FIG. 9B, these circuits are represented as logic circuit portions. The second impurity region (B) 209c of the first n-channel TFT 201 has a structure that emphasizes measures against hot carriers. Further, in order to increase the withstand voltage and stabilize the operation, as shown in FIG. 13A, the TFT of this logic circuit portion may be formed by the first p-channel TFT 280 and the first n-channel TFT 281. good. This TFT has a double gate structure in which two gate electrodes are provided between a pair of source and drain, and such a TFT can be similarly manufactured using the process of this embodiment. The first p-channel TFT 280 includes channel-forming regions 236a and 236b in the island-shaped semiconductor layer, third impurity regions 238a, 239a, and 240a that function as source or drain regions, and a fourth impurity region that serves as an LDD region ( A) The structure has fourth impurity regions (B) 238c, 239c, and 240c that partially overlap with 238b, 239b, and 240b and the gate electrode 237 to be LDD regions. In the first n-channel TFT 281, channel formation regions 241 a and 241 b in the island-shaped semiconductor layer, first impurity regions 243 a, 244 a, and 245 a functioning as a source or drain region and a second impurity region that becomes an LDD region ( A) Second impurity regions (B) 243c, 244c, and 245c that partially overlap with 243b, 244b, and 245b and the gate electrode 242 and become LDD regions are provided. The channel length is 3 to 7 μm, and the length of the LDD region overlapping the gate electrode in the channel length direction is 0.1 to 0.3 μm.

  In addition, a second p-channel TFT 202 and a second n-channel TFT 203 having a similar structure can be applied to a sampling circuit including analog switches. Since the sampling circuit emphasizes countermeasures against hot carriers and low off-current operation, the TFT of this circuit is formed by a second p-channel TFT 282 and a second n-channel TFT 283 as shown in FIG. Also good. The second p-channel TFT 282 has a triple gate structure in which three gate electrodes are provided between a pair of source and drain, and such a TFT can be similarly manufactured using the process of this embodiment. The second p-channel TFT 282 includes third impurity regions 249 a, 250 a, 251 a, 252 a, which function as source or drain regions in the island-shaped semiconductor layer, and fourth LDD regions that function as source or drain regions. The structure has fourth impurity regions (B) 249c, 250c, 251c, and 252c that partially overlap with the impurity regions (A) 249b, 250b, 251b, and 252b and the gate electrode 247 to be LDD regions. The second n-channel TFT 283 includes channel formation regions 253a and 253b in the island-shaped semiconductor layer, first impurity regions 245a, 244a and 243a which function as source or drain regions, and a second impurity region which becomes an LDD region ( A) Second impurity regions (B) 245c, 244c, and 243c that partially overlap with 245b, 244b, and 243b and the gate electrode 254 and become LD regions are provided. The channel length is 3 to 7 μm, and the length of the LDD region overlapping the gate electrode in the channel length direction is 0.1 to 0.3 μm.

  The practitioner can select whether the structure of the TFT gate electrode is a single gate structure or a multi-gate structure in which a plurality of gate electrodes are provided between a pair of source and drain according to the characteristics of the circuit. . A reflective liquid crystal display device can be manufactured by using the active matrix substrate completed in this embodiment.

[Example 7]
In Example 6, an example in which a heat-resistant conductive material such as W or Ta is used as the material of the gate electrode is shown. The reason for using such a material is that it is necessary to activate the impurity element added to the semiconductor layer for the purpose of controlling the conductivity type after forming the gate electrode by thermal annealing at 400 to 700 ° C. This is because the gate electrode needs to have heat resistance. However, such a heat-resistant conductive material has a sheet resistance of about 10Ω, and is not necessarily suitable for a display device having a screen size of 4 inches class or more. When the gate line connected to the gate electrode is formed of the same material, the routing length on the substrate inevitably increases, and the problem of wiring delay due to the influence of wiring resistance cannot be ignored.

  For example, when the pixel density is VGA, 480 gate wirings and 640 source lines are formed, and in the case of XGA, 768 gate wirings and 1024 source wirings are formed. The screen size of the display area is 340 mm for the 13-inch class and 460 mm for the 18-inch class. In this embodiment, as a means for realizing such a liquid crystal display device, a method of forming a gate wiring with a low-resistance conductive material such as Al or copper (Cu) will be described with reference to FIG.

  First, the steps shown in FIGS. 7A to 8C are performed in the same manner as in the sixth embodiment. Then, for the purpose of controlling the conductivity type, a step of activating the impurity element added to each island-like semiconductor layer is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 1 ppm or less, preferably 0.1 ppm or less in a nitrogen atmosphere at 400 to 700 ° C., typically 500 to 600 ° C. In this example, the temperature is 500 ° C. for 4 hours. Heat treatment is performed.

  In this heat treatment, conductive layers (C) 172a to 172f are formed with a thickness of 5 to 80 nm from the surface of the conductive layers 140 to 145 having the second tapered shape. For example, when the conductive layer having the second tapered shape is W, tungsten nitride is formed, and when it is Ta, tantalum nitride is formed. Further, a heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means for hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed (FIG. 10A).

  After activation and hydrogenation, gate lines 173 and 174 are formed of a low resistance conductive material. The low-resistance conductive material is mainly composed of Al or Cu, and the gate line is formed from a low-resistance conductive layer formed from such a material. For example, an Al film containing 0.1 to 2% by weight of Ti is formed on the entire surface as a low resistance conductive layer (not shown). The low resistance conductive layer is formed with a thickness of 200 to 400 nm (preferably 250 to 350 nm). Then, a predetermined resist pattern is formed and etched to form gate lines 173 and 174. At this time, a capacitor line 175 connected to a storage capacitor provided in the pixel portion is also formed using the same material. In the case where the low-resistance conductive layer is made of a material containing Al as a main component, the gate line can be formed while maintaining selective processability with the base by wet etching using a phosphoric acid-based etching solution. The first interlayer insulating film 176 is formed in the same manner as in Example 6 (FIG. 10B).

  Thereafter, a second interlayer insulating film 159 made of an organic insulating material, source lines 160 to 164, drain lines 165 to 168, and pixel electrodes 169 and 171 are formed in the same manner as in Example 6 to complete the active matrix substrate. I can do it. (FIG. 10C) FIGS. 11A and 11B are top views of this state, and the BB ′ cross section of FIG. 11A and the CC ′ cross section of FIG. 10 (C) corresponding to BB ′ and CC ′. 11A and 11B, the gate insulating film, the first interlayer insulating film, and the second interlayer insulating film are omitted, but the island-shaped semiconductor layers 104, 105, and 108 are not illustrated. Source lines 160, 161, 164, drain lines 165, 166, and a pixel electrode 169 are connected to the source and drain regions through contact holes. 11A and 11B show the DD ′ cross section of FIG. 11A and the EE ′ cross section of FIG. 11B, respectively. The gate line 173 is formed so as to overlap the gate electrode 220, and the gate line 174 is formed so as to overlap the gate electrode 225 and the outside of the island-like semiconductor layers 104 and 108, and the gate electrode and the low-resistance conductive layer are in contact without any contact hole And is electrically connected. Thus, by forming the gate line with a low-resistance conductive material, the wiring resistance can be sufficiently reduced. Therefore, the present invention can be applied to a display device having a pixel portion (screen size) of 4 inches class or more.

[Example 8]
The active matrix substrate manufactured in Embodiment 6 can be applied to a reflective display device as it is. On the other hand, in the case of a transmissive liquid crystal display device, a pixel electrode provided in each pixel of the pixel portion may be formed using a transparent electrode. In this embodiment, a method for manufacturing an active matrix substrate corresponding to a transmissive liquid crystal display device will be described with reference to FIGS.

  The active matrix substrate is manufactured in the same manner as in Example 6. In FIG. 14A, a conductive metal film is formed by sputtering or vacuum evaporation for the source wiring and the drain wiring. This structure will be described in detail with reference to FIG. 14B by taking the drain line 256 as an example. The Ti film 256a is formed with a thickness of 50 to 150 nm and is in contact with the semiconductor film forming the source or drain region of the island-like semiconductor layer. Form. Overlying the Ti film 256a, an Al film 256b is formed with a thickness of 300 to 400 nm, and a Ti film 256c or a titanium nitride (TiN) film is formed with a thickness of 100 to 200 nm to form a three-layer structure. Thereafter, a transparent conductive film is formed over the entire surface, and a pixel electrode 257 is formed by patterning processing and etching processing using a photomask. The pixel electrode 257 is formed on the second interlayer insulating film made of an organic resin material, and is provided with a portion overlapping with the drain line 256 of the pixel TFT 204 without using a contact hole to form an electrical connection.

  In FIG. 14C, a transparent conductive film is first formed over the second interlayer insulating film, and after patterning and etching are performed to form the pixel electrode 258, the drain line 259 is connected to the pixel electrode 258 and the contact hole. It is the example which formed the connection part without interposing. As shown in FIG. 14D, the drain line 259 is formed by forming a Ti film 259a with a thickness of 50 to 150 nm and forming a contact with the semiconductor film forming the source or drain region of the island-like semiconductor layer. An Al film 259b is formed over the film 259a so as to have a thickness of 300 to 400 nm. With this configuration, the pixel electrode 258 comes into contact only with the Ti film 259 a that forms the drain wiring 259. As a result, it is possible to reliably prevent the transparent conductive film material and Al from coming into direct contact and reacting.

As a material for the transparent conductive film, indium oxide (In ₂ O ₃ ), indium oxide tin oxide alloy (In ₂ O ₃ —SnO ₂ ; ITO), or the like is used by using a sputtering method, a vacuum evaporation method, or the like. I can do it. Etching treatment of such a material is performed with a hydrochloric acid based solution. However, in particular, since etching of ITO is likely to generate a residue, an indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO) may be used to improve etching processability. Since the indium zinc oxide alloy has excellent surface smoothness and thermal stability with respect to ITO, the Al film 256b is formed on the end face of the drain wiring 256 in the structure shown in FIGS. 21A and 21B. It is possible to prevent the electrode 257 from contacting and causing a corrosion reaction. Similarly, zinc oxide (ZnO) is also a suitable material, and zinc oxide (ZnO: Ga) to which gallium (Ga) is added in order to increase visible light transmittance and conductivity can be used.

  In Example 6, an active matrix substrate on which a reflective liquid crystal display device can be manufactured was manufactured with five photomasks. However, by adding one photomask (total of six), it is compatible with a transmissive liquid crystal display device. The completed active matrix substrate can be completed. Although this embodiment has been described as a process opposite to that in Embodiment 6, such a configuration can be applied to the active matrix substrate shown in Embodiment 7.

[Example 9]
In this embodiment, a process of manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 6 will be described. First, as shown in FIG. 16A, spacers made of columnar spacers are formed on the active matrix substrate in the state of FIG. 9B. The spacer may be provided by dispersing particles of several μm, but here, a method of forming a resin film on the entire surface of the substrate and then patterning it is adopted. Although there is no limitation on the material of such a spacer, for example, NN700 manufactured by JSR Co. is used, and after applying with a spinner, a predetermined pattern is formed by exposure and development processing. Further, it is cured by heating at 150 to 200 ° C. in a clean oven or the like. The spacers produced in this way can have different shapes depending on the conditions of exposure and development processing. Preferably, the spacers are columnar and have a flat top, so that the substrate on the opposite side is formed. When combined, the mechanical strength of the liquid crystal display panel can be ensured. The shape is not particularly limited, such as a conical shape or a pyramid shape. For example, when the shape is conical, specifically, the height is 1.2 to 5 μm, the average radius is 5 to 7 μm, the average radius and the bottom radius The ratio is 1 to 1.5. At this time, the taper angle of the side surface is ± 15 ° or less.

  The arrangement of the spacers may be arbitrarily determined. Preferably, as shown in FIG. 16A, in the pixel portion, a columnar spacer 406 is formed so as to overlap with the contact portion 231 of the pixel electrode 169 and cover the portion. Good. Since the flatness of the contact portion 231 is impaired and the liquid crystal is not well aligned in this portion, the columnar spacer 406 is formed in this manner by filling the contact portion 231 with the resin for the spacer, thereby allowing disclination and the like. Can be prevented. In addition, spacers 405a to 405e are also formed on the TFT of the driver circuit. This spacer may be formed over the entire surface of the driver circuit portion, or may be provided so as to cover the source line and the drain line as shown in FIG.

  Thereafter, an alignment film 407 is formed. Usually, a polyimide resin is used for the alignment film of the liquid crystal display element. After the alignment film was formed, rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. The region not rubbed in the rubbing direction from the end of the columnar spacer 406 provided in the pixel portion was set to 2 μm or less. In the rubbing process, generation of static electricity is often a problem, but the effect of protecting the TFT from static electricity can be obtained by the spacers 405a to 405e formed on the TFT of the drive circuit. Although not described in the drawings, the spacers 406 and 405a to 405e may be formed after the alignment film 407 is formed first.

  A light shielding film 402, a transparent conductive film 403, and an alignment film 404 are formed on the counter substrate 401 on the opposite side. The light shielding film 402 is formed of a Ti film, a Cr film, an Al film or the like with a thickness of 150 to 300 nm. Then, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are attached to each other with a sealant 408. A filler (not shown) is mixed in the zeal material 408, and two substrates are bonded to each other with a uniform interval by the filler and the spacers 406 and 405a to 405e. Thereafter, a liquid crystal material 409 is injected between both substrates. A known liquid crystal material may be used as the liquid crystal material. For example, in addition to the TN liquid crystal, a thresholdless antiferroelectric mixed liquid crystal exhibiting electro-optical response in which the transmittance continuously changes with respect to the electric field can be used. Some thresholdless antiferroelectric mixed liquid crystals exhibit V-shaped electro-optic response characteristics. Thus, the active matrix liquid crystal display device shown in FIG. 16B is completed.

  FIG. 17 is a top view of such an active matrix substrate, and is a top view showing the positional relationship between the pixel portion and the drive circuit portion, the spacer, and the sealing material. A scanning signal drive circuit 605 and an image signal drive circuit 606 are provided as drive circuits around the pixel portion 604 on the glass substrate 101 described in Embodiment 6. Further, a signal processing circuit 607 such as a CPU or a memory may be added. These drive circuits are connected to the external input / output terminal 602 by connection wiring 603. In the pixel portion 604, a gate wiring group 608 extending from the scanning signal driving circuit 605 and a source wiring group 609 extending from the image signal driving circuit 606 intersect to form a pixel, and each pixel has a pixel TFT 204. And a storage capacitor 205 are provided.

  In FIG. 16, columnar spacers 406 provided in the pixel portion may be provided for all pixels, but may be provided every several to several tens of pixels arranged in a matrix as shown in FIG. . That is, the ratio of the number of spacers to the total number of pixels constituting the pixel portion can be 20 to 100%. Further, the spacers 405a to 405e provided in the driver circuit portion may be provided so as to cover the entire surface, or may be provided in accordance with the positions of the source and drain wirings of each TFT. In FIG. 17, the arrangement of the spacers provided in the drive circuit portion is indicated by 610-612. 17 is outside the pixel portion 604 and the scanning signal driving circuit 605, the image signal driving circuit 606, and other signal processing circuits 607 on the substrate 101, and more than the external input / output terminal 602. Form inside.

  The structure of such an active matrix liquid crystal display device will be described with reference to the perspective view of FIG. In FIG. 18, the active matrix substrate includes a pixel portion 604, a scanning signal driving circuit 605, an image signal driving circuit 606, and other signal processing circuits 607 formed on the glass substrate 101. A pixel TFT 204 and a holding capacitor 205 are provided in the pixel portion 604, and a driver circuit provided around the pixel portion is configured based on a CMOS circuit. From the scan signal driver circuit 605 and the image signal driver circuit 606, a gate line (corresponding to 224 in FIG. 9B when formed continuously with the gate electrode) and a source line 164 are provided in the pixel portion 604, respectively. It extends and is connected to the pixel TFT 204. A flexible printed circuit (FPC) 613 is connected to an external input terminal 602 and used to input an image signal or the like. The FPC 613 is firmly bonded by the reinforcing resin 614. The connection distribution 603 is connected to each drive circuit. Further, the counter substrate 401 is provided with a light shielding film and a transparent electrode (not shown).

  The liquid crystal display device having such a configuration can be formed using the active matrix substrate shown in Examples 6 to 8. When the active matrix substrate shown in Embodiment 6 is used, a reflective liquid crystal display device can be obtained. When the active matrix substrate shown in Embodiment 8 is used, a transmissive liquid crystal display device can be obtained.

[Example 10]
FIG. 19 is an example of a circuit configuration of the active matrix substrate shown in Examples 6 to 8, and is a diagram illustrating a circuit configuration of a direct-view display device. This active matrix substrate has an image signal driving circuit 606, scanning signal driving circuits (A) and (B) 605, and a pixel portion 604. Note that the drive circuit described in this specification is a generic name including the image signal drive circuit 606 and the scanning signal drive circuit 605.

  The image signal driving circuit 606 includes a shift register circuit 501a, a level shifter circuit 502a, a buffer circuit 503a, and a sampling circuit 504. The scanning signal driver circuits (A) and (B) 605 include a shift register circuit 501b, a level shifter circuit 502b, and a buffer circuit 503b.

  The shift register circuits 501a and 501b have a driving voltage of 5 to 16 V (typically 10 V), and the TFT of the CMOS circuit forming this circuit is the same as the first p-channel TFT 200 of FIG. The n-channel TFT 201 is used. Alternatively, the first p-channel TFT 280 and the first n-channel TFT 281 shown in FIG. Further, since the level shifter circuits 502a and 502b and the buffer circuits 503a and 503b have a drive voltage as high as 14 to 16 V, it is desirable to have a multi-gate TFT structure as shown in FIG. Forming a TFT with a multi-gate structure increases the breakdown voltage, and is effective in improving the reliability of the circuit.

  The sampling circuit 504 is composed of an analog switch and has a drive voltage of 14 to 16 V. However, the sampling circuit 504 is driven by alternately inverting the polarity, and it is necessary to reduce the off-current value. It is desirable to form with two p-channel TFTs 202 and a second n-channel TFT 203. Alternatively, in order to effectively reduce the off-state current value, the second p-channel TFT 282 and the second n-channel TFT 283 shown in FIG. 13B may be used.

  In addition, the driving voltage of the pixel portion is 14 to 16 V, and it is required to further reduce the off-current value as compared with the sampling circuit from the viewpoint of low power consumption. As shown in FIG. Based on the gate structure.

  The configuration of this example can be easily realized by manufacturing a TFT according to the steps shown in Examples 6 to 8. In the present embodiment, only the configuration of the pixel portion and the drive circuit is shown, but if the steps of Embodiments 6 to 8 are followed, a signal dividing circuit, a frequency divider circuit, a D / A converter, a γ correction circuit, An operational amplifier circuit, a signal processing circuit such as a memory circuit or an arithmetic processing circuit, or a logic circuit can be formed over the same substrate. As described above, the present invention can realize a semiconductor device including a pixel portion and a driver circuit thereof on the same substrate, for example, a liquid crystal display device including a signal control circuit and the pixel portion.

[Example 11]
In this embodiment, a self-luminous display panel (hereinafter referred to as an EL display device) using an electroluminescence (EL) material by using the active matrix substrate shown in the above-described embodiment is shown. An example of manufacturing will be described. In this specification, an EL display device is a generic term for a display panel in which a light-emitting element formed on a substrate is sealed between the substrate and a cover material, and a display module in which an IC is mounted on the display panel. It is. Note that the light-emitting element includes a layer (light-emitting layer) containing an organic compound from which luminescence (Electro Luminescence) generated by applying an electric field is obtained, an anode layer, and a cathode layer. In addition, luminescence in an organic compound includes light emission (fluorescence) when returning from a singlet excited state to a ground state and light emission (phosphorescence) when returning from a triplet excited state to a ground state, one of these, Or both luminescence is included.

  FIG. 20A is a top view of an EL display panel using the present invention. In FIG. 20A, 10 is a substrate, 11 is a pixel portion, 12 is a source side driver circuit, 13 is a gate side driver circuit, and each driver circuit reaches the FPC 17 via wirings 14 to 16 to an external device. Connected.

  FIG. 20B is a diagram illustrating the FF ′ cross section of FIG. 20A. At this time, the counter plate 80 is provided at least on the pixel group, preferably on the driver circuit and the pixel group. The counter plate 80 is bonded to an active matrix substrate on which a TFT and an EL layer are formed with a sealing material 19. A filler (not shown) is mixed in the sealing material 19, and two substrates are bonded to each other with a substantially uniform interval. Furthermore, the outside of the sealing material 19 and the upper surface and the periphery of the FPC 17 are sealed with a sealing material 81. The sealing material 81 is made of a material such as silicon resin, epoxy resin, phenol resin, or butyl rubber.

  Thus, when the active matrix substrate 10 and the counter substrate 80 are bonded together by the sealing material 19, a space is formed between them. The space is filled with a filler 83. This filler 83 also has the effect of bonding the opposing plate 80. As the filler 83, PVC (polyvinyl chloride), epoxy resin, silicon resin, PVB (polyvinyl butyral), EVA (ethylene vinyl acetate), or the like can be used. In addition, since the EL layer is weak and easily deteriorated by moisture including moisture, it is desirable to mix a desiccant such as barium oxide in the filler 83 because the moisture absorption effect can be maintained. In addition, a passivation film 82 formed of a silicon nitride film, a silicon oxynitride film, or the like is formed over the EL layer to prevent corrosion due to an alkali element or the like contained in the filler 83.

  The counter plate 80 includes a glass plate, an aluminum plate, a stainless steel plate, a FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a Mylar film (trade name of DuPont), a polyester film, an acrylic film, an acrylic plate, etc. Can be used. Moreover, moisture resistance can also be improved using the sheet | seat of the structure which pinched | interposed several tens micrometer aluminum foil with the PVF film or the mylar film. In this way, the EL element is hermetically sealed from the outside air.

  In FIG. 20B, a driving circuit TFT (however, a CMOS circuit in which an n-channel TFT and a p-channel TFT are combined is illustrated) 22 and a pixel on the substrate 10 and the base film 21 are illustrated. The part TFT 23 (however, only the TFT for controlling the current to the EL element is shown here) is formed. Among these TFTs, in particular, n-channel TFTs are provided with an LDD region having the structure shown in this embodiment in order to prevent a decrease in on-current due to the hot carrier effect and a decrease in characteristics due to Vth shift and bias stress.

  For example, the driver circuit TFT 22 may be used as the p-channel TFTs 200 and 202 and the n-channel TFTs 201 and 203 shown in FIG. 9B. As the pixel portion TFT 23, a pixel TFT 204 shown in FIG. 9B or a p-channel TFT having a similar structure may be used.

  In order to manufacture an EL display device from the active matrix substrate in the state of FIG. 9B or FIG. 10B, an interlayer insulating film (planarization film) 26 made of a resin material is formed over the source line and the drain line, A pixel electrode 27 made of a transparent conductive film electrically connected to the drain of the pixel portion TFT 23 is formed thereon. As the transparent conductive film, a compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used. Then, after the pixel electrode 27 is formed, an insulating film 28 is formed, and an opening is formed on the pixel electrode 27.

  Next, the EL layer 29 is formed. The EL layer 29 may have a laminated structure or a single layer structure by freely combining known EL materials (a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, or an electron injection layer). A known technique may be used to determine the structure. EL materials include low-molecular materials and high-molecular (polymer) materials. When a low molecular material is used, a vapor deposition method is used. When a high molecular material is used, a simple method such as a spin coating method, a printing method, or an ink jet method can be used.

  The EL layer is formed by a vapor deposition method, an inkjet method, a dispenser method, or the like using a shadow mask. In any case, color display is possible by forming light emitting layers (red light emitting layer, green light emitting layer, and blue light emitting layer) capable of emitting light having different wavelengths for each pixel. In addition, there are a method in which a color conversion layer (CCM) and a color filter are combined, and a method in which a white light emitting layer and a color filter are combined, but either method may be used. Of course, an EL display device emitting monochromatic light can also be used.

  After the EL layer 29 is formed, the cathode 30 is formed thereon. It is desirable to remove moisture and oxygen present at the interface between the cathode 30 and the EL layer 29 as much as possible. Therefore, it is necessary to devise such that the EL layer 29 and the cathode 30 are continuously formed in a vacuum, or the EL layer 29 is formed in an inert atmosphere and the cathode 30 is formed in a vacuum without being released to the atmosphere. In this embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus.

  In this embodiment, a laminated structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used as the cathode 30. Specifically, an LiF (lithium fluoride) film having a thickness of 1 nm is formed on the EL layer 29 by vapor deposition, and an aluminum film having a thickness of 300 nm is formed thereon. Of course, you may use the MgAg electrode which is a well-known cathode material. The cathode 30 is connected to the wiring 16 in a region indicated by 31. The wiring 16 is a power supply line for applying a predetermined voltage to the cathode 30, and is connected to the FPC 17 through an anisotropic conductive paste material 32. A resin layer 80 is further formed on the FPC 17 to increase the adhesive strength of this portion.

  In order to electrically connect the cathode 30 and the wiring 16 in the region indicated by 31, it is necessary to form contact holes in the interlayer insulating film 26 and the insulating film 28. These may be formed when the interlayer insulating film 26 is etched (when the pixel electrode contact hole is formed) or when the insulating film 28 is etched (when the opening before the EL layer is formed). Further, when the insulating film 28 is etched, the interlayer insulating film 26 may be etched all at once. In this case, if the interlayer insulating film 26 and the insulating film 28 are the same resin material, the shape of the contact hole can be improved.

  The wiring 16 is electrically connected to the FPC 17 through a gap (but sealed with a sealing material 81) between the sealil 19 and the substrate 10. Although the wiring 16 has been described here, the other wirings 14 and 15 are also electrically connected to the FPC 17 under the sealing material 81 in the same manner.

  Here, a more detailed cross-sectional structure of the pixel portion is shown in FIG. 21, a top structure is shown in FIG. 22A, and a circuit diagram is shown in FIG. 22B. In FIG. 21A, a switching TFT 2402 provided over a substrate 2401 is formed with the same structure as the pixel TFT 204 of FIG. The double gate structure has a structure in which two TFTs are substantially connected in series, and there is an advantage that the off-current value can be reduced. In this embodiment, a double gate structure is used, but a triple gate structure or a multi-gate structure having more gates may be used.

  Further, the current control TFT 2403 is formed using the n-channel TFT 201 shown in FIG. At this time, the drain line 35 of the switching TFT 2402 is electrically connected to the gate electrode 37 of the current control TFT by the wiring 36. A wiring indicated by 38 is a gate line for electrically connecting the gate electrodes 39a and 39b of the switching TFT 2402.

  At this time, it is very important that the current control TFT 2403 has the structure of the present invention. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows, and it is also an element with a high risk of deterioration due to heat or hot carriers. Therefore, by providing the current control TFT with an LDD region that partially overlaps the gate electrode, the TFT can be prevented from being deteriorated and the operation stability can be improved.

  In this embodiment, the current control TFT 2403 is illustrated with a single gate structure, but a multi-gate structure in which a plurality of TFTs are connected in series may be used. Further, a structure may be employed in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of portions so that heat can be emitted with high efficiency. Such a structure is effective as a countermeasure against deterioration due to heat.

  Further, as shown in FIG. 22A, the wiring that becomes the gate electrode 37 of the current control TFT 2403 overlaps with the drain line 40 of the current control TFT 2403 through an insulating film in a region indicated by 2404. At this time, a capacitor is formed in a region indicated by 2404. This capacitor 2404 functions as a capacitor for holding the voltage applied to the gate of the current control TFT 2403. The drain line 40 is connected to a current supply line (power supply line) 2501, and a constant voltage is always applied.

  A first passivation film 41 is provided on the switching TFT 2402 and the current control TFT 2403, and a planarizing film 42 made of a resin insulating film is formed thereon. It is very important to flatten the step due to the TFT using the flattening film 42. Since an EL layer to be formed later is very thin, a light emission defect may occur due to the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming it so that the EL layer can be formed as flat as possible.

  Reference numeral 43 denotes a pixel electrode (EL element cathode) made of a highly reflective conductive film, which is electrically connected to the drain of the current control TFT 2403. As the pixel electrode 43, it is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a laminated film thereof. Of course, a laminated structure with another conductive film may be used. Further, the light emitting layer 44 is formed in a groove (corresponding to a pixel) formed by banks 44a and 44b formed of an insulating film (preferably resin). Although only one pixel is shown here, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) may be formed separately. A π-conjugated polymer material is used as the organic EL material for the light emitting layer. Typical polymer materials include polyparaphenylene vinylene (PPV), polyvinyl carbazole (PVK), and polyfluorene. There are various types of PPV organic EL materials such as “H. Shenk, H. Becker, O. Gelsen, E. Kluge, W. Kreuder, and H. Spreitzer,“ Polymers for Light Emitting ”. Materials such as those described in “Diodes”, Euro Display, Proceedings, 1999, p. 33-37 ”and Japanese Patent Laid-Open No. 10-92576 may be used.

  As a specific light emitting layer, cyanopolyphenylene vinylene may be used for a light emitting layer that emits red light, polyphenylene vinylene may be used for a light emitting layer that emits green light, and polyphenylene vinylene or polyalkylphenylene may be used for a light emitting layer that emits blue light. The film thickness may be 30 to 150 nm (preferably 40 to 100 nm). However, the above example is an example of an organic EL material that can be used as a light emitting layer, and it is not absolutely necessary to limit to this. An EL layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light-emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, an example in which a polymer material is used as the light emitting layer is shown, but a low molecular weight organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer or the charge injection layer. As these organic EL materials and inorganic materials, known materials can be used.

  In this embodiment, the EL layer has a laminated structure in which a hole injection layer 46 made of PEDOT (polythiophene) or PAni (polyaniline) is provided on the light emitting layer 45. An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of the present embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (upward of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used, but it is possible to form after forming a light-emitting layer or hole injection layer with low heat resistance. A film that can be formed at a low temperature is preferable.

  When the anode 47 is formed, the EL element 2405 is completed. Here, the EL element 2405 refers to a diode formed by the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 46, and the anode 47. As shown in FIG. 22A, since the pixel electrode 43 substantially matches the area of the pixel, the entire pixel functions as an EL element. Therefore, the use efficiency of light emission is very high, and a bright image display is possible.

  By the way, in the present embodiment, a second passivation film 48 is further provided on the anode 47. The second passivation film 48 is preferably a silicon nitride film or a silicon nitride oxide film. This purpose is to cut off the EL element from the outside, and has both the meaning of preventing deterioration due to oxidation of the organic EL material and the meaning of suppressing degassing from the organic EL material. This increases the reliability of the EL display device.

  As described above, the EL display panel according to the present invention has a pixel portion composed of pixels having a structure as shown in FIG. 22, and includes a switching TFT having a sufficiently low off-current value and a current control TFT resistant to hot carrier injection. Have. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.

  FIG. 21B shows an example in which the structure of the EL layer is inverted. The current control TFT 2601 is formed using the p-channel TFT 200 of FIG. Refer to Example 7 for the manufacturing process. In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film made of a compound of indium oxide and zinc oxide is used. Of course, a conductive film made of a compound of indium oxide and tin oxide may be used.

  Then, after banks 51a and 51b made of insulating films are formed, a light emitting layer 52 made of polyvinylcarbazole is formed by solution coating. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode 54 made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, the EL element 2602 is formed. In the case of the present embodiment, the light generated in the light emitting layer 53 is emitted toward the substrate on which the TFT is formed as indicated by an arrow. In the case of the structure as in this embodiment, the current control TFT 2601 is preferably a p-channel TFT.

  The configuration of this embodiment can be implemented by freely combining the configurations of the TFTs of Embodiments 6 to 8. Further, it is effective to use the EL display panel of this embodiment as the display unit of the electronic apparatus of Embodiment 13.

[Example 12]
In this embodiment, an example in which the pixel has a structure different from the circuit diagram illustrated in FIG. 22B is illustrated in FIG. In this embodiment, 2701 is a source wiring of the switching TFT 2702, 2703 is a gate wiring of the switching TFT 2702, 2704 is a current control TFT, 2705 is a capacitor, 2706 and 2708 are current supply lines, and 2707 is an EL element. .

  FIG. 23A shows an example in which the current supply line 2706 is shared between two pixels. In other words, the two pixels are formed so as to be symmetrical about the current supply line 2706. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined.

  FIG. 23B illustrates an example in which the current supply line 2708 is provided in parallel with the gate wiring 2703. In FIG. 23B, the current supply line 2708 and the gate wiring 2703 are provided so as not to overlap with each other. However, if the wirings are formed in different layers, they overlap with each other through an insulating film. It can also be provided. In this case, the exclusive area can be shared by the power supply line 2708 and the gate wiring 2703, so that the pixel portion can be further refined.

  In FIG. 23C, a current supply line 2708 is provided in parallel with the gate wiring 2703 as in the structure of FIG. 23B, and two pixels are symmetrical with respect to the current supply line 2708. It is characterized in that it is formed. It is also effective to provide the current supply line 2708 so as to overlap any one of the gate wirings 2703. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined. In FIGS. 23A and 23B, a capacitor 2404 is provided in order to hold a voltage applied to the gate of the current control TFT 2403; however, the capacitor 2404 can be omitted.

  Since the n-channel TFT of the present invention as shown in FIG. 21A is used as the current control TFT 2403, it has an LDD region provided so as to overlap with the gate electrode through the gate insulating film. In this overlapping region, a parasitic capacitance generally called a gate capacitance is formed, but this embodiment is characterized in that this parasitic capacitance is actively used in place of the capacitor 2404. The capacitance of this parasitic capacitance 23 is determined by the length of the LDD region included in the overlapped region because the gate electrode and the LDD region change in the overlapped area, and the structure shown in FIGS. Similarly, the capacitor 2705 can be omitted.

  The configuration of this embodiment can be implemented by freely combining the configurations of the TFTs of Embodiments 6 to 8. Further, it is effective to use the EL display panel of this embodiment as the display unit of the electronic apparatus of Embodiment 13.

[Example 13]
The CMOS circuit and the pixel portion formed by implementing the present invention can be used in various electro-optical devices (active matrix liquid crystal display, active matrix EC display). That is, the present invention can be applied to all electronic devices in which these electro-optical devices are incorporated in the display unit.

  Such electronic devices include video cameras, digital cameras, projectors (rear type or front type), head mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones) Or an electronic book). Examples of these are shown in FIGS. 24, 25 and 26. FIG.

  FIG. 24A shows a personal computer, which includes a main body 3001, an image input portion 3002, a display portion 3003, a keyboard 3004, and the like. The present invention can be applied to the image input unit 3002, the display unit 3003, and other signal control circuits.

  FIG. 24B illustrates a video camera, which includes a main body 3101, a display portion 3102, an audio input portion 3103, operation switches 3104, a battery 3105, an image receiving portion 3106, and the like. The present invention can be applied to the display portion 3102 and other signal control circuits.

  FIG. 24C illustrates a mobile computer, which includes a main body 3201, a camera portion 3202, an image receiving portion 3203, operation switches 3204, a display portion 3205, and the like. The present invention can be applied to the display portion 3205 and other signal control circuits.

  FIG. 24D illustrates a goggle type display including a main body 3301, a display portion 3302, an arm portion 3303, and the like. The present invention can be applied to the display portion 3302 and other signal control circuits.

  FIG. 24E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 3401, a display portion 3402, a speaker portion 3403, a recording medium 3404, an operation switch 3405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 3402 and other signal control circuits.

  FIG. 24F illustrates a digital camera, which includes a main body 3501, a display portion 3502, an eyepiece portion 3503, an operation switch 3504, an image receiving portion (not shown), and the like. The present invention can be applied to the display portion 3502 and other signal control circuits.

  FIG. 25A shows a front type projector, which includes a projection device 3601, a screen 3602, and the like. The present invention can be applied to a liquid crystal display device 3808 constituting a part of the projection device 3601 and other signal control circuits.

  FIG. 25B shows a rear projector, which includes a main body 3701, a projection device 3702, a mirror 3703, a screen 3704, and the like. The present invention can be applied to the liquid crystal display device 3808 constituting a part of the projection device 3702 and other signal control circuits.

  Note that FIG. 25C illustrates an example of the structure of the projection devices 3601 and 3702 in FIGS. 25A and 25B. The projection devices 3601 and 3702 include a light source optical system 3801, mirrors 3802 and 3804 to 3806, a dichroic mirror 3803, a prism 3807, a liquid crystal display device 3808, a phase difference plate 3809, and a projection optical system 3810. The projection optical system 3810 is composed of an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.

  FIG. 25D illustrates an example of the structure of the light source optical system 3801 in FIG. In this embodiment, the light source optical system 3801 includes a reflector 3811, a light source 3812, lens arrays 3813 and 3814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system illustrated in FIG. 25D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.

  However, the projector shown in FIG. 25 shows a case where a transmissive electro-optical device is used, and an application example in a reflective electro-optical device is not shown.

  FIG. 26A shows a cellular phone, which includes a main body 3901, an audio output portion 3902, an audio input portion 3903, a display portion 3904, operation switches 3905, an antenna 3906, and the like. The present invention can be applied to the audio output unit 3902, the audio input unit 3903, the display unit 3904, and other signal control circuits.

  FIG. 26B illustrates a portable book (electronic book) including a main body 4001, display portions 4002 and 4003, a storage medium 4004, operation switches 4005, an antenna 4006, and the like. The present invention can be applied to the display portions 4002 and 4003 and other signal circuits.

  FIG. 26C shows a display, which includes a main body 4101, a support base 4102, a display portion 4103, and the like. The present invention can be applied to the display portion 4103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-8.

Effect of the invention

By adopting the configuration of the present invention, the following basic significance can be obtained.
(A) Even if the amorphous semiconductor film has a region irradiated while moving the linear beam over a plurality of times, a crystalline semiconductor film with good crystallinity can be obtained. However, the shape of the laser beam at or near the irradiation surface is not limited to a linear shape, and may be a rectangular shape.
(B) When laser annealing is performed on a large-area substrate, it is particularly effective because it is not necessary to expand the length of the linear beam in accordance with the size of the large-area substrate.
(C) When a TFT is manufactured using the crystalline semiconductor film, the TFT has good electrical characteristics and has characteristics with little variation.

  The figure which shows the optical system which forms the conventional linear beam.   The figure which shows the example of the pitch of the superimposition of the linear beam at the time of irradiating 2 pulses of a linear beam.   The figure which shows the absorption coefficient of the amorphous silicon film and a polycrystalline silicon film with respect to a wavelength.   The figure which shows the example of the method of irradiating a linear beam to a large area board | substrate.   The figure which shows the example which introduced the beam expander to the structure of FIG.   The figure which shows the optical system which forms a linear beam.   Sectional drawing which shows the manufacturing process of TFT of a pixel TFT and a driver circuit.   Sectional drawing which shows the manufacturing process of TFT of a pixel TFT and a driver circuit.   Sectional drawing which shows the manufacturing process of TFT of a pixel TFT and a driver circuit.   Sectional drawing which shows the manufacturing process of TFT of a pixel TFT and a driver circuit.   Sectional drawing which shows the structure of TFT and pixel TFT of a drive circuit.   Sectional drawing which shows the structure of TFT of a drive circuit.   The top view which shows the structure of TFT and pixel TFT of a drive circuit.   Sectional drawing which shows the structure of pixel TFT.   FIG. 6 is a top view illustrating a pixel in a pixel portion.   Sectional drawing which shows the manufacturing process of an active-matrix liquid crystal display device.   FIG. 7 is a top view illustrating input / output terminals, wiring, circuit arrangement, spacers, and sealing material arrangement of a liquid crystal display device.   The perspective view which shows the structure of a liquid crystal display device.   FIG. 11 is a block diagram illustrating a circuit structure of an active matrix display device.   4A and 4B are a top view and a cross-sectional view illustrating a structure of an EL display device.   FIG. 6 is a cross-sectional view of a pixel portion of an EL display device.   FIG. 6 is a top view and a circuit diagram of a pixel portion of an EL display device.   7 is an example of a circuit diagram of a pixel portion of an EL display device.   FIG. 11 illustrates an example of a semiconductor device.   FIG. 11 illustrates an example of a semiconductor device.   FIG. 11 illustrates an example of a semiconductor device.   The figure which shows the example of the method of irradiating a linear beam to a large area board | substrate.

Claims (8)

A first step of forming a first crystalline silicon film partially crystallize the amorphous silicon film by heat treatment in an atmosphere which is heated substrate amorphous silicon film is formed ,
A second step of forming a second crystalline silicon film by irradiating the first crystalline silicon film with a laser beam,
The second step includes
Forming a first crystalline region by irradiating the first crystalline silicon film while moving the laser beam relatively;
Irradiating the first crystalline silicon film on which the first crystalline region is formed to a region including a part of the first crystalline region while moving the laser beam relatively. A second crystalline region is formed by,
The laser beam is one or a plurality of types selected from an Ar laser, a second harmonic of a YAG laser, a second harmonic of a YVO ₄ laser, and a second harmonic of a YLF laser. Manufacturing method.
A first step of forming a first crystalline silicon film partially crystallize the amorphous silicon film by heat treatment in an atmosphere which is heated substrate amorphous silicon film is formed ,
A second step of forming a second crystalline silicon film by irradiating the first crystalline silicon film with a laser beam having a linear or rectangular shape at or near the irradiation surface;
The second step includes
Forming a first crystalline region by irradiating the first crystalline silicon film while moving the laser beam relatively;
Irradiating the first crystalline silicon film on which the first crystalline region is formed to a region including a part of the first crystalline region while moving the laser beam relatively. A second crystalline region is formed by,
The laser beam is one or a plurality of types selected from an Ar laser, a second harmonic of a YAG laser, a second harmonic of a YVO ₄ laser, and a second harmonic of a YLF laser. Manufacturing method.
A first step of forming a first crystalline silicon film partially crystallize the amorphous silicon film by heat treatment in an atmosphere which is heated substrate amorphous silicon film is formed ,
A second crystal is irradiated by irradiating the first crystalline silicon film with a laser beam having a linear or rectangular shape at or near the irradiation surface while moving relatively in the short direction of the laser beam. A second step of forming a porous silicon film,
The second step includes
Irradiating the first crystalline silicon film while moving the laser beam relatively in the short direction of the laser beam to form a first crystalline region;
Relative to the first crystalline silicon film in which the first crystalline region is formed, the laser beam is relative to a region including a part of the first crystalline region in a short direction of the laser beam. A second crystalline region is formed by irradiating while moving
The laser beam is one or a plurality of types selected from an Ar laser, a second harmonic of a YAG laser, a second harmonic of a YVO ₄ laser, and a second harmonic of a YLF laser. Manufacturing method.
In any one of Claims 1 thru | or 3,
A method for manufacturing a semiconductor device, wherein an element that promotes crystallization is added to the amorphous silicon film before the first step.
In claim 4,
The element is added by applying the element as a solution to the amorphous silicon film.
In claim 4 or claim 5,
A method for manufacturing a semiconductor device, wherein the element is nickel.
In any one of Claims 1 thru | or 6,
The grain size of the first crystalline region, the grain size of the second crystalline region, and the grain size of the region where the first crystalline region and the second crystalline region overlap are the same. There is provided a method for manufacturing a semiconductor device.
In any one of Claims 1 thru | or 7,
The method for manufacturing a semiconductor device is characterized in that the heat treatment is performed in a nitrogen atmosphere at a temperature of 500 ° C. for 1 hour and in a nitrogen atmosphere at a temperature of 550 ° C. for 4 hours.

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