JP2000349299A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a semiconductor device to be improved in operating characteristics and reliability and lessened in power consumption, by a method wherein an offset region is formed between the channel forming region of an N-channel TFT of a pixel section and the LDD region of an N-channel TFT of a pixel section. SOLUTION: Channel forming regions 115 and 125, source or drain regions 121 to 123, and LDD(low concentration drain) regions 117 to 120 are provided to the active layer of an N-channel TFT(thin film transistor)149 of a pixel section. An offset region is provided between the LDD regions 117 to 120 and the channel forming regions 115 and 125, and the regions are provided so as not to overlap with a gate electrode by the offset region. Impurities which turn the LDD regions 117 to 120 into N-type are set at 1×1016 to 5×1018 atoms/cm3 in concentration, and the LDD regions 117 to 120 are 1/2 to 1/10 as high in impurity concentration as the LDD regions 111 and 112 of an N-channel TFT 148 of a drive circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit formed of thin film transistors (hereinafter, referred to as TFTs) on a substrate having an insulating surface, and a method for manufacturing the same. In particular, the present invention is suitable for an electro-optical device typified by a liquid crystal display device in which a pixel portion (or a pixel matrix circuit) and a driver circuit provided therearound are provided over the same substrate, and an electronic device equipped with the electro-optical device. Available to
In this specification, a semiconductor device generally refers to a device that functions by utilizing semiconductor characteristics, and includes the above-described electro-optical device and an electronic device including the electro-optical device in its category.

[0002]

2. Description of the Related Art Development of a semiconductor device having a circuit formed by a TFT on a substrate having an insulating surface is in progress. An active matrix liquid crystal display device is well known as a typical example. Among them, a TFT having an active layer formed of a crystalline silicon film (hereinafter, referred to as a crystalline silicon TFT) has a high field-effect mobility, so that various functional circuits can be formed. The electro-optical device integrally formed thereon has been developed.

For example, a drive circuit integrated type active matrix liquid crystal display device is provided with a pixel portion for displaying an image, a drive circuit for performing an image display, and the like. The drive circuit includes a shift register circuit, a level shifter circuit, a buffer circuit, a sampling circuit, and the like which are formed based on a CMOS circuit. Such a circuit is provided over the same substrate.

When viewed individually, the operating conditions of these circuits are not always the same, and the characteristics required for the TFTs are not less different. For example, the pixel portion has a configuration in which a pixel TFT composed of an n-channel TFT and a storage capacitor are provided, and the pixel TFT is driven by applying a voltage to a liquid crystal as a switching element. Since the liquid crystal is driven by alternating current, a method called frame inversion drive is often used. In this method, in order to keep power consumption low, a characteristic required of the pixel TFT is to sufficiently reduce an off-current value (a drain current flowing when the TFT is turned off). On the other hand, since a high driving voltage is applied to the buffer circuit of the driving circuit, it is necessary to increase the breakdown voltage so that the buffer circuit is not broken even when the high voltage is applied. Further, in order to increase the current driving capability, it is necessary to sufficiently secure an on-current value (a drain current flowing when the TFT is turned on).

However, there is a problem that the off-current value of the crystalline silicon TFT tends to be high. Also, I
As with the MOS transistor used for C and the like, a deterioration phenomenon such as a decrease in the on-current value is observed in the crystalline silicon TFT. The main cause is hot carrier injection, and it is considered that hot carriers generated by a high electric field near the drain cause a deterioration phenomenon.

As a structure of a TFT for reducing an off-current value, a lightly doped drain (LDD) is used.
ain) The structure is known. In this structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source or drain region formed by adding an impurity element at a high concentration. This region is referred to as an LDD region. Calling.

As means for preventing deterioration due to hot carriers, a so-called GOLD in which an LDD region is arranged so as to overlap a gate electrode with a gate insulating film interposed therebetween.
(Gate-drain Overlapped LDD) structure is known. With such a structure, a high electric field in the vicinity of the drain is relaxed to prevent hot carrier injection, which is effective in preventing a deterioration phenomenon. For example, "Mutuko Hatano, Hajime
Akimoto and TakeshiSakai, IEDM97 TECHNICAL DI
GEST, p523-526, 1997, discloses a GOLD structure formed by sidewalls formed of silicon, but it has been confirmed that extremely superior reliability can be obtained as compared with TFTs of other structures. .

[0008]

However, the required characteristics of the pixel TFT in the pixel portion and the TFT of a driving circuit such as a shift register circuit and a buffer circuit are not necessarily the same. For example, a large reverse bias (negative voltage for an n-channel TFT) is applied to the gate of the pixel TFT, but the TFT of the driving circuit does not basically operate in the reverse bias state. Regarding the operation speed, the pixel TFT is 1/100 of the TFT of the driving circuit.
The following is good.

Although the GOLD structure has a high effect of preventing the deterioration of the ON current value, it has a problem that the OFF current value becomes larger than that of the normal LDD structure. Therefore, it was not a preferable structure to be applied to the pixel TFT. Conversely, the ordinary LDD structure has a high effect of suppressing the off-current value, but has a low effect of relaxing the electric field near the drain to prevent deterioration due to hot carrier injection. As described above, in a semiconductor device having a plurality of integrated circuits having different operating conditions, such as an active matrix liquid crystal display device, it is not always preferable to form all the TFTs with the same structure. Such problems have become more apparent as the characteristics of crystalline silicon TFTs have increased, and the performance required for active matrix type liquid crystal display devices has increased.

The present invention is a technique for solving such a problem, and includes a TFT arranged in each circuit of a semiconductor device.
By improving the structure of the device according to the function of the circuit, the operating characteristics and reliability of the semiconductor device are improved,
In addition, an object is to reduce power consumption.

[0011]

FIG. 11 is a view for explaining the structure of the present invention. In FIG. 11, a channel forming region of an active layer, an LDD region, a gate insulating film on the active layer, and a gate insulating film on the active layer are formed. In the TFT having the gate electrode described above, the positional relationship between the gate electrode and the LDD region is described.

FIG. 11A shows an active layer having a channel forming region 501, an LDD region 502, and a drain region 503, and a structure in which a gate insulating film 504 and a gate electrode 505 are provided on the active layer. . The LDD region 502 has a gate electrode 505 through a gate insulating film 504.
And are provided so as to overlap. Such an LDD region is referred to herein as Lov. Lov has a function of relaxing a high electric field generated near the drain, can prevent deterioration due to hot carriers, and is suitable for use in an n-channel TFT such as a shift register circuit, a level shifter circuit, and a buffer circuit of a driving circuit. I have.

In FIG. 11B, a channel forming region 501, LDD regions 506 and 507, and a drain region 50 are formed.
8 and a gate insulating film 504 on the active layer.
And a gate electrode 505 are provided. L
The DD region 506 is provided so as to overlap with the gate electrode 505 via the gate insulating film 504. Also, LDD
The region 507 is provided so as not to overlap with the gate electrode 505, and such an LDD region is referred to as Loff in this specification. Loff has the effect of reducing the off-current value, and Lo
With the configuration provided with v and Loff, it is possible to prevent deterioration due to hot carriers and to reduce the off-current value, and to reduce the n-channel type T of the sampling circuit of the driving circuit.
Suitable for use in FT.

FIG. 11C shows that a channel forming region 501, an offset region 509, and an LDD region 51 are formed in the active layer.
0, a drain region 511 is provided. LDD region 510 is provided so as not to overlap with gate electrode 505, and is separated by offset region 509. The offset region 509 has the same composition as the channel forming region 501. By forming an offset area in this way, L
By providing off, the off-state current value can be effectively reduced, which is suitable for use in an n-channel TFT in a pixel portion. The concentration of the impurity element imparting n-type in the LDD region 510 of the pixel portion depends on the LDD of the driving circuit.
1/2 of the density in the regions 502, 506, and 507
Is preferably reduced to 1/10.

As described above, according to the structure of the present invention, in a semiconductor device having a pixel portion and a driving circuit for the pixel portion on the same substrate, the LDD region of the n-channel TFT of the pixel portion is And the LDD region of the first n-channel TFT of the driving circuit is arranged so as not to overlap with the gate electrode of the n-channel TFT.
The LDD region of the second n-channel TFT of the driving circuit is disposed so as to overlap with the gate electrode of the FT.
The n-channel TFT of the pixel portion is disposed so as to at least partially overlap the gate electrode of the n-channel TFT.
An offset region is formed between the channel forming region of the FT and the LDD region of the n-channel TFT of the pixel portion.

According to another aspect of the present invention, in a semiconductor device having a pixel portion and a driver circuit for the pixel portion over the same substrate, the driver circuit is provided so that the entire LDD region overlaps the gate electrode. First n-channel TFT
And a second n-channel TFT provided so that a part of the LDD region overlaps with the gate electrode. The LDD region of the n-channel TFT forming the pixel portion is
An offset region is formed between the channel formation region of the n-channel TFT in the pixel portion and the LDD region of the n-channel TFT in the pixel portion, the entirety of the D region being provided so as not to overlap the gate electrode. It is characterized by being.

In the configuration of the invention described above, the first n-channel TFT and the second n-channel TFT of the driving circuit are provided.
In the LDD region of the FT, the n-channel type TF of the pixel portion is provided.
It is characterized in that it contains an impurity element imparting n-type at a higher concentration than the LDD region of T, and its concentration ratio is 2
It is desirable to set the range of times to 10 times or less. Specifically, the concentration of the impurity element imparting n-type is set to 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms in the LDD regions of the first n-channel TFT and the second n-channel TFT of the driving circuit.
s / cm ³ , and the n-channel type TF
In the LDD region of T, 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³
Is desirable.

In the structure of the invention, the offset region is made of a semiconductor film having the same composition as a channel forming region in contact with the offset region, and the offset region has a size of 1 × 10 ¹⁵ to 1 × 10 ^18. An impurity element imparting p-type may be contained in a concentration range of atoms / cm ³ .

In the above structure of the present invention, the pixel portion includes a semiconductor layer connected to an n-channel TFT of the pixel portion and containing an impurity element imparting n-type conductivity, a capacitor wiring, and the semiconductor layer and the capacitor wiring. A storage capacitor may be formed with the insulating film between them.

Further, a method for manufacturing a semiconductor device according to the present invention
In a method for manufacturing a semiconductor device having a pixel portion and a driver circuit for the pixel portion over the same substrate, the active layer of the first and second n-channel TFTs forming the driver circuit may have 2 ×
A first step of selectively adding an impurity element imparting n-type in a concentration range of 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ , and a step of adding 3 to the active layer of the p-channel TFT forming the driving circuit.
A second step of selectively adding an impurity element imparting p-type in a concentration range of × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ , and a first and second n-channel type for forming the drive circuit T
An impurity element imparting n-type is selectively added to the active layer of the FT and the active layer of the n-channel TFT in the pixel portion in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ^3. Third
And a step of 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms on the active layer of the n-channel TFT in the pixel portion via an insulating film covering at least the side surface of the gate electrode of the n-channel TFT.
a fourth step of selectively adding an impurity element imparting n-type in a concentration range of s / cm ³ , wherein the first step forms a storage capacitor of the pixel portion. The same concentration of impurity elements can be simultaneously added to the semiconductor layer. Further, in the fourth step, an n-type impurity region and an offset region sandwiched between the n-type impurity region and the channel formation region are formed in the n-channel TFT of the pixel portion. I have.

Another method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a pixel portion and a driving circuit for the pixel portion over the same substrate, wherein the first and second forming the driving circuit are performed. 2, the active layer of the n-channel TFT,
A first step of selectively adding an impurity element imparting n-type in a concentration range of 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ ;
In the active layer of the n-channel TFT in the pixel portion, an n-type TFT having a concentration of 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ is interposed via an insulating film covering at least a side surface of the gate electrode of the n-channel TFT. A second step of selectively adding an impurity element for imparting a mold, and a p-channel type TF for forming the drive circuit.
A third step of selectively adding an impurity element imparting p-type to the T active layer in a concentration range of 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ , and a first step of forming the drive circuit. And the second
1 × 10 ²⁰ to 1 × 10 ²¹ at the active layer of the n-channel TFT and the active layer of the n-channel TFT in the pixel portion.
a fourth step of selectively adding an impurity element imparting n-type in a concentration range of oms / cm ³ , wherein in the first step a semiconductor forming a storage capacitor of the pixel portion is provided. Impurity elements of the same concentration can be added simultaneously. Further, an n-type impurity region and an offset region sandwiched between the n-type impurity region and the channel forming region are formed in the n-channel TFT of the pixel portion by the second step. I have.

In another manufacturing method of the semiconductor device according to the present invention, the offset region is formed in a self-aligned manner using an insulating film covering a gate electrode of an n-channel TFT as a mask. Is 25-1 thick
It is preferably 00 nm.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. FIG. 1 illustrates a cross-sectional structure in which a pixel portion and a TFT of a driver circuit provided around the pixel portion are formed over the same substrate.

The substrate 101 has an insulating surface. In addition to an insulating substrate such as a glass substrate or a quartz substrate, a metal substrate, a silicon substrate, or a ceramic substrate having an insulating film formed on the surface may be used. It is possible. As the glass substrate, it is desirable to use a low alkali glass substrate as represented by, for example, Corning # 1737 substrate. Further, it is preferable that a base film 102 containing silicon oxide or silicon nitride as a main component be closely formed on the surface thereof. On the substrate 101, an n-channel TFT 149 of a pixel portion, a storage capacitor 150, a first n-channel TFT 147 of a driving circuit, and a p-channel TFT
The FT 146 and the second n-channel TFT 148 are formed.

For the active layer of these TFTs, a crystalline semiconductor film is applied to form an island pattern. The crystalline semiconductor film is a crystalline silicon film formed by a known laser crystallization technique or a thermal crystallization technique, or a crystallization technique using a catalyst element that promotes crystallization of the amorphous silicon film. Most preferably, a membrane is used. Of course, other semiconductor materials can be used instead. The thickness of the active layer is 20 to 150 nm, preferably 30 to 75 nm.

In the active layer of the p-channel TFT 146 of the driving circuit, the channel forming region 103 and the source region 10
4. The drain region 105 is formed. The active layer of the first n-channel type TFT 147 includes a channel formation region 106, a source region 109, a drain region 108, an LD
D region 107 is formed. This LDD region 107
Contains an impurity element imparting n-type at 2 × 10 ^{16 to} 5 × 10
It is contained at a concentration of ¹⁹ atoms / cm ³ . The impurity element imparting n-type may be any known element in the field of semiconductor technology, and typically, phosphorus (P), arsenic (As), or the like may be used. The LDD region 107 is an Lov region provided so as to overlap the gate electrode 128 via the gate insulating film 126, and is provided only on the drain region side. Of course, the Lov region may be provided on the source region side. Such a p-channel TFT 146 and an n-channel TFT 14
7, a shift register circuit, a level shifter circuit,
A buffer circuit or the like can be formed.

The second n-channel type TF of the driving circuit
The active layer of T148 includes a channel forming region 110, a source region 113, a drain region 114, and an LDD region 11.
1, 112 are formed. This LDD region 111,
Reference numeral 112 includes Lov and Loff. Such an n-channel TFT 148 can be suitably used for a sampling circuit or the like.

In the active layer of the n-channel TFT 149 in the pixel portion, channel forming regions 115 and 125, source or drain regions 121 to 123, and LDD regions 117 to 12 are provided.
0 is provided. The LDD region is provided so as not to overlap the gate electrode by the offset region as shown in FIG. 11C, and the impurity concentration imparting n-type to the LDD region is 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ^3. However, it is preferable that the impurity concentration is set to １ ／ to 1/10 compared to the LDD region of the n-channel TFT of the driving circuit.

The LDD region of the n-channel TFT of the drive circuit is provided mainly for the purpose of relaxing a high electric field near the drain and preventing deterioration of the on-current value due to hot carrier injection. On the other hand, the n-channel type TF
The LDD region of T is provided for the main purpose of reducing the off-current value, and may have the above-described concentration range.

The Lov of the n-channel TFT of this drive circuit
The length of the region in the channel length direction is 3 to 8 μm in channel length.
0.5 to 3.0 μm, preferably 1.0 to 1.
The thickness may be set to 5 μm. Also, the Loff region is 0.3 to 2.
The thickness may be 0 μm, preferably 0.5 to 1.5 μm.
On the other hand, the length in the channel length direction of the Loff region of the n-channel TFT in the pixel portion may be 0.5 to 3.5 μm, typically 1.5 to 2.5 μm. The offset area is set to 0.02 to 0.1 μm.

The gate insulating film 126 includes a silicon nitride film,
It is formed using a silicon oxide film or a silicon oxynitride film (for example, a film formed using SiH ₄ , N ₂ O, NH _3, or the like as a raw material by a plasma CVD method). The thickness of the gate insulating film 126 is preferably 20 to 200 nm, more preferably 70 to 150 nm. The gate electrodes 127 to 130 are made of titanium (T
i), a material containing one or more elements selected from tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), nickel (Ni), and copper (Cu). For example, a two-layer structure of tantalum nitride (TaN) and Ta may be used from the gate insulating film side.

A cap layer 132 is formed to a thickness of 20 to 100 nm so as to cover the gate electrode and the gate insulating film. The material of the cap layer 132 is not particularly limited as long as it is an insulating film, and may be formed of a silicon oxide film or a silicon nitride film. The first interlayer insulating film is a protective insulating film 13
3 and an interlayer insulating film 134 closely formed thereon, and may be formed of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a stacked structure of a combination thereof. For example, a silicon oxynitride film can be used for the protective insulating film 133 and a silicon oxide film can be used for the interlayer insulating film 134. The total thickness of the first interlayer insulating film is 500 to 1
The thickness may be set to 500 nm.

In the first interlayer insulating film, contact holes reaching the source or drain regions of the respective TFTs are formed, and the source wirings 135, 137, 138, 140
And drain wirings 136, 139 and 141 are provided.
Although not shown, a Ti film having a thickness of 200 nm
Al film containing Ti is 450 nm, and Ti film is
A three-layer structure with a thickness of nm may be used.

The passivation film 142 is formed of a silicon nitride film, a silicon oxide film, or a silicon oxynitride film.
It is formed with a thickness of 0 to 500 nm, typically 50 to 200 nm. Further, the second interlayer insulating film 143 is
It is formed to a thickness of 2000 nm. The second interlayer insulating film is preferably formed using an organic resin film such as polyimide, polyamide, acrylic, polyimide amide, or benzocyclobutene. Advantages of using an organic resin film include a relatively simple method of forming the film, a reduction in parasitic capacitance due to a low relative dielectric constant, and an excellent flatness. For example, when a polyimide of a type that is thermally polymerized after being applied is used, it can be formed at about 300 ° C.
Note that an organic resin film other than those described above, an organic silicon oxide compound, or the like can also be used.

In the pixel portion, a contact hole reaching the drain wiring 141 is formed in the second interlayer insulating film 143 and the passivation film 142, and a pixel electrode 144 is provided. For a pixel electrode, a transparent conductive film is used for a transmissive display device, and a metal film is used for forming a reflective display device. Suitable materials for the transparent conductive film include:
Indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ),
Zinc oxide (ZnO) or the like, typically formed using an indium tin oxide (ITO) film.

With such a structure, an active matrix substrate having a pixel portion and its driving circuit is formed on the same substrate. The driving circuit includes a first n-channel TFT 1
47, a p-channel TFT 146, and a second n-channel TFT 148 are formed, so that a logic circuit based on a CMOS circuit can be formed. In the pixel portion, an n-channel TFT 149 is formed. Further, a capacitance wiring 131 formed simultaneously with the gate electrode, an insulating film made of the same material as the gate insulating film,
A storage capacitor 150 is formed from the semiconductor layer 124 to which the impurity element imparting n-type is added, which is connected to the source or drain region 123 of the semiconductor device 9.

As described above, the present invention makes it possible to optimize the structure of the TFT constituting each circuit according to the specifications required by the pixel portion and the driving circuit, and to improve the operation performance and reliability of the semiconductor device. can do. More specifically, the design of the LDD region of the n-channel TFT is made different according to each circuit specification, and the Lov region or the Loff region is appropriately provided, so that the TFT structure emphasizing measures against hot carriers on the same substrate. And T that emphasizes low off-current value
FT structure can be realized.

[0038]

[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS. Here, a method for simultaneously manufacturing TFTs of a pixel portion and a driving circuit provided in the periphery thereof will be described in the order of steps. However, for the sake of simplicity, in the driving circuit, a CMOS circuit which is a basic circuit such as a shift register circuit and a buffer circuit, and an n-channel TFT forming a sampling circuit are illustrated.

In FIG. 2A, a low alkali glass substrate or a quartz substrate is preferably used as the substrate 201.
In this embodiment, a low alkali glass substrate was used. In this case, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. T of this substrate 201
A base film 202 such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on a surface on which the FT is formed in order to prevent impurity diffusion from the substrate 201. For example, a silicon oxynitride film made of SiH ₄ , NH ₃ , and N ₂ O by plasma CVD is 100 nm, and S
a silicon oxynitride film made of iH ₄ and N ₂ O
It is preferable to form a laminate with a thickness of 0 nm.

Next, 20 to 150 nm (preferably 30 nm)
Semiconductor film 20 having an amorphous structure with a thickness of
3 is formed by a known method such as a plasma CVD method or a sputtering method. In this embodiment, an amorphous silicon film is formed to a thickness of 55 nm by a plasma CVD method. Examples of the semiconductor film having an amorphous structure include an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used. Since the base film 202 and the amorphous silicon film 203a can be formed by the same film formation method, both may be formed continuously. After the formation of the base film, it is possible to prevent the surface from being contaminated by not once exposing it to the atmosphere, thereby reducing the variation in the characteristics of the TFT to be manufactured and the fluctuation of the threshold voltage. (Fig. 2 (A))

Then, a crystalline silicon film 203b is formed from the amorphous silicon film 203a using a known crystallization technique. For example, a laser crystallization method or a thermal crystallization method (solid phase growth method) may be applied.
According to the technique disclosed in Japanese Patent No. 30652, a crystalline silicon film 203b was formed by a crystallization method using a catalytic element. Prior to the crystallization step, depending on the amount of hydrogen contained in the amorphous silicon film, heat treatment may be performed at 400 to 500 ° C. for about 1 hour to reduce the amount of hydrogen to 5 atomic% or less before crystallization. desirable. When the amorphous silicon film is crystallized, rearrangement of atoms occurs and the film becomes denser. Therefore, the thickness of the crystalline silicon film to be formed is larger than the initial thickness of the amorphous silicon film (55 nm in this embodiment). Also decreased by about 1 to 15%. (FIG. 2 (B))

Then, the crystalline silicon film 203b is patterned in an island shape to form island-shaped semiconductor layers 204 to 207. After that, a mask layer 208 of a silicon oxide film having a thickness of 50 to 100 nm is formed by a plasma CVD method or a sputtering method. (Fig. 2 (C))

Then, a resist mask 209 is provided.
Island-shaped semiconductor layers 210 to 212 forming channel type TFT
1 × 10 for the purpose of controlling the threshold voltage¹⁶~ 5
× 10 ¹⁷atoms / cm^ThreeImpurities that give p-type at a moderate concentration
Boron (B) was added as an element. Add boron (B)
The addition may be performed by an ion doping method, or an amorphous silicon
Can be added at the same time as
You. It is not always necessary to add boron (B) here.
Set the threshold voltage of the n-channel TFT within a predetermined range.
It was preferable to implement it in order to fit in. (Figure 2
(D))

In order to form an LDD region of an n-channel TFT of a driving circuit, an impurity element imparting n-type is selectively added to the island-shaped semiconductor layers 210 and 211. For this purpose, resist masks 213 to 216 were formed in advance. As an impurity element imparting n-type, phosphorus (P) or arsenic (As) may be used. Here, an ion doping method using phosphine (PH ₃ ) is applied to add phosphorus (P). Impurity regions 217, 218 formed
(P) concentration of 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³
Should be within the range. In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 217 to 219 formed here is expressed as (n ⁻ ). The impurity region 219 is a semiconductor layer for forming a storage capacitor in a pixel portion, and phosphorus (P) is added to this region at the same concentration. (FIG. 2 (E))

Next, a step of removing the mask layer 208 with hydrofluoric acid or the like and activating the impurity element added in FIGS. 2D and 2E is performed. The activation can be performed by a heat treatment at 500 to 600 ° C. for 1 to 4 hours in a nitrogen atmosphere or a laser activation method. Further, both may be performed in combination. In this embodiment, a KrF excimer laser beam (wavelength 248 n
m) to form a linear beam and generate an oscillation frequency of 5 to 5
Scanning was performed at 0 Hz, an energy density of 100 to 500 mJ / cm ^{2 and an} overlap ratio of the linear beam of 80 to 98%, and the entire surface of the substrate on which the island-shaped semiconductor layer was formed was processed. There are no particular restrictions on the laser light irradiation conditions, and the conditions may be determined appropriately by the practitioner.

Then, the gate insulating film 220 is formed by plasma C
The insulating film containing silicon is formed with a thickness of 10 to 150 nm by a VD method or a sputtering method. For example, 120
A silicon oxynitride film is formed with a thickness of nm. As the gate insulating film, another insulating film containing silicon may be used as a single layer or a stacked structure. (FIG. 3 (A))

Next, a conductive film to be a gate electrode and a gate wiring is formed. This conductive film may be formed of a single-layer conductive film, but preferably has a stacked structure of two or three layers as necessary. In this embodiment, a stacked film including the first conductive film 221 and the second conductive film 222 is formed. As the first conductive film 221 and the second conductive film 222, an element selected from Ta, Ti, Mo, W, and Cr, or a conductive film containing the above elements as a main component (typically, a tantalum nitride film, a tungsten nitride film, Film, a titanium nitride film), or an alloy film combining the above elements (typically, Mo-W
An alloy film, a Mo—Ta alloy film), or a silicide film of the above element (typically, a tungsten silicide film or a titanium silicide film) can be used.

The first conductive film 221 has a thickness of 10 to 50 nm (preferably 20 to 30 nm), and the second conductive film 222 has a thickness of 20 to 50 nm.
The thickness may be 0 to 400 nm (preferably 250 to 350 nm). In this embodiment, a 30 nm thick tantalum nitride film is formed on the first conductive film, and a 350 nm Ta film is formed on the second conductive film.
All were formed by sputtering using a film. In the film formation by the sputtering method, if an appropriate amount of Xe or Kr is added to Ar of the gas for sputtering, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. Although not shown, it is effective to form a silicon film under the first conductive film 221 with a thickness of about 2 to 20 nm. Thereby, it is possible to improve the adhesion of the conductive film formed thereon and prevent oxidation. (FIG. 3 (B))

Next, resist masks 223 to 227 are formed, and the first conductive film 221 and the second conductive film 222 are simultaneously etched to form gate electrodes 228 to 231, a gate wiring (wiring connected to the gate electrode), The capacitor wiring 232 is formed. At this time, the gate electrode 234 formed in the drive circuit,
235 is formed so as to overlap with part of the impurity regions 217 and 218 via the gate insulating film 220. This overlapping portion will later become the Lov region. (FIG. 3 (C))

Then, using the gate electrode and the capacitor wiring as a mask, the gate insulating film 220 is etched so that at least the gate insulating films 233 to 236 remain under the gate electrode to expose a part of the island-shaped semiconductor layer. Let it.
(At this time, the insulating film 237 is also formed below the capacitor wiring.) This is because the impurity element is efficiently added in a step of adding an impurity element for forming a source region or a drain region in a later step. This step may be omitted, and the gate insulating film may be left on the entire surface of the island-shaped semiconductor layer. (FIG. 3
(D))

Next, in order to form a source region and a drain region of the p-channel TFT of the driving circuit, a step of adding an impurity element imparting p-type is performed. Here, the impurity region is formed in a self-aligned manner using the gate electrode 228 as a mask. At this time, the region where the n-channel TFT is to be formed is covered with a resist mask 238. Then, an impurity region 239 was formed by an ion doping method using diborane (B ₂ H ₆ ). The boron (B) concentration in this region is set to 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ . In this specification, the concentration of the impurity element imparting p-type contained in the impurity region 239 formed here is expressed as (p ⁺ ). (FIG. 4 (A))

Next, in the n-channel TFT, an impurity region functioning as a source region or a drain region was formed. Resist masks 240 to 242 were formed so as to cover the gate electrode and a region to be a p-channel TFT, and impurity regions 243 to 247 were formed by adding an impurity element imparting n-type. This is the phosphine (P
H ₃₎ Ion doping using was phosphorus (P) concentration of this region and ^{1 × 10 2 0 ~1 × 10} 21 atoms / cm 3. In this specification, the impurity region 24 formed here is used.
The concentration of the impurity element imparting n-type contained in 3 to 247 is represented as (n ⁺ ). (FIG. 4 (B))

The impurity regions 243 to 247 contain phosphorus (P) or boron (B) already added in the previous step, but phosphorus (P) is added at a sufficiently high concentration. Therefore, it is not necessary to consider the influence of phosphorus (P) or boron (B) added in the previous step. Further, the concentration of phosphorus (P) added to the impurity region 243 is ２〜 to １ ／ of the concentration of boron (B) added in FIG.
The conductivity of the mold was ensured, and the characteristics of the TFT were not affected at all.

Next, the resist mask is removed, and at least the gate electrodes 228 to 231 and the gate insulating films 233 to 231 are removed.
The cap layer 248 to cover the side surface of
It is formed to a thickness of 0 nm. The cap layer may be formed using a silicon nitride film or a silicon oxynitride film. In this embodiment, a silicon oxynitride film is formed by a plasma CVD method for 100 n.
m. Then, the n-channel type T of the pixel portion
In order to form an LDD region of the FT, a process of adding an impurity for imparting n-type was performed. Here, an impurity element imparting n-type is added to the island-like semiconductor layer thereunder via the cap layer 248 by an ion doping method. The concentration of phosphorus (P) added here is 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ^3, which is higher than the concentration of the impurity element added in FIGS. 2 (E), 4 (A) and 4 (B). Was also added at a low concentration, so that only the impurity regions 249 and 250 were formed. In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 249 and 250 formed here is expressed as (n ⁻ ). (FIG. 4 (C))

Here, the impurity regions 249 and 250 are formed outside the gate electrode by the thickness of the cap layer formed on the side walls of the gate electrode and the gate insulating film. That is, an offset area is formed. No impurity element is added to the offset region by the ion doping method, and the offset region is formed with the same composition as the channel formation region. The length of the offset region can be controlled by appropriately selecting the thickness of the cap layer.

Then, a protective insulating film 251 to be a part of the first interlayer insulating film is formed later. The protective insulating film 251 may be formed using a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a stacked film including a combination thereof. Further, the film thickness may be 100 to 400 nm.

Thereafter, a heat treatment step is performed to activate the n-type or p-type imparting impurity elements added at the respective concentrations. This step can be performed by a furnace annealing method, a laser annealing method, or a rapid thermal annealing method (RTA method). Here, the activation step was performed by furnace annealing. The heat treatment is performed in a nitrogen atmosphere at 300 to 650 ° C., preferably 500 to 650 ° C.
The heat treatment was performed at 550 ° C., here 525 ° C., for 4 hours. Further, in an atmosphere containing 3 to 100% hydrogen,
Heat treatment was performed at 00 to 450 ° C. for 1 to 12 hours to hydrogenate the island-shaped semiconductor layer. In this step, dangling bonds in the active layer are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

When the island-shaped semiconductor layer was formed from an amorphous silicon film by a crystallization method using a catalyst element, a trace amount of the catalyst element remained in the island-shaped semiconductor layer. Of course, it is possible to complete the TFT in such a state,
It was more preferable to remove the remaining catalyst element from at least the channel formation region. One of the means for removing the catalytic element is a means utilizing the gettering action of phosphorus (P). The concentration of phosphorus (P) necessary for gettering is substantially the same as that of the impurity region (n ⁺ ) formed in FIG. 4B, and the n-channel TFT and the p-type The catalyst element could be gettered from the channel forming region of the channel type TFT. (FIG. 4 (D))

After completing the activation step, the protective insulating film 251 is formed.
An interlayer insulating film 252 having a thickness of 500 to 1500 nm
To form The protective insulating film 251 and the interlayer insulating film 252
Was used as a first interlayer insulating film. Thereafter, contact holes reaching the source region or the drain region of each TFT are formed, and the source wirings 253 to 25 are formed.
6 and drain wirings 257 to 259 are formed. Although not shown, in the present embodiment, this wiring is
nm, aluminum film containing Ti 300 nm, Ti film 1
A 50 nm-thick laminated film having a three-layer structure continuously formed by a sputtering method was used.

Next, as the passivation film 260,
A silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is 50 to 500 nm (typically, 100 to 300 nm).
(nm). When hydrogenation was performed in this state, favorable results were obtained with respect to the improvement of TFT characteristics.
For example, in an atmosphere containing 3 to 100% hydrogen, 300
A heat treatment at a temperature of 450 ° C. for 1 to 12 hours may be performed, or a similar effect may be obtained by using a plasma hydrogenation method. Note that an opening may be formed in the passivation film 260 at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed later. (FIG. 5 (A))

Thereafter, a second interlayer insulating film 261 made of an organic resin is formed to a thickness of 1.0 to 1.5 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Here, a polyimide of a type that is thermally polymerized after being applied to the substrate and baked at 300 ° C. is used. Then, a contact hole reaching the drain wiring 259 is formed in the second interlayer insulating film 261, and a pixel electrode 262 is formed. As the pixel electrode 262, a transparent conductive film may be used in the case of a transmissive liquid crystal display device, and a metal film may be used in the case of a reflective liquid crystal display device.
In this embodiment, an indium tin oxide (ITO) film is formed to a thickness of 100 nm by a sputtering method in order to obtain a transmission type liquid crystal display device. (FIG. 5 (B))

Thus, an active matrix substrate having a drive circuit and a pixel portion on the same substrate was completed. A pixel TFT composed of a p-channel TFT 285, a first n-channel TFT 286, a second n-channel TFT 287 was formed in the driving circuit, and an n-channel TFT 288 was formed in the pixel portion.

The p-channel TFT 285 of the driving circuit has a channel forming region 263, a source region 264, and a drain region 265. First n-channel type TF
In T286, the channel formation region 266 and the Lov region 26
7, a source region 268 and a drain region 269. The length of the Lov region in the channel length direction is 0.5 to
It is 3.0 μm, preferably 1.0 to 1.5 μm. The second n-channel TFT 287 includes a channel forming region 270, LDD regions 271 and 272, and a source region 27.
3. It has a drain region 274. The LDD region is divided into a Lov region and an Loff region, and the length of the Loff region in the channel length direction is 0.3 to 2.0 μm, preferably 0.5 to 1.5 μm. N-channel type TF in pixel section
T288 includes channel formation regions 275 and 276, Lof
f regions 277 to 280 are provided. The length of the Loff region in the channel length direction is 0.5 to 3.0 μm, preferably 1.
5 to 2.5 μm. The Loff region is offset with respect to the gate electrode, and the length of the offset region is 0.0
2 to 0.2 μm. Further, a capacitor wiring 232 formed at the same time as the gate electrode, an insulating film made of the same material as the gate insulating film, and a semiconductor layer doped with an impurity element imparting n-type and connected to the drain region 283 of the n-channel TFT 288. 284 form a storage capacitor 289. In FIG. 5B, the n-channel TFT 2 in the pixel portion is used.
Although 88 has a double gate structure, it may have a single gate structure or a multi-gate structure provided with a plurality of gate electrodes.

[Embodiment 2] This embodiment will be described with reference to FIGS. 6A and 6B, in which a pixel portion and a TFT of a driving circuit provided around the pixel portion are simultaneously manufactured by a method different from that of Embodiment 1. FIG.

First, FIG. 2A to FIG.
The steps up to FIG. The cap layer 30 covers at least the side surfaces of the gate electrodes 228 to 231.
Form one. The cap layer may be formed of a silicon nitride film or a silicon oxynitride film with a thickness of 25 to 200 nm. In this embodiment, a silicon oxynitride film is formed by plasma CV.
Formed to a thickness of 100 nm by D method. Then, an impurity element for imparting n-type is added to the island-shaped semiconductor layer thereunder via the cap layer 301 by an ion doping method, so that an impurity region 303 serving as an LDD region of the n-channel TFT in the pixel portion is formed. Formed. The concentration of phosphorus (P) added here was 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ . (FIG. 6
(A))

Then, using the gate electrode and the capacitor wiring as a mask, the gate insulating film 220 is etched so that at least the gate insulating films 233 to 236 remain under the gate electrode to expose a part of the island-shaped semiconductor layer. I let it.
(At this time, the insulating film 237 is also formed below the capacitor wiring.) This is performed in order to efficiently perform a step of adding an impurity element to the source region or the drain region in a later step. This step may be omitted, and the gate insulating film may be left on the entire surface of the island-shaped semiconductor layer.
(FIG. 6 (B))

Subsequent steps may be performed in the same manner as in Example 1 (the step of FIG. 4C is omitted), and the active matrix substrate shown in FIG. 5B can be manufactured.

[Embodiment 3] Another embodiment of the present embodiment will be described with reference to FIGS. 13A and 13B in which TFTs of a pixel portion and a driving circuit provided around the pixel portion are simultaneously manufactured.

First, the steps up to FIG. 4B were performed in the same manner as in Example 1. Here, in FIG. 13A, the first wirings 403 and 404 are formed simultaneously with the same material as the gate electrode. The insulating films 401 and 402 are the gate insulating film 2
It is formed of the same material as 20. Then, a cap layer 248 is formed to cover at least the side surface of the gate electrode. The cap layer may be formed of a silicon nitride film or a silicon oxynitride film with a thickness of 25 to 200 nm. In this embodiment, a silicon oxynitride film is formed by a plasma CVD method.
It is formed to a thickness of 00 nm. Then, the cap layer 248
Then, an impurity element imparting n-type is added to the island-like semiconductor layer therebelow by ion doping method, thereby forming an impurity region serving as an LDD region of an n-channel TFT in a pixel portion. The concentration of phosphorus (P) added here is 1 × 10 ^{16 to} 5
× 10 ¹⁸ atoms / cm ³ . (FIG. 13A)

Thereafter, the cap layer 248 was removed by etching using hydrofluoric acid or the like. Then, as shown in FIG. 13B, the second wirings 405 and 406 made of a conductive film such as aluminum (Al) or copper (Cu) are connected to the wiring 40.
3 and 404 were patterned. Then, a first interlayer insulating film 407 made of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or the like was formed. Subsequent steps may be performed in the same manner as in Embodiment 1. A source or drain wiring, a passivation film, a second interlayer insulating film, and a pixel electrode are formed to complete the active matrix substrate shown in FIG.

The first wiring 403 and the second wiring 405, and the first wiring 404 and the second wiring 406 are integrally formed with each other, and the wiring from the input / output terminal to the input / output end of each circuit and the pixel section are formed. Provided as part of the gate wiring. Al and C
By providing the second wirings 405 and 406 with a low-resistance material such as u, the wiring resistance can be reduced and a large-screen direct-view display device (20-inch class or more) can be supported.

[Embodiment 4] In this embodiment, a process for manufacturing an active matrix type liquid crystal display device from an active matrix substrate will be described. As shown in FIG. 7, an alignment film 601 is formed on the active matrix substrate in the state shown in FIG. Usually, a polyimide resin is often used for an alignment film of a liquid crystal display element.
The light-shielding film 603, the transparent conductive film 604, and the alignment film 605 were formed on the opposite substrate 602 on the opposite side. After forming the alignment film, a rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. Then, the pixel portion, the active matrix substrate on which the CMOS circuit is formed, and the opposing substrate are bonded to each other via a sealing material or a spacer (both not shown) by a known cell assembling process. After that, a liquid crystal material 606 is injected between the two substrates,
It was completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix type liquid crystal display device shown in FIG. 7 was completed.

Next, the structure of the active matrix type liquid crystal display device will be described with reference to the perspective view of FIG. 8 and the top view of FIG. 8 and 9 use the same reference numerals in order to correspond to the sectional structural views of FIGS. 2 to 5 and 7.
The cross-sectional structure along the line AA ′ shown in FIG.
This corresponds to the cross-sectional view of the pixel portion shown in FIG.

The active matrix substrate includes a pixel portion 701, a scanning signal driving circuit 702, and an image signal driving circuit 703 formed on the glass substrate 201.
An n-channel TFT 288 is provided in the pixel portion, and a driver circuit provided in the periphery is configured based on a CMOS circuit. The scan signal driver circuit 702 and the image signal driver circuit 703 are each connected to a gate wiring 231 (connected to a gate electrode and denoted by the same reference numeral in the sense of being formed so as to extend) and a source wiring 256 so that the n-channel of the pixel portion is formed. Type TFT288. Further, the FPC 731 is connected to the external input / output terminal 734.

FIG. 9 is a top view showing a part (almost one pixel) of the pixel portion 701. The gate wiring 231 intersects an active layer therebelow via a gate insulating film (not shown). Although not shown, an Loff region including a source region, a drain region, and an n ⁻ region is formed in the active layer. 290 is a contact portion between the source wiring 256 and the source region 281, and 292 is a drain wiring 25
Reference numeral 292 denotes a contact portion between the drain wiring 259 and the pixel electrode 262. The storage capacitor 289 is formed in a region where the capacitor wiring 232 overlaps with the semiconductor layer 284 extending from the drain region of the n-channel TFT 288 via a gate insulating film.

Although the active matrix type liquid crystal display device of the present embodiment has been described with reference to the structure described in the first embodiment, the active matrix type liquid crystal display device can be freely combined with any of the structures of the first to third embodiments. A display device can be manufactured.

[Embodiment 5] FIG. 10 shows Embodiments 1 to 3.
FIG. 2 is a diagram showing an example of a circuit configuration of an active matrix substrate shown in FIG. The active matrix substrate of this embodiment includes an image signal drive circuit 1001, a scan signal drive circuit (A) 1007, a scan signal drive circuit (B) 1011, and a precharge circuit 101.
2. The pixel portion 1006 is provided. Note that the driving circuit described in this specification refers to the image signal driving circuit 1001,
This is a generic term including the scanning signal drive circuit (A) 1007.

The image signal driving circuit 1001 includes a shift register circuit 1002, a level shifter circuit 1003, a buffer circuit 1004, and a sampling circuit 1005. The scan signal driver circuit (A) 1007 includes a shift register circuit 1008, a level shifter circuit 1009, and a buffer circuit 1010. The scanning signal driving circuit (B) 1011 has a similar configuration.

The shift register circuits 1002 and 1008 have a driving voltage of 5 to 16 V (typically 10 V), and the n-channel TFT of the CMOS circuit forming this circuit has a structure indicated by 286 in FIG. 5B. Is suitable.

The level shifter circuits 1003 and 100
9 and the buffer circuits 1004 and 1010 have a drive voltage of 14
Up to 16V, but like the shift register circuit,
CMOS including n-channel TFT 286 in FIG.
Circuit is suitable. In these circuits, forming the gate in a multi-gate structure increases the withstand voltage, which is effective in improving the reliability of the circuit.

The sampling circuit 1005 has a driving voltage of 1
Although the voltage is 4 to 16 V, the polarity is alternately inverted, and the off-current value needs to be reduced.
The CMOS circuit including the n-channel TFT 287 in FIG. Although only an n-channel TFT is shown in FIG. 5B, in an actual sampling circuit, a p-channel TFT is also formed.
At this time, the structure shown in FIG. 285 is sufficient for the p-channel TFT.

The pixel portion 1006 has a drive voltage of 14 to
16V, and it is required to further reduce the off-state current value from the sampling circuit from the viewpoint of low power consumption.
L formed by providing an offset region with respect to the gate electrode as in the n-channel TFT 288 shown in FIG.
It is desirable to have a structure having a DD (Loff) region.

The structure of this embodiment can be easily realized by fabricating a TFT according to the steps shown in Embodiments 1 to 3. In the present embodiment, only the configuration of the pixel portion and the drive circuit is shown. However, according to the steps of the first or second embodiment, a signal dividing circuit, a frequency dividing circuit, a D / A converter, a γ correction A circuit, an operational amplifier circuit, a signal processing circuit such as a memory circuit and an arithmetic processing circuit, or a logic circuit can be formed over the same substrate.

As described above, according to the present invention, a semiconductor device including a pixel portion and a driver circuit over the same substrate, for example, a semiconductor device including a signal driver circuit and a pixel portion can be realized.

[Embodiment 6] The present invention can be applied to an active matrix type EL display device. FIG.
1 is a circuit diagram of an active matrix EL display device. An X-direction drive circuit 12 and a Y-direction drive circuit 13 are provided around the pixel section 11. Each pixel of the pixel section 11 has a switching TFT 14, a capacitor 15, a current controlling TFT 16, and an organic EL element 17, and a switching TFT
The X direction signal line 18a and the Y direction signal line 20a are connected to the FT 14, and the power supply line 19a is connected to the current control TFT.

In the active matrix EL display device of the present invention, the TFT used for the X-direction drive circuit 12, the Y-direction drive circuit 13, or the current control TFT 17 is shown in FIG.
(B) p-channel TFT 285, n-channel TF
It is formed by combining T286 or n-channel TFT 287. Also, the switching TFT 14 is replaced with the one shown in FIG.
It is formed by the n-channel TFT 288 of FIG.

The active matrix type E of the present embodiment
Any configuration of the first to third embodiments may be combined with the L display device.

[Embodiment 7] An active matrix substrate in which a pixel portion and a driving circuit manufactured by carrying out the present invention are integrally formed on the same substrate can be used for various electro-optical devices (active matrix liquid crystal display devices, active matrix (A matrix type EL display device, an active matrix type EC display device). That is, the present invention can be applied to all electronic devices incorporating these electro-optical devices as display media.

Examples of such electronic devices include a video camera, a digital camera, a projector (rear or front type), a head mounted display (goggle type display), a car navigation system, a personal computer, a mobile phone, and an electronic book. Can be One example of these is shown in FIG.

FIG. 14A shows a mobile phone,
01, audio output unit 9002, audio input unit 9003, display device 9004, operation switch 9005, antenna 900
6. The present invention can be applied to a display device 9004 including an active matrix substrate.

FIG. 14B shows a video camera, which includes a main body 9101, a display device 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 91.
06. The present invention can be applied to the display device 9102 including the active matrix substrate.

FIG. 14C shows a mobile computer, which includes a main body 9201, a camera section 9202, and an image receiving section 920.
3, an operation switch 9204, and a display device 9205. The present invention can be applied to a display device 9205 including an active matrix substrate.

FIG. 14D shows a goggle type display, which includes a main body 9301, a display device 9302, and an arm 93.
03. The present invention can be applied to the display device 9302. Although not shown, it can be used for other signal control circuits.

FIG. 14E shows a rear type projector, which includes a main body 9401, a light source 9402, a display device 9403,
Polarizing beam splitter 9404, reflector 940
5, 9406 and a screen 9407. The invention can be applied to the display device 9403.

FIG. 14F shows a portable book, and a main body 95.
01, a display device 9503, a storage medium 9504, operation switches 9505, and an antenna 9506,
Data stored on a mini disk (MD) or DVD,
This is for displaying the data received by the antenna. In the present invention, the display device 9503 can be applied to a direct-view display device.

FIG. 15A shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display 2402, and a speaker 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402 and other signal control circuits.

FIG. 15B shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

FIG. 16A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 forming a part of the projection device 2601 and other signal control circuits.

FIG. 16B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like. The present invention relates to a projection device 2
The present invention can be applied to the liquid crystal display device 2808 forming a part of the signal control circuit 702 and other signal control circuits.

FIG. 16C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 16A and 16B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 16D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 16C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 16D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 16, a case where a transmission type electro-optical device is used is shown, and examples of application to a reflection type electro-optical device and an EL display device are not shown.

Although not shown here, the present invention is also applicable to a car navigation system and a display unit of an image sensor personal computer. As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields. Further, the electronic apparatus according to the present embodiment can be realized by using a configuration including any combination of the first to sixth embodiments.

[Embodiment 8] In this embodiment, a self-luminous display panel (hereinafter, referred to as an EL display device) using an electroluminescent (EL) material on an active matrix substrate similar to that of the first embodiment. ) Will be described. FIG. 17A shows a top view of the EL display panel. In FIG. 17A, 10
Denotes a substrate, 11 denotes a pixel portion, 12 denotes a source side driving circuit, 13
Is a gate side drive circuit, and each drive circuit reaches the FPC 17 via the wirings 14 to 16 and is connected to an external device.

FIG. 17B is a sectional view taken along the line AA ′ in FIG. At this time, the opposing plate 8 is provided at least above the pixel portion, preferably above the driving circuit and the pixel portion.
0 is provided. The opposing plate 80 is made of a TFT and an EL with a sealing material 19
It is bonded to an active matrix substrate on which a self-light emitting layer using a material is formed. A filler (not shown) is mixed in the sealant 19, and the two substrates are bonded to each other at substantially uniform intervals by the filler. Further, the outside of the seal member 19 and the upper surface and the periphery of the FPC 17 are sealed with a sealant 81. The sealant 81 uses a material such as a silicone resin, an epoxy resin, a phenol resin, and butyl rubber.

As described above, when the active matrix substrate 10 and the counter substrate 80 are bonded by the sealant 19, a space is formed therebetween. The space is filled with a filler 83. The filler 83 also has an effect of bonding the opposing plate 80. Filler 83 is made of PVC (polyvinyl chloride), epoxy resin, silicone resin, P
VB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. In addition, since the self-luminous layer is weak to moisture including water and easily deteriorates, it is desirable to mix a desiccant such as barium oxide into the filler 83 because the moisture absorbing effect can be maintained. Further, a passivation film 82 formed of a silicon nitride film, a silicon oxynitride film, or the like is formed over the self-luminous layer to prevent corrosion by an alkali element or the like contained in the filler 83.

A glass plate, an aluminum plate, a stainless steel plate, FRP (Fiberglass-Reinforced Pl)
astics) plate, PVF (polyvinyl fluoride) film, mylar film (trade name of DuPont), polyester film, acrylic film or acrylic plate. Further, moisture resistance can be enhanced by using a sheet having a structure in which an aluminum foil of several tens of μm is sandwiched between PVF films or mylar films. In this way, the EL element is in a sealed state and is isolated from the outside air.

In FIG. 17B, a TFT for a drive circuit (here, a C-type TFT combining an n-channel TFT and a p-channel TFT) is formed on the substrate 10 and the base film 21.
2 illustrates a MOS circuit. 22) and TFT for pixel portion
23 (however, here, TF for controlling the current to the EL element)
Only T is shown. ) Is formed. These T
Among the FTs, an n-channel TFT, in particular, an LDD region having the configuration shown in this embodiment is provided in order to prevent a decrease in on-current due to a hot carrier effect and a decrease in characteristics due to a Vth shift or bias stress.

For example, the p-channel TFT 146 and the n-channel TF shown in FIG.
T147 may be used. In addition, the TFT in the pixel portion includes:
Although it depends on the driving voltage, if it is 10 V or more, the first n-channel TFT 147 shown in FIG. 1 or a p-channel TFT having a structure similar to that may be used. The first n
The channel type TFT 147 has a structure in which an LDD overlapping the gate electrode is provided on the drain side. However, if the driving voltage is 10 V or less, TFT deterioration due to the hot carrier effect can be almost neglected, so there is no need to provide the TFT. .

In order to manufacture an EL display device from the active matrix substrate in the state shown in FIG. 1, an interlayer insulating film (flattening film) 26 made of a resin material is formed on a source wiring and a drain wiring, and a pixel portion is formed thereon. A pixel electrode 27 made of a transparent conductive film electrically connected to the drain of the TFT 23 is formed. A compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used for the transparent conductive film. After the pixel electrode 27 is formed, an insulating film 28 is formed, and the pixel electrode 27 is formed.
An opening is formed thereon.

Next, a self-luminous layer 29 is formed. The self-luminous layer 29 may have a laminated structure or a single-layer structure by freely combining known EL materials (a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, or an electron injection layer). A known technique may be used to determine the structure. EL materials include low molecular weight materials and high molecular weight (polymer) materials. When a low molecular material is used, an evaporation method is used. When a high molecular material is used, a simple method such as a spin coating method, a printing method, or an ink jet method can be used.

The self-luminous layer is formed using a shadow mask by an evaporation method, an inkjet method, a dispenser method, or the like. In any case, a color display is possible by forming a light emitting layer (a red light emitting layer, a green light emitting layer, and a blue light emitting layer) capable of emitting light having different wavelengths for each pixel. In addition, there are a method in which a color conversion layer (CCM) and a color filter are combined, and a method in which a white light emitting layer and a color filter are combined, and any method may be used. Needless to say, a monochromatic EL display device can be used.

After forming the self-luminous layer 29, the cathode 30 is formed thereon. It is desirable to remove moisture and oxygen existing at the interface between the cathode 30 and the self-luminous layer 29 as much as possible. Therefore, it is necessary to devise a method of continuously forming the self-luminous layer 29 and the cathode 30 in a vacuum or forming the self-luminous layer 29 in an inert atmosphere and forming the cathode 30 in a vacuum without opening to the atmosphere. . In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

In this embodiment, the cathode 30 is made of Li
A laminated structure of an F (lithium fluoride) film and an Al (aluminum) film is used. Specifically, a 1 nm-thick LiF (lithium fluoride) film is formed on the self-luminous layer 29 by a vapor deposition method, and a 300 nm-thick aluminum film is formed thereon. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 30 is connected to the wiring 16 in a region indicated by 31. The wiring 16 is a power supply line for applying a predetermined voltage to the cathode 30, and is connected to the FPC 17 via the anisotropic conductive paste material 32. A resin layer 80 is further formed on the FPC 17 to increase the adhesive strength at this portion.

In order to electrically connect the cathode 30 and the wiring 16 in the region indicated by 31, it is necessary to form contact holes in the interlayer insulating film 26 and the insulating film 28. These may be formed at the time of etching the interlayer insulating film 26 (at the time of forming a contact hole for a pixel electrode) or at the time of etching the insulating film 28 (at the time of forming an opening before forming a self-luminous layer). Further, when etching the insulating film 28, the etching may be performed all at once up to the interlayer insulating film 26. In this case, if the interlayer insulating film 26 and the insulating film 28 are the same resin material, the shape of the contact hole can be made good.

The wiring 16 is composed of the seal 19 and the substrate 10.
Is electrically connected to the FPC 17 through a gap (but closed with a sealant 81). Although the wiring 16 has been described here, the other wirings 14 and 15 are also electrically connected to the FPC 17 under the sealing material 18 in the same manner.

FIG. 18 shows a more detailed sectional structure of the pixel portion, FIG. 19A shows a top structure thereof, and FIG.
(B) shows. In FIG. 18A, a switching TFT 2402 provided over a substrate 2401 has the same structure as the pixel TFT 149 of FIG. The double gate structure has a structure in which two TFTs are substantially connected in series, and has an advantage that an off current value can be reduced by forming an LDD provided with an offset region that does not overlap with the gate electrode. . In this embodiment, a double gate structure is used, but a triple gate structure or a multi-gate structure having more gates may be used.

The current control TFT 2403 is formed using the first n-channel TFT 147 shown in FIG. This TFT structure is a structure in which an LDD that overlaps with a gate electrode is provided only on the drain side, and has a structure in which the parasitic capacitance and series resistance between the gate and the drain are reduced to increase the current driving capability. From another point of view, being a structure is very important. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows and the element has a high risk of deterioration due to heat or hot carriers.
Therefore, by providing the current control TFT with an LDD region that partially overlaps with the gate electrode, deterioration of the TFT can be prevented and operation stability can be improved. At this time, the drain line 35 of the switching TFT 2402 is electrically connected to the gate electrode 37 of the current controlling TFT by the wiring 36. A wiring indicated by 38 is a gate line that electrically connects the gate electrodes 39a and 39b of the switching TFT 2402.

In this embodiment, the current controlling TFT 24 is used.
03 is shown with a single gate structure.
A multi-gate structure in which FTs are connected in series may be used.
Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

Further, as shown in FIG. 19A, the wiring to be the gate electrode 37 of the current controlling TFT 2403 has 24 wirings.
In a region indicated by 04, the region overlaps with the drain line 40 of the current controlling TFT 2403 via an insulating film. At this time, 24
In a region indicated by 04, a capacitor is formed. The capacitor 2404 functions as a capacitor for holding a voltage applied to the gate of the current control TFT 2403. The drain line 40 is a current supply line (power supply line) 2
501, a constant voltage is always applied.

The first passivation film 4 is formed on the switching TFT 2402 and the current control TFT 2403.
And a planarizing film 42 made of a resin insulating film thereon.
Is formed. It is very important to flatten the step due to the TFT using the flattening film 42. Since a self-light-emitting layer formed later is very thin, light emission failure may occur due to the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming it so that the light emitting layer can be formed as flat as possible.

Reference numeral 43 denotes a pixel electrode (cathode of an EL element) made of a conductive film having high reflectivity.
403 is electrically connected to the drain. Pixel electrode 43
It is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof. Of course, a stacked structure with another conductive film may be employed. A groove (corresponding to a pixel) formed by banks 44a and 44b formed of an insulating film (preferably resin).
The light emitting layer 44 is formed in the inside. Although only one pixel is shown here, R (red), G (green), B (blue)
The light-emitting layers corresponding to the respective colors may be separately formed. As the organic EL material for the light emitting layer, a π-conjugated polymer material is used. Typical polymer-based materials include polyparaphenylenevinylene (PPV), polyvinylcarbazole (PVK), and polyfluorene.
There are various types of PPV-based organic EL materials.
e, W. Kreuder, and H. Spreitzer, “Polymers for Light
Emitting Diodes ”, Euro Display, Proceedings, 1999,
pp. 33-37 "and JP-A-10-92576.

As a specific light emitting layer, cyanopolyphenylene vinylene is used for a light emitting layer emitting red light, polyphenylene vinylene is used for a light emitting layer emitting green light, and polyphenylene vinylene or polyalkylphenylene is used for a light emitting layer emitting blue light. Good. Thickness is 30-150nm
(Preferably 40 to 100 nm). However, the above example is an example of an organic EL material that can be used as a light emitting layer, and there is no need to limit the invention to this.
The light-emitting layer, the charge transport layer, or the charge injection layer may be freely combined to form a self-light-emitting layer (a layer for emitting light and moving carriers therefor). For example, in this embodiment, an example in which a polymer material is used for the light emitting layer is shown, but a low molecular organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

In this embodiment, PEDOT is formed on the light emitting layer 45.
This is a self-luminous layer having a laminated structure provided with a hole injection layer 46 made of (polythiophene) or PAni (polyaniline). An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of this embodiment, the light emitting layer 45
Since the light generated in step (1) is emitted toward the upper surface side (upward of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, it is possible to form after forming a light-emitting layer or a hole-injecting layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

When the anode 47 is formed, the self-luminous element 2405 is completed. The EL element 240 referred to here
Reference numeral 5 denotes a capacitor formed by the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 46, and the anode 47. FIG.
As shown in FIG. 9A, the pixel electrode 43 substantially matches the area of the pixel, so that the entire pixel functions as an EL element. Therefore, the efficiency of light emission is extremely high, and a bright image can be displayed.

In this embodiment, a second passivation film 48 is further provided on the anode 47. Second
As the passivation film 48, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated due to oxidation and the effect of suppressing outgassing from the organic EL material. Thereby, the reliability of the EL display device is improved.

As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. 19, and a switching TFT having a sufficiently low off-current value and a current control device which is strong against hot carrier injection. And a TFT. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.

FIG. 18B shows an example in which the structure of the light emitting layer is inverted. The current control TFT 2601 has the same structure as the p-channel TFT 146 in FIG. Embodiment 1 can be referred to for the manufacturing process. In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

The banks 51a and 51b made of insulating films
Is formed, a light emitting layer 52 made of polyvinyl carbazole is formed by applying a solution. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode 54 made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, an EL element 2602 is formed. In the case of the present embodiment, the light generated in the light emitting layer 53 is emitted toward the substrate on which the TFT is formed, as indicated by the arrow. In the case of the structure as in this embodiment, it is preferable that the current control TFT 2601 be formed of a p-channel TFT.

The EL display device described in this embodiment as described above can be used as the display unit of the electronic device of the seventh embodiment.

[Embodiment 9] In this embodiment, FIG. 20 shows an example in which a pixel having a structure different from that of the circuit diagram shown in FIG. 19B is used. In this embodiment, 2701
270 is the source wiring of the switching TFT 2702, 270
3 is a gate wiring of the switching TFT 2702, 27
04 is a current control TFT, 2705 is a capacitor, 27
Reference numerals 06 and 2708 denote current supply lines, and 2707 denotes an EL element.

FIG. 20A shows an example in which the current supply line 2706 is shared between two pixels. That is, it is characterized in that the two pixels are formed to be line-symmetric with respect to the current supply line 2706. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 20B shows the current supply line 270.
8 is provided in parallel with the gate wiring 2703. Note that in FIG. 20B, the current supply line 2708 and the gate wiring 2703 are provided so as not to overlap with each other; however, if the wirings are formed in different layers, they overlap with each other via an insulating film. It can also be provided as follows. In this case, since the power supply line 2708 and the gate wiring 2703 can share an occupied area, the pixel portion can have higher definition.

In FIG. 20C, a current supply line 2708 is provided in parallel with the gate wiring 2703 similarly to the structure of FIG. 20B, and two pixels are connected to the current supply line 2708.
It is characterized in that it is formed so as to be line-symmetric with respect to.
It is also effective to provide the current supply line 2708 so as to overlap with one of the gate wirings 2703. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition. FIG.
20A and 20B, a capacitor 270 is used to hold the voltage applied to the gate of the current controlling TFT 2705.
4, but the capacitor 2704 can be omitted.

As the current controlling TFT 2705, FIG.
Since the n-channel TFT of the present invention as shown in FIG. 1A is used, an LDD region is provided so as to overlap with a gate electrode via a gate insulating film. Although a parasitic capacitance generally called a gate capacitance is formed, this embodiment is characterized in that this parasitic capacitance is actively used instead of the capacitor 2704. The capacitance of the parasitic capacitance is determined by the gate electrode and the LDD region. And changes in the area that overlaps,
It is determined by the length of the LDD region included in the overlapping region. In the structure shown in FIGS. 20A, 20B, and 20C, the capacitor 2704 can be omitted similarly.

Note that the circuit configuration of the EL display device shown in this embodiment is selected from the TFT configuration shown in Embodiment Mode 1 and is shown in FIG.
The circuit shown in FIG. In addition, the EL display panel of this embodiment can be used as the display unit of the electronic device of the seventh embodiment.

[Embodiment 10] As the definition of pixels and the number of gradations increase, the suppression of the off-current value of the pixel TFT is an important item in manufacturing a high-quality display device. In the present embodiment, attention is paid to the off-state current value in two bias states, and the result of examining which TFT structure is suitable for suppressing the off-state current value is shown.

One of the defined off-current values is that the drain voltage (V _DS ) = 1 V and the gate voltage (V _GS ) = − 17.5.
This is represented by I (off) 1 with the off-current value at V. The other is an off-current value at a drain voltage (V _DS ) = 14 V and a gate voltage (V _GS ) = − 4.5 V, which is I (o).
ff) expressed as 2. The polarity of V _GS shown here is n-channel type T
This is for the FT, and has the opposite polarity in the case of the p-channel TFT. It is presumed that the band of I (off) 1 becomes sharp due to the high gate voltage, and the tunnel current is dominant in the flowing current. The magnitude of this current depends on the state of the interface between the gate insulating film and the semiconductor layer, the crystallinity of the semiconductor layer, and the like. On the other hand, it can be seen that I (off) 2 is a leak current determined by the state of the junction between the channel formation region and the source / drain region.

The manufacturing conditions of the TFT may be the same as those described in Example 1. However, the manufacturing conditions of Lov and Loff were changed as needed for comparison. FIGS. 21A and 21B show the results of examining the effect of Loff on the off-state current.
The characteristics of the TFT provided with Loff = 1.5 μm shown in FIG. 21A and the TF without Loff shown in FIG.
Even if the characteristics of T are compared, it is not recognized that the values of I (off) 1 and I (off) 2 have a significant difference. V for the same V _GS
A higher _DS means a higher leakage current.

FIG. 22 shows the result of studying the dependence of the off-state current on the drain structure. Focusing on the structure on the drain side, three types of samples having a single drain, Lov, and Lov and Loff are shown. FIG.
It is clear from the characteristics of the above that even if the sample having the single drain structure is omitted and considered, if Lov exists, Lof
The leak current does not change regardless of the presence or absence of f.

FIG. 23 shows the Lov dependence of the off current, and shows that the off current depends on the length of Lov. FIG. 24 is a result of comparing three samples in which Lov is provided only on the drain side, Lov is provided on both sides of the source / drain, and an offset region is provided on the drain side. It can be seen that the off current can be reduced by providing the offset region. I have.

As described above, it has been clarified that the off-state current is increased by the presence of Lov and depends on the length. Lov is necessary to suppress the hot carrier effect, but it is judged that a structure without Lov is suitable for a pixel TFT that does not require much drain withstand voltage and rather requires a small off-state current. it can. However, it is impossible to reduce the leak current with the single drain structure. To ensure long-term reliability,
In order to reduce the electric field concentrated near the drain, Loff
It was concluded that a method to optimize the concentration of was suitable. That is, with respect to the deterioration due to the hot carrier effect, an attempt was made to minimize the deterioration by optimizing the concentration of Loff.

An impurity concentration suitable for lowering I (off) 2 is, as shown in FIG. 25, 5 × 10 ^{12 to 2} × 10 ¹³ / cm ^2.
(Acceleration voltage: 80 keV).

As described above, when it is intended to reduce the off-state current, it has become clear that it is necessary to optimize the impurity concentration of Loff without providing Lov. Further, it was shown that the offset region was extremely effective for the purpose of reducing the off current.

[0145]

According to the present invention, in a semiconductor device in which a plurality of functional circuits are formed on the same substrate (specifically, an electro-optical device in this case) according to specifications required by the functional circuits. It is possible to arrange TFTs having appropriate performance, and the operating characteristics and reliability thereof can be greatly improved.

In particular, the LD of the n-channel TFT in the pixel portion
By forming the D region with n ⁻ concentration and only Loff, the off current value can be significantly reduced, which can contribute to lower power consumption of the pixel portion. Also, n of the driving circuit
When the LDD region of the channel type TFT is n ⁻ concentration and Lov
By increasing the current drive capability,
In addition, deterioration due to hot carriers can be prevented, and deterioration of the ON current value can be reduced. In addition, the operation performance and reliability of a semiconductor device (specifically, an electronic device in this case) having such an electro-optical device as a display medium can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a pixel portion and a driving circuit according to an embodiment.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a pixel portion and a driver circuit.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a pixel portion and a driver circuit.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of a pixel portion and a driver circuit.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a pixel portion and a driver circuit.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a pixel portion and a driver circuit.

FIG. 7 is a cross-sectional structural view of an active matrix liquid crystal display device.

FIG. 8 is a perspective view of an active matrix liquid crystal display device.

FIG. 9 is a top view of a pixel portion.

FIG. 10 is a circuit block diagram of an active matrix liquid crystal display device.

FIG. 11 illustrates a positional relationship between a gate electrode and an LDD region.

FIG. 12 illustrates a structure of an active matrix EL display device.

FIG. 13 is a cross-sectional view illustrating a manufacturing process of a pixel portion and a driver circuit.

FIG. 14 illustrates an example of a semiconductor device.

FIG. 15 illustrates an example of a semiconductor device.

FIG. 16 illustrates an example of a projector.

17A and 17B are a top view and a cross-sectional view illustrating a structure of an EL display device.

FIG. 18 is a cross-sectional view of a pixel portion of an EL display device.

FIG. 19 is a top view and a circuit diagram of a pixel portion of an EL display device.

FIG. 20 is an example of a circuit diagram of a pixel portion of an EL display device.

FIG. 21 is a graph showing the drain voltage dependence of off-state current.

FIG. 22 is a graph illustrating an effect of Loff on off-state current.

FIG. 23 is a graph illustrating Lov dependence of off-state current.

FIG. 24 is a graph illustrating an effect of an offset region on off-state current.

FIG. 25 is a graph illustrating dose dependency of an off-state current of an impurity element added to Loff.

[Explanation of symbols]

 Reference Signs List 201 substrate 202 base film 204 to 207 island-shaped semiconductor layer 208 gate insulating film 228 to 231 gate electrode 232 capacity wiring 248 cap layer 251 protective insulating film 252 interlayer insulating film 253 to 259 source or drain electrode 260 passivation film 261 second interlayer Insulating film 262 Pixel electrode

Claims (18)

[Claims] 1. A semiconductor device having a pixel portion and a driver circuit for the pixel portion over the same substrate, wherein an LDD region of an n-channel TFT of the pixel portion is connected to a gate electrode of the n-channel TFT of the pixel portion. The LDD region of the first n-channel TFT of the driving circuit is arranged so as not to overlap with the gate electrode of the first n-channel TFT, and the second n-channel TFT of the driving circuit is The LDD region of the TFT is disposed so as to at least partially overlap the gate electrode of the second n-channel TFT, and the channel formation region of the n-channel TFT of the pixel portion and the n-channel of the pixel portion A semiconductor device, wherein an offset region is formed between an LDD region of a type TFT. 2. A semiconductor device having a pixel portion and a driver circuit for the pixel portion over the same substrate, wherein the driver circuit includes a first n-channel provided so that an entire LDD region overlaps with a gate electrode. Type TFT and L
A second n-channel TFT provided so that a part of the DD region overlaps with the gate electrode; and the LDD region of the n-channel TFT forming the pixel portion is such that the entire LDD region is a gate electrode. An offset region is formed between a channel forming region of the n-channel TFT of the pixel portion and an LDD region of the n-channel TFT of the pixel portion. Semiconductor device. 3. The LDD region of the n-channel TFT of the pixel portion according to claim 1, wherein the LDD regions of the first n-channel TFT and the second n-channel TFT of the driving circuit are provided in the LDD region of the n-channel TFT of the pixel portion. A semiconductor device comprising an impurity element imparting n-type at a higher concentration than the impurity element. 4. The LDD region of the n-channel TFT of the pixel portion according to claim 1, wherein the LDD regions of the first n-channel TFT and the second n-channel TFT of the driving circuit are provided in the LDD region of the n-channel TFT of the pixel portion. 2. A semiconductor device comprising an impurity element imparting n-type at a concentration of 2 to 10 times the concentration of n. 5. The driving circuit according to claim 1, wherein the LDD regions of the first n-channel TFT and the second n-channel TFT of the driving circuit are 2 × 10 ^{16 to} 5 × 10 ^19.
An impurity element imparting n-type is contained in the concentration range of atoms / cm ³ , and the LDD region of the n-channel type TFT in the pixel portion has n concentration of 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ^3. A semiconductor device including an impurity element for imparting a mold. 6. The semiconductor device according to claim 1, wherein the offset region is formed of a semiconductor film having the same composition as a channel forming region in contact with the offset region. 7. An offset region according to claim 1, wherein said offset region contains a p-type impurity element in a concentration range of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ atoms / cm ^3. Semiconductor device. 8. The pixel portion according to claim 1, wherein the pixel portion includes a semiconductor layer including an impurity element which is connected to an n-channel TFT of the pixel portion and imparts n-type conductivity;
A semiconductor device, wherein a storage capacitor is formed by an insulating film between the semiconductor layer and a capacitor wiring. 9. The semiconductor device according to claim 1, wherein the semiconductor device is one selected from a mobile phone, a video camera, a mobile computer, a goggle type display, a projector, a mobile book, and a digital camera. A semiconductor device, characterized in that: 10. A method for manufacturing a semiconductor device having a pixel portion and a driving circuit for the pixel portion over the same substrate, wherein the active layers of the first and second n-channel TFTs forming the driving circuit have two layers. × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³
A first step of selectively adding an impurity element imparting n-type within a concentration range of 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm 2 in an active layer of a p-channel TFT forming the drive circuit. P in the concentration range of ³
A second step of selectively adding an impurity element for imparting a mold; an active layer of first and second n-channel TFTs forming the driving circuit; and an active layer of an n-channel TFT of the pixel portion. A third step of selectively adding an n-type impurity element in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ , and an active layer of an n-channel TFT in the pixel portion. Is selectively added with an impurity element imparting n-type in a concentration range of 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ through an insulating film covering at least a side surface of a gate electrode of the n-channel TFT. And a fourth step of manufacturing the semiconductor device. 11. A method for manufacturing a semiconductor device having a pixel portion and a driving circuit for the pixel portion on the same substrate, wherein: an active layer of first and second n-channel TFTs forming the driving circuit; A first step of selectively adding an n-type imparting impurity element in a concentration range of 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ to a semiconductor layer forming a storage capacitor in a pixel portion; In the active layer of the p-channel TFT forming the drive circuit, the p-type TFT is formed in a concentration range of 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ^3.
A second step of selectively adding an impurity element for imparting a mold; an active layer of first and second n-channel TFTs forming the driving circuit; and an active layer of an n-channel TFT of the pixel portion. A third step of selectively adding an n-type impurity element in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ , and an active layer of an n-channel TFT in the pixel portion. Is selectively added with an impurity element imparting n-type in a concentration range of 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ through an insulating film covering at least a side surface of a gate electrode of the n-channel TFT. And a fourth step of manufacturing the semiconductor device. 12. The method according to claim 10, wherein the n-channel type T of the pixel portion is formed by the fourth step.
A method for manufacturing a semiconductor device, wherein an n-type impurity region and an offset region sandwiched between the n-type impurity region and a channel formation region are formed in the FT. 13. A method for manufacturing a semiconductor device having a pixel portion and a driving circuit for the pixel portion over the same substrate, wherein the active layers of the first and second n-channel TFTs forming the driving circuit have two layers. × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³
A first step of selectively adding an impurity element imparting n-type within a concentration range of: and an insulating layer covering at least a side surface of a gate electrode of the n-channel TFT in the active layer of the n-channel TFT in the pixel portion. A second step of selectively adding an impurity element imparting n-type in a concentration range of 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ through a film; and a p-channel type for forming the drive circuit. the active layer of the TFT, p in a concentration range of ^{3 × 10 20 ~3 × 10 21} atoms / cm 3
A third step of selectively adding an impurity element for imparting a mold; an active layer of first and second n-channel TFTs forming the driving circuit; and an active layer of an n-channel TFT of the pixel portion. A fourth step of selectively adding an impurity element imparting n-type in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ^3. Method. 14. A method for manufacturing a semiconductor device having a pixel portion and a driving circuit for the pixel portion on the same substrate, wherein: an active layer of first and second n-channel TFTs forming the driving circuit; A first step of selectively adding an n-type imparting impurity element in a concentration range of 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ to a semiconductor layer forming a storage capacitor in a pixel portion; On the active layer of the n-channel TFT in the pixel portion, an n-type TFT having a concentration of 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ is provided via an insulating film covering at least the side surface of the gate electrode of the n-channel TFT. A second step of selectively adding an impurity element for imparting an impurity to the active layer of the p-channel TFT forming the driving circuit, in a concentration range of 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ^3.
A third step of selectively adding an impurity element for imparting a mold; an active layer of first and second n-channel TFTs forming the driving circuit; and an active layer of an n-channel TFT of the pixel portion. A fourth step of selectively adding an impurity element imparting n-type in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ^3. Method. 15. The method according to claim 13, wherein
By the second step, the n-channel type T
A method for manufacturing a semiconductor device, wherein an n-type impurity region and an offset region sandwiched between the n-type impurity region and a channel formation region are formed in the FT. 16. The method according to claim 12, wherein
A method for manufacturing a semiconductor device, wherein the offset region is formed in a self-aligned manner using an insulating film covering a gate electrode of an n-channel TFT as a mask. 17. The method of claim 10, claim 11, claim 13,
15. The method for manufacturing a semiconductor device according to claim 14, wherein the thickness of the insulating film is 20 to 100 nm. 18. The semiconductor device according to claim 10, wherein the semiconductor device is a mobile phone, a video camera, a mobile computer, a goggle type display,
A method for manufacturing a semiconductor device, which is one selected from a projector, a portable book, and a digital camera.