JPH10240164A - Driving circuit integrated type display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a voltage per unit length in a channel area and improve a dielectric withstand voltage by making a channel length of a thin film transistor composing a buffer circuit included in a scanning drive circuit longer than that of a thin film transistor composing a buffer circuit included in a signal line drive circuit. SOLUTION: In the periphery of a display area, a signal line drive circuit 1 and a scanning line drive circuit 2 are arranged, and the signal line drive circuit 1 is constituted of a timing generation circuit 10, etc., comprising a buffer circuit, and the scanning line drive circuit 2 is constituted of a buffer circuit 3. A CMOS circuit included in the scanning line drive circuit 2 and a CMOS circuit included in the signal line drive circuit 1 are formed on a glass substrate through a same process. If a channel length of a TFT in the buffer of the scanning line drive circuit 2 is formed two times longer than that of the buffer of the signal drive circuit 1, a voltage per unit length applied across the source and drain of TFT is reduced, and it possible to improve a dielectric withstand voltage of the drain.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat display device such as a liquid crystal display device, and more particularly to an active matrix liquid crystal display device in which a pixel switching element and a driving circuit are formed on the same substrate using a polycrystalline silicon thin film transistor. About.

[0002]

2. Description of the Related Art In recent years, in order to increase the effective display area and reduce the cost of an active matrix type liquid crystal display device, a technology for incorporating a drive circuit on an active matrix substrate on which pixel electrodes are formed has been developed. I have. In order to simultaneously form not only the switching element of the pixel electrode but also the driving circuit, a high-performance switching element is required. For example, a thin film transistor (Thin Film Transistor,
(Hereinafter referred to as TFT).

Generally, in a conventional liquid crystal display device integrated with a driving circuit, a scanning line driving circuit for driving a scanning line is a serial / parallel conversion circuit comprising a shift register and a buffer circuit for amplifying the output of the circuit and outputting it to the scanning line. The signal line driving circuit for driving one signal line includes a serial-parallel conversion circuit including a shift register and a sampling circuit, and a buffer circuit for amplifying the output of the circuit and outputting the amplified signal to the signal line.

By the way, a video signal having an amplitude of, for example, 5 V which gives a gradation to liquid crystal is applied to a signal line, and a scanning signal having an amplitude of, for example, 20 V which controls a gate of a TFT is applied to a scanning line. Therefore, the scanning line driving circuit generates a signal having a larger amplitude than the signal line driving circuit.

[0005]

However, in the conventional driving circuit integrated type display device, the drain withstand voltage of the TFT constituting the buffer circuit included in the scanning line driving circuit is not sufficient, and the TFT is damaged during operation. As a result, a required scanning signal cannot be obtained, and a defect that a video signal cannot be displayed is caused.

Further, while the scanning line driving circuit operates in a horizontal scanning cycle, the signal line driving circuit needs to operate at a considerable speed since the video signal input from the outside is serial-parallel converted during one horizontal scanning period. There is.

On the other hand, in the conventional driving circuit integrated type display device, the configuration of the scanning line driving circuit and the signal line driving circuit has not been optimized. SUMMARY OF THE INVENTION In view of the above technical background, it is an object of the present invention to provide a drive circuit integrated type display device in which the withstand voltage of a scan line drive circuit is improved and a desired operation speed of a signal line drive circuit can be obtained.

[0008]

Means for Solving the Problems The first invention of the present invention is:
The channel length of a thin film transistor included in a buffer circuit included in a scan line driver circuit is longer than the channel length of a thin film transistor included in a buffer circuit included in a signal line driver circuit.

By employing this configuration, the channel length of the thin film transistor is determined on the signal line drive circuit side so as to obtain a desired operation speed, while the distance between the source and the drain is increased on the scan line drive circuit side. By doing so, it is possible to reduce the voltage applied per unit length of the channel region and improve the breakdown voltage.

According to a second aspect of the present invention, a unit switch element constituting a buffer circuit included in a scanning line drive circuit is constituted by a plurality of thin film transistors connected in series,
On the other hand, a unit switch element included in a buffer circuit included in a signal line driver circuit is formed using a smaller number of thin film transistors than switch elements of a scan line driver circuit.

That is, while the buffer circuit of the signal line driving circuit is formed of a predetermined thin film transistor, in the scanning line driving circuit, a portion corresponding to a single thin film transistor on the signal line driving circuit side is connected in series with a plurality of thin film transistors. It consists of. By employing this configuration, the channel length of the thin film transistor is determined so that a desired operation speed is obtained on the signal line driving circuit side, while the substantial distance between the source and the drain is increased in the scanning line driving circuit. Voltage can be reduced per unit length of the channel region, and the withstand voltage can be improved.

According to a third aspect of the present invention, a thin film transistor constituting a buffer circuit included in a scanning line driving circuit is connected so that its channel region is connected to a drain region via a region having a lower impurity concentration than the drain region. And a thin film transistor in a buffer circuit included in the one signal line driving circuit is configured such that a channel region and a drain region are directly connected.

By adopting this configuration, the channel length of the thin film transistor is determined on the signal line driving circuit side so as to obtain a desired operation speed, while the source-drain voltage is reduced on the scanning line driving circuit side by this low efficiency. Therefore, the voltage applied to the channel region per unit length can be reduced, and the breakdown voltage can be improved.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit block diagram of an array substrate of a drive circuit integrated type active matrix type liquid crystal display device in this embodiment.

In the display area 14 of the glass substrate 3, a plurality of signal lines 6 and scanning lines 8 are arranged orthogonally to each other, and a pixel electrode 17 is connected to each intersection via a TFT 4. The pixel electrode 17 is capacitively coupled to the opposing electrode 18 via the liquid crystal to form a liquid crystal capacitance Clc.

Around the display area 14, a signal line driving circuit 1 for driving the signal lines 6 and a scanning line driving circuit 2 for driving the scanning lines are arranged. Signal line drive circuit 1
Is a timing signal generating circuit 10 comprising a shift register and a buffer circuit connected to the shift register; and an analog switch 11 controlled by the output of the timing signal generating circuit 10 for serial-parallel conversion of an externally input video signal. Consists of On the other hand, the scanning line drive circuit 2 includes a serial-parallel conversion circuit 12 including a shift register and a buffer circuit 13 connected to the shift register.

A shift register included in the serial-parallel conversion circuit 10 of the signal line driving circuit 1 generates a timing signal based on a clock XCK and a start pulse XST input from the outside, and a sample-hold circuit generates a timing signal based on the timing signal. Video signal VIDEO input from outside
Is sampled.

On the other hand, a signal obtained by converting a clock YCK and a start pulse YST input from the outside so as to have a predetermined amplitude via level shift circuits 15 and 16 is input to the shift register of the scanning line drive circuit 2. At this time, the start pulse is set to 2 necessary to drive the scanning line 8.
The amplitude is adjusted to 0 V, and the shift register sequentially transfers the start pulse to the next stage based on the clock timing, and drives the scanning line 8.

FIG. 2 shows an example of the buffer circuit. The buffer circuit is a known CMOS circuit, that is, an n-ch TFT 10.
2 and a p-ch TFT 101. The input IN of this buffer circuit is connected to the outputs of the serial-parallel conversion circuits 10 and 12, while the output OUT of the buffer circuit is connected to the individual signal lines 6 or scanning lines 12.

The shift registers included in the serial / parallel conversion circuits 10 and 12 are also basically constituted by clocked inverters using this CMOS circuit. FIG.
FIG. 2 shows a cross-sectional view of a main part of an array substrate. For the sake of explanation, the scanning line driving circuit region and the signal line driving circuit region are illustrated in parallel. As shown in the figure, the pixel driving TFT 25 in the display area, the n-ch TFT 23 and the p-ch TFT 2 forming the CMOS circuit included in the scanning line driving circuit 2
4. The n-ch TFT 203 and the p-ch TFT 204 constituting the CMOS circuit included in the signal line driving circuit 1 are formed on the glass substrate 22 in the same step. The channel region 28, source region 32, and drain region 33 of each TFT are formed of a polycrystalline silicon thin film. Here, the channel width (W) / channel length (L) of the TFT forming the shift register of the signal line driving circuit is 10 μm / 5 μm, and the TFT forming the shift register of the scanning line driving circuit.
Is 10 μm / 10 μm. Similarly, the channel length of the TFT in the buffer of the scanning line driving circuit was set to be twice as long as that of the buffer of the signal line driving circuit.

Next, a method of manufacturing the liquid crystal display device of the above embodiment will be described. On one main surface of the transparent insulating substrate 26, an amorphous silicon thin film 27 is
After the formation of m, the amorphous silicon thin film 27 is polycrystallized using a XeCl excimer laser annealing apparatus. Next, the polycrystalline silicon film 27 is patterned using a photolithography method to form an active layer 28 of the TFT. After a gate insulating film 29 made of a silicon oxide film or a silicon nitride film is formed by a plasma CVD method, a molybdenum
A tungsten alloy film (MoW) is formed by a sputtering method,
The gate electrode 30 is formed by patterning. At this time, a storage capacitor electrode 31 and a scanning line and a storage capacitor line (not shown) are formed simultaneously with the gate electrode 30. Thereafter, impurities are implanted by ion doping using the gate electrode 30 as a mask to form a source region 32 and a drain region 33 of the TFT. As an impurity, for example, phosphorus having an area density of 5 × 10 15 / cm 2 is used for an n-type TFT and p-type
Boron was used for FT. Next, on the gate electrode 30
Then, an interlayer insulating film 34 of a silicon oxide film is formed by a plasma CVD method, and an ITO film is further formed thereon and patterned to form a pixel electrode 35. A part of the pixel electrode 35 is opposed to the storage capacitor electrode 31 via the interlayer insulating film 34 to form a storage capacitor. Further, the gate electrode is formed of two layers of MoW film, the first layer of MoW film before ion doping is not formed at the position where the storage capacitor is formed, and the underlying polycrystalline silicon film is doped with impurities to form n.
Alternatively, a storage capacitor may be formed with a storage capacitor electrode formed only of the second layer MoW film. Next, after forming contact holes in the interlayer insulating film 34 and the gate insulating film 29,
A source electrode 36 and a drain electrode 37 are formed simultaneously with a signal line (not shown) by forming and patterning an Al film by a sputtering method. Subsequently, an insulating protection film 38 of a silicon nitride film is formed over the entire surface, and is patterned into a predetermined pattern to form the active matrix substrate 22.

On the other hand, on one main surface of the transparent insulating substrate 39,
Black matrix 40, colored layer 41, and ITO
An opposing electrode 42 made of a transparent conductive film was formed, and an opposing substrate 43 was obtained. Alignment films 44 and 45 made of a low-temperature curing type polyimide film are applied to the pixel electrode side of the active matrix substrate 22 and the counter electrode side of the counter substrate 43. Rubbing treatment is performed so that the orientation axis becomes 90 degrees when these substrates are arranged facing each other, the two substrates are assembled to face each other to form a cell, and a nematic liquid crystal 46 is injected into the gap therebetween and sealed. Furthermore, polarizing plates were stuck on both sides of the cell to produce an active matrix liquid crystal display.

When such a liquid crystal display device was operated and inspected, there was no display defect due to a defect in the drive circuit.
High yield was obtained. That is, in a scanning line driving circuit requiring a high withstand voltage, a voltage per unit length applied between the source and the drain of the TFT can be reduced by increasing the channel length, and the drain withstand voltage can be increased. On the other hand, the signal line driver circuit is configured by a TFT having a channel length that is half of the TFT included in the scanning line driver circuit, so that a sufficient ON current can be obtained, and therefore, a high-speed operation can be performed.

(Embodiment 2) FIG. 4 is a sectional view showing a main part of an array substrate in a second embodiment of the active matrix type liquid crystal display device of the present invention. That is, in the scanning line driving circuit 2, each of the p-ch TFT 23 and the n-ch TFT 24 is configured by thin film transistors Tr1 and Tr2 whose source (drain) regions are coupled to each other, while in the signal line driving circuit, a CMOS circuit is used. Single pc
It comprises an hTFT 203 and an n-ch TFT 204.

In the above configuration, when the drain withstand voltage characteristic with respect to the sum of the channel length L1 of Tr1 and the channel length L2 of Tr2 was examined, the characteristic 50 in FIG. 3 was obtained. Compared with the characteristic 51 of the TFT having the normal structure, in this embodiment, L1 and L1
Even if the sum of 2 was equal to or shorter than L of a normal TFT, a sufficiently high breakdown voltage was obtained.

On the other hand, in the signal line driving circuit, a single T
Since a CMOS circuit is configured by FT, a sufficient ON current can be obtained. (Embodiment 3) FIG. 6 is a schematic sectional view showing a third example. In the same manner as in the embodiment of the first example, impurities are implanted by ion doping using the gate electrode as a mask, and TF
After forming the source / drain regions of T, the gate electrode was further patterned so as to be thinner by a certain amount, and low-concentration impurities were implanted again. As described above, an n type impurity region 52, 53 having a concentration lower than the impurity concentration of the drain region or the source region by dL in the channel direction is provided between the channel region and the drain region and between the channel region and the source region. TFTs 54 and 55 were formed. Since other configurations and manufacturing methods are common to the first example, the same portions are denoted by the same reference numerals and description thereof will be omitted.

By adopting such a TFT structure,
The voltage between the drain electrode and the source electrode was reduced by the voltage drop caused by the low-efficiency impurity region, and the drain withstand voltage obtained by the experiment was improved as shown by the characteristic 56 in FIG. It is clear from FIG. 7 that increasing dL is effective, and sufficient withstand voltage was obtained by increasing dL on the scanning line driving circuit side which requires a higher withstand voltage than the signal line driving circuit side. . In the present embodiment, in addition to using this structure for the n-type TFT of the drive circuit,
5 to further suppress the leak current when the scanning signal is off.

On the other hand, in the signal line driving circuit, since the low-efficiency impurity region is not provided, the resistance when the TFT is ON can be reduced, and more current can flow, so that the operation can be performed at high speed. Was. The same effect can be obtained by providing a low-concentration impurity region shorter than the scanning line driving circuit side.

In this embodiment, a low-concentration impurity region is provided only in the n-ch TFT of the scanning line driving circuit. The reason for this is that the p-ch TFT uses holes as carriers, so that the limitation on the drain withstand voltage is less strict than that of the n-ch TFT. P-chT if necessary
It goes without saying that a low-concentration impurity region may be provided in the FT.

It is also effective to combine this structure with the selection of the channel length as shown in the first embodiment. Further, when the structure shown in the second embodiment is also used in this structure, the withstand voltage is further improved as shown by the characteristic 57 in FIG.

The present invention is not limited to the above example, but can be implemented by improving the breakdown voltage by combining the respective embodiments up to the breakdown voltage required from the driving voltages of various liquid crystal display devices.

For example, in the above embodiment, the method of each embodiment is applied to all the TFTs constituting the shift register and the buffer circuit of the scanning line drive circuit. However, as shown in FIG. When 300 is provided at the subsequent stage of the shift register, since YST and YCK having a small amplitude (for example, 10 V amplitude) are input to the shift register, only TFTs after the buffer circuit whose amplitude is adjusted by the level shift circuit are Each of the above embodiments may be applied. As the timing signal generating circuit, a decoder circuit may be used instead of the shift register.

[0033]

According to the present invention, it is possible to obtain a driving circuit integrated type display device in which the withstand voltage of the scanning line driving circuit is improved and a desired operation speed of the signal line driving circuit is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a circuit board of a liquid crystal display device integrated with a driving circuit according to an embodiment of the present invention.

FIG. 2 shows an example of a buffer circuit in the embodiment of FIG.

FIG. 3 is a sectional view of a main part of the liquid crystal display device in the embodiment of FIG.

FIG. 4 is a sectional view showing a main part of a drive circuit integrated type liquid crystal display device according to another embodiment of the present invention.

FIG. 5 shows a characteristic diagram of the driving circuit TFT in FIG.

FIG. 6 is a sectional view showing a main part of a drive circuit integrated type liquid crystal display device according to still another embodiment of the present invention.

FIG. 7 shows characteristic vinegar of the driving circuit TFT in FIG.

FIG. 8 is a block diagram showing a circuit board of a liquid crystal display device with an integrated drive circuit according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Signal line drive circuit 2 ... Scan line drive circuit 6 ... Signal line 8 ... Scan line 10, 12 ... Serial-parallel conversion circuit 11,13 ... Buffer circuit 23,25 ... N-type TFT 24 ... P-type TFT

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yoshiro Aoki 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Inside the Toshiba Yokohama office

Claims (3)

[Claims] A plurality of scanning lines and signal lines arranged on one main surface so as to intersect with each other, a pixel thin film transistor arranged corresponding to an intersection of the scanning line and the signal line, and a pixel thin film transistor A pixel electrode connected to the signal line, a timing signal generation circuit, a first buffer circuit connected to the pixel electrode, and a video signal input from the outside based on the output of the first buffer circuit are serially parallelized. A signal line drive circuit including a serial / parallel conversion circuit including an analog switch for conversion; a serial / parallel conversion circuit for serial / parallel conversion of an externally input scan signal; and a signal line for supplying an output of the serial / parallel conversion circuit to the scan line. An active matrix type substrate including a scanning line driving circuit including two buffer circuits; and a counter electrode disposed on the inner surface of the active matrix type substrate and facing the active matrix substrate. An opposing substrate having an opposing electrode formed therein, wherein the first buffer circuit and the second buffer circuit include a thin film transistor formed in the same process as the pixel thin film transistor, and Wherein the channel length of the thin film transistor is longer than the channel length of the thin film transistor in the second buffer circuit. 2. A plurality of scanning lines and signal lines arranged on one main surface so as to intersect with each other, a pixel thin film transistor arranged corresponding to an intersection of the scanning line and the signal line, and a pixel thin film transistor. A pixel electrode connected to the signal line, a timing signal generation circuit, a first buffer circuit connected to the pixel electrode, and a video signal input from the outside based on the output of the first buffer circuit are serially parallelized. A signal line driving circuit including a serial / parallel conversion circuit including an analog switch for conversion; a serial / parallel conversion circuit for serial / parallel conversion of a scanning signal input from the outside; An active matrix substrate provided with a scanning line driving circuit including a second buffer circuit, which is disposed opposite to the active matrix substrate, and facing an inner surface of the active matrix substrate. An opposing substrate having an opposing electrode on which a pole is formed, wherein the first buffer circuit and the second buffer circuit include a unit switching element manufactured in the same process as the pixel thin film transistor, and The unit switching element in the buffer circuit is composed of a plurality of thin film transistors connected in series, and the unit switching element in the second buffer circuit is a single thin film transistor or a unit switching element in the first buffer circuit. A drive circuit integrated display device comprising a smaller number of thin film transistors connected in series to each other. 3. A plurality of scanning lines and signal lines arranged on one main surface so as to intersect with each other, a pixel thin film transistor arranged corresponding to an intersection of the scanning line and the signal line, and a pixel thin film transistor. A pixel electrode connected to the signal line, a timing signal generation circuit, a first buffer circuit connected to the pixel electrode, and a video signal input from the outside based on the output of the first buffer circuit are serially parallelized. A signal line driving circuit including a serial / parallel conversion circuit including an analog switch for conversion; a serial / parallel conversion circuit for serial / parallel conversion of a scanning signal input from the outside; An active matrix substrate provided with a scanning line driving circuit including a second buffer circuit, which is disposed opposite to the active matrix substrate, and facing an inner surface of the active matrix substrate. An opposing substrate having an opposing electrode on which a pole is formed, wherein the first buffer circuit and the second buffer circuit include a thin film transistor formed in the same process as the pixel thin film transistor, and the first buffer The thin film transistor in the circuit has its channel region connected to the drain region via a region with a lower impurity concentration than the drain region,
The thin film transistor in the second buffer circuit has a channel region and a drain region directly connected to each other or connected via a low-concentration impurity region shorter than the thin film transistor in the first buffer circuit. Circuit integrated display device.