JPH08220505A - Liquid crystal display - Google Patents

Abstract

PURPOSE: To improve reliability as well as display quality by setting a silicon thin film transistor constituting a level converter of high power supply voltage, to a high pressure resistance structure. CONSTITUTION: In a drain side drive circuit part, a shaft resistor RD and a level converter CD are driven by separate system power source systems, and power supply voltage VddL of the shift resistor RD is less than the power source voltage VDddH of the level converter CD. Though the shift resistor RD is composed of a complementary structure of n-ch and p-ch of p-siTFT, its low voltage drive prevents the deterioration of the characteristics. On the other hand, through the level converter CD is also composed of a complementary structure of n-ch and p-ch of p-siTFT, as for n-chTFT, a so-called low-concn. drain structure in which a low concn. region is interposed between a source and drain region formed by doping impurity therein highly concentratively and a channel region without doping is adapted to improve voltage resistance in high-voltage drive.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a liquid crystal display device (LC
D: Liquid Crystal Display), and more particularly to a drive circuit built-in type LCD in which a drive circuit unit is integrally formed on a substrate similarly to a display pixel unit.

[0002]

2. Description of the Related Art LCDs have advantages such as small size, thin shape and low power consumption, and are being put to practical use in fields such as OA equipment and AV equipment. In particular, an active matrix type using a thin film transistor (TFT) as a switching element has a duty ratio of 100 in principle.
Percentage static drive can be performed in multiplex, and it is used for large-screen and high-definition video displays.

The active matrix LCD is a substrate (TFF substrate) in which TFTs are connected to display electrodes arranged in a matrix (TFF substrate) and a substrate having a common electrode (counter substrate).
However, it is configured by laminating the liquid crystal in between. The opposing portion of the display electrode and the common electrode serves as a pixel capacitor having a liquid crystal as a dielectric layer, and a voltage selected by the TFT is applied. The liquid crystal has electro-optical anisotropy and modulates light in response to an electric field formed by the pixel capacitance.

In recent years, p-S has been used as a channel layer of TFT.
LCD having a built-in drive circuit in which the matrix pixel section and the peripheral drive circuit section are formed on the same substrate by using i
Is being developed. In general, p-Si has higher mobility than a-Si, and miniaturization by a gate self-aligned structure and speedup by reduction of parasitic capacitance are achieved.
A high-speed drive circuit can be formed by forming a complementary structure of the -ch TFT and the p-ch TFT. Thus, by integrally forming the drive circuit unit and the matrix pixel unit, the manufacturing cost can be reduced and the LCD module can be downsized.

FIG. 11 shows the structure of such an LCD.
The part surrounded by the dotted line in the center is the matrix pixel part, and the gate line (G
1 to Gm) and drain lines for pixel signals (D1 to Dm)
n) are arranged to intersect. At each intersection, a TFT and a display electrode (not shown) connected to the TFT are formed. Gate drivers (GD) for selecting gate lines (G1 to Gm) are arranged on the left and right of the pixel portion, and video signals are sampled on the upper and lower portions of the pixel portion and further synchronized with the scanning of the gate driver (GD). A drain driver (DD) for applying a pixel signal voltage is arranged on each drain line (D1 to Dn). These drivers (GD, DD) are mainly composed of a shift register and a level converter for boosting the output of the shift register, and the like, and these are constituted by the complementary structure of n-ch and p-ch of p-Si TFT.

FIG. 12 shows the structure of such a p-Si TFT. On a substrate (10) such as high heat resistant quartz glass, p-Si (11) is formed by atmospheric pressure CVD at about 600 ° C.
Are formed and patterned in an island shape. p-Si
On top of (11), a gate insulating film such as SiO2 (12)
Is coated. On the gate insulation film (12), there is a gate electrode (13) obtained by doping p-Si formed by atmospheric pressure CVD to a high n-type concentration to reduce the resistance and patterning this. An injection stopper (14) is formed on the gate electrode (13) by laminating an insulating film that blocks the injection of impurities of another conductivity type. Also,
The p-Si (11) has a self-aligned structure using the gate electrode (13) as a mask, and has n-type or p-type source / drain regions (11S, 11D).
A non-doped channel region (11N) is formed. The entire surface is covered with an interlayer insulating film (15) such as SiNx, and source and drain electrodes (16S, 16D) made of Al are provided on the interlayer insulating film (15),
The source / drain regions (11S, 11D) are connected to each other through contact holes (CT). Although not shown, a display electrode made of ITO is formed in the pixel portion and connected to the source electrode (16S), and a predetermined connection is formed with the interlayer insulating film in the drive circuit portion.

[0007]

Generally, the video signal input to the LCD module is 12 to 16 [V],
The drain driver also has a structure that can support this.
It is driven by a power supply voltage of [V] or higher. On the other hand, the gate driver requires a power supply voltage of 15 to 30 [V].

Since the shift register on the drain side requires a speed several hundred times higher than that on the gate side, the driving ability can be improved by applying the scaling rule, that is, by reducing the device size, voltage, and current at a constant ratio. Further, a level converter is provided as necessary to sufficiently widen the voltage range applied to the liquid crystal. Even if the level converter is not provided, it is necessary to increase the output voltage of the shift register to obtain a predetermined voltage range, and a high power supply voltage is required.

In order to improve the display characteristics as described above, a high power supply voltage is required. At the same time, however, the characteristics such as the transconductance and the change of the threshold value of the TFTs forming the driving circuit portion are deteriorated, and the reliability is improved. It is unavoidable that the display characteristics deteriorate, and it is difficult to achieve both display characteristics and reliability. In addition, the substrate (1
When an inexpensive glass substrate is used as 0), the process temperature cannot be increased to 600 ° C. or higher, and laser annealing is also used to accelerate the generation of Si crystal grains in order to increase the mobility. Since the laser beam irradiation is performed while scanning the entire surface of the substrate, the throughput is significantly reduced. Therefore, the throughput is improved by decreasing the scanning speed of the peripheral drive circuit section in which the TFTs are densely arranged and increasing the scanning speed of the pixel section, but on the other hand, the mobility of the pixel section is decreased and the driving voltage range of the liquid crystal is reduced. Has been narrowed, which causes a problem such as a decrease in contrast ratio.

[0010]

SUMMARY OF THE INVENTION The present invention has been made to solve this problem. First, a gate line group and a drain line group arranged on a substrate so as to intersect with each other, and at each intersection thereof. A formed thin film transistor group and a drive circuit unit for driving the gate line and the drain line, and the drive circuit unit for driving the drain line is composed of a polycrystalline silicon thin film transistor, and is connected to the drain line according to an input signal. A shift register unit that controls a sampling operation of a signal voltage to be applied, and
In a liquid crystal display device including a level converter unit that amplifies an output signal of the shift register, the level converter is driven by a power supply voltage higher than that of the shift register, and a polycrystalline silicon thin film transistor that constitutes the level converter, The withstand voltage is set higher than that of the polycrystalline silicon thin film transistor forming the shift register.

Secondly, a thin film transistor group formed at each intersection of the gate line group and the drain line group arranged on the substrate so as to intersect with each other, and a driving circuit section for driving the gate line and the drain line. Further, the drive circuit unit for driving the gate line is composed of a polycrystalline silicon thin film transistor, a shift register unit for applying a scanning signal to the gate line, and a level converter unit for amplifying an output signal of the shift register. In the liquid crystal display device having, the level converter is driven by a power supply voltage higher than that of the shift register, and the polycrystalline silicon thin film transistor forming the level converter is more than the polycrystalline silicon thin film transistor forming the shift register. Withstand voltage is high

Thirdly, in the first or second configuration,
The level converter includes a first n-type polycrystalline silicon thin film transistor having an input signal gate-input and a source connected to GND, a second n-type polycrystalline silicon thin film transistor having an inverted input signal gate-input and a source connected to GND, The drain of the second n-type polycrystalline silicon thin film transistor is input to the gate and the drain is connected to the first n-type polycrystalline silicon thin film transistor.
Of a first p-type polycrystalline thin film transistor in which the source is connected to a high-voltage power source in common with the drain of the first polycrystalline silicon thin film transistor, and the first n-type polycrystalline silicon thin film transistor and the first p-type polycrystalline thin film transistor A drain signal is input to the gate, the source is connected to a high-voltage power supply, and the drain is commonly output as the drain of the second n-type polycrystalline silicon thin film transistor.
The first n-type polycrystalline silicon thin film transistor is configured to have a high breakdown voltage.

Fourthly, in the third structure, the first n-type polycrystalline silicon thin film transistor is in contact with opposite sides of the heavily doped source and drain regions, respectively, to form a non-doped channel region. A low-doped region is interposed between the two.

[0014]

In the first and second configurations, by lowering the drive power supply voltage of the shift register, the characteristic deterioration of the polycrystalline silicon thin film transistor forming the shift register can be prevented and the reliability can be improved. Further, by increasing the drive power supply voltage of the level converter, it is possible to sufficiently widen the voltage range applied to the liquid crystal and improve the display characteristics.

Further, it becomes possible to apply the scaling law to the polycrystalline silicon thin film transistors forming the shift register, that is, to reduce the device size, voltage, and current at a fixed ratio, which makes it possible to enhance the driving capability and miniaturize the device. By doing so, the drive circuit unit is downsized. Further, the polycrystalline silicon thin film transistor that constitutes the level converter having a high power supply voltage has a high withstand voltage structure, whereby the display quality and the reliability are improved.

Also, in the case of laser annealing in a lower temperature process, the driving voltage range can be made sufficiently large, so that the display quality is not deteriorated even if the mobility of the pixel portion is lowered. Therefore, it is possible to improve the throughput by spending the irradiation time only on the peripheral drive circuit portion where the polycrystalline silicon thin film transistors are densely arranged.

In the third configuration, the L-level is applied to the gate of the second p-type polycrystalline silicon thin film transistor which is turned on by the input signal of the H-level and connected to the source, and the second p-type polycrystalline silicon is applied. The withstand voltage of the entire level converter can be increased by increasing the withstand voltage of the first n-type polycrystalline silicon thin film transistor, which outputs the H level from the high voltage power source connected to the source of the thin film transistor. That is, the first n-type polycrystalline silicon thin film transistor is turned off by the L level input signal from the shift register and turned on by the inverted input signal during the period occupying most of the entire driving period. n
The L level is applied to the gate of the first p-type polycrystalline silicon thin film transistor from the GND connected to the source of the type polycrystalline silicon thin film transistor to turn it on, and the drain is set to the H level from the high voltage power source connected to the source. Therefore, the first n-type polycrystalline silicon thin film transistor is in a state in which a voltage is applied between the source and the drain during OFF. In particular, since the level converter is driven by a power supply voltage higher than that of the shift register, the first n-type polycrystalline silicon thin film transistor that constitutes the level converter has a channel portion that is higher than any other element in the drive circuit portion. Is in a state where a strong electric field is applied,
The characteristics are easy to change. Therefore, by increasing the withstand voltage of only the first n-type polycrystalline silicon thin film transistor, the withstand voltage of the entire drive circuit portion is increased, and the element formation area and the drive capability which are inevitable in the structure for realizing the high withstand voltage are obtained. Also, problems such as a decrease in drive speed are minimized. Therefore, the display quality and reliability are improved, and the device is downsized.

In the fourth structure, the first n-type polycrystalline silicon thin film transistor is brought into contact with the opposite side of the heavily doped source and drain regions, and the lightly doped region is interposed. , Withstand voltage is increased.

[0019]

EXAMPLES Next, the present invention will be described in detail based on examples. FIG. 1 shows the configuration of the drive circuit section on the drain side. Output of the sample-hold circuit (SH) that samples the input video signal and applies it to the drain line of the pixel section, the shift register (RD) that controls the sampling operation of the sample-hold circuit (SH), and the shift register (RD) It is composed of a level converter (CD) for amplifying. The shift register (RD) and the level converter (CD) are driven by separate power supply systems, and the power supply voltage VddL of the shift register (RD) is lower than the power supply voltage VDddH of the level converter (CD).

On the other hand, the structure of the drive circuit section on the gate side is shown in FIG.
, A shift register (RG) for applying a scanning signal to the gate line of the pixel portion, and a shift register (R
It is composed of a level converter (CG) that amplifies the output of G). Also in this case, the shift register (RG) and the level converter (CG) are driven by the power supply system of different systems, and the power supply voltage VddL of the shift register (RG) is smaller than the power supply voltage VddH of the level converter (CG).

The shift registers (RD, RG) are p-Si.
Although it is composed of a complementary structure of n-ch and p-ch of the TFT, the characteristics are prevented from being deteriorated because it is driven by a low voltage. Further, scaling is performed to enhance the driving capability and miniaturization of the driving circuit unit is performed. On the other hand, the level converter (CD, CG) is also p-
The n-ch TFT is composed of a complementary structure of n-ch and p-ch of SiTFT. However, in order to improve the breakdown voltage in high voltage driving, the n-chTFT has a source and a source formed by doping impurities at a high concentration. A so-called low-concentration drain (LDD: Lightly) in which a low-concentration region is interposed between the drain region and the non-doped channel region.
Doped Drain) structure is adopted. That is, by interposing the low-concentration region (LD) to relax the strong electric field near the interface between the source and the channel and between the drain and the channel, the hot carrier phenomenon is prevented and the breakdown voltage is improved.

As a result, the upper limit of the drain signal voltage range applied to the liquid crystal is made sufficiently high, and the amplitude of the gate signal voltage for controlling ON / OFF of the TFT for selecting the drain signal voltage correspondingly is increased. A larger configuration is possible. The contrast ratio can be improved by expanding the voltage range applied to the pixel portion. FIG. 3 shows an equivalent circuit diagram of a level converter (CD, CG) that boosts the output of each stage of the shift register (RD, RG) shown in FIGS. 1 and 2. A second n-ch TFT (2) that connects the source to GND and is turned on by an inverted input signal from the shift register to output L level, and the source to the high power supply voltage V
Second pc connected to ddH and related to H level output
The second p-chT is turned on by the input signal from the shift register by connecting the hTFT (4) and the source to GND.
A first n-ch TFT (1) that applies an L level to the gate of FT (4) to output an H level, and a second n-ch TFT (2) whose source is connected to a high power supply voltage VddH.
Is turned on by the L level output from the second p-chTF
Second p-ch for applying H level to the gate of T (4)
It consists of a TFT (4).

The input (in) from the shift register is at the L level except for the period when the duty ratio is several hundredths. That is, the second n-ch TFT (2) is turned on and the L level is output by the inverted input signal of the H level for most of the driving period. This L level is the first p-chT
The first p-ch TFT is input to the gate of FT (3).
(3) is turned on, and the first n-c from the high power supply voltage VddH.
H level is led to the drain common to hTFT (1),
Further applied to the gate of the second p-ch TFT (4),
Turn it off. At this time, the first n-ch TFT
(1) is OFF due to the L level input signal, a large voltage is applied between the source and drain, and a strong electric field exists in the channel. Such an element is likely to cause deterioration of element characteristics such as a decrease in mutual conductance and a change in threshold voltage.

In particular, the power supply voltage VddH of the level converter
Is higher than the power supply voltage VddL of the shift register, as shown in FIG.
The sample-hold circuit (SH) on the drain side shown by is also composed of an n-ch p-SiTFT, but in the sampling and holding operation of the video signal, it is as large as the complementary structure described above. An electrostatic field is rarely generated over a long period of time. That is, p-SiT
In an LCD with a built-in drive circuit using an FT, the element that is most likely to deteriorate is the first n element that constitutes the level converter.
-ChTFT (1).

Therefore, in the present invention, the first n-ch TF
By increasing the breakdown voltage of T (1), the breakdown voltage of the entire drive circuit portion is efficiently increased, and the reliability of the device is improved. 4 and 5 show how the characteristics of the n-ch TFT element deteriorate depending on the applied voltage time. FIG. 4 is a characteristic diagram showing the shift amount ΔVth [v] from the initial value Vtho of the threshold voltage Vth with respect to the bias application time, and FIG. 5 is an initial value g of the mutual conductance gm with respect to the bias application time.
FIG. 7 is a characteristic diagram showing a ratio Δgm / gmo of a deterioration amount Δgm from mo. In each figure, the solid line (A) is LD
For the device adopting the D structure, the gate voltage Vg = 0
[V] is the shift amount ΔVth or the change amount Δgm / gmo when the drain voltage Vd = 20 [v]. As a comparative example, the broken line (B) indicates the ΔVth value when Vg = Vd = 20 [v]. Or Δgm / gmo value, one-dot chain line (C)
Is ΔVth when Vg = 0 [v] and Vd = 20 [v]
Value or Δgm / gmo value. In FIG. 4, focusing on the alternate long and short dash line (C), the TFT is OFF, and
When the drain voltage is applied, there is a change in the threshold value of 6 [v] or more. Looking at the broken line (B), when the TFT is ON and the source and drain are in conduction, 2-4 [ V], which is relatively small. Further, looking at the solid line (A), the shift amount of the threshold voltage is that the TFT is OFF and
Even when the drain voltage is applied, it is reduced to 0.4 [v] or less by adopting the LDD structure.

Further, focusing on the alternate long and short dash line (C) from FIG. 5, the deterioration amount of gm is about 60% or more when the TFT is OFF and the drain voltage is applied.
Looking at the broken line (B), it is as small as 1 to several% over time. Also, looking at the solid line (A), the deterioration amount of gm is T
Even when the FT is OFF and the drain voltage is applied, it is reduced to 4% or less by adopting the LDD structure. That is, the LDD structure element is
It can be seen that even when a high voltage is applied during OFF and a load is applied, the amount of change in characteristics is significantly reduced compared to an element that does not adopt LDD.

Therefore, from the consideration using FIG. 3 described above, in normal LCD driving, the load applied to the first n-ch TFT (1) constituting the level converter is large and the state is easily deteriorated. , The first n-ch TF
By adopting the LDD structure with emphasis on the breakdown voltage only for T (1), the breakdown voltage of the entire drive circuit unit can be efficiently increased and the reliability can be improved.

In addition, the shift register (R
D), the level converter (CD), and the drain side drive circuit section including the sample and hold circuit (SH), and the gate side drive circuit section including the shift register (RG) and the level converter (CG) shown in FIG. Among the TFT elements constituting each of the stages, the LDD structure is adopted in the level converter (CD, C shown in FIG. 3).
There is only one first n-ch TFT (1) that constitutes G). The LDD structure reduces the driving ability and driving speed,
Although it is disadvantageous in terms of display quality and miniaturization of the device because it increases the element formation area, the present invention only adopts the LDD structure for the first n-ch TFT (1) which is most likely to deteriorate. So problems in this regard are minimized.

Such a level converter (CD, C
The structure of the n-ch TFT having the LDD structure which constitutes G) is shown in FIG. On the substrate (10) such as quartz glass, p-
An island layer of Si (11) is formed, and both end portions are source regions (11) heavily doped with n-type impurities.
S) and the drain region (11D). Then, these source and drain regions (11S, 11D)
Between the non-doped channel region (11N),
An LD portion (11L) that is lightly doped is formed in each. On top of these, the gate insulating film (12)
And a gate electrode (13) made of n-type doped p-Si is formed on a portion of the gate insulating film (12) corresponding to the channel layer (11N). An insulating film which is an injection stopper (14) is formed on the gate electrode (13). An interlayer insulating film (15) is covered on these, source and drain electrodes (16S, 16D) and their wirings are formed, and via a contact hole (CT) opened in the interlayer insulating film (15). Source / drain area (11S, 1
1D).

The TFT having this structure is excellent in suppressing the leak current at the time of OFF and can improve the retention characteristic of the pixel capacitance, and is suitable as a switching element.
The structure of FIG. 6 is also adopted in the pixel portion. Hereinafter, FIG. 7 to FIG.
The manufacturing method will be described using 0. First, on a transparent substrate (10) made of highly heat-resistant quartz glass, 640 ° C., 0.
By using low pressure CVD with SiH4 or Si2H6 as the material gas under the condition of about 3 Torr, a p-thickness of about 600Å
A film of Si (11) is formed. After etching the p-Si (11) into an island shape, HTO (High Temperture) is formed on the entire surface.
Oxide) film, that is, under high temperature and low pressure conditions of about 880 ° C. and about 0.8 Torr, a SiO2 film having a thickness of about 1000 Å is coated by low pressure CVD using a mixed gas of SiH2Cl2 (dichlorosilane) and N2O as a material gas, and gate insulation It is a membrane (12). The p-Si may be polycrystallized by heat treatment of a-Si, and the HTO film may be p-Si.
-Si may be thermally oxidized. (Refer to FIG. 7 for the above.) Subsequently, the p-Si serving as the gate wiring is replaced with the above-mentioned p-Si.
Similar to (11), low pressure CVD is used to form a film with a thickness of about 3000 Å, and POCl3 is used as a diffusion source to dope this gate p-Si to an n-type to reduce the resistance. The doping may be performed by mixing a dopant gas such as PCl3 during the film growth. Then, SiO2 is deposited to a thickness of 2500 to 3000 Å by atmospheric pressure CVD at about 400 ° C, and this is etched into a gate pattern by using a mixed solution containing HF (hydrofluoric acid) or BHF (buffered hydrofluoric acid) as an etchant. To form the injection stopper (14). Also, C as an etchant
Etching may be performed by a dry method using HF3 gas. Using the same mask, plasma etching using a mixed gas containing SF6 and Cl2 as the main components was performed to form a gate p-S.
i is etched to form the gate electrode (13) and
The connection line is formed. (Refer to FIG. 8 above) Next, after masking resist is applied to the p-ch TFT region, n-ch p-Si (11) is masked with the gate electrode (13) as n. Phosphorus (P), which is a type impurity, is ion-implanted with a dose amount of 10 ↑ 13 / cm to form a low concentration np-Si region. (Refer to FIG. 9 above.) Furthermore, the resist (R) having a larger pattern than the gate electrode (13) is used to form the first n-ch TFT (1) in the level converter (CD, CG) section and the gate electrode (13) in the pixel section.
After masking, phosphorus (P) is dosed again 10 ↑ 15
/ Ch is ion-implanted to form a high concentration n + p-Si region. As a result, the LD region of n-p-Si (11 L)
And n + p-Si source / drain regions (11S, 1S) on both sides of the non-doped channel layer (11N).
1D) is formed to complete the LDD structure. (that's all,
(Refer to FIG. 10) After removing all the resist, masking resist is applied to regions other than the p-ch region, and ion implantation of boron (B), which is a p-type impurity, is performed, and the source / drain regions of the p-ch TFT are p + -type. Dope At this time, the implantation stopper (14) serves as a mask in the gate self-alignment structure and prevents implantation of B ions into the n + type gate electrode (13). (Not shown) After removing the resist and performing activation annealing, a CVD film of SiO2 is formed on the entire surface as an interlayer insulating film (15), a predetermined contact hole (CT) is formed by etching, and then an Al film is formed. The film and etching, and the interlayer insulating film are formed a predetermined number of times, and further, the ITO is formed and etched to form the source / drain electrodes (16S, 16D) and their connecting lines, the display electrode for driving the liquid crystal, and , TFT connection is formed, and the matrix pattern of the pixel portion and the drive circuit portion are completed.

As described with reference to FIG. 10, the LDD structure is
Since it is formed by selectively covering the resist (R) on the gate electrode (13),
An element adopting the LDD structure and an element not adopting the LDD structure can be freely determined. Therefore, in the present invention, the TF that constitutes the level converter having a high power supply voltage
Of the T elements, in particular, the LDD structure is adopted only for the element that has a long OFF period, a high voltage is applied, and the characteristics are likely to be deteriorated to increase the breakdown voltage, and the LDD is not used for other elements. In addition to increasing the degree of integration, it has been possible to improve the driving capability by scaling.

The above is the TFT for the high temperature process.
Of the structure (1) and the method of manufacturing the same.
When an inexpensive glass substrate is used as 0), it is manufactured by a low temperature process in which the process temperature is suppressed to 600 ° C. or lower in terms of heat resistance of the substrate. In this case, p in FIG.
Since -Si (11) suppresses the film formation temperature to 600 ° C or lower, laser annealing is performed after the film formation to supplement the energy and promote the growth of crystal grains. At this time, if the entire surface is scanned, it takes a long time and the throughput is significantly reduced.
The time is shortened by spending the irradiation time only on the peripheral drive circuit section in which the FTs are concentrated. At this time, the speed of the pixel portion decreases, but in the present invention, the withstand voltage of the level converter (CD, CG) is improved. Therefore, the applied voltage should be sufficiently increased to widen the drive voltage range of the liquid crystal. Therefore, it is possible to prevent a decrease in contrast ratio due to signal distortion or the like.

Such a high withstand voltage level converter (C
As the TFT constituting D, CG), in addition to the LDD structure shown in FIGS. 6 and 7 to 10, a structure in which the width of the gate electrode (13) is widened to increase the length of the channel (11N), Alternatively, by providing two gate electrodes, p-S
A double gate structure in which two channel regions (11N) are provided in series in the island layer of i (11) is also possible. In the large channel length structure and the double gate structure, the number of steps is small and the manufacturing cost can be kept low as compared with the LDD structure.

[0034]

As is apparent from the above description, p-Si
In an LCD with a built-in drive circuit using TFTs, among the transistor elements that form a level converter having a high drive power supply voltage, only the elements that are easily deteriorated are made to have a high withstand voltage, so that the overall withstand voltage is efficiently increased, and the device is improved. Reliability was improved. Further, as a result, it is possible to minimize the decrease in the driving capability and the driving speed due to the high breakdown voltage and the increase in the element formation area. Therefore, it is possible to improve the display quality and the size of the device while improving the reliability. it can.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a drain side drive circuit unit incorporated in a liquid crystal display device.

FIG. 2 is a configuration diagram of a gate side drive circuit unit incorporated in a liquid crystal display device.

FIG. 3 is an equivalent circuit diagram of a level converter incorporated in a liquid crystal display device.

FIG. 4 is a characteristic diagram of bias application time of the TFT element-threshold voltage shift amount.

FIG. 5 is a characteristic diagram of a bias application time of a TFT element-amount of change in transconductance.

FIG. 6 is a sectional view of a TFT incorporated in a liquid crystal display device according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing process of a TFT incorporated in a liquid crystal display device according to an embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a manufacturing process of a TFT incorporated in a liquid crystal display device according to an embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a manufacturing process of a TFT incorporated in a liquid crystal display device according to an embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a manufacturing process of a TFT incorporated in a liquid crystal display device according to an embodiment of the present invention.

FIG. 11 is a configuration diagram of a liquid crystal display device.

FIG. 12 is a cross-sectional view of a TFT incorporated in a liquid crystal display device.

[Explanation of symbols]

 1, 2 n-ch TFT 3, 4 p-ch TFT 10 substrate 11 p-Si 12 gate insulating film 13 gate electrode 14 injection stopper 15 interlayer insulating film 16 source / drain electrode G gate line D drain line GD gate driver DD drain driver RD , RG Shift register CD, CG Level converter SH Sample and hold circuit CT Contact hole

Claims (4)

[Claims] 1. A gate line group and a drain line group arranged on a substrate so as to intersect with each other, a thin film transistor group formed at each intersection thereof, and a driving circuit unit for driving the gate line and the drain line. Further, the drive circuit section for driving the drain line,
A liquid crystal display device including a shift register unit configured by a polycrystalline silicon thin film transistor, which controls a sampling operation of a signal voltage to be applied to the drain line from an input signal, and a level converter unit which amplifies an output signal of the shift register The level converter is driven by a power supply voltage higher than that of the shift register, and the polycrystalline silicon thin film transistor that constitutes the level converter has a higher breakdown voltage than the polycrystalline silicon thin film transistor that constitutes the shift register. A liquid crystal display device characterized by the above. 2. A gate line group and a drain line group arranged on a substrate so as to intersect with each other, a thin film transistor group formed at each intersection thereof, and a driving circuit unit for driving the gate line and the drain line. Further, the drive circuit unit for driving the gate line is composed of a polycrystalline silicon thin film transistor, a shift register unit for applying a scanning signal to the gate line, and a level converter for amplifying an output signal of the shift register. In the liquid crystal display device, the level converter is driven by a power supply voltage higher than that of the shift register, and the polycrystalline silicon thin film transistor forming the level converter is more than the polycrystalline silicon thin film transistor forming the shift register. Is also high withstand voltage The liquid crystal display device according to claim. 3. The level converter includes a first n-type polycrystalline silicon thin film transistor having an input signal gate-inputted and a source connected to GND, and a second n-type polycrystalline silicon thin film transistor having an inverted input signal gate-inputted to a source connected to GND. A first p-type polysilicon gate connected to the drain of the second n-type polycrystalline silicon thin film transistor, the drain being common to the drain of the first n-type polycrystalline silicon thin film transistor, and the source being connected to a high voltage power source. Type polycrystalline thin film transistor, and drain signals of the first n-type polycrystalline silicon thin film transistor and the first p-type polycrystalline thin film transistor are input to the gate, the source is connected to a high voltage power source, and the drain is the second n-type. The second p that is commonly output as the drain of the polycrystalline silicon thin film transistor 3. A liquid crystal display device according to claim 1, wherein the liquid crystal display device comprises a type polycrystalline silicon thin film transistor, and the first n-type polycrystalline silicon thin film transistor has a high breakdown voltage. 4. The first n-type polycrystal silicon thin film transistor is in contact with opposite sides of a heavily doped source and drain regions, respectively, and is lightly doped between a non-doped channel region. 4. A liquid crystal display device according to claim 3, wherein the liquid crystal display device has an intervening region.