JPH0982969A - Thin-film transistor and liquid-crystal display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a leakage current by adjusting channel length and disposing a channel in response to field strength so that the difference of field strength applied to each gate electrode is reduced. SOLUTION: A buffer layer 102 and a semiconductor film 103 are formed onto a transparent insulating substrate 101, and a gate insulating film 104 is formed onto the semiconductor film 103. A plurality of opening sections are shaped to the gate insulating film 104, and a drain electrode 105 and a source electrode 106 are connected electrically and formed to the semiconductor film 103 through the opening sections. Two gate electrodes 107 are formed between the drain electrode and the source electrode on the gate electrode 104. The channel length L1 , L2 of the gate electrodes 107 is optimized and shaped in response to the magnitude of field strength at a place, where the gate electrode is formed. That is, the channel length of the gate electrodes is adjusted and disposed in response to field strength so that field strength per each gate electrode is equalized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor, and more particularly to a thin film transistor having a plurality of gate electrodes.

The present invention also relates to a liquid crystal display device having a thin film transistor.

[0003]

2. Description of the Related Art In recent years, thin film transistors (hereinafter referred to as TFTs)
Has been widely put into practical use in the fields of liquid crystal display devices, contact sensors, and the like, and is being actively developed.

In particular, in a liquid crystal display device, a switching TFT for the pixel portion and a peripheral drive circuit system (so-called LCD driver; liquid crystal drive circuit) for driving the pixel on the same substrate around which the image is displayed are provided. To TF
A liquid crystal display device integrated with a drive circuit having a structure created by T has been developed. For example, a thin film transistor (p-SiTF) using non-single crystal silicon for a semiconductor film is used.
T) has attracted particular attention as a technique suitable for this field.

Since an electric field is concentrated in the vicinity of the drain junction in the TFT and an abnormal leak current is likely to occur, reducing this large leak current is a problem in improving the characteristics of the TFT.

Such a leak current is generated when the transistor is off (when the gate voltage is 0 V in the n-type TFT is negative), and therefore the on / off switching operation of the transistor does not function sufficiently. is there.

In order to reduce such a leak current of the TFT, it is sufficient to avoid concentration of an electric field between the gate and the drain, but in order to realize this, LDD
(Lightly Doped Drain) structure, multi-gate structure, etc. have been proposed.

The LDD structure has a charge distribution in the vicinity of the drain so that the electric field is not concentrated at the drain junction, and is intended to reduce the leak current when the transistor is off. In order to have a charge distribution in the vicinity of the drain, it is necessary to form a region (n-region for an n-ch TFT, p-region for a p-ch TFT) having a smaller charge than that of a normal source / drain region. The ideal length of the -region or p-region is about several micrometers. Mask alignment is performed by a photolithography method to form this region. However, if the substrate becomes large, expansion and contraction of the substrate causes the mask alignment accuracy to deteriorate. For this reason, an n-region of the order of a few micrometers or p
There is a problem that it is difficult to form the region with high accuracy.

Further, in order to form the n-region or the p-region, it is necessary to implant impurities into the semiconductor at a low dose through the gate insulating film, but at this time, the film thickness of the gate insulating film becomes uneven. In that case, there is a problem in that the net amount of impurities implanted into the semiconductor varies, and it is difficult to form an n-region or p-region having an appropriate concentration.

On the other hand, in the multi-gate structure, by providing a plurality of gate electrodes in one transistor, the electric field conventionally applied to one transistor is distributed to the plurality of transistors formed by each gate electrode. Electric field concentration can be avoided.

FIG. 9 is a sectional view schematically showing an example of a multi-gate thin film transistor. Insulating substrate 90
A buffer layer 902 and a semiconductor film 903 are formed on
A gate insulating film 904 is formed on the semiconductor film 903. A plurality of openings is formed in the gate insulating film 904, and a source electrode 905 and a drain electrode 906 are formed through the openings so as to be electrically connected to the semiconductor film 903. Two gate electrodes 907 having a channel length L are provided between the source electrode and the drain electrode on the gate insulating film 904.
Is formed, and the interlayer insulating film 9 is formed on the gate electrode.
08 is formed.

[0012] The problems of such a multi-gate TFT are to secure the source / drain breakdown voltage and to improve the aperture ratio. The source-drain breakdown voltage is a breakdown voltage when the channel region is destroyed by applying a voltage between the source and drain. That is, in the conventional multi-gate TFT, since the channel length in each gate electrode is the same in the same active layer, when a high voltage is applied to the source / drain, the electric field concentrates on the channel close to the source electrode, which is a high potential electrode. There is a problem that it is easily destroyed.

For example, in a liquid crystal display device using a polymer-dispersed liquid crystal as a light valve, it is common that a high voltage of 20 V or more is applied between the source and drain, and improvement of the source-drain breakdown voltage is a problem. .

On the other hand, the multi-gate TFT does not require fine mask alignment as in the LDD structure and has an advantage that it can be easily formed on a large substrate. In particular, when this multi-gate TFT is used as a pixel switching element of a liquid crystal display device, it is desired to reduce the transistor size in order to improve the aperture ratio.

In order to secure a high source / drain breakdown voltage, the channel length may be lengthened, but if all the channel lengths are formed long in order to secure the breakdown voltage between the source / drain in the TFT of the conventional structure, the transistor size becomes large. There is a problem that the aperture ratio becomes large and the aperture ratio decreases.

[0016]

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem. That is,
An object of the present invention is to provide a thin film transistor which has a high source / drain breakdown voltage and a large aperture ratio while reducing a leak current.

It is another object of the present invention to provide a liquid crystal display device provided with a thin film transistor which has a large aperture ratio and can be easily formed on a large substrate and can be driven at a high voltage.

[0018]

A thin film transistor according to the present invention comprises a semiconductor film having a plurality of contact regions, first and second electrodes formed so as to be connected to the plurality of contact regions, and a first semiconductor film of the semiconductor film. A region corresponding to the gate insulating film formed on the surface opposite to the first electrode and the second electrode, and between the first electrode and the second electrode on the surface opposite to the semiconductor film of the gate insulating film. In addition, the channel length is adjusted according to the electric field strength so that the electric field strength per each gate electrode is made uniform, that is, the difference in the electric field strength applied to each gate electrode is relaxed. And a gate electrode of.

As the semiconductor film, for example, a non-single-crystal crystalline silicon film may be formed, or an amorphous silicon film may be formed, and a semiconductor film other than these may be used. You may

The thin film transistor of the present invention may be of any type such as stagger type, inverted stagger type and coplanar type. This is the same even when not particularly described below.

The thin film transistor of the present invention has a semiconductor film having a plurality of contact regions, first and second electrodes formed so as to be connected to the plurality of contact regions, a first electrode and a second electrode of the semiconductor film. In a region having a first electric field strength between the first electrode and the second electrode on the surface of the gate insulating film opposite to the semiconductor film and on the surface opposite to the semiconductor film of the gate insulating film. A formed first gate electrode having a first channel length, and a first gate electrode formed in a region having a second electric field intensity smaller than the first electric field intensity between the electrodes and having a first channel length shorter than the first channel length. And a second gate electrode having a channel length of 2.

The thin film transistor of the present invention has a semiconductor film having a plurality of contact regions, source and drain electrodes formed so as to be connected to the plurality of contact regions, and a surface of the semiconductor film opposite to the source and drain electrodes. A first gate having a first channel length, disposed between the formed gate insulating film and a source electrode and a drain electrode on the surface of the gate insulating film opposite to the semiconductor film and in proximity to the drain electrode. An electrode and a second gate electrode having a second channel length shorter than the first channel length arranged between the first gate electrode and the source electrode are provided.

The thin film transistor of the present invention has a semiconductor film having a plurality of contact regions, first and second electrodes formed so as to be connected to the plurality of contact regions, a first electrode and a second electrode of the semiconductor film. Of the first electrode and the second electrode of the first electrode on the surface of the gate insulating film opposite to the semiconductor film and the surface of the gate insulating film opposite to the semiconductor film. A first gate electrode having a first channel length formed adjacent to the electrode side and a second gate electrode having a first channel length formed adjacent to the first electrode side of the second electrode.
And a third gate electrode having a second channel length shorter than the first channel length formed between the first gate electrode and the second gate electrode. To do.

In the thin film transistor of the present invention, the semiconductor film formed on the insulating substrate, the gate insulating film having a plurality of openings formed on the semiconductor film, and the semiconductor film are connected through the openings. Uniform electric field strength per gate electrode between the first electrode and the second electrode formed on the gate insulating film and the first electrode and the second electrode formed on the gate insulating film Thus, that is, the plurality of gate electrodes are provided by adjusting the channel length of the gate electrode according to the electric field strength so that the difference in the electric field strength applied to each gate electrode is relaxed. To do.

In the thin film transistor of the present invention, the semiconductor film formed on the insulating substrate, the gate insulating film having a plurality of openings formed on the semiconductor film, and the semiconductor film are connected through the openings. A first electrode and a second electrode formed on the gate insulating film and a region having a first electric field strength between the first electrode and the second electrode on the gate insulating film. A first gate electrode having a first channel length and a second channel length formed in a region having a second electric field strength smaller than the first electric field strength between the electrodes on the gate insulating film and being shorter than the first channel length. And a second gate electrode having a channel length of.

In the thin film transistor of the present invention, the semiconductor film formed on the insulating substrate, the gate insulating film having a plurality of openings formed on the semiconductor film, and the semiconductor film connected to the semiconductor film through the openings. And a source electrode and a drain electrode formed on the gate insulating film, and a first channel length disposed between the source electrode and the drain electrode on the gate insulating film and adjacent to the drain electrode. A first gate electrode and a second channel shorter than the first channel length disposed between the first gate electrode and the source electrode on the gate insulating film.
And a second gate electrode having a channel length of. Further, the thin film transistor of the present invention, a semiconductor film formed on an insulating substrate, a gate insulating film having a plurality of openings formed on the semiconductor film,
A first electrode and a second electrode formed on the gate insulating film so as to be connected to the semiconductor film through the opening, and a first electrode formed adjacent to the second electrode side of the first electrode. A first gate electrode having a channel length of, a second gate electrode having a first channel length formed adjacent to the first electrode side of the second electrode, a first gate electrode and a second gate electrode And a third gate electrode having a second channel length shorter than the first channel length formed between the second gate electrode and the second gate electrode.

The liquid crystal display device of the present invention includes a semiconductor film having a plurality of contact regions, first and second electrodes formed so as to be connected to the plurality of contact regions, and the first electrode of the semiconductor film. And a gate insulating film formed on a surface opposite to the second electrode, and a region corresponding to a portion between the first electrode and the second electrode on a surface of the gate insulating film opposite to the semiconductor film, respectively. The thin film transistor is provided with a plurality of gate electrodes arranged by adjusting the channel length according to the electric field strength so as to reduce the difference in electric field strength applied to the gate electrode.

In the liquid crystal display device of the present invention, the semiconductor film formed on the insulating substrate, the gate insulating film having a plurality of openings formed on the semiconductor film, and the semiconductor film via the openings. A first electrode and a second electrode formed on the gate insulating film so as to connect with the first electrode on the gate insulating film;
Between the first electrode and the second electrode so that the electric field strength per each gate electrode is as uniform as possible, that is, the difference in the electric field strength applied to each gate electrode is relaxed. And a plurality of gate electrodes arranged by adjusting the channel length of the gate electrode.

With the above-mentioned structure, the thin film transistor of the present invention is arranged by optimizing the channel lengths of the plurality of gate electrodes, thereby alleviating the difference in the electric field strength applied to each gate electrode. Also, the leak current at the time of turning off can be reduced. Therefore, the source / drain breakdown voltage of the channel of the gate electrode formed on the drain electrode side, which is the most problematic in a multi-gate thin film transistor, is improved.

Further, the light-shielding area between the source and drain electrodes due to the gate electrode can be reduced, and when used in a liquid crystal display device, the aperture ratio of the display device is improved.

In a liquid crystal display device having such a thin film transistor, the aperture ratio is improved and
It can also be used for driving in which a high voltage is applied between the drains.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION An example of a thin film transistor of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a sectional view schematically showing an example of the thin film transistor of the present invention.

The buffer layer 10 is formed on the transparent insulating substrate 101.
2. The semiconductor film 103 is formed, and the gate insulating film 104 is formed on the semiconductor film 103. Semiconductor film 10
For No. 3, a non-single crystal silicon film may be formed, or an amorphous silicon film may be formed. A plurality of openings are formed in the gate insulating film 104, and the drain electrode 105 and the source electrode 106 are electrically connected to the semiconductor film 103 through the openings. Two gate electrodes 107 are formed between the drain electrode and the source electrode on the gate insulating film 104, and an interlayer insulating film 108 is formed on the gate electrodes.

FIG. 10 is a sectional view schematically showing an example of a thin film transistor of the present invention, which is an example in which the structure of the thin film transistor of the present invention is applied to an inverted stagger type thin film transistor. 110 is a channel protective film. FIG. 11 is a cross-sectional view schematically showing an example of the thin film transistor of the present invention, which is an example in which the structure of the thin film transistor of the present invention is applied to a stagger type thin film transistor.

As described above, the present invention may be applied to various thin film transistors such as a coplanar type, an inverted stagger type and a stagger type. The same applies to the case where no particular description is given below.

Channel lengths L1 and L2 of the gate electrode 107
Is optimized and formed corresponding to the magnitude of the electric field strength at the position where the gate electrode is formed. That is, the channel length of the gate electrode is adjusted according to the electric field strength so that the electric field strength for each gate electrode is uniform.

Further, in a region between the drain electrode and the source electrode where a large electric field intensity is applied, the gate electrode 107a having a channel length L1 is provided so as to correspond to the large electric field intensity.
May be formed, and the gate electrode 107b having a channel length of L2 shorter than L1 may be formed in a region to which an electric field intensity smaller than this is applied.

Further, the drain electrode 105 and the source electrode 1
06, a gate electrode 107a having a channel length L1 is formed adjacent to the drain electrode 105.
1 between the gate electrode 107a and the source electrode 106
Gate electrode 107b having a channel length L2 shorter than 1
May be formed.

In the case of the thin film transistor illustrated in FIG. 1,
Since the electric field is concentrated on the gate electrode 107a close to the drain electrode 105, the gate electrode 10 on the drain electrode 105 side is
The channel length L1 of 7a is the gate electrode 10 on the source electrode side.
It is formed longer than the channel length L2 of 7b. Regardless of the channel length of either gate electrode, the source and
It is formed to have a channel length that can cope with the drain breakdown voltage.

FIG. 2 shows the relationship between the channel position and the channel potential.

L is the channel length, y is the distance from the channel end on the high potential electrode side, Vds is the source / drain voltage, and Vy
Is the channel potential at a distance y from the channel end on the high potential electrode side (see FIG. 3). It is shown that the electric field concentrates at the channel position closer to the drain electrode as Vds increases. Therefore, by optimizing the channel lengths of the plurality of gate electrodes and arranging them as illustrated in FIG. 1, concentration of the electric field can be avoided. For example, the source / drain breakdown voltage is improved as compared with a multi-gate TFT having the same channel length as illustrated in FIG.

The number of gate electrodes provided is not limited to two, and more gate electrodes may be provided as necessary. FIG. 4 is a cross-sectional view schematically showing an example of the thin film transistor of the present invention having four gate electrodes.

The design of the channel lengths of the plurality of gate electrodes may be performed based on the relationship between the channel position and the channel potential as illustrated in FIG. 2, for example.

When divided into two gate electrodes having channel lengths L1 and L2, the value of y / L such that Vy / Vsd is about 0.5 is about 0.7, so that the gate electrode on the drain electrode side is The ratio of the channel length L1 to the channel length L2 of the gate electrode on the gate electrode side may be about 7: 3. Similarly, when divided into three, y / L values such that Vy / Vsd is about 0.33 and about 0.67 are about 0.5,
Since it is about 0.85, the ratio of the channel lengths L1, L2, L3 of the gate electrode from the drain electrode side may be about 10: 7: 3.

Here, these exemplified ratios are one example of division, and may be designed as necessary, such as transistor characteristics and required source / drain breakdown voltage.

Further, the source electrode and the drain electrode may be replaced by adjusting the channel length of the gate electrode.

The thin film transistor illustrated in FIG. 1 may be used for a driving circuit of a liquid crystal display device, for example.

FIG. 5 shows another thin film transistor according to the present invention.
It is sectional drawing which showed the example schematically. This TFT is used as, for example, a pixel switching element of a liquid crystal display device, and the drain electrode and the source electrode are driven while being inverted.

The buffer layer 50 is formed on the transparent insulating substrate 501.
2. A semiconductor film 503 is formed, and a gate insulating film 504 is formed on the semiconductor film 503. A plurality of openings is formed in the gate insulating film 504, and the first electrode 505 and the second electrode 506 are formed through the openings in the semiconductor film 50.
It is formed by being electrically connected to the No. 3. Here, the electrode having the higher potential is the drain electrode, the electrode having the lower potential is the gate electrode, and the drain electrode and the source electrode may be inverted and driven. A plurality of gate electrodes 507a, 507b, and 507c are formed between the first electrode 503 and the second electrode 504 on the gate insulating film 504. An interlayer insulating film 508 is formed on the gate electrode.

Also in the thin film transistor illustrated in FIG. 5, as in the thin film transistor illustrated in FIG. 1, the channel lengths L1, L2, and L3 of the respective gate electrodes correspond to the magnitude of the electric field strength at the position where the gate electrode is formed. And is optimized and formed. That is, the channel length of the gate electrode is adjusted according to the electric field strength so that the electric field strength for each gate electrode is uniform.

In the case of this thin film transistor, since the drain electrode and the source electrode are driven while being inverted from each other,
There can be two regions between the first electrode and the second electrode to which a large electric field strength is applied. In these regions, the gate electrodes 5 having channel lengths L1 and L3 that can cope with this large electric field strength
07a and 507c may be formed, and a gate electrode 507b having a channel length L2 shorter than L1 and L3 may be formed in a region to which an electric field intensity smaller than the electric field intensity is applied.

A gate electrode 507a having a channel length L1 is formed adjacent to the second electrode side of the first electrode, and a gate electrode 507c having a channel length L3 is formed adjacent to the first electrode side of the second electrode. A gate electrode 507 having a channel length L1 is formed.
L between a and the gate electrode 507c having a channel length L3
1, a gate electrode 5 having a channel length L2 shorter than L3
07b may be formed.

In the case of the thin film transistor illustrated in FIG. 4,
Since the electric field concentrates on the gate electrode 507a adjacent to the first electrode and the gate electrode 507c adjacent to the second electrode,
The channel lengths L1 and L3 of the gate electrodes on both electrode sides are formed longer than the channel length L2 of the gate electrode 507b away from both electrodes so that the source / drain breakdown voltage can be secured for the electric field strength at each channel position. ing. Regardless of the channel length of any of the gate electrodes L1, L2, and L3, the channel length is formed so as to correspond to the source / drain breakdown voltage with respect to the electric field strength at the disposed channel position. That is, each of the gate electrodes 507a and 507c, the first electrode 505, and the second electrode 507c centering on the gate electrode 507b having the channel length L2.
Electrodes 506 are symmetrically formed, and in this case L1
~ L3> L2.

The design of the channel lengths of the plurality of gate electrodes 507 may be performed based on the relationship between the channel position and the channel potential as illustrated in FIG. 2, for example, as described above.

Thus, by optimizing the channel length of the gate electrode 507 according to the channel position, even if the drain electrode and the source electrode are driven by being inverted, the source / drain breakdown voltage can be improved. It can be ensured and the leak current can be reduced. Further, the transistor size is smaller than that of the conventional multi-gate TFT in which the channel length is not optimized, and the aperture ratio is improved when used in a liquid crystal display device.

The thin film transistor illustrated in FIG. 5 may be used as a pixel switching element of a liquid crystal display device, for example.

FIG. 6 is a sectional view schematically showing an example of the liquid crystal display device of the present invention.

In this liquid crystal display device, a TFT array composed of a plurality of pixel switching TFTs 602, pixel electrodes 603, gate lines 604, and signal lines 605 is formed on a transparent insulating substrate 601. An insulating protective film 606 and a liquid crystal layer 607 are formed on these TFT arrays, and a glass substrate 609 on which a counter electrode 608 is formed is arranged on the TFTs. Also, a driving circuit (not shown) for driving these TFT arrays is also provided. It is arranged. Polymer dispersed liquid crystal may be used for the liquid crystal layer.

The driving circuit TFT is a p-ch TFT 61.
CMOS (Comple consisting of 0 and n-ch TFT 611)
mentaly MOS) 612. Reference numeral 613 indicates a liquid crystal capacity, and 614 indicates an auxiliary capacity. The pixel switching TFT 602 uses a thin film transistor having a plurality of gate electrodes, and the channel lengths of the plurality of gate electrodes are optimized and formed in accordance with the magnitude of the electric field strength at the position where the gate electrodes are formed. ing. For example, the thin film transistor of the present invention illustrated in FIGS. 4, 5, and 10 may be used.

FIG. 7 is a diagram schematically showing a circuit of the liquid crystal display device illustrated in FIG.

A thin film transistor formed by optimizing the channel length of a plurality of gate electrodes corresponding to the magnitude of the electric field strength at the position where the gate electrodes are formed is also used in the drive circuit of the TFT array. For example, the thin film transistor illustrated in FIG. 1 may be used as the driving circuit TFT.

A liquid crystal display device provided with such a thin film transistor is a liquid crystal display device having a reduced leak current and a high on / off switching characteristic. Further, since it has an excellent source / drain breakdown voltage, it can be used for high voltage driving, and the liquid crystal display device has an improved aperture ratio. In addition, since a TFT with a multi-gate structure is adopted,
There is no need for fine mask alignment such as that of the DD structure TFT, and it is possible to cope with an increase in the size of the display screen.

Next, a method of manufacturing the thin film transistor of the present invention will be described with reference to FIG.

First, as shown in FIG. 8A, plasma CVD is performed on a translucent insulating substrate 801 made of a glass substrate or the like.
A buffer layer 802 made of SiOx, SixNy or the like is formed by a method or the like. Further, an amorphous silicon film having a film thickness of 50 nm, for example, is deposited by the plasma CVD method or the like, and a semiconductor is formed by the excimer laser annealing method or the like, and then the semiconductor pattern 803 is formed by photolithography and etching.

Then, as shown in FIG. 8B, the normal pressure C
For example, a gate insulating film 80 having a film thickness of 70 nm is formed by the VD method or the like.
4 is formed, and further, for example, Al and Mo having a film thickness of 250 nm are formed.
Ta or the like is patterned by photolithography and etching to form a plurality of gate electrodes 805 on the same semiconductor pattern. What is characteristic of the present invention is the length of the plurality of channels formed at this time. This length is
That is, the channel length is optimized according to the electric field strength. In this case, the channel length (L ₁ ) closest to the drain electrode is the other channel lengths (L ₂ , L ₃ ,
It is formed longer than L _n ).

Next, as shown in FIG. 8C, using the gate electrode 805 as a mask, impurities such as phosphorus are doped by, for example, an ion doping method, and then at 300 ° C.
The impurities are activated by annealing for 1 hour to form an impurity implantation region 806. After that, for example, plasma CVD
A contact hole 808 is formed by photolithography and etching after forming an interlayer insulating film 807 made of SiOx or the like having a thickness of 400 nm by a method or the like.

Then, as shown in FIG. 8D, for example, 4
The drain electrode 80 is formed by sputtering 00 nm Al or the like and further by photolithography and etching.
9. After forming the source electrode 810 and annealing at 450 ° C. for 30 minutes, hydrogen plasma treatment is performed to complete the coplanar thin film transistor 811.

Multi-gate TFT and TFT of conventional structure
T of the present invention having the same size (channel length / channel width)
In the FT, the source / drain breakdown voltage is improved even when the TFT size (channel length / channel width) is equal to that of the conventional multi-gate TFT. Further, the jump of the leak current at the time of off bias can be suppressed more effectively than the conventional multi-gate TFT.

As described above, since the thin film transistor of the present invention has a multi-gate structure, it does not require fine mask alignment as in the LDD structure, so that it can be easily formed on a large-sized substrate and has a high source / drain breakdown voltage. A thin film transistor capable of increasing the aperture ratio when used in a display device.

In the thin film transistor illustrated in FIG. 8, SiOx is used for the interlayer insulating film, but SixNy may be used. Further, the implanted impurities are As and B.
May be used. Further, the impurity activation condition is not limited to 300 ° C., and may be 600 ° C., for example, and lamp annealing / excimer laser annealing may be used as the activation method.

[0072]

As described above, according to the thin film transistor of the present invention, the channel lengths of a plurality of gate electrodes are optimized in accordance with the electric field strength at the respective positions, so that the leakage current is reduced. Reduce and source
The drain breakdown voltage becomes high.

According to the liquid crystal display device of the present invention, since the source / drain breakdown voltage is high, it is possible to support high voltage driving and increase the aperture ratio.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing an example of a thin film transistor of the present invention.

FIG. 2 is a diagram showing a relationship between a channel position and a channel potential.

FIG. 3 is a diagram showing channel positions and channel lengths of thin film transistors.

FIG. 4 is a sectional view schematically showing an example of a thin film transistor of the invention.

FIG. 5 is a sectional view schematically showing an example of a thin film transistor of the present invention.

FIG. 6 is a diagram schematically showing a liquid crystal display device of the present invention.

FIG. 7 is a diagram schematically showing a circuit of a liquid crystal display device of the present invention.

FIG. 8 is a diagram showing a manufacturing process of the thin film transistor of the invention.

FIG. 9 is a diagram schematically showing an example of a conventional thin film transistor.

FIG. 10 is a diagram schematically showing an example of a thin film transistor of the invention.

FIG. 11 is a diagram schematically showing an example of a thin film transistor of the invention.

[Explanation of symbols]

101 ... Insulating substrate, 102 ... Buffer layer, 103 ...
... Semiconductor film 104 ... Gate insulating film, 105 ... Drain electrode, 1
06 ... Source electrode 107a ... Gate electrode (L1), 107b ... Gate electrode (L2) 108 ... Interlayer insulating film, 109 ... Impurity implantation region, 1
10 ... Channel protective film 501 ... Insulating substrate, 502 ... Buffer layer, 503 ...
... Semiconductor film 504 ... Gate insulating film, 505 ... First electrode, 50
6 ... Second electrode 507a ... gate electrode (L1), 507b ... gate electrode (L2) 507c ... gate electrode (L3), 508 ... interlayer insulating film 509 ... impurity injection region 601 ... transparent insulation Substrate 602 ... Pixel switching TFT 603 ... Pixel electrode, 604 ... Gate line, 605 ...
Signal line 606 ... Insulating protective film, 607 ... Liquid crystal layer, 608 ...
Counter electrode 609 ... Glass substrate, 610 ... P-ch TFT, 6
11 ... n-ch TFT 612 ... CMOS, 613 ... Liquid crystal capacitance, 614 ...
Auxiliary capacitance 801 ... Translucent insulating substrate, 802 ... Buffer layer 803 ... Semiconductor pattern, 804 ... Gate insulating film 805 ... Gate electrode, 806 ... Impurity implantation region, 8
07 ... Interlayer insulating film 808 ... Contact hole, 809 ... Drain electrode, 810 ... Source electrode 811, ... Thin film transistor 901 ... Insulating substrate, 902 ... Buffer layer, 903 ...
... Semiconductor film 904 ... Gate insulating film, 905 ... Drain electrode, 9
06 ... Source electrode 907 ... Gate electrode, 908 ... Interlayer insulating film, 909
...... Implanted region

Claims (7)

[Claims] 1. A semiconductor film having a plurality of contact regions, a first electrode and a second electrode formed so as to be connected to the plurality of contact regions, a first electrode and a first electrode of the semiconductor film. A gate insulating film formed on the surface opposite to the second electrode; and a region corresponding to the area between the first electrode and the second electrode on the surface opposite to the semiconductor film of the gate insulating film, A thin film transistor comprising: the plurality of gate electrodes arranged so that a channel length is adjusted according to the electric field strength so as to reduce a difference in electric field strength applied to each gate electrode. 2. A semiconductor film formed on an insulating substrate, a gate insulating film having a plurality of openings formed on the semiconductor film, the semiconductor film being connected to the semiconductor film through the openings. Between the first electrode and the second electrode formed on the gate insulating film and the first electrode and the second electrode on the gate insulating film, a difference in electric field strength applied to each gate electrode. And a plurality of gate electrodes arranged to adjust the channel length according to the electric field strength so as to alleviate the above. 3. A semiconductor film formed on an insulating substrate, a gate insulating film having a plurality of openings formed on the semiconductor film, the semiconductor film being connected to the semiconductor film through the openings. A first electrode and a second electrode formed on the gate insulating film, and a region having a first electric field strength between the first electrode and the second electrode on the gate insulating film. A first gate electrode having a first channel length, and the first channel formed in a region having a second electric field strength smaller than the first electric field strength between the electrodes on the gate insulating film. A second gate electrode having a second channel length shorter than the length of the thin film transistor. 4. A semiconductor film formed on an insulating substrate, a gate insulating film having a plurality of openings formed on the semiconductor film, the semiconductor film being connected to the semiconductor film through the openings. A source electrode and a drain electrode formed on the gate insulating film, and a first electrode disposed between the source electrode and the drain electrode on the gate insulating film and adjacent to the drain electrode.
A first gate electrode having a channel length of, and a second channel length shorter than the first channel length disposed between the first gate electrode on the gate insulating film and the source electrode. And a second gate electrode having the thin film transistor. 5. A semiconductor film formed on an insulating substrate, a gate insulating film having a plurality of openings formed on the semiconductor film, the semiconductor film being connected to the semiconductor film through the openings. A first electrode and a second electrode formed on the gate insulating film, and a first gate electrode having a first channel length formed adjacent to the second electrode side of the first electrode A second gate electrode having a first channel length formed adjacent to the first electrode side of the second electrode, and between the first gate electrode and the second gate electrode A thin film transistor having a third gate electrode having a second channel length shorter than the formed first channel length. 6. A semiconductor film having a plurality of contact regions, a first electrode and a second electrode formed so as to be connected to the plurality of contact regions, a first electrode and a first electrode of the semiconductor film. A gate insulating film formed on the surface opposite to the second electrode; and a region corresponding to the area between the first electrode and the second electrode on the surface opposite to the semiconductor film of the gate insulating film, A liquid crystal comprising: a thin film transistor having a plurality of gate electrodes arranged so that a channel length is adjusted according to the electric field strength so as to reduce a difference in electric field strength applied to each gate electrode. Display device. 7. A semiconductor film formed on an insulating substrate, a gate insulating film having a plurality of openings formed on the semiconductor film, the semiconductor film being connected to the semiconductor film through the openings. Between the first electrode and the second electrode formed on the gate insulating film and the first electrode and the second electrode on the gate insulating film, a difference in electric field strength applied to each gate electrode. A liquid crystal display device comprising: a thin film transistor having a plurality of gate electrodes arranged by adjusting a channel length according to the electric field strength so as to alleviate the above.