TWI470327B - Pixel structure - Google Patents

Description

Pixel structure

The present invention relates to a pixel structure, and more particularly to a pixel structure having a multi-channel region.

Thin Film Transistor Liquid Crystal Display (TFT-LCD) has become the mainstream in many flat panel displays. According to the choice of channel layer material, the thin film transistor liquid crystal display can be divided into an amorphous silicon TFT liquid crystal display and a low temperature polysilicon thin film transistor (LTPS-TFT) liquid crystal display. Two.

Since the electron mobility of the low-temperature polycrystalline germanium film transistor can reach 200 cm ² /V-sec or more, the area of the thin film transistor component can be made smaller to meet the requirement of a high aperture ratio, thereby increasing the display brightness of the display. Reduce overall power consumption issues. However, the low temperature polycrystalline germanium film transistor also has a high leakage current (about 10 ^-9 microamperes), and it is easy to induce a hot carrier effect in the drain. This in turn leads to component degradation. Therefore, a light doped Drain (LDD) or a multi-channel region is often added between the channel region and the source/drain in the low-temperature polycrystalline germanium transistor to avoid the above problem.

1 is a pixel structure of a conventional polycrystalline germanium thin film transistor liquid crystal display. Referring to FIG. 1 , the pixel structure 100 includes a scan line 110 , a data line 120 , a polysilicon layer 130 , and a transparent pixel electrode 140 . The scan line 110 has at least one L-type branch 112, and the polysilicon layer 130 intersects the L-type branch 112 to form a first channel region 132 and a second channel region 134. In addition, the low-temperature polysilicon layer 130 has a source region 136 and a drain region 138 at both ends to form a multi-channel designed polysilicon film transistor 150. The data line 120 is electrically connected to the source region 136, and the transparent pixel electrode 140 is electrically connected to the drain region 138. In addition, the portion of the polysilicon layer 130 overlapping the pixel electrode 140 further constitutes a storage capacitor 152. Because of the multi-channel design, the low temperature polysilicon thin film transistor 150 has a low leakage current in a closed state, which contributes to the improvement of the quality of the pixel structure 100. However, the configuration of the L-shaped branch 112 affects the position at which the storage capacitor 152 is disposed and causes the display aperture ratio of the pixel structure 100 to decrease.

The present invention provides a pixel structure to solve the problem that the polycrystalline germanium film transistor of a multi-channel design limits the display aperture ratio of the pixel structure.

The invention provides a pixel structure comprising a scan line, a data line, a semiconductor pattern and a pixel electrode. The scan line and the data line are staggered and have a branch, and the branch is located below the data line. The semiconductor pattern includes at least two channel regions, at least one doped region, and a source region and a drain region. The channel area is below the scan line. The doped regions are connected between the channel regions. The pixel electrode is electrically connected to the drain region, wherein the source region is connected between one of the channel regions and the data line, and the drain region is connected between the other channel region and the pixel electrode.

In an embodiment of the invention, at least one of the channel regions is located below the branch, and the length of the channel region below the branch is substantially the same as the width of the branch.

In an embodiment of the invention, the semiconductor pattern includes a polysilicon pattern.

In an embodiment of the invention, the semiconductor pattern further includes a capacitor electrode electrically connected to the drain region and the pixel electrode, wherein the capacitor electrode is located below the pixel electrode. In addition, the pixel structure further includes a common electrode disposed between the capacitor electrode and the pixel electrode.

In an embodiment of the invention, the capacitor electrode and the branch are respectively located on opposite sides of the scan line.

In an embodiment of the invention, the shape of the doped region includes an L shape.

In an embodiment of the invention, the semiconductor pattern extends from a first side of the data line to a second side of the data line.

In an embodiment of the invention, a portion of the scan line, the source region and the drain region under the channel region constitute a polysilicon film transistor.

The present invention utilizes variations in the semiconductor pattern to cause the semiconductor pattern to intersect the scan lines at least in two regions, thereby helping to reduce leakage current of the polysilicon thin film transistor. In addition, the present invention sets the branch of the scan line below the data line, which can further prevent the display aperture ratio of the pixel structure from being affected. In general, the pixel structure provided by the present invention has a high display aperture ratio and the polycrystalline germanium film transistor in the pixel structure has good electrical properties.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

2 is a diagram showing a pixel structure of an embodiment of the present invention. Referring to FIG. 2, the pixel structure 200 is electrically connected to a scan line 210 and a data line 220, wherein the scan line 210 and the data line 220 are staggered. The pixel structure 200, the scan line 210, and the data line 220 are disposed, for example, on a substrate (not shown). The pixel structure 200 includes a semiconductor pattern 230 and a pixel electrode 240. The semiconductor pattern 230 includes at least two channel regions 232A, 232B, at least one doped region 234, and a source region 236 and a drain region 238. The channel regions 232A, 232B are located below the scan line 210, wherein the channel region 232A and the channel region 232B have different width to length ratios. Doped region 234 is connected between channel region 232A and channel region 232B. The pixel electrode 240 is electrically connected to the drain region 238, wherein the source region 236 is connected between the channel region 232A and the data line 220, and the drain region 238 is connected between the channel region 232B and the pixel electrode 240.

A portion of the scan line 210 located below the channel region 232A and the channel region 232B can be considered a gate in the pixel structure 200 to control the opening and closing of the pixel structure 200. In addition, the semiconductor pattern 230 is made of, for example, a polysilicon material, that is, the semiconductor pattern 230 is a polysilicon pattern. Therefore, the channel region 232A and the portion of the scan line 210, the source region 236 and the drain region 238 under the channel region 232B together form a polysilicon thin film transistor 250. When the polysilicon thin film transistor 250 is turned off, the grain interface of the polysilicon pattern in the channel regions 232A, 232B may cause leakage current, which affects the quality of the pixel structure 200. In order to solve the problem that leakage current may be caused when the polysilicon thin film transistor 250 is turned off, the concept of a multi-channel design is proposed. However, it is known from the prior art that the provision of a branch extending along the scan line 210 for a multi-channel design affects the display aperture ratio of the pixel structure 200. Therefore, the present invention herein proposes to utilize the flex structure of the semiconductor pattern 230 to achieve a multi-channel design.

The semiconductor pattern 230 of the present embodiment has, for example, a structure in which a plurality of bends are formed, and overlaps with the scanning line 210 in a plurality of regions to form a plurality of channels. The semiconductor pattern 230 is a transparent pattern, and thus the display aperture ratio of the pixel structure 200 is not affected by the design of the multi-channel of the present embodiment. That is to say, the pixel structure 200 of the present embodiment is less prone to leakage current and maintains a good display aperture ratio.

The semiconductor pattern 230 has, for example, a U-shaped doped region 234, and the semiconductor pattern 230 connecting the ends of the U-doped region 234 intersects the scan line 210 to form the channel region 232A and the channel region 232B. With such a design, the polysilicon thin film transistor 250 has a plurality of channel regions 232A and 232B to enhance the electrical characteristics of the polysilicon thin film transistor 250.

In detail, when the polysilicon film transistor 250 is turned on, the direction of current flow in the channel regions 232A and 232B is, for example, perpendicular to the direction in which the scanning line 210 extends. Therefore, the widths D1, D2 of the scan lines 210 affect the lengths L1, L2 of the channel regions 232A, 232B. In general, the longer the lengths L1, L2 of the channel regions 232A, 232B, the lower the leakage current of the polysilicon thin film transistor 250. Therefore, in order to increase the length L2 of the channel region 232B, the width D2 of the scan line 210 in the channel region 232B is, for example, greater than the width D1 of the scan line 210 in other regions. Of course, in other embodiments, in order to increase the length L1 of the channel region 232A, the width of the scan line 210 in the channel region 202A may also be widened.

The semiconductor pattern 230 further includes a capacitor electrode 252 electrically connected to the drain region 238 and the pixel electrode 240, and the capacitor electrode 252 is located under the pixel electrode 240. In fact, in the present embodiment, the doping region 234, the source region 236, the drain region 238, and the capacitor electrode 252 are made of doped polysilicon material. In other embodiments, the pixel structure 200 may further include a common electrode (not shown) disposed between the capacitor electrode 252 and the pixel electrode 240. In addition, the drain region 238 is electrically connected to the pixel electrode 240 through the contact window Td, and the source region 236 is electrically connected to the data line 220 through the contact window Ts. In the present embodiment, the contact window Td and the contact window Ts are located on the same side of the scan line 210, and the semiconductor pattern 230 is substantially bent into a U-shape to intersect the scan line 210 at the channel region 232A and the channel region 232B.

Of course, the contact window Td and the contact window Ts may also be located on opposite sides of the scan line 210. FIG. 3 illustrates a pixel structure of another embodiment of the present invention. Referring to FIG. 3, the pixel structure 300 is similar to the design of the pixel structure 200, wherein the contact window Td and the contact window Ts of the pixel structure 300 are located on opposite sides of the scan line 210. In addition, the semiconductor pattern 330 of the pixel structure 300 has three channel regions 332A, 332B, 332C and two U-shaped doped regions 334A, 334B. At this time, part of the scan lines 210, the source regions 236 and the drain regions 238 under the channel regions 332A, 332B, and 332C together form a polysilicon thin film transistor 350.

In this embodiment, the portions where the scan lines 210 and the semiconductor patterns 330 intersect have different widths D1, D2, and D3, respectively. Therefore, the channel region 332A, the channel region 332B, and the channel region 332C may have different width to length ratios. In practice, the width D1, D2, D3 of the scan line 210 corresponding to the channel regions 332A, 332B, 332C may be greater than the width of the scan line 210 in other regions, so that the polysilicon thin film transistor 350 has better electrical characteristics. Further, the semiconductor pattern 330 is made of, for example, a polycrystalline germanium material, and the polycrystalline germanium material has a light transmissive property. Therefore, the structure of the folded semiconductor pattern 330 in the present embodiment can achieve the design of multiple channels, and at the same time, the pixel structure 300 has a good display aperture ratio.

4 is a diagram showing a pixel structure according to still another embodiment of the present invention. Referring to FIG. 4, the pixel structure 400 is similar to the pixel structure 200 of FIG. 2. The data line 420 and the scan line 410 are staggered, except that the scan line 410 has a branch 412, and the branch 412 and the semiconductor pattern 230. intersect. The portion of semiconductor pattern 230 that intersects branch 412 constitutes channel region 432, while doped regions 434A and 434B are located between channel region 232A and channel region 432, and between channel region 232B and channel region 432, respectively. In practice, the semiconductor pattern 230 of the present embodiment is identical in appearance to the semiconductor pattern 230 of FIG. 2, and the pixel structure 400 has three channel regions 232A, 232B, and 432 due to the design of the branch 412. In addition, the appearance of the doped regions 434A and 434B is also changed from U-shape to two L-shapes.

The pixel structure 400 utilizes the same semiconductor pattern as the pixel structure 200 230 to form three channel regions 232A, 232B and 432, the channel regions 232A, 232B and 432, the source region 236 and the drain region 238 under the partial scan line 410 together form a polysilicon film transistor 450. Because of the design of the multiple channels, the polysilicon thin film transistor 450 is less prone to leakage current in the off state.

In addition, the branch 412 is a rectangular pattern, and the design of the present embodiment helps the pixel structure 400 to maintain a good display aperture ratio compared to the conventional L-shaped branch 112. The branch 412 and the capacitor electrode 252 are respectively located on both sides of the scan line 410, so the arrangement position and area of the capacitor electrode 252 are not affected by the branch 142. That is, the capacitance electrode 252 can be disposed at any position of the area surrounded by the scan line 410 and the data line 220 with different design requirements. In addition, the extending direction of the branch 412 is substantially perpendicular to the extending direction of the scanning line 410, and the length of the channel region 432 below the branch 412 is substantially the same as the width D of the branch 412. Thus, variations in line width of scan line 410 and branch 412 may result in different length to width ratios between channel regions 232A, 232B, and 432. This embodiment utilizes the same design as the semiconductor pattern 230 to have the pixel structure 400 have more than two channel regions 232A, 232B, and 432 to enhance the quality of the pixel structure.

5A and 5B show two pixel structures of still another embodiment of the present invention. Referring to FIG. 5 , the pixel structure 500 includes a scan line 510 , a data line 520 , a semiconductor pattern 530 , and a pixel electrode 540 . Scan line 510 and data line 520 are staggered and scan line 510 has a branch 512 and branch 512 is located below data line 520. The semiconductor pattern 530 includes at least two channel regions 532A, 532B, at least one doped region 534, and a source region 536 and a drain region 538.

Channel regions 532A, 532B are located below scan line 510, wherein channel regions 532A, 532B have different width to length ratios. Doped region 534 is connected between channel regions 532A and 532B. The pixel electrode 540 is electrically connected to the drain region 538, and the source region 536 is connected between the channel region 532A and the data line 520. In addition, the drain region 538 is connected between the channel region 532B and the pixel electrode 540. Further, the doped region 534 of the present embodiment has an L-type outer shape, wherein the doped region 534 is connected between the channel region 532A and the channel region 532B. The channel region 532A and the portion of the scan line 510, the source region 536 and the drain region 538 below the channel region 532B together form a polysilicon film transistor 550.

In the present embodiment, the semiconductor pattern 530 extends from the first side of the data line 520 to the second side of the data line 520. The source region 536 of the semiconductor pattern 530 is electrically connected to the data line 520 through the contact window Ts, and the drain region 538 is electrically connected to the pixel electrode 540 through the contact window Td. In the pixel structure 500, the contact window Ts and the contact window Td are located on opposite sides of the scanning line 510. Therefore, the bent structure of the semiconductor pattern 530 of the present embodiment traverses both sides of the data line 520, the scan line 510, and the branch 512 to overlap the scan line 510 and its branch 512 over a plurality of regions. Therefore, the pixel structure 500 has a plurality of channel regions 532A and 532B to help reduce the leakage current of the polysilicon film transistor 550 in the off state. In short, the pixel structure 500 has good quality. In addition, the branch 512 of the scan line 510 is located below the data line 520, which can further prevent the display aperture ratio of the pixel structure 500 from being affected.

The extending direction of the branch 512 is substantially perpendicular to the direction in which the scanning line 510 extends, and the length L2 of the channel region 532B below the branch 512 is substantially the same as the width D1 of the branch 512. Therefore, the lengths L2, L1 of the channel regions 532A and 532B in this embodiment are related to the width of the scanning line 510 and the widths D1, D2 of the branch 512, respectively. If the widths D1 and D2 of the scanning line 510 and the branch 512 are wider, the leakage current of the polysilicon thin film transistor 550 can be effectively reduced.

In addition, in order to stabilize the display voltage when the pixel structure 500 is displayed, the semiconductor pattern 530 may further include a capacitor electrode 552 under the pixel electrode 540, which is electrically connected to the drain region 538 and the pixel electrode 540. Furthermore, referring to FIG. 5B , the pixel structure 500 may also be disposed with the common electrode 560 between the pixel electrode 540 and the capacitor electrode 552 . Since the branch 512 of the scan line 510 is located below the data line 520, the positions of the common electrode 560 and the capacitor electrode 552 are not affected by the arrangement of the branches 512, and the position design of the common electrode 560 and the capacitor electrode 552 is further made flexible.

FIG. 6 is a diagram showing a pixel structure according to still another embodiment of the present invention. Referring to FIG. 6, the pixel structure 600 is similar to the pixel structure 500, except that the semiconductor pattern 630 is different from the semiconductor pattern 530. The semiconductor pattern 630 of the pixel structure 600 includes three-channel regions 632A, 632B, 632C and two doped regions 634A, 634B. Additionally, doped regions 634A, 634B are coupled between channel regions 632A, 632B, and 632C. The source region 538 is connected between the channel region 632A and the data line 520, and the drain region 638 is connected between the channel region 632C and the pixel electrode 540. In addition, the capacitor electrode 552 and the branch 512 are respectively located on both sides of the scan line 510.

In the present embodiment, the extending direction of the branch 512 of the scan line 510 is substantially perpendicular to the extending direction of the scan line 510, and the length L of the channel region 632B below the branch 512 is substantially the same as the width D of the branch 512. Therefore, the wider the width D2 of the scan line 510 and its branch 51, the channel regions 632A, 632B, and 632C may have a longer channel length to enhance the electrical characteristics of the polysilicon thin film transistor 650.

The branch 512 is located below the data line 520. Therefore, in the design of the pixel structure 600, only the main line portion of the scan line 510 and the data line 520 is a light shielding film layer. Therefore, the pixel structure 600 has a high display aperture ratio. Additionally, the semiconductor pattern 630 extends from the first side of the data line 520 to the second side to intersect the scan line 510 and its branches 512 in a plurality of regions, namely the channel regions 632A, 632B, and 632C. The three channel regions 632A, 632B and 632C of the semiconductor pattern 630 are connected by L-type doped regions 634A, 634B. The source region 536, the drain region 538, and a portion of the scan lines 510 under the channel regions 632A, 632B, and 632C together form a polysilicon thin film transistor 650. Under such a design, the polysilicon thin film transistor 650 has multiple channels, so that in the off state, leakage current is less likely to occur, which contributes to the pixel structure 600 having good quality.

In summary, the present invention utilizes different semiconductor pattern designs to have a plurality of channel regions in the pixel structure while placing the branches of the scan lines below the data lines. Therefore, the display aperture ratio of the pixel structure is not limited by the branching of the scanning line. That is, the pixel structure of the present invention has a high display aperture ratio. Further, in the pixel structure of the present invention, the semiconductor pattern and the scanning line are overlapped with a plurality of regions to form a plurality of channel regions, which contributes to a reduction in leakage current when the polysilicon film transistor in the pixel structure is in a closed state. Overall, the pixel structure of the present invention has a high display aperture ratio while also having good quality.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100, 200, 300, 400, 500, 600‧‧‧ pixel structure

110, 210, 410, 510‧‧‧ scan lines

Branches 112, 412, 512‧‧

120, 220, 520‧‧‧ data lines

130‧‧‧Polysilicon layer

132, 134, 232A, 232B, 332A, 332B, 332C, 432, 532A, 532B, 632A, 632B, 632C‧‧‧ passage area

136, 236, 336, 536 ‧ ‧ source area

138, 238, 538‧‧ ‧ bungee area

140, 240, 540‧‧ ‧ pixel electrodes

150, 250, 350, 450, 550, 650‧‧‧ polycrystalline germanium film transistors

152‧‧‧ Storage Capacitor

230, 330, 530, 630‧‧‧ semiconductor patterns

234, 334A, 334B, 434A, 434B, 534, 634A, 634B‧‧‧ doped areas

252, 552‧‧‧ Capacitance electrodes

560‧‧‧Common electrode

L, L1, L2‧‧‧ length

Td, Ts‧‧‧ contact window

D, D1, D2, D3‧‧‧ width

FIG. 1 is a schematic diagram of a pixel structure of a conventional polycrystalline germanium thin film transistor liquid crystal display.

2 is a schematic diagram showing the structure of a pixel according to an embodiment of the present invention.

FIG. 3 is a schematic diagram showing the structure of a pixel according to another embodiment of the present invention.

FIG. 4 is a schematic diagram showing the structure of a pixel according to still another embodiment of the present invention.

5A and 5B are schematic diagrams showing the structure of two pixel elements according to still another embodiment of the present invention.

FIG. 6 is a schematic diagram showing the structure of a pixel according to still another embodiment of the present invention.

500. . . Pixel structure

510. . . Scanning line

520. . . Data line

530. . . Semiconductor pattern

532A, 532B. . . Channel area

534. . . Doped region

536. . . Source area

538. . . Bungee area

540. . . Pixel electrode

550. . . Polycrystalline germanium film transistor

552. . . Capacitor electrode

D1, D2. . . width

L1, L2. . . length

Td, Ts. . . Contact window

Claims (8)

A pixel structure includes: a scan line having a branch; a data line interlaced with the scan line, wherein the branch is located below the data line; and a semiconductor pattern comprising: at least two channel regions, located at Below the scan line, at least one of the channel regions is located below the branch, and the length of the channel region below the branch is substantially the same as the width of the branch; at least one doped region is connected between the channel regions a source region and a drain region; and a pixel electrode electrically connected to the drain region, wherein the source region is connected between one of the channel regions and the data line, and the drain region is connected Between another channel region and the pixel electrode. The pixel structure of claim 1, wherein the semiconductor pattern comprises a polysilicon pattern. The pixel structure of claim 2, wherein the semiconductor pattern further comprises a capacitor electrode electrically connected to the drain region and the pixel electrode, wherein the capacitor electrode is located below the pixel electrode. The pixel structure of claim 3, further comprising a common electrode disposed between the capacitor electrode and the pixel electrode. The pixel structure of claim 4, wherein the capacitor electrode and the branch are respectively located on opposite sides of the scan line. The pixel structure as described in claim 1 of the patent scope, wherein the blending The shape of the miscellaneous area includes an L shape. The pixel structure of claim 1, wherein the semiconductor pattern extends from a first side of the data line to a second side of the data line. The pixel structure of claim 1, wherein a portion of the scan line, the source region and the drain region below the channel region form a polycrystalline germanium transistor.