201245830 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種畫素結構，且特別是有關於一種 具有多通道區的畫素結構。 【先前技術】 薄膜電晶體顯示器（Thin Film Transistor Liquid Crystal Display, TFT-LCD )已成為目前許多平面顯示器中 的主流。根據通道層材質的選擇，薄膜電晶體液晶顯示器 可分為非晶石夕薄膜電晶體（amorphous silicon TFT)液晶顯 示器及低溫多晶矽薄膜電晶體（Low-Temperature PolySilicon Thin Film Transistor，LTPS-TFT)液晶顯示器等 兩種。 由於低溫多晶矽薄膜電晶體的電子遷移率可以達到 200cm2/V-sec以上，所以可使薄膜電晶體元件所佔面積更 小以符合高開口率（aperture)的需求，進而增進顯示器的 顯示亮度並減少整體的功率消耗問題。但相對來說，低溫 多晶石夕薄膜電晶體亦具有較高的漏電流（leakage current) (約為10 9微安培）’而且容易在沒極（drain)誘發熱載 子效應（hot carrier effect)，進而導致元件退化。因此， 現今多在低溫多晶石夕薄膜電晶體中之通道區與源極/;及極 之間加入淺摻雜汲極（Light Doped Drain，簡稱LDD)或 是利用多重通道區的設計，以避免上述問題。 圖1為習知之多晶矽薄膜電晶體液晶顯示器之畫素結 201245830 構。請參照圖〗，晝素結構100包括掃描線11〇、資料 120、多晶矽層130以及透明畫素電極14〇。掃描線具 有至少一 L型分支H2，且多晶矽層13〇與L型分支 相交以形成第一通道區132以及第二通道區134。另外， 低溫多晶矽層130的兩端分別有源極區136與汲極區 138’以形成多通道設計的多晶矽薄膜電晶體15〇。資料線 120電性連接源極區136，而透明畫素電極14〇則電性 ，極區U8。此外，多晶石夕層13〇與畫素電極14〇重叠的 = —儲存電容152。因為多通道的設計，低溫多 :23晶體150在關閉的狀態下具有較低的漏電流， 而有助於提昇晝素結構1⑻的品質。然而，L型分支112 響儲存電容152所配置驗置並使得畫素結 構100的顯不開口率下降。 【發明内容】 本發明是提供-種晝素結構 晶石夕薄膜電晶體使書辛 解决夕通道§又计的多 題。 一畜、、、°構的顯不開口率受到限制的問 本發明提出一種書素4士 線、-半導體圖案以及二素包括-掃描線、-資料 排列，並具有一分支，=京電極。掃描線與資料線交錯 案包括ϋί二通;S:且t支位於資料線下方。半導體圖 極區。通道區位於掃描I少—摻雜區以及一源極區與一汲 晝素電極與汲極區電枓下方。摻雜區連接於通道區之間。 運接’其中源極區連接於其.中一個201245830 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a pixel structure, and more particularly to a pixel structure having a multi-channel region. [Prior Art] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has become the mainstream in many flat panel displays. According to the choice of material of the channel layer, the thin film transistor liquid crystal display can be divided into an amorphous silicon TFT liquid crystal display and a low-temperature polysilicon thin film transistor (LTPS-TFT) liquid crystal display. Wait for two. Since the electron mobility of the low-temperature polycrystalline germanium film transistor can reach 200 cm 2 /V-sec or more, the area of the thin film transistor component can be made smaller to meet the requirement of a high aperture ratio, thereby increasing the display brightness of the display and reducing the display brightness. The overall power consumption problem. However, relatively low temperature polycrystalline slab thin film transistors also have a high leakage current (about 10 9 microamperes)' and are easy to induce hot carrier effect in the drain (hot carrier effect) ), which in turn causes component degradation. Therefore, in the low temperature polycrystalline slab film transistor, a light doped Drain (LDD) or a multi-channel region is used in the channel region and the source electrode. Avoid the above problems. 1 is a pictorial junction of a conventional polycrystalline germanium thin film transistor liquid crystal display device 201245830. Referring to the figure, the halogen structure 100 includes a scanning line 11A, a material 120, a polysilicon layer 130, and a transparent pixel electrode 14A. The scan line has at least one L-shaped branch H2, and the polysilicon layer 13A intersects the L-type branch to form a first channel region 132 and a second channel region 134. In addition, the low temperature polysilicon layer 130 has a source region 136 and a drain region 138' at both ends to form a polysilicon film transistor 15 of a multi-channel design. The data line 120 is electrically connected to the source region 136, and the transparent pixel electrode 14 is electrically, and the polar region U8. In addition, the polycrystalline slab layer 13 〇 overlaps with the pixel electrode 14 = = storage capacitor 152. Because of the multi-channel design, the low temperature is more: 23 crystal 150 has a lower leakage current in the closed state, which helps to improve the quality of the halogen structure 1 (8). However, the L-shaped branch 112 responds to the configuration of the storage capacitor 152 and causes the apparent aperture ratio of the pixel structure 100 to decrease. SUMMARY OF THE INVENTION The present invention provides a method for the preparation of a strontium crystal structure. The present invention proposes a book 4 ray, a semiconductor pattern, and a bismuth-including scan line, a data arrangement, and a branch, = a Beijing electrode. The scan line and the data line are interleaved, including ϋί two-way; S: and the t branch is located below the data line. Semiconductor map polar region. The channel region is located below the scan I-doped region and a source region and below the germanium electrode and the drain region. The doped regions are connected between the channel regions.接接' where the source region is connected to one of them
S 4 201245830 ^^㈣線之間，秘純接料—_道區與畫素 方，t 通道區位於分支下 Ϊ上S 刀支下方之通道區的長度與分支的寬度實 石夕圖ί本U之實％例中’上述之半導體圖案包括多晶 在本發明之-實施例中，上述之半導 電容電極，與祕區以及畫素電極電性連接，ί中^電 極位於晝^極下方。糾，«結構更包括1用電電ς 配置於電谷電極與晝素電極之間。 / - » 在本發明之一實施例中，上述之電 位於掃描線的兩侧。 /、为支分別S 4 201245830 ^^(4) between the lines, the secret pure material -_ road area and the pixel side, the t channel area is located on the lower jaw of the branch, the length of the channel area below the S knife branch and the width of the branch. In the case of U, the above-mentioned semiconductor pattern includes polycrystal. In the embodiment of the present invention, the above-mentioned semi-conductive capacitor electrode is electrically connected to the secret region and the pixel electrode, and the electrode is located below the electrode. . Correction, «The structure includes 1 electric ς arranged between the electric valley electrode and the halogen electrode. / - » In one embodiment of the invention, the electrical power is located on either side of the scan line. /, for the branch
形。在本發明之i施例中，上述之摻雜區的形狀包括L 在本發明之一實施例中，上述之 的第一側延伸至資料線的第二側。 圖案由資料線 在本發明之一實施例中，上述之通道區下 描線、源極區與汲極區構成一多晶矽薄膜電晶體的份掃 本發明利用半導體圖案的變化使半導 線至少相交於兩個區域，而有助於降低多晶石^^掃描 的漏電流。另外，本發明將掃描線的分支設置於杳二晶體 方’可以進一步避免晝素結構的顯示開口率受„料線下 而言，本發明所提供的畫素結構具有高顯示開：‘且g 201245830 結構中的多晶矽薄膜電晶體具有良好的電性。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂’下文特舉較佳實施例’並配合所附圖式’作詳細說 明如下。 【實施方式】 圖2為本發明之一實施例之晝素結構。請參照圖2， 晝素結構200電性連接一掃描線21〇及一資料線220，其 中掃描線210及資料線220交錯排列。晝素結構2〇〇、掃 描線210以及資料線220例如是配置於一基板上（未繪 示）。晝素結構200包括一半導體圖案230以及一畫素電極 240。半導體圖案230包括至少二通道區232A、232B、至 少一摻雜區234以及一源極區236與一汲極區238。通道 區232A、232B位於掃描線210下方，其中通道區232A 與通道區232B具有不同的寬度長度比值。摻雜區234連 接於通道區232A與通道區232B之間。晝素電極240與汲 極區238電性連接’其中源極區236連接於通道區232A 與資料線220之間，而汲極區238接於通道區232B與晝 素電極240之間。 位於通道區232A與通道區232B下方的部份掃插線 210在晝素結構200中可視為閘極，以控制晝素結構2〇〇 的開啟與關閉。另外，半導體圖案230例如是由多晶矽材 質製作而成’也就是說半導體圖案230為一多晶石夕圖案。 因此，通道區232A與通道區232B下方的部份掃描線 201245830 源極區236與〉及極區238共同構成一多晶碎薄膜電晶體shape. In the embodiment of the invention, the shape of the doped region described above includes L. In one embodiment of the invention, the first side of the invention extends to the second side of the data line. The pattern is composed of a data line. In an embodiment of the present invention, the channel trace, the source region and the drain region of the channel region constitute a polysilicon film transistor. The invention utilizes a change of the semiconductor pattern to make the half wire intersect at least two. Areas that help reduce the leakage current of the polycrystalline silicon. In addition, the present invention sets the branch of the scan line to the second crystal side to further prevent the display aperture ratio of the halogen structure from being under the material line. The pixel structure provided by the present invention has a high display opening: 'and g The above-mentioned and other objects, features and advantages of the present invention will become more apparent from the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 2 is a structure of a halogen substrate according to an embodiment of the present invention. Referring to FIG. 2, the pixel structure 200 is electrically connected to a scan line 21A and a data line 220, wherein the scan line 210 and the data The pixel structure 220, the scanning line 210 and the data line 220 are disposed on a substrate (not shown), for example. The halogen structure 200 includes a semiconductor pattern 230 and a pixel electrode 240. The 230 includes at least two channel regions 232A, 232B, at least one doped region 234, and a source region 236 and a drain region 238. The channel regions 232A, 232B are located below the scan line 210, wherein the channel region 232A and the pass The track region 232B has different width to length ratios. The doped region 234 is connected between the channel region 232A and the channel region 232B. The germanium electrode 240 is electrically connected to the drain region 238, wherein the source region 236 is connected to the channel region 232A and Between the data lines 220, the drain region 238 is connected between the channel region 232B and the pixel electrode 240. A portion of the sweep line 210 located below the channel region 232A and the channel region 232B can be regarded as a gate in the pixel structure 200. In order to control the opening and closing of the halogen structure 2, the semiconductor pattern 230 is made of, for example, a polycrystalline silicon material, that is, the semiconductor pattern 230 is a polycrystalline stone pattern. Therefore, the channel region 232A and the channel region Part of the scan line below the 232B 201245830 source region 236 and the > and the polar region 238 together constitute a polycrystalline film transistor
250。當多晶矽薄膜電晶體250關閉時，通道區232A、232B 中多晶石夕圖案的晶粒介面可能引發漏電流的現象，而影響 畫素結構200的品質。為了解決多晶石夕薄膜電晶體250關 閉時可能引發漏電流的問題，多重通道設計的概念被提 出。然而，由先前技術可知，為了多重通道設計而設置由 掃描線210沿伸出來的分支會影響晝素結構2〇〇的顯示開 口率。所以’本發明在此提出利用半導體圖案230的折曲 結構以達到多通道的設計。 本實施例之半導體圖案230例如具有多重折曲的結 構’並與掃描線210重疊於多個區域而構成多重通道。半 導體圖案230為透明圖案，因此晝素結構200的顯示開口 率不會因本實施例之多重通道的設計而受到影響。也就是 說，本實施例之晝素結構200不易有漏電流的現象發生， 同時可以維持良好的顯示開口率。 半導體圖案230例如具有U型的摻雜區234，並且連 接U型摻雜區234兩端的半導體圖案230與掃描線210相 交，而構成通道區232A與通道區232B。藉由這樣的設計 使多晶矽薄膜電晶體250有多個通道區232A與232B，以 提升多晶矽薄膜電晶體250的電性特性。 詳細而言，多晶矽薄膜電晶體250開啟時，電流在通 道區232A與232B的傳輸方向例如是垂直於掃描線210的 延伸方向。所以，掃描線210的寬度Dl、D2會影響通道 區232A、232B的長度U、L2。一般來說，通道區232A、 201245830 232B的長度Ll、L2越長則有助於降低多晶矽薄膜電晶體 250的漏電流。因此，為了增加通道區232B的長度L2， 掃描線210位於通道區232B中寬度D2例如是大於掃描線 210在其他區域的寬度D1。當然，在其他實施例中，為了 增加通道區232A的長度L1 ’也可以使掃描線21〇在通道 區202A中的寬度變寬。 半導體圖案230更包括一電容電極252，其與汲極區 238以及晝素電極240電性連接，且電容電極252位於晝 素電極240下方。實際上’在本實施例中摻雜區234、源 極區236、汲極區238與電容電極252是由摻雜的多晶矽 材質所構成。在其他實施例中，晝素結構2〇〇可以更包括 一共用電極(未繪示）’配置於電容電極252與晝素電極24〇 之間。另外’汲極區238是藉由接觸窗Td與晝素電極24〇 電性連接，而源極區236是藉由接觸窗Ts與資料線220 電性連接。在本實施例中，接觸窗Td與接觸窗Ts是位於 掃描線210的同一側，而半導體圖案23〇大致折曲成一 u 型以與掃描線210相交於通道區232A與通道區232B » 當然，接觸窗Td與接觸窗Ts也可以是位於掃描線210 相對的兩側。圖3繪示為本發明之另一實施例的晝素結 構。請參照圖3，畫素結構300與晝素結構200的設計相 似，其中畫素結構300的接觸窗Td與接觸窗Ts是位於掃 插線210相對的兩側。另外，晝素結構3〇〇的半導體圖案250. When the polysilicon thin film transistor 250 is turned off, the grain interface of the polycrystalline spine pattern in the channel regions 232A, 232B may cause leakage current, which affects the quality of the pixel structure 200. In order to solve the problem that leakage current may be caused when the polycrystalline silicon transistor 250 is turned off, the concept of a multi-channel design is proposed. However, it is known from the prior art that the provision of a branch extending along the scan line 210 for a multi-channel design affects the display opening ratio of the pixel structure 2A. Therefore, the present invention proposes to utilize the folded structure of the semiconductor pattern 230 to achieve a multi-channel design. The semiconductor pattern 230 of the present embodiment has, for example, a structure in which a plurality of bends are formed and overlaps the plurality of regions with the scanning line 210 to constitute a plurality of channels. The semiconductor pattern 230 is a transparent pattern, so the display aperture ratio of the halogen structure 200 is not affected by the design of the multiple channels of the present embodiment. That is, the halogen structure 200 of the present embodiment is less prone to leakage current, and at the same time, a good display aperture ratio can be maintained. The semiconductor pattern 230 has, for example, a U-shaped doped region 234, and the semiconductor pattern 230 connected across the U-doped region 234 intersects the scan line 210 to form a channel region 232A and a channel region 232B. With such a design, the polysilicon thin film transistor 250 has a plurality of channel regions 232A and 232B to enhance the electrical characteristics of the polysilicon thin film transistor 250. In detail, when the polysilicon film transistor 250 is turned on, the direction of current flow in the channel regions 232A and 232B is, for example, perpendicular to the direction in which the scanning line 210 extends. Therefore, the widths D1, D2 of the scan lines 210 affect the lengths U, L2 of the channel regions 232A, 232B. In general, the longer the lengths L1, L2 of the channel regions 232A, 201245830 232B, the lower the leakage current of the polysilicon film transistor 250. Therefore, in order to increase the length L2 of the channel region 232B, the width D2 of the scan line 210 in the channel region 232B is, for example, greater than the width D1 of the scan line 210 in other regions. Of course, in other embodiments, the width of the scan line 21 〇 in the channel region 202A may be widened in order to increase the length L1 ′ of the channel region 232A. The semiconductor pattern 230 further includes a capacitor electrode 252 electrically connected to the drain region 238 and the pixel electrode 240, and the capacitor electrode 252 is located below the pixel electrode 240. Actually, in the present embodiment, the doping region 234, the source region 236, the drain region 238, and the capacitor electrode 252 are composed of a doped polysilicon material. In other embodiments, the halogen structure 2〇〇 may further include a common electrode (not shown) disposed between the capacitor electrode 252 and the halogen electrode 24〇. In addition, the drain region 238 is electrically connected to the pixel electrode 24A through the contact window Td, and the source region 236 is electrically connected to the data line 220 through the contact window Ts. In the present embodiment, the contact window Td and the contact window Ts are located on the same side of the scan line 210, and the semiconductor pattern 23 is substantially bent into a u-shape to intersect the scan line 210 in the channel region 232A and the channel region 232B. The contact window Td and the contact window Ts may also be located on opposite sides of the scan line 210. 3 is a diagram showing a pixel structure of another embodiment of the present invention. Referring to FIG. 3, the pixel structure 300 is similar to the design of the pixel structure 200, wherein the contact window Td of the pixel structure 300 and the contact window Ts are located on opposite sides of the scanning line 210. In addition, the semiconductor pattern of the three-dimensional structure of the halogen structure
330具有三個通道區332A、332B、332C以及兩個ϋ型的 摻雜區 334Α、334Β。此時’通道區 332Α、332Β、332C330 has three channel regions 332A, 332B, 332C and two doped regions 334, 334. At this time, the channel area 332Α, 332Β, 332C
S 201245830 下方的部份掃描線210、源極區236與汲極區238共同構 成一多晶矽薄膜電晶體350。 在本實施例中，掃描線210與半導體圖案330相交的 部伤分別具有不同的寬度Dl、D2及D3。所以，通道區 332A、通道區332B及通道區332(：可以具有不同的寬度 長度比值。實務上，掃描線21〇對應於通道區332A、332b、 3。320中的寬度D卜D2、D3可以大於掃描線210在其他 區域中的寬度，以使多晶矽薄膜電晶體35〇具有較好的電 性特性。此外’半導體圖案33〇例如為多晶矽材質所製成， 而多晶矽材質具有可透光的特性。因此，本實施例中折曲 狀半導體圖案330的結構可以達到多重通道的設計，並同 時使晝素結構300具有良好的顯示開口率。 圖4繪示為本發明之再一實施例之晝素結構。請參照 圖4，晝素結構400與圖2之晝素結構2〇〇相似，資料線 420與掃描線410交錯排列，其不同之處在於，掃描線41〇 具有一分支412，且分支412與半導體圖案230相交。半 導體圖案230與分支412相交的部分構成通道區432，而 摻雜區434A與434B則分別是位於通道區232A與通道區 432之間，以及通道區232B與通道區432之間。實務上， 本實施例之半導體圖案230與圖2之半導體圖案23〇之外 型相同，而由於分支412的設計而使晝素結構4⑻中具有 二個通道區232A、232B及432。另外，摻雜區434A與 434B的外型也由U型改變成兩個l型。 畫素結構400利用與晝素結構2〇〇相同的半導體圖案 201245830 230以形成三個通道區232A、232B及432，則通道區 232A、232B及432下方的部份掃描線41〇、源極區236與 汲極區238共同構成一多晶矽薄膜電晶體45〇。因為多重 通道的設計而使多晶矽薄膜電晶體45〇在關閉狀態下不易 發生漏電流的現象。 此外，分支412為一矩形圖案，相較於習知之[型分 支112而言，本實施例之設計有助於使晝素結構4〇〇保有 良好的顯示開口率。分支412與電容電極252分別位於掃 描線410的兩側，所以電容電極252的配置位置及面積不 會受到分支142的影響。也就是說，隨著不同的設計需求， 電容電極252可配置在掃描線410與資料線220所圍區域 的任何位置上。另外，分支412的延伸方向實質上垂直於 掃描線410的延伸方向’而分支412下方之通道區432的 長度與分支412的寬度D實質上相同。因此，掃描線410 與分支412的線寬變化可使各通道區232A、232B及432 之間有不同的長度寬度比值。本實施例利用與半導體圖案 230相同的設計使晝素結構400具有兩個以上的通道區 232A、232B及432，以提昇晝素結構的品質。 圖5A與圖5B為本發明之又一實施例之兩種晝素結 構。請參照圖5，畫素結構500包括一掃描線510、一資料 線520、一半導體圖案530以及一晝素電極540。掃描線 510及資料線520交錯排列並且掃描線510具有一分支 512，且分支512位於資料線520下方。半導體圖案530 包括至少二通道區532A、532B、至少一摻雜區534以及 201245830 一源極區536與一汲極區538。 通道區532A、532B位於掃描線510下方，其中通道 區532A、532B具有不同的寬度長度比值。摻雜區534連 接於通道區532A與532B之間。晝素電極540與汲極區 538電性連接’而源極區536連接於通道區532A與資料線 520之間。另外’汲極區538連接於通道區532B與晝素電 極540之間。進一步而言’本實施例之摻雜區534具有l 型之外型，其中摻雜區534連接於通道區532A與通道區 532B之間。通道區532A與通道區532B下方的部份掃描 線510、源極區536與汲極區538共同構成一多晶矽薄臈 電晶體550。 ' 在本實施例中’半導體圖案530由資料線520的第一 側延伸至資料線520的第二側。半導體圖案530之源極區 536例如是藉由接觸窗Ts與資料線52〇電性連接，而及極 區538則是藉由接觸窗Td與晝素電極540電性連接。書 素結構500中’接觸窗Ts與接觸窗Td是位於掃描線 相對的兩側。因此，本實施例之半導體圖案53〇的折曲釺 構橫越資料線520、掃描線510及分支512的兩側以與掃 描線510及其分支512重疊於多個區域。所以，晝素結構 500具有多個通道區532A與532B ’以有助於減低多晶石夕 薄膜電晶體550在關閉狀態下發生漏電流的情形。^古 之，晝素結構500具有良好的品質。另外，掃描線51〇: 分支512位於資料線520下方，可進一步避免晝素結構5〇〇 的顯示開口率受到影響。 201245830 分支512的延伸方向實質上垂直於掃描線51〇的延伸 方向，且分支512下方之通道區532B的長度L2與分支512 的寬度D1實質上相同。因此，本實施例中通道區532A與 532B的長度L2、L1分別與掃描線510的寬度及分支512 的寬度D1、D2有關。若掃描線510與分支512的寬度D1、 D2越寬，則越可有效降低多晶矽薄膜電晶體55〇的漏電 流。 另外’為了穩定畫素結構500進行顯示時的顯示電 壓’半導體圖案530可以更包括一位於晝素電極540下方 之電容電極552，其與汲極區538以及晝素電極54〇電性 連接。更進一步來說，請參照圖5B，晝素結構5〇〇也可以 配置有共用電極560於晝素電極540與電容電極552之 間。由於掃描線510的分支512位於資料線520下方，所 以共用電極560與電容電極552的位置不會受到分支512 的配置而影響，進一步使共用電極56〇與電容電極552的 位置設計較具有彈性。 圖6繪示為本發明之再一實施例之畫素結構。請參照 圖6，晝素結構600與晝素結構5〇〇相似，其差異在於半 導體圖案630與半導體圖案53〇的外型不同。晝素結構6〇〇 之半導體圖案630包括三通道區632A、632B、632C以及 二摻雜區634A、634B。此外，摻雜區634A、634B連接於 通道區632A、632B與632C之間。源極區538連接於通 道區632A與資料線520之間，而汲極區638連接於通道 區632C與晝素電極540之間。另外，電容電極552與分A portion of the scan line 210, the source region 236, and the drain region 238 under S 201245830 together form a polysilicon thin film transistor 350. In the present embodiment, the portion of the scan line 210 intersecting the semiconductor pattern 330 has different widths D1, D2, and D3, respectively. Therefore, the channel region 332A, the channel region 332B, and the channel region 332 (: may have different width-to-length ratios. In practice, the scan line 21A corresponds to the channel region 332A, 332b, 3. The width D in D2 D2, D3 may It is larger than the width of the scan line 210 in other regions, so that the polycrystalline germanium thin film transistor 35 has good electrical properties. Further, the 'semiconductor pattern 33 is made of, for example, a polycrystalline germanium material, and the polycrystalline germanium material has a light transmissive property. Therefore, the structure of the folded semiconductor pattern 330 in this embodiment can achieve the design of multiple channels, and at the same time, the halogen structure 300 has a good display aperture ratio. FIG. 4 is a diagram showing another embodiment of the present invention. Referring to FIG. 4, the pixel structure 400 is similar to the pixel structure 2A of FIG. 2, and the data line 420 and the scan line 410 are staggered, except that the scan line 41 has a branch 412, and The branch 412 intersects the semiconductor pattern 230. The portion of the semiconductor pattern 230 that intersects the branch 412 constitutes the channel region 432, while the doped regions 434A and 434B are located between the channel region 232A and the channel region 432, respectively. And between the channel region 232B and the channel region 432. In practice, the semiconductor pattern 230 of the present embodiment is identical in appearance to the semiconductor pattern 23 of FIG. 2, and has two of the pixel structures 4 (8) due to the design of the branch 412. The channel regions 232A, 232B, and 432. In addition, the shapes of the doping regions 434A and 434B are also changed from U-shape to two-type L. The pixel structure 400 is formed by using the same semiconductor pattern 201245830 230 as the halogen structure 2〇〇. The three channel regions 232A, 232B and 432, the portion of the scan line 41A below the channel regions 232A, 232B and 432, the source region 236 and the drain region 238 together form a polysilicon thin film transistor 45. Because of the multiple channels The polycrystalline silicon thin film transistor 45 is designed to be less prone to leakage current in the off state. Further, the branch 412 is a rectangular pattern, and the design of the present embodiment contributes to the design of the [type branch 112]. The halogen structure 4〇〇 maintains a good display aperture ratio. The branch 412 and the capacitor electrode 252 are respectively located on both sides of the scan line 410, so the arrangement position and area of the capacitor electrode 252 are not affected by the branch 142. It is said that, with different design requirements, the capacitor electrode 252 can be disposed at any position of the area surrounded by the scan line 410 and the data line 220. In addition, the extending direction of the branch 412 is substantially perpendicular to the extending direction of the scan line 410. The length of the channel region 432 below the 412 is substantially the same as the width D of the branch 412. Therefore, the change in the line width of the scan line 410 and the branch 412 allows for different length to width ratios between the channel regions 232A, 232B, and 432. The embodiment utilizes the same design as the semiconductor pattern 230 to provide the halogen structure 400 with more than two channel regions 232A, 232B, and 432 to enhance the quality of the pixel structure. Figures 5A and 5B show two alternative pixel structures of another embodiment of the present invention. Referring to FIG. 5, the pixel structure 500 includes a scan line 510, a data line 520, a semiconductor pattern 530, and a halogen electrode 540. Scan line 510 and data line 520 are staggered and scan line 510 has a branch 512 and branch 512 is located below data line 520. The semiconductor pattern 530 includes at least two channel regions 532A, 532B, at least one doped region 534, and 201245830 a source region 536 and a drain region 538. Channel regions 532A, 532B are located below scan line 510, wherein channel regions 532A, 532B have different width to length ratios. Doped region 534 is connected between channel regions 532A and 532B. The halogen electrode 540 is electrically connected to the drain region 538 and the source region 536 is connected between the channel region 532A and the data line 520. Further, the drain region 538 is connected between the channel region 532B and the halogen electrode 540. Further, the doped region 534 of the present embodiment has a l-type profile in which a doped region 534 is connected between the channel region 532A and the channel region 532B. The channel region 532A and the portion of the scan line 510, the source region 536 and the drain region 538 below the channel region 532B together form a polysilicon thin transistor 550. The semiconductor pattern 530 in the present embodiment extends from the first side of the data line 520 to the second side of the data line 520. The source region 536 of the semiconductor pattern 530 is electrically connected to the data line 52, for example, via the contact window Ts, and the polar region 538 is electrically connected to the pixel electrode 540 via the contact window Td. In the book structure 500, the contact window Ts and the contact window Td are located on opposite sides of the scanning line. Therefore, the bent structure of the semiconductor pattern 53A of the present embodiment traverses both sides of the data line 520, the scanning line 510, and the branch 512 to overlap the scanning line 510 and its branch 512 over a plurality of regions. Therefore, the halogen structure 500 has a plurality of channel regions 532A and 532B' to help reduce the leakage current of the polycrystalline spine transistor 550 in the off state. ^ Ancient, the alizarin structure 500 has good quality. Further, the scanning line 51A: the branch 512 is located below the data line 520, and it is further prevented that the display aperture ratio of the pixel structure 5A is affected. The extension direction of the branch 512 of 201245830 is substantially perpendicular to the extending direction of the scanning line 51A, and the length L2 of the channel region 532B below the branch 512 is substantially the same as the width D1 of the branch 512. Therefore, the lengths L2, L1 of the channel regions 532A and 532B in this embodiment are related to the width of the scanning line 510 and the widths D1, D2 of the branch 512, respectively. If the widths D1, D2 of the scanning line 510 and the branch 512 are wider, the leakage current of the polysilicon thin film transistor 55A can be effectively reduced. Further, the display voltage for display when the pixel structure 500 is stabilized may further include a capacitor electrode 552 located below the pixel electrode 540, which is electrically connected to the drain region 538 and the pixel electrode 54. Furthermore, referring to FIG. 5B, the halogen structure 5〇〇 may be disposed with the common electrode 560 between the pixel electrode 540 and the capacitor electrode 552. Since the branch 512 of the scan line 510 is located below the data line 520, the positions of the common electrode 560 and the capacitor electrode 552 are not affected by the arrangement of the branches 512, and the position design of the common electrode 56 and the capacitor electrode 552 is further made flexible. FIG. 6 is a diagram showing a pixel structure according to still another embodiment of the present invention. Referring to Fig. 6, the halogen structure 600 is similar to the halogen structure 5, except that the semiconductor pattern 630 is different from the semiconductor pattern 53A. The semiconductor pattern 630 of the germanium structure 6" includes three-channel regions 632A, 632B, 632C and two doped regions 634A, 634B. Further, doped regions 634A, 634B are connected between channel regions 632A, 632B and 632C. The source region 538 is connected between the channel region 632A and the data line 520, and the drain region 638 is connected between the channel region 632C and the pixel electrode 540. In addition, the capacitor electrode 552 and points
S 12 201245830 支512分別位於掃描線51〇的兩侧。 在本實施例中，掃描線510之分支512的延伸方向實 質上垂直於掃描線510的延伸方向，而分支512下方之通 道區632B的長度L與分支512的寬度D實質上相同。因 此，掃描線510與其分支51的寬度D2越寬時，通道區 632jV、632B與632C可具有較長的通道長度，以提升多晶 碎薄膜電晶體650的電性特性。S 12 201245830 The branches 512 are respectively located on both sides of the scanning line 51〇. In the present embodiment, the extending direction of the branch 512 of the scanning line 510 is substantially perpendicular to the extending direction of the scanning line 510, and the length L of the channel region 632B below the branch 512 is substantially the same as the width D of the branch 512. Therefore, the wider the width D2 of the scan line 510 and its branch 51, the channel regions 632jV, 632B and 632C may have a longer channel length to enhance the electrical characteristics of the polycrystalline thin film transistor 650.
>上分支512位於資料線52〇下方，所以晝素結構6〇〇的 〇又汁中僅掃描線510與資料線520的主要線路部份為遮光 膜層。因此，晝素結構600具有高顯示開口率。另外，半 導體圖案630由資料線52〇的第一側延伸至第二側，以與 掃描線510及其分支512相交於多個區域，也就是通道區 632A、632B與632〇半導體圖案63〇之三個通道區632A、 632B與632C間由L型的換雜區634A、634B所連接。源 極區536、汲極區538以及位於通道區632A、632B盥632C 下方的ί份掃描線51°共同構成-多日日日石夕薄膜電晶體 650。在這樣的設計下，多晶石夕薄膜電晶體㈣具有多重通 道’因此Μ狀態時’不易發生漏電流的現象，而有助於 使晝素結構600具有良好的品質。 、’、’τ'上所述’本發明利用不同的半導體圖案設計，使畫 素結構中具有多個通道區，同時將掃描_分支設置於資 料線下f目此’晝素結構的顯示開σ率不會因掃描線的 分^受麻制。亦即，本發明之晝素結構具有高顯示開 口；<另外’本發明之晝素結構中，半導體圖案與掃描線 201245830 3===成多個通道區，有助於降低晝素結構 體而言，在關閉狀態時產生漏電流的情形。整 有良好的品質。·^素結構具有高顯示開口率，同時也具 限定發Γ已以較佳實施例揭露如上，㈣並非用以 脱離太壬何所屬技術領域中具有通常知識者，在不 月之精神和範圍内，當可作些許之更動與潤飾， 、4《明之保護朗當視後附之中請專職圍所界定者 為準。 【圖式簡單說明] 圖1為習知之多晶矽薄膜電晶體液晶顯示器之晝素結 構示意圖。 圖2為本發明之一實施例之晝素結構示意圖。 圖3綠示為本發明之另一實施例的畫素結構示意圖。 圖4緣示為本發明之再一實施例之畫素結構示意圖。 圖5Α與圖5Β為本發明之又一實施例之兩種畫素結構 示意圖。 圖6繪示為本發明之再一實施例之畫素結構示意圖。 201245830 【主要元件符號說明】 100、200、300、400、500、600 :晝素結構 110、210、410、510 :掃描線 112、412、512 :分支 120、220、520 :資料線 130 :多晶矽層 132、134、232A、232B、332A、332B、332C、432、 532A、532B、632A、632B、632C :通道區 136、236、336、536 :源極區 138、238、538 :汲極區 140、240、540 :晝素電極 150、250、350、450、550、650 :多晶矽薄膜電晶體 152 :儲存電容 230、330、530、630 :半導體圖案 234、334A、334B、434A、434B、534、634A、634B : 摻雜區 252、552 :電容電極 5 60 .共用電極 L、LI、L2 :長度 Td、Ts :接觸窗 D、D卜D2、D3 :寬度 15> The upper branch 512 is located below the data line 52, so that only the main line portion of the scanning line 510 and the data line 520 is a light shielding film layer. Therefore, the halogen structure 600 has a high display aperture ratio. In addition, the semiconductor pattern 630 extends from the first side of the data line 52A to the second side to intersect the scan line 510 and its branch 512 in a plurality of regions, that is, the channel regions 632A, 632B, and 632, the semiconductor pattern 63. The three channel regions 632A, 632B and 632C are connected by L-shaped replacement regions 634A, 634B. The source region 536, the drain region 538, and the 扫描 scanning line 51° located below the channel regions 632A, 632B 盥 632C collectively constitute a multi-day day-and-day lithography film 650. Under such a design, the polycrystalline silicon thin film transistor (4) has a plurality of channels 'so that the leakage current is less likely to occur in the germanium state, and contributes to the good quality of the halogen structure 600. The invention uses different semiconductor pattern designs to have a plurality of channel regions in the pixel structure, and at the same time, the scan_branch is set under the data line, and the display of the pixel structure is opened. The σ rate is not affected by the division of the scan line. That is, the halogen structure of the present invention has a high display opening; <in addition, in the halogen structure of the present invention, the semiconductor pattern and the scanning line 201245830 3=== into a plurality of channel regions, contributing to the reduction of the halogen structure In this case, a leakage current is generated in the off state. Good quality. The structure has a high display aperture ratio, and at the same time, it has a limited hairpin which has been disclosed in the preferred embodiment as above. (4) It is not used to deviate from the general knowledge in the technical field of the art, in the spirit and scope of the moon. Within, when there are some changes and refinements that can be made, 4 of the "Protection of the Ming Dynasty" is subject to the definition of full-time enclosure. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing the structure of a conventional polycrystalline germanium thin film transistor liquid crystal display. 2 is a schematic view showing the structure of a halogen in accordance with an embodiment of the present invention. FIG. 3 is a schematic diagram showing the structure of a pixel according to another embodiment of the present invention. FIG. 4 is a schematic diagram showing the structure of a pixel according to still another embodiment of the present invention. 5A and 5B are schematic diagrams showing two pixel structures of still another embodiment of the present invention. FIG. 6 is a schematic diagram showing the structure of a pixel according to still another embodiment of the present invention. 201245830 [Description of main component symbols] 100, 200, 300, 400, 500, 600: Alizarin structure 110, 210, 410, 510: Scanning lines 112, 412, 512: Branches 120, 220, 520: Data line 130: Polysilicon Layers 132, 134, 232A, 232B, 332A, 332B, 332C, 432, 532A, 532B, 632A, 632B, 632C: channel regions 136, 236, 336, 536: source regions 138, 238, 538: bungee regions 140 , 240, 540: halogen electrodes 150, 250, 350, 450, 550, 650: polycrystalline germanium film transistor 152: storage capacitors 230, 330, 530, 630: semiconductor patterns 234, 334A, 334B, 434A, 434B, 534, 634A, 634B: doped regions 252, 552: capacitor electrode 5 60. common electrode L, LI, L2: length Td, Ts: contact window D, D Bu D2, D3: width 15