JPH098314A - Thin film transistor - Google Patents

Abstract

PURPOSE: To obtain a thin film transistor in which the OFF current is reduced by eliminating the OFF current flowing along the crystal grain boundary in a channel region and a lightly doped region and the ON/OFF current ratio is enhanced while suppressing the fluctuation by avoiding the increase of OFF current being produced statistically. CONSTITUTION: In the semiconductor layer 2 constituting a TFT 101 of LDD structure, the region including, a channel region 6 and a lightly doped regions 9a, 9b is formed narrower than half the grain size of polysilicon.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor, and more particularly to the structure of a thin film transistor (hereinafter referred to as TFT) used for a switching element of a liquid crystal display device.

[0002]

2. Description of the Related Art Generally, a TFT used as a switching element of a liquid crystal display device has a large ON current,
In addition, it is required that the leak current (off current) is small, that is, the on / off current ratio is high. The reason for this is that, for example, in the case of a liquid crystal display device, a high ON current is required to charge the pixel electrodes in a short time, and in order to hold the charged charges for one frame. This is because a low OFF current is required.

Further, in order to realize a liquid crystal display device having good display quality and display quality without display unevenness and point defect picture elements,
It is necessary to suppress variations in electrical characteristics of each pixel TFT. For example, a pixel T having a large off current value of the TFT
If FT is present, the charged electric charge cannot be retained for one frame, and a sufficient voltage cannot be applied to the liquid crystal, so that the light transmittance of the liquid crystal of the picture element is different from the normal one. As a result, point-defect picture elements such as bright spots or display unevenness occur, resulting in deterioration of display quality and display quality.

As a method of increasing the above-mentioned on / off current ratio, conventionally, for example, in the case of a polysilicon TFT, the on-current is improved and the off-current is reduced by improving the crystallinity by expanding the crystal grain size or the like. Methods have been reported (eg literature: IDRC '94 WORKSHOP; A
MLCDs 1.7 Lehighly unv.).

[0005]

As described above, by increasing the crystal grain size, the on-current can be improved and the off-current can be reduced, and the on / off current ratio can be increased. There is a risk that a TFT having extremely poor electrical characteristics is stochastically generated due to the positional relationship between the channel portion and the channel portion.

That is, for example, in a TFT in which a crystal grain boundary exists so as to cross a channel region so as to connect from a source region to a drain region, a leak current easily flows along the crystal grain boundary, so that the TFT is turned off. The current value suddenly increases.

Therefore, the voltage which should be originally applied to the liquid crystal corresponding to the picture element TFT is not applied, and the light transmittance of the liquid crystal deviates from the normal one, and as a result, the display unevenness and the point defect picture element are eliminated. Will be generated. in this way,
A TFT having extremely poor electrical characteristics significantly deteriorates the display quality and display quality of a liquid crystal display device.
It is considered that the presence of such a TFT is a fatal defect for the liquid crystal display device.

Conventionally, in a pixel TFT used in a liquid crystal display device, the channel region width is determined irrespective of the crystal grain size, so that the off current varies widely due to the stochastic generation of TFTs having extremely poor off characteristics. However, it has been difficult to prevent display unevenness and point defects in conventional liquid crystal display devices.

The present invention has been made in view of the above problems, and provides a thin film transistor which has a low off-current, a small variation in the off-current, and a stochastic increase in leak current. The purpose is to

[0010]

A thin film transistor according to the present invention (Claim 1) comprises a semiconductor layer formed on an insulating substrate and a semiconductor layer formed on the insulating substrate so as to face the semiconductor layer via an insulating film. Electrode formed so as to be located in the semiconductor layer, a channel region formed in a portion of the semiconductor layer facing the gate electrode, and a high-concentration impurity region formed in the semiconductor layer on both sides of the channel region. It has and.
The semiconductor layer has a channel region having a structure in which there is no current path from one of the high-concentration impurity regions to the other along the crystal grain boundary of the polycrystalline silicon forming the semiconductor layer. . Thereby, the above object is achieved.

A thin film transistor according to the present invention (claim 2) is formed so as to be located on a semiconductor layer formed on an insulating substrate and on the insulating substrate so as to face the semiconductor layer with an insulating film interposed therebetween. A gate electrode, a channel region formed in a portion of the semiconductor layer facing the gate electrode, and a high-concentration impurity region formed in the semiconductor layer so as to be adjacent to the channel region. . The dimension of the portion of the semiconductor layer that is the channel region in the direction perpendicular to the direction in which the operating current flows is smaller than 1/2 of the average crystal grain size of the polycrystalline silicon forming the semiconductor layer. ing. Thereby, the above object is achieved.

A thin film transistor according to the present invention (claim 3) is formed so as to face a semiconductor layer formed on an insulating substrate and to face the semiconductor layer via an insulating film on the insulating substrate. A gate electrode, a channel region formed in a portion of the semiconductor layer facing the gate electrode, a high-concentration impurity region formed on both sides of the channel region in the semiconductor layer, and a semiconductor layer in the semiconductor layer. And a low concentration impurity region formed so as to be located between the channel region and at least one of the both high concentration impurity regions. The semiconductor layer has both the channel region and the low-concentration impurity region, or one of the channel region and the low-concentration impurity region along the crystal grain boundary of the polycrystalline silicon forming the semiconductor layer. The structure is such that there is no current path from one end of the concentration impurity region to the other end. Thereby, the above object is achieved.

A thin film transistor according to the present invention (claim 4) is formed so as to face a semiconductor layer formed on an insulating substrate and to face the semiconductor layer via an insulating film on the insulating substrate. A gate electrode, a channel region formed in a portion of the semiconductor layer facing the gate electrode, a high-concentration impurity region formed on both sides of the channel region in the semiconductor layer, and a semiconductor layer in the semiconductor layer. And a low concentration impurity region formed so as to be located between the channel region and at least one of the both high concentration impurity regions. In the semiconductor layer, both the channel region and the low-concentration impurity region, or either the channel region and the low-concentration impurity region, the semiconductor layer has a dimension in a direction perpendicular to a direction in which an operating current flows. The average crystal grain size of polycrystalline silicon is smaller than ½. Thereby, the above object is achieved.

The present invention (Claim 5) is defined by Claim 1 or 2.
In the thin film transistor described, a plurality of the channel regions are provided in parallel.

The present invention (Claim 6) is defined by Claim 3 or 4.
In the thin film transistor described above, a plurality of both of the channel region and the low-concentration impurity region or one of the channel region and the low-concentration impurity region are provided in parallel.

[0016]

According to the present invention (claim 1), the high-concentration impurity regions on both sides of the channel region of the semiconductor layer forming the thin film transistor are formed along the crystal grain boundaries of the polycrystalline silicon forming the semiconductor layer. Since there is no current path from one side to the other side, the off current does not flow along the crystal grain boundaries in the channel region. Therefore, the off-current value can be reduced, and the stochastic increase of the off-current can be completely eliminated, whereby the on / off current ratio can be improved and its variation can be suppressed.

In the present invention (claim 2), the dimension of the channel region of the semiconductor layer forming the thin film transistor in the direction perpendicular to the direction in which the operating current flows is the average of the polycrystalline silicon forming the semiconductor layer. 1/2 of crystal grain size
Since the structure is narrower than that, crystal grain boundaries are not formed in a state where the channel region is connected from the source region to the drain region. Therefore, it is possible to reduce the off-current value as described above and completely eliminate the stochastic increase in the off-current, thereby improving the on / off current ratio and suppressing the variation thereof.

In the present invention (claim 3), LDD
Both the channel region and the low-concentration impurity region of the semiconductor layer forming the thin film transistor of the structure, or one of these is provided along the crystal grain boundary of the polycrystalline silicon forming the semiconductor layer. Since there is no current path from one side end to the other side end, the off current flowing along the crystal grain boundaries in the channel region or the low concentration impurity region can be completely removed, thereby turning on / off. It is possible to improve the current ratio and suppress variations in the on / off current ratio.

In the present invention (claim 4), LDD
Both the channel region and the low-concentration impurity region of the semiconductor layer forming the thin film transistor having the structure have a dimension in the direction perpendicular to the direction in which the operating current flows, and the polycrystalline silicon forming the semiconductor layer Since the structure is narrower than 1/2 of the average crystal grain size of, the on / off current ratio can be improved and the variation in the on / off current ratio can be suppressed.

That is, when the width of the region including the low concentration impurity region and the channel region of the semiconductor layer is ½ or less of the crystal grain size, that is, 1 μm or less, the channel region and the low concentration impurity region are The off current flowing along the crystal grain boundaries can be completely removed. Therefore, the off-current value can be reduced, and the stochastic increase of the off-current can be completely eliminated, and the on / off current ratio can be improved and its variation can be suppressed.

Further, when the width of the region including the low concentration impurity region of the semiconductor layer is narrower than the crystal grain boundary, that is, 1 μm or less, off flowing along the crystal grain boundary in the low concentration impurity region. The current can be completely removed, the off current value can be reduced and the variation can be dramatically improved, and the width of the channel region is not narrowed.
There is an advantage that the on-current can be steeply raised in a bias state where the on-current is not limited by the resistance value of the low-concentration impurity region, that is, a so-called subthreshold region, and the switching operation can be speeded up.

When the width of the region including the channel region of the semiconductor layer is narrower than the crystal grain boundary, that is, 1 μm or less, the crystal grain boundary is connected in the channel region from the source region to the drain region. Is not formed, a rapid increase in off-current can be suppressed, and since the width of the low-concentration impurity region is not narrowed, the resistance value of the low-concentration impurity region is low and a large on-current can be obtained. It is possible to further improve the on / off current ratio.

According to the present invention (claim 5), in the thin film transistor according to claim 1 or 2, since a plurality of the channel regions are provided in parallel, the on-state is obtained by narrowing the width of each channel region. A reduction in current can be avoided.

In the present invention (claim 6), in the thin film transistor according to claim 3 or 4, a plurality of both the channel region and the low concentration impurity region, or one of these regions are provided in parallel. Therefore, it is possible to avoid reduction of the on-current due to narrowing the width of each channel region or the low concentration impurity region.

[0025]

First, the basic principle of the present invention will be described.

It is generally known that a polycrystalline silicon thin film is composed of a set of single crystal grains, and the crystal grain size is about several microns. It is considered that there is a crystal grain boundary at the boundary between the crystal grains and the crystal grain boundary does not adversely affect the electrical characteristics of the TFT and is a cause.

In the case of a TFT used in a liquid crystal display device, for example, it is important to keep the leak current in the off state small.

In FIG. 2, LDD (lightly doped drain)
3 shows the channel width dependence of off-state current in a polycrystalline silicon TFT having a structure. Here, the dotted line shows the average value of the data in each gate width of the off current.

In the case of single crystal silicon, it is generally known that the off-state current of a transistor changes linearly with the channel width. However, as shown in the figure, in polycrystalline silicon, the off-current has a non-linear relationship with the channel width, and especially when the channel width exceeds 1 μm, the off-current value is extremely large and its variation increases. I understand that. The crystal grain size of this polycrystalline silicon TFT is about 2 to 3 μm.

This phenomenon can be explained by considering the off-current as the sum of the following two factors in consideration of the positional relationship between the channel and the grain boundary (see FIGS. 3 and 4). ).

Constituent element A: Off-current flowing vertically through the grain boundaries Constituent element B: Off-current flowing along the grain boundaries When the channel width is 1 μm, the channel width is 1/2 or less of the crystal grain size. Therefore, if the distance between the source region and the drain region is equal to or larger than the crystal grain size, the crystal grain boundary is not formed in a form connecting from the source region to the drain region. Therefore, it is considered that the off current is composed of only the constituent element A. It is considered that the constituent element A does not particularly depend on the positional relationship between the crystal grain size and the channel region. From the above, in this case, it is considered that the off current value and its variation are small.

On the other hand, when the channel width is 1.5 μm and 2 μm, even if the distance between the source region and the drain region is equal to or larger than the crystal grain size, depending on the positional relationship between the channel region and the crystal grain boundary, the source region may be formed. Since a pixel TFT having a crystal grain boundary connected from the drain region to the drain region is generated stochastically, the off current is composed of the sum of the constituent element A and the constituent element B in the picture element TFT. Is expected to increase rapidly.

In an actual individual pixel TFT, the ratio of the constituent elements A and B constituting the entire off current depends on the positional relationship between the channel region and the crystal grain boundary in each TFT, and the constituent ratio also. From the results of FIG. 2, when the channel width of 2 μm is extrapolated from the results up to the channel width of 1 μm, the component A is 0.04 to 0.
1 pA, whereas component B is 0 to 0.3 pA
Therefore, it is considered that the component B has a variation of about three times that of the component A.

Therefore, it is considered that, due to the contribution of the constituent element B, the variation in the off current between the picture element TFTs included in one liquid crystal display device also increases sharply.

From the above, the channel width is narrower than the crystal grain size, that is, about 1/2 or less of the crystal grain size, and the distance between the source and the drain is longer than the crystal grain size (at least the crystal grain size). (Equal or higher), the crystal grain boundaries are not formed in a form connecting from the source region to the drain region. Here, FIG. 4 schematically shows the relationship between the grain boundary connections and the channel width.

That is, in this case, the off-current is constituted by the off-current component of only the above-mentioned constituent element A, so that the off-current can be reduced and the TFT in which the off-current is increased stochastically. It is thought that this can be prevented.

On the other hand, when the channel width is wider than the crystal grain size, that is, when the channel width is approximately equal to or larger than the crystal grain size, regardless of the length of the channel or the length of the low concentration impurity region, the drain from the source is drained. The crystal grain boundaries are formed so that they are connected to each other.

That is, in this case, the above-mentioned component A,
It is considered that the off current is constituted by both current components of B, the value of the off current and its variation become large, and a TFT having a large off current is stochastically generated.

In the case of the LDD structure TFT, the off current value is reduced mainly by the high electric field relaxation in the region extending from the channel region to the drain region by the low concentration impurity region. The leak current mechanism in the low-concentration impurity region, that is, the leak current is composed of the off-current A flowing across the crystal grain boundaries and the off-current B flowing along the crystal grain boundaries is large in the off current of the LDDTFT. It is thought to have an influence. Therefore, in consideration of what has already been described above, the width of the low-concentration impurity region is narrower than the crystal grain boundary and is approximately 1/2 or less of the crystal grain size, and the length of the low-concentration impurity region is the crystal grain size. It is considered that it is possible to reduce the off current and the variation by setting the length to be at least equal to or larger than the crystal grain size as compared with the above.

Further, although it is possible to reduce the off-current and the variation in the low-concentration impurity region alone, there is a possibility that a crystal grain boundary is formed so as to cross the channel region. The increase in off-current that occurs cannot be completely eliminated. Therefore, if the gate width (width of the current path) of both the low-concentration impurity region and the channel region is set to ½ or less of the crystal grain size, the risk of an increase in off-current that occurs stochastically can be completely eliminated. it is conceivable that.

Further, even if only the width of the channel region is smaller than the crystal grain boundary and is approximately 1/2 or less of the crystal grain size, the crystal grain boundary is not formed so as to cross the channel region. It is considered that stochastic increase in off-current can be reduced.

In the above description, the LDD is used as the TFT.
Although the structure is mentioned, the above LD is used as the TFT.
An offset structure may be used in which a portion of the D structure TFT that is a low concentration impurity region is a region where impurities are not introduced.

In the TFT having this offset structure, the resistance value in the region where impurities are not introduced becomes high, so that the TFT for high breakdown voltage is used.
It can be used as FT.

On the other hand, the dependence of the on-current on the channel width is shown in FIG.
As shown in, there is a linear relationship that is usually expected. Therefore, in consideration of the non-linear relationship between the off current and the channel width, the on / off ratio can be improved by setting the width of the channel region to 1/2 or less of the crystal position.

Examples of the present invention will be described below.

(Embodiment 1) FIG. 1 is a diagram for explaining a thin film transistor according to a first embodiment of the present invention, and FIG. 1 (a) is a diagram schematically showing a sectional structure of the thin film transistor. 1B is a plan view thereof, and FIG. 1C is a diagram showing a planar shape of a channel region and source / drain regions.

In the figure, 101 is a thin film transistor of the LDD structure of this embodiment, which is a semiconductor layer 2 made of polysilicon formed on an insulating substrate 1 and the semiconductor layer 2.
A gate electrode 4 formed on the gate insulating film 3
A channel region 6 formed in a portion of the semiconductor layer 2 facing the gate electrode 4, and high-concentration impurities formed in the semiconductor layer 2 on both sides of the channel region 6 as source and drain regions 8a and 8b. Regions and low-concentration impurity regions 9a formed in the semiconductor layer 2 so as to be located between the channel region 6 and the source / drain regions 8a, 8b.
9b.

Then, in this embodiment, the semiconductor layer 2 is formed.
In the region including the channel region 6 and the low-concentration impurity regions 9a and 9b, the width, that is, the dimension in the direction perpendicular to the direction in which the operating current flows is 1/2 of the crystal grain size of polycrystalline silicon.
It is as follows. The lengths of the channel region 6 and the low concentration impurity regions 9a and 9b are equal to or larger than the crystal grain size.

Here, the gate insulating film 3 and the interlayer insulating film 10 are successively formed on the semiconductor layer 2 and the substrate 1, and the source region 8a and the drain are penetrated through these insulating films. Contact holes 11a and 11b reaching the region 8b are formed. Electrodes 12a and 12b are formed in the contact holes 11a and 11b, respectively, and the gate electrode 4 is arranged on the gate insulating film 3 immediately above the channel region 6.

Next, the manufacturing method will be described. 6 and 7 are schematic cross-sectional views for explaining the method of manufacturing the thin film transistor of this embodiment in the order of steps.

First, the semiconductor layer 2 made of polysilicon is formed on the insulating substrate 1 (FIG. 6A). The insulating substrate 1 is, for example, an insulating substrate such as quartz, or SiO.
An Si substrate covered with an insulating film such as ₂ , Si ₃ N ₄ is used.
In addition, the semiconductor layer 2 is made of, for example, Si ₂
Using a mixture of H ₆ (disilane) and N ₂ or He, a reduced pressure C under the conditions of 450 to 475 ° C. and 25 to 50 Pa.
The amorphous silicon having a thickness of 1000 to 1200 angstrom is deposited by the VD method, and then heat treated to be polycrystallized. This heat treatment is performed by annealing for 12 to 24 hours in a heat treatment furnace in a N ₂ atmosphere at 600 ° C. Large-grain polycrystalline silicon having a grain size of 2 to 3 μm can be obtained by the above method.

Then, the width of the region including the channel region and the low-concentration impurity region in the polycrystallized semiconductor layer 2 is 1 using the ordinary photolithography technique.
/ 2 or less, that is, 1 μm or less is patterned in an island shape (FIG. 6B). The crystal grain size of polycrystalline silicon can be controlled by the following method. For example, in a method of performing silicon ion implantation after depositing amorphous silicon and then performing annealing, the crystal grain size can be reduced to 0.
It can be controlled to 16-2.5 μm (JAPAN DISP
LAY'92 455-458). Further, when SiH ₄ is used as the source gas of polycrystalline silicon, a crystal grain size of about submicron can be obtained (SID 90 DIGEST 311-314).

In addition to the above-described low pressure CVD method, plasma CVD or sputtering method may be used for forming amorphous silicon. A laser annealing method may be used to polycrystallize the amorphous silicon.

Next, CV is formed on the entire surface of the substrate 1 and the semiconductor layer 2.
The gate insulating film 3 is formed to a thickness of about 800 Å by the D method (FIG. 6C).

Next, on the gate oxide film 3 on the semiconductor layer 2, polysilicon doped with phosphorus is added to about 4000.
The gate electrode 4 is formed to a thickness of angstrom, and then the polysilicon layer is patterned to form the gate electrode 4 on the semiconductor layer 2 immediately above the region to be a channel. Then, P ⁺ is formed on the semiconductor layer 2 using the gate electrode 4 as a mask.
The low concentration impurity region 5 is formed by implanting ions. As a result, the portion of the semiconductor layer 2 immediately below the gate electrode 4 becomes the channel region 6. The dose of ion implantation at this time is 5 × 10 ¹³ cm ^-2 or less (5 × 10 ¹³ cm ^−2).
18 cm ^-3 or less) (Fig. 6 (d)). In the case of the TFT having the offset structure, this ion implantation becomes unnecessary.

Next, a resist film 7 is formed so as to cover the gate electrode 4 and a portion in the vicinity thereof, and then P ⁺ ions are implanted into the entire surface using the resist film 7 as a mask to form the source region 8a and the drain region 8b. Form. At this time, low-concentration impurity regions 9a and 9b are formed in the portion of the semiconductor layer 2 below the resist film 7 except the channel region 6. The dose of ion implantation at this time is 3 × 10 ¹⁵ cm
^-2 (4 × 10 ²⁰ cm ^-3 ) (Fig. 7 (a)).

Next, after removing the resist film 7, an inter-layer insulating film 10 is formed on the entire surface of the substrate, and then at 950 ° C. for 3 hours.
Impurities are activated by performing heat treatment for 0 minutes (FIG. 7B).

After that, the source region 8a and the drain region 8 are formed.
By selectively removing the interlayer insulating film 10 and the gate insulating film 3 so as to reach b, the contact holes 11a,
11b are formed, and the contact holes 11a and 11b are formed.
Part of the electrode 12 is filled with a conductive material such as aluminum.
Then, a and 12b are formed to complete the thin film transistor 100 (FIG. 7C).

As described above, in this embodiment, the width of the region including the low-concentration impurity regions 9a and 9b and the channel region 6 of the semiconductor layer 2 is set to 1/2 or less of the crystal grain size, that is, 1 μm or less. The off-current component B in the region and the low-concentration impurity region, that is, the off-current flowing along the crystal grain boundary can be completely removed. As a result, the off-current value can be reduced, and the stochastic increase in the off-current can be completely eliminated, and the on / off current ratio can be improved and its variation can be suppressed.

As a result, for example, when the TFT is incorporated in a liquid crystal display device, the pixel electrodes can be charged with electric charges in a short time, and the charged electric charges can be sufficiently retained for one frame. Each pixel TFT
It is possible to obtain a liquid crystal display device having good display quality and display quality without display unevenness and point defect picture elements by suppressing the variation in the electrical characteristics of the display device.

(Embodiment 2) FIG. 8 is a view for explaining a thin film transistor according to a second embodiment of the present invention, and FIG. 8 (a) is a plan view showing the shape of a semiconductor layer constituting the thin film transistor, FIG. 8B is a plan view showing the completed thin film transistor.

In the figure, 102 is a thin film transistor of the LDD structure of the present embodiment, which is formed by using a normal photolithography technique and has a width of a region including low-concentration impurity regions 9a and 9b of a polycrystallized semiconductor layer. Is smaller than the crystal grain boundary, that is, 1 μm or less, and the channel region 6
As for, it doesn't narrow its width. That is, it differs from the thin film transistor of the first embodiment only in that the width of the channel region 6 is not narrowed.

In the second embodiment having such a structure, the width of the region including the low concentration impurity regions 9a and 9b of the semiconductor layer 2 is set to be smaller than the crystal grain boundary (1 μm) or less. The off-current flowing along the crystal grain boundaries in the region can be completely removed, and the reduction and variation in the off-current value can be dramatically improved. Further, since the width of the channel region is not narrowed, the on-state current is not limited by the resistance value of the low-concentration impurity region, that is, a so-called sub-threshold region in which the on-state current rises sharply and the switching operation can be accelerated. There are advantages.

(Embodiment 3) FIG. 9 is a view for explaining a thin film transistor according to a third embodiment of the present invention, and FIG. 9 (a) is a plan view showing the shape of a semiconductor layer forming the thin film transistor, FIG. 9B is a plan view showing the completed thin film transistor.

In the figure, 103 is a thin film transistor of the LDD structure of this embodiment, which is formed by using an ordinary photolithography technique to change the width of the region including the channel region 6 of the polycrystallized semiconductor layer to a grain boundary. Narrower than, that is,
1 μm or less, and the low concentration impurity regions 9a and 9b
As for, it doesn't narrow its width. That is, it differs from the thin film transistor of the first embodiment only in that the width of the low concentration impurity region is not narrowed.

In the present embodiment having such a structure, the width of the region including the channel region 6 of the semiconductor layer 2 is narrower than the crystal grain boundary, that is, 1 μm or less, so that the inside of the channel region is changed from the source region to the drain region. Since a crystal grain boundary is not formed in a connected state, a rapid increase in off current can be suppressed. In addition, the low-concentration impurity regions 9a and 9b
Is not narrowed, the resistance value of the low-concentration impurity region is low, a large ON current can be obtained, and the ON / OFF current ratio can be further improved.

(Embodiment 4) FIG. 10 is a view for explaining a thin film transistor according to a fourth embodiment of the present invention.
10A is a diagram schematically showing the cross-sectional structure of the thin film transistor, FIG. 10B is a plan view thereof, and FIG. 10C is a diagram showing the planar shapes of the channel region and the source / drain regions.

In the figure, reference numeral 104 denotes the thin film transistor of this embodiment, which is formed on the insulating substrate 1 by a semiconductor layer 2 made of polysilicon and formed on the semiconductor layer 2 with a gate insulating film 3 interposed therebetween. Gate electrode 4 and the semiconductor layer 2
A channel region 6 formed in a portion facing the gate electrode 4 and a high-concentration impurity region formed in the semiconductor layer 2 on both sides of the channel region 6 as source / drain regions 8a and 8b. .

Then, in this embodiment, the semiconductor layer 2 is formed.
In the region including the channel region 6, the width, that is, the dimension in the direction perpendicular to the direction in which the operating current flows is 1 of the crystal grain size.
/ 2 or less. The length of the narrowed portion of the semiconductor layer 2 is equal to or larger than the crystal grain size.

The thin film transistor 104 of this embodiment is
The thin-film transistor of the first embodiment is different from the thin-film transistor of the first embodiment only in that it does not have a low-concentration impurity region, and the thin-film transistor of the present embodiment having such a configuration also has the same off-state current as the first embodiment. And the variation thereof can be suppressed.

(Fifth Embodiment) FIG. 11 is a diagram for explaining a thin film transistor according to a fifth embodiment of the present invention.
11A is a diagram schematically showing a cross-sectional structure of the thin film transistor, FIG. 11B is a plan view thereof, and FIG. 11C is a diagram showing a planar shape of a channel region and source / drain regions.

In the figure, reference numeral 105 denotes a thin film transistor having the LDD structure of this embodiment, which is a semiconductor layer 2 made of polysilicon and formed on the insulating substrate 1.
A gate electrode 4 formed on the gate insulating film 3
A plurality of channel regions 6 formed in a portion of the semiconductor layer 2 facing the gate electrode 4, and source and drain regions 8a, 8 on both sides of each channel region 6 in the semiconductor layer 2.
a high-concentration impurity region formed as b and the semiconductor layer 2
Inside each of the channel regions 6 and the source / drain regions 8
and a plurality of low-concentration impurity regions 9a and 9b formed so as to be located between a and 8b.

The thin film transistor 105 of this embodiment has a plurality of current paths connecting the source and drain regions 8a and 8b, and each current path includes the channel region 6 and the low-concentration impurity regions 9a and 9b on both sides thereof. And the width thereof, that is, the dimension in the direction perpendicular to the direction in which the operating current flows is half or less of the crystal grain size. In this embodiment, since there are a plurality of current paths between the source and drain regions, the source and drain regions are wider than those in the first embodiment, and the source and drain regions 8
Two contact holes are formed on each of a and 8b. The other structure is the same as that of the thin film transistor according to the first embodiment.

In this embodiment having such a configuration, the first
In addition to the effect of the embodiment described above, since a plurality of current paths including a channel region and a low-concentration impurity region are provided in parallel between the source and drain regions, the on-current caused by narrowing the width of each current path It is possible to avoid the reduction of

Although the TFT having the LDD structure is mentioned as the TFT in the second, third and fifth embodiments,
The TFT may have an offset structure in which the low concentration impurity region of the LDD structure TFT is used as a region into which impurities are not introduced.

In the TFT having this offset structure, the resistance value in the region where impurities are not introduced becomes high, so that T for high breakdown voltage is used.
It can be used as FT.

[0077]

As described above, according to the present invention (Claim 1), the channel region of the semiconductor layer forming the thin film transistor is formed along the grain boundary of the polycrystalline silicon forming the semiconductor layer. Since there is no current path from one of the high-concentration impurity regions on both sides of the region to the other, the off-current does not flow along the crystal grain boundaries in the channel region, which reduces the off-current value and increases the probability. It is possible to improve the on / off current ratio and suppress variations in the on / off current ratio by eliminating the increase in the off current.

According to the present invention (claim 2), the dimension of the channel region of the semiconductor layer forming the thin film transistor in the direction perpendicular to the direction in which the operating current flows is the average of the polycrystalline silicon forming the semiconductor layer. Since it has a structure narrower than 1/2 of the crystal grain size of, the crystal grain boundary is not formed in the channel region in a state where it is connected from the source region to the drain region. There is an effect that the current ratio can be improved and its variation can be suppressed.

According to the present invention (claim 3), both the channel region and the low-concentration impurity region of the semiconductor layer forming the thin film transistor having the LDD structure, or either one of them, is a polycrystalline layer forming the semiconductor layer. Since there is no current path from one end of the both high-concentration impurity regions to the other end along the crystal grain boundary of silicon, the structure is formed along the crystal grain boundary in the channel region or the low-concentration impurity region. The off-current flowing therethrough can be completely removed, whereby the on / off current ratio can be improved and the variation in the on / off current ratio can be suppressed.

According to the present invention (claim 4), both the channel region and the low-concentration impurity region of the semiconductor layer forming the thin film transistor having the LDD structure, or either one of them is perpendicular to the direction in which the operating current flows. Since the size in the vertical direction is smaller than 1/2 of the average crystal grain size of the polycrystalline silicon forming the semiconductor layer, the on / off current ratio is improved as described above, and the on / off current is further improved. This has the effect of suppressing variations in current ratio.

For example, by making the width of the region including the low-concentration impurity region and the channel region of the semiconductor layer narrower than the crystal grain size, the off-current flowing along the crystal grain boundaries in these regions is completely removed. Therefore, it is possible to improve the on / off current ratio and suppress variations.

Further, by making the width of the region including the low concentration impurity region of the semiconductor layer narrower than the crystal grain boundary, the off current flowing along the crystal grain boundary in the low concentration impurity region is eliminated, so that the off current is reduced. Since the reduction and dispersion of the value can be dramatically improved and the width of the channel region is not narrowed, the on-current is not limited by the resistance value of the low-concentration impurity region, that is, the so-called sub-threshold region. There are advantages that the rising can be made sharp and the switching operation can be speeded up.

Further, by making the width of the region including the channel region of the semiconductor layer narrower than the crystal grain boundary, the crystal grain boundary is not formed so as to cross the channel region longitudinally, and as a result, stochastically. It is possible to reduce the sudden increase in off-current. In addition, since the width of the low concentration impurity region is not narrowed, the resistance value of the low concentration impurity region is low, a large ON current can be obtained, and the ON / OFF current ratio can be further improved. is there.

According to the present invention (claims 5 and 6), in the thin film transistor, since the plurality of channel regions or low concentration impurity regions are provided in parallel, each channel region or low concentration impurity region is provided. It is possible to avoid reduction of the on-current due to the narrowed width of the region.

As a result, when the TFT of the present invention is incorporated into a liquid crystal display device, the pixel electrodes can be charged with electric charges in a short time, and the charged electric charges can be sufficiently retained for one frame. In addition, it is possible to realize a liquid crystal display device having good display quality and display quality free from display unevenness and point defect picture elements by suppressing variations in the electrical characteristics of the picture element TFTs.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a thin film transistor according to a first embodiment of the present invention, FIG. 1 (a) is a diagram schematically showing a cross-sectional structure of the thin film transistor, and FIG. 1 (b) is a plan view thereof. FIG. 1C is a diagram showing a planar shape of the channel region and the source / drain regions.

FIG. 2 is a diagram showing a channel width dependence of off-state current.

FIG. 3 is a diagram for explaining an off-current generation mechanism.

FIG. 4 is a diagram showing a relationship between a channel width and a leak current path.

FIG. 5 is a diagram showing the channel width dependence of on-current.

FIG. 6 is a schematic cross-sectional view for explaining the method of manufacturing the thin film transistor of the first embodiment in the order of steps.

FIG. 7 is a schematic cross-sectional view for explaining the method of manufacturing the thin film transistor of the first embodiment in the order of steps.

FIG. 8 is a diagram for explaining a thin film transistor according to a second embodiment of the present invention, FIG. 8 (a) is a diagram showing a planar shape of a channel region and a source / drain region of the thin film transistor, and FIG. 4] is a plan view schematically showing the structure of the thin film transistor.

FIG. 9 is a diagram for explaining a thin film transistor according to a third embodiment of the present invention, FIG. 9 (a) is a diagram showing a planar shape of a channel region and a source / drain region of the thin film transistor, and FIG. 4] is a plan view schematically showing the structure of the thin film transistor.

FIG. 10 is a diagram for explaining a thin film transistor according to a fourth embodiment of the present invention, FIG. 10 (a) is a diagram schematically showing a cross-sectional structure of the thin film transistor, and FIG. 10 (b).
Is a plan view thereof, and FIG. 10C is a diagram showing a planar shape of a channel region and source / drain regions.

FIG. 11 is a diagram for explaining a thin film transistor according to a fifth embodiment of the present invention, FIG. 11 (a) is a diagram schematically showing a sectional structure of the thin film transistor, and FIG. 11 (b).
FIG. 11C is a plan view thereof, and FIG. 11C is a diagram showing a planar shape of the channel region and the source / drain regions.

[Explanation of symbols]

1 Insulating Substrate 2 Semiconductor Layer 3 Gate Insulating Film 4 Gate Electrode 6 Channel Region 8a Source Region 8b Drain Region 9a, 9b Low Concentration Impurity Region 10 Interlayer Insulating Film 11a, 11b Contact Ball 12a, 12b Electrode 101, 102, 103, 104 , 105 thin film transistor

Claims (6)

[Claims] 1. A semiconductor layer formed on an insulating substrate, a gate electrode formed on the insulating substrate so as to face the semiconductor layer via an insulating film, and a gate of the semiconductor layer. The semiconductor layer includes a channel region formed in a portion facing the electrode, and high-concentration impurity regions formed in the semiconductor layer so as to be located on both sides of the channel region. A thin film transistor having a structure in which there is no current path from one of the high-concentration impurity regions to the other along the crystal grain boundary of the polycrystalline silicon forming the layer. 2. A semiconductor layer formed on an insulating substrate, a gate electrode formed on the insulating substrate so as to face the semiconductor layer via an insulating film, and a gate of the semiconductor layer. A channel region of the semiconductor layer, which includes a channel region formed in a portion facing the electrode and a high-concentration impurity region formed in the semiconductor layer so as to be adjacent to the channel region. Is a thin film transistor in which the dimension in the direction perpendicular to the direction in which the operating current flows is smaller than 1/2 of the average crystal grain size of the polycrystalline silicon forming the semiconductor layer. 3. A semiconductor layer formed on an insulating substrate, a gate electrode formed on the insulating substrate so as to face the semiconductor layer with an insulating film interposed therebetween, and a gate of the semiconductor layer. A channel region formed in a portion facing the electrode, a high-concentration impurity region formed in the semiconductor layer so as to be located on both sides of the channel region, and the channel region and the high-concentration regions in the semiconductor layer. A low-concentration impurity region formed so as to be located between at least one of the impurity regions, and the semiconductor layer has either of the channel region and the low-concentration impurity region, or the channel region and the low-concentration impurity region. One of them has a structure in which there is no current path from one end of each of the high-concentration impurity regions to the other end along the crystal grain boundary of the polycrystalline silicon forming the semiconductor layer. Transistor. 4. A semiconductor layer formed on an insulating substrate, a gate electrode formed on the insulating substrate so as to face the semiconductor layer with an insulating film interposed therebetween, and a gate of the semiconductor layer. A channel region formed in a portion facing the electrode, a high-concentration impurity region formed on both sides of the channel region in the semiconductor layer, and the channel region and the high-concentration regions in the semiconductor layer. A low-concentration impurity region formed so as to be located between at least one of the impurity regions, and both the channel region and the low-concentration impurity region in the semiconductor layer, or the channel region and the low-concentration impurity region. One of them is a thin film transistor in which the dimension in the direction perpendicular to the direction in which the operating current flows is smaller than 1/2 of the average crystal grain size of the polycrystalline silicon forming the semiconductor layer. 5. The thin film transistor according to claim 1, wherein a plurality of the channel regions are provided in parallel. 6. The thin film transistor according to claim 3, wherein a plurality of both of the channel region and the low-concentration impurity region or one of the channel region and the low-concentration impurity region are provided in parallel. .