JP3788022B2 - Thin film transistor and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a thin film transistor (hereinafter referred to as TFT) used for liquid crystal driving, EL element driving, sensor driving, and the like, and a method for manufacturing the same. More specifically, the present invention relates to a vertical TFT.
[0002]
[Prior art]
In the active matrix substrate of the liquid crystal display device, as shown in FIG. 4A, a pixel region defined by data lines 90 and scanning lines 91 made of a conductive film such as aluminum or tantalum is formed on a transparent substrate. There is a liquid crystal capacitor 94 (liquid crystal cell) to which an image signal is input via the pixel switching TFT 30. For the data line 90, a data side drive circuit 82 including a shift register 84, a level shifter 85, a video line 87, and an analog switch 86 is configured. A scanning side drive circuit 83 including a shift register 88 and a level shifter 89 is configured for the scanning line 91. Note that a storage capacitor 93 is formed in the pixel region between the scanning line 91 in the previous stage, and the storage capacitor 93 has a function of improving the charge storage characteristics of the liquid crystal capacitor 94.
[0003]
In the data side and scanning side drive circuits, as shown in FIG. 4B, an N-type TFT 10 and a P-type TFT 20 constitute a complementary TFT circuit. Such a complementary TFT circuit constitutes a shift register or the like in one or more stages.
[0004]
As shown in FIGS. 5A and 5B, the driving circuit TFTs 10 and 20 are similar to the pixel switching TFT 30 as shown in FIGS. 5A and 5B, and the first source / drain region 2A, the channel formation region 3A, and the first The gate insulating film 6A is formed on the surface of the island-like silicon film 5A constituting the source / drain region 4A, and the gate electrode 7A formed on the surface of the gate insulating film 6A passes through the gate insulating film 6A. It faces the channel forming region 3A.
[0005]
In manufacturing the TFT 1A having such a structure, a polycrystalline silicon film 5A (semiconductor film) formed on the substrate 8A is used. That is, in order to increase the operating speed of the driving circuit, it is necessary that the operating speed of the TFT is high. Therefore, a polycrystalline silicon film having high mobility is formed using a high temperature process, and the TFT is formed from this polycrystalline silicon film. Form. Therefore, conventionally, it is necessary to use an expensive quartz glass that can withstand a high temperature process as the substrate 8A, and there is a problem that an inexpensive glass substrate having a low strain point cannot be used.
[0006]
Therefore, after forming an amorphous silicon film on the substrate so that a polycrystalline silicon film with high mobility can be formed on an inexpensive glass substrate with a low strain point, laser annealing or solid phase growth is applied to this amorphous silicon film. A low temperature process in which a crystal grain is grown by crystallizing an amorphous silicon film by melting or solidifying the amorphous silicon film by a crystallization treatment such as a method has been studied.
[0007]
[Problems to be solved by the invention]
However, as described in, for example, “Jpn.J.Appl.Phys., Vol.27, no.10 (1988) L1809”, when crystal grains of a silicon film are grown by such crystallization treatment, The silicon film becomes a polycrystalline semiconductor film having a columnar structure in which the column axis is oriented in the film deposition direction at the time of film formation, that is, in the direction perpendicular to the substrate 8A. On the other hand, when the amorphous silicon film is not crystallized as described above but deposited as a polycrystalline silicon film from the beginning, for example, “J. Appl. Phys. Vol. 61, no. 11, 1 June (1987 As described in pp 5031-5037 ", the silicon film becomes a polycrystalline semiconductor film having a columnar structure in which the column axis is oriented in the film deposition direction during film formation, that is, in the direction perpendicular to the substrate 8A. Therefore, in the TFT having the conventional structure as shown in FIG. 7A, the channel crosses the grain boundary (indicated by the vertical line B in the channel formation region 3A) in the channel length direction (direction indicated by the arrow CH). It will be. As a result, there is a problem that even if the crystallinity of the silicon film is increased, the on-current of the TFT 1A is not sufficiently improved.
As a conventional example, for example, a technique described in Japanese Patent Application Laid-Open No. 07-297406 can be cited.
[0008]
Therefore, it is conceivable to shorten the channel length to increase the on-current. However, if the channel length is shortened, there is a problem that the withstand voltage between the source and the drain is lowered accordingly.
[0009]
In view of the above problems, an object of the present invention is to provide a TFT capable of improving the on-current and improving the source-drain breakdown voltage by forming a channel in consideration of the crystal structure of the polycrystalline semiconductor film. And a method of manufacturing the same.
[0010]
[Means for Solving the Problems]
In order to solve the above problems, a thin film transistor of the present invention includes a lower-layer side semiconductor film including a first region serving as one of source / drain regions, a polycrystalline semiconductor film including a channel formation region, and the other of the source / drain regions. A gate insulating film formed to cover the lower layer side semiconductor film, the polycrystalline semiconductor film, and the upper layer side semiconductor film, an upper layer side semiconductor film including the second region is formed in this order on the substrate; A thin film transistor including a gate electrode formed on the gate insulating film, wherein the polycrystalline semiconductor film and the upper semiconductor film have side end surfaces in a source / drain direction, respectively, One side end face of the semiconductor film and one side end face of the upper layer side semiconductor film are disposed on the lower layer side semiconductor film, and the first region and the multiple connection of the lower layer side semiconductor film are arranged. An LDD region into which a low-concentration impurity is introduced or an offset region that does not contain an impurity is formed in a third region between the one side end surface of the semiconductor film, and a lower-layer side semiconductor that constitutes the first region LDD into which low-concentration impurities are introduced into a side end portion of the film and a fourth region between the second region of the upper semiconductor film and the one side end surface of the upper semiconductor film An offset region that does not contain a region or an impurity is formed, and the gate electrode faces the side end surface of the polycrystalline semiconductor film and the side end surface of the upper semiconductor film through the gate insulating film, and the gate electrode The electrode is opposite to the third region and the fourth region with the gate insulating film interposed therebetween.
[0011]
In the present invention, the polycrystalline semiconductor film has a columnar structure in which a column axis is directed upward in the substrate surface. That is, when a channel formation region is formed by a polycrystalline semiconductor film obtained by melting and solidifying an amorphous semiconductor film by crystallizing treatment such as laser annealing, electron beam annealing, lamp annealing, or solid phase growth method, a channel is formed. In the formation region, a polycrystalline semiconductor film having a columnar structure in which the column axis is oriented in the film deposition direction when the semiconductor film is formed, that is, the out-of-plane direction of the substrate. Corresponding to such a crystal structure, in the present invention, a vertical TFT is configured by making the gate electrode face the side end face parallel to the column axis of the polycrystalline semiconductor film. Therefore, the direction parallel to the column axis is the channel length direction. Therefore, in the channel length direction, the channel does not cross the grain boundary, so the carrier mobility is high. Therefore, an on-current can be improved in a TFT manufactured by a low temperature process. However, in the vertical TFT configured as described above, the thickness of the polycrystalline semiconductor film constituting the channel formation region becomes the channel length. Therefore, in order to secure the source-drain breakdown voltage in the vertical TFT, it is necessary to increase the film thickness of the polycrystalline semiconductor film constituting this channel formation region, and therefore a long time is required for the film forming process. However, according to the present invention, in the vertical TFT, the side edge of the gate electrode between the side edge near the side edge of the polycrystalline semiconductor film in the first region and the side edge of the polycrystalline semiconductor film. A portion facing the portion, and a portion facing the side end portion of the gate electrode between the side end portion of the second region near the side end surface of the polycrystalline semiconductor film and the side end surface of the polycrystalline semiconductor film At least one of them, an LDD region into which a low concentration impurity is introduced or a semiconductor region into which no impurity is introduced is formed, and the vertical TFT has an LDD structure or an offset gate structure. Therefore, even if the channel length in the vertical TFT is short, that is, even if the thickness of the polycrystalline semiconductor film constituting the channel formation region is thin, a sufficient source / drain voltage can be ensured. The time required for film formation can be shortened.
The thin film transistor of the present invention is characterized in that the formation position of one side end face of the polycrystalline semiconductor film coincides with the formation position of one side end face of the upper semiconductor film. The polycrystalline semiconductor film and the upper semiconductor film have the same patterning shape.
[0012]
In manufacturing the vertical thin film transistor having such a structure, a polycrystalline structure having a columnar structure in which the amorphous semiconductor film for forming the channel formation region is subjected to crystallization treatment and the column axis is directed upward in the substrate surface. After forming the semiconductor film, the polycrystalline semiconductor film is patterned to expose the side end faces substantially parallel to the column axis, and then the gate insulating film and the gate electrode may be formed sequentially.
[0013]
In the present invention, when the first region and the second region are composed of a lower layer side semiconductor film and an upper layer side semiconductor film respectively formed on the lower layer side and the upper layer side of the polycrystalline semiconductor film, In at least one of the upper-layer side semiconductor film and the lower-layer-side semiconductor film, the LDD region in which the low-concentration impurity is introduced or the semiconductor in which no impurity is introduced in a portion facing the side end portion of the gate electrode A region may be formed.
[0014]
In manufacturing the vertical thin film transistor having such a configuration, after forming the polycrystalline semiconductor film and the upper semiconductor film in this order, the polycrystalline semiconductor film and the upper semiconductor film are patterned together. By doing so, it is preferable to reduce the number of patterning steps.
[0015]
In the present invention, when the side end surface of the polycrystalline semiconductor film is located on a formation region of the lower-layer semiconductor film in which the first region is formed, the side end surface of the polycrystalline semiconductor film and the lower layer It is preferable that an insulating film that slightly cuts between these films is provided between the side semiconductor films. With this configuration, after forming the lower-layer side semiconductor film and the insulating film in this order, the polycrystalline semiconductor film for forming the channel formation region is formed on the entire surface of the substrate, and then the polycrystalline semiconductor film is formed. When patterning the semiconductor film, the insulating film serves as an etching stopper. Therefore, it is possible to prevent the lower semiconductor film from being over-etched.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described with reference to the drawings. Note that each embodiment will be described using the driving TFT of the liquid crystal display device described with reference to FIG. 4B as an example. The TFT according to the present invention includes a pixel switching TFT of the liquid crystal display device, Furthermore, it can be used in various fields such as EL element driving and sensor driving.
[0017]
[Embodiment 1]
1A and 1B are a cross-sectional view and a plan view of a TFT to which the present invention is applied, respectively.
[0018]
1A and 1B, a TFT 1 according to this embodiment is a TFT for a drive circuit formed by a low-temperature process on a substrate 8 made of a glass plate as a substrate of a liquid crystal panel. The TFT 1 includes a high concentration first source / drain region 2, a high concentration second source / drain region 4, a channel formation region 3 for forming a channel, and a gate insulating film 6 for the channel formation region 3. It is the same as the conventional TFT 1 in that it has the gate electrode 7 facing through the electrode.
[0019]
However, in this embodiment, the first source / drain region 2, the channel formation region 3, and the second source / drain region 4 are respectively lower semiconductor films such as doped silicon films formed on the surface of the substrate 8. 201, a polycrystalline semiconductor film 301 such as a polycrystalline silicon film laminated on the surface of the lower semiconductor film 201, and an upper semiconductor film 401 such as a doped silicon film laminated on the surface of the polycrystalline semiconductor film 301. Is formed.
[0020]
In the polycrystalline semiconductor film 301 constituting the channel formation region 3, the side end faces 302 and 402 are positioned on the lower-layer side semiconductor film 201, similarly to the upper-layer side semiconductor film 401. Here, an insulating film 9 for an etching stopper that slightly cuts between these films is formed between the side end face 302 of the polycrystalline semiconductor film 301 constituting the channel formation region 3 and the lower semiconductor film 201. Yes.
[0021]
In this embodiment, the polycrystalline semiconductor film 301 constituting the channel formation region 3 and the upper semiconductor film 401 including the second source / drain region 4 are collectively patterned as will be described later. Have the same patterning shape.
[0022]
A gate insulating film 6 made of a silicon oxide film or the like is formed on the surface of the upper layer side semiconductor 401 constituting the second source / drain region 4, and this gate insulating film 6 is a polycrystalline semiconductor constituting the channel forming region 3. The side end surface 302 of the film 301 is covered. In this embodiment, the gate electrode 7 formed on the surface of the gate insulating film 6 faces the side end face 302 of the polycrystalline semiconductor film 301 constituting the channel forming region 3 with the gate insulating film 6 interposed therebetween.
[0023]
An interlayer insulating film 11 made of a silicon oxide film or the like is formed on the surface side of the gate electrode 7, and the first source / drain region 2 and the second source / drain region 2 are formed through contact holes 111, 112 of the interlayer insulating film 11. The first source / drain electrode 12 and the second source / drain electrode 13 are electrically connected to the drain region 4.
[0024]
In the TFT 1 configured as described above, in this embodiment, first, in the lower-layer side semiconductor film 201 in which the first source / drain region 2 is formed, a low-concentration impurity is present in a portion facing the side end portion of the gate electrode 7. An LDD region 203 into which is introduced is formed. Further, the LDD region 403 into which the low concentration impurity is introduced is formed in the upper semiconductor film 401 in which the second source / drain region 4 is formed, in a portion facing the side end portion of the gate electrode 7. . Therefore, the TFT 1 has an LDD structure while being a vertical type.
[0025]
In manufacturing the vertical TFT 1 configured as described above, if a high temperature process is used, it is necessary to use an expensive quartz glass that can withstand the high temperature process as the substrate 8. In this embodiment, an inexpensive glass substrate is used. A low temperature process is employed so that it can be used. Accordingly, in the TFT 1 of the present embodiment, the channel forming region 3 is formed in the channel forming region 3 after forming an amorphous semiconductor film on the substrate 8 and then laser annealing, electron beam annealing, lamp annealing, solid phase growth method on the amorphous semiconductor film. The polycrystalline semiconductor film 301 is obtained by performing a crystallization treatment such as the above. This polycrystalline semiconductor film 301 is a column axis (indicated by an arrow A) in the film deposition direction at the time of film formation, that is, the out-of-plane direction of the substrate 8 in the process where the amorphous semiconductor film is melted and solidified to grow crystal grains. It has a columnar structure that faces. In this columnar structure, in order to show that the column axis A is perpendicular to the substrate 8, in FIG. 1A, a grain boundary is provided in the channel formation region 3 (polycrystalline semiconductor film 301) as a vertical line B. It is represented by
[0026]
In accordance with such a crystal structure, in this embodiment, the side end face 302 of the polycrystalline semiconductor film 301 constituting the channel formation region 3 is perpendicular to the substrate 8, and the gate electrode 7 is gate-insulated with respect to the side end face 302. It faces through the membrane 6. Therefore, when a gate potential is applied to the gate electrode 7, a channel is formed on the side end face 302 of the polycrystalline semiconductor film 301 constituting the channel formation region 3, and the channel length direction (indicated by an arrow CH) at this time Direction) is parallel to the column axis A of the polycrystalline semiconductor film 301. Therefore, since the channel does not cross the grain boundary B in the direction of the channel length CH, the carrier mobility is high. Therefore, the on-current can be improved in the TFT 1 manufactured by the low temperature process.
[0027]
Further, in this embodiment, the TFT 1 is of a vertical type and has an LDD structure, so that the ON current is ensured and the source-drain breakdown voltage is increased. That is, in the vertical TFT 1, since the film thickness of the polycrystalline semiconductor film 301 constituting the channel forming region 3 becomes the channel length as it is, in order to secure the source-drain breakdown voltage with this structure, this channel forming region is used. 3, it is necessary to increase the film thickness of the polycrystalline semiconductor film 301, so that a long time is required for the film forming process. In this embodiment, the lower semiconductor film in which the first source / drain region 2 is formed In the portion facing the side end portion of the gate electrode 7 in 201 and the portion facing the side end portion of the gate electrode 7 in the upper semiconductor film 401 in which the second source / drain region 4 is formed, a low concentration LDD region 203 and 403, and a high source-drain breakdown voltage is secured. Therefore, according to this embodiment, even if the channel length of the vertical TFT 1 is short, that is, even when the thickness of the polycrystalline semiconductor film 301 constituting the channel formation region 3 is thin, a sufficient source / drain voltage is ensured. Therefore, the time for forming the channel formation region 4 can be shortened.
[0028]
In addition, since the TFT 1 having an LDD structure has a small off-leakage current, it is suitable for pixel switching. Therefore, the vertical TFT 1 of this embodiment is suitable for both driving circuit and pixel switching.
[0029]
An example of a manufacturing method of the TFT 1 having such a configuration will be described with reference to FIGS. 2 and 3 are process cross-sectional views illustrating a manufacturing method of the TFT 1 of this embodiment.
[0030]
First, as shown in FIG. 2A, an impurity such as phosphorus or boron is added to the entire surface of the substrate 8 by about 10%. ¹⁵ cm ^-3 ~ About 10 ¹⁸ cm ^-3 After forming a semiconductor film such as a low-concentration doped silicon film containing a certain amount, it is patterned into an island shape to form an island-shaped lower semiconductor film 201. In addition to the case where the doped semiconductor film is formed as a polycrystalline semiconductor film, a crystallized amorphous semiconductor film may be used.
[0031]
Next, a resist mask RM1 that covers at least the region to be the LDD region 203 in the lower layer side semiconductor film 201 is formed. In this state, impurities are introduced into the lower layer side semiconductor film 201 to reduce the impurities to about 10 ¹⁸ cm ^-3 ~ About 10 ²⁰ cm ^-3 A high-concentration first source / drain region 2 containing a certain amount is formed. Note that the LDD region 203 is formed from a portion of the lower semiconductor film 201 where no impurity is introduced.
[0032]
Next, as shown in FIG. 2B, an insulating film such as a silicon oxide film or a silicon nitride film is formed on the entire surface of the substrate 8 by sputtering, CVD, vapor deposition, or the like, and then the insulating film is patterned. Then, the etching stopper insulating film 9 partially overlapping the first source / drain region 2 (lower semiconductor film 201) is left.
[0033]
Next, as shown in FIG. 2C, an amorphous semiconductor film 300 having a thickness of about 100 Å to several μm is formed. If an amorphous silicon film is used as the amorphous semiconductor film 300, there are methods such as a plasma CVD method, an LPCVD method, a vapor deposition method, and a sputtering method. If it is a plasma CVD method, it can form into a film at the temperature of 350 degrees C or less. In the case of the LPCVD method, the deposition temperature differs depending on the source gas, and disilane (Si ₂ H ₆ ) Gas, a temperature of about 450 ° C. or less, silane (SiH _Four ) If a gas is used, the film can be formed at a temperature of about 560 ° C. or less. Further, in the case of a vapor deposition method or a sputtering method, a film can be formed at a temperature of about 200 ° C. or less. Here, by adding phosphorus or boron at a low concentration as the amorphous semiconductor film 300, channel doping may be performed to adjust the threshold voltage of the TFT1.
[0034]
Next, the amorphous semiconductor film 300 is subjected to crystallization treatment such as laser annealing, electron beam annealing, lamp annealing, or solid phase growth method, so that the amorphous semiconductor film 300 is changed to a polycrystalline semiconductor film 300B. In the laser annealing method, for example, a line beam having an excimer laser beam length of 400 mm is used, and its output intensity is, for example, 200 mJ / cm. ² It is. The line beam is scanned so that a portion corresponding to 90% of the peak value of the laser intensity in the width direction overlaps each region. In this crystallization treatment, the amorphous semiconductor film 300 is melted and solidified to grow crystal grains, thereby forming a polycrystalline semiconductor film 300B. The polycrystalline semiconductor film 300 </ b> B has a columnar crystal structure (columnar structure) in which the column axis A is directed in a direction perpendicular to the substrate 8.
[0035]
Next, as shown in FIG. 2D, impurities such as phosphorus or boron are added to the entire surface of the substrate 8 by about 10%. ¹⁵ cm ^-3 ~ About 10 ¹⁸ cm ^-3 A low concentration semiconductor film 400 such as a doped silicon film is formed. As a result, the semiconductor film 400 is stacked on the polycrystalline semiconductor film 300B after the amorphous semiconductor film 300 is crystallized.
[0036]
Next, a resist mask RM2 is formed to cover a region of the semiconductor film 400 that covers the region to be the LDD region 403. In this state, an impurity is introduced into the semiconductor film 400 to remove the impurity by about 10%. ¹⁸ cm ^-3 ~ About 10 ²⁰ cm ^-3 A high concentration second source / drain region 4 is formed to a certain extent. The LDD region 403 is formed from a portion of the upper semiconductor film 401 where no impurity is introduced.
[0037]
Next, after removing the resist mask RM2, a new resist mask RM3 is formed as shown in FIG.
[0038]
Then, using the resist mask RM3, the semiconductor film 400 and the polycrystalline semiconductor film 300B are patterned at once, as shown in FIG. 2F, the polycrystalline semiconductor film 301 constituting the channel formation region 3, The upper-side semiconductor film 401 including the two source / drain regions 4 and the LDD region 403 is left. At this time, patterning is performed so that the side end face 302 of the polycrystalline semiconductor film 301 and the side end face 402 of the upper layer side semiconductor film 401 are positioned on the insulating film 9 for the etching stopper formed on the surface of the lower layer side semiconductor film 201. To do. The insulating film 9 for the etching stopper prevents the lower semiconductor film 201 from being over-etched when the upper semiconductor film 401 and the polycrystalline semiconductor film 301 are formed by patterning. When the polycrystalline semiconductor film 301 and the polycrystalline semiconductor film 301 are formed by patterning in this way, the end portion of the insulating film 9 for the etching stopper is between the side end face 302 of the polycrystalline semiconductor film 301 and the lower semiconductor film 201. Will be slightly interrupted.
[0039]
Next, as shown in FIG. 3A, a thickness of about 600 is formed on the entire surface of the substrate 8 by a plasma CVD method, a CVD method, a sputtering method or the like using TEOS (tetraethoxysilane) or oxygen gas as a source gas. A gate insulating film 6 made of a silicon oxide film of ˜1500 Å is formed.
[0040]
Next, a conductive film such as a doped semiconductor film, a metal film (tantalum, chromium, aluminum, or the like), a silicide film (tungsten silicide, molybdenum silicide, or the like) is formed over the entire surface of the substrate 8, and then illustrated in FIG. By patterning in this manner, a gate electrode 7 is formed on the side end face 302 of the polycrystalline semiconductor film 301 so as to face the gate insulating film 6.
[0041]
Next, after an interlayer insulating film 11 is formed on the entire surface of the substrate 8, contacts are made at positions corresponding to the first source / drain region 2 and the second source / drain region 3 as shown in FIG. Holes 111 and 112 are formed.
[0042]
A conductive film such as a doped semiconductor film, a metal film (tantalum, chromium, aluminum, etc.), a silicide film (tungsten silicide, molybdenum silicide, etc.) is formed on the entire surface of the substrate 8, and then patterned to form a first source / A drain electrode 12 and a second source / drain electrode 13 are formed.
[0043]
According to such a manufacturing method of the TFT 1, since the TFT 1 can be manufactured by a low temperature process, an inexpensive glass substrate can be used as the substrate 8. Further, when the polycrystalline semiconductor film 301 constituting the channel formation region 3 is patterned into an island shape, since the insulating film 9 for an etching stopper is formed in advance under the position corresponding to the side end face 302, the first The lower semiconductor film 201 constituting the source / drain region 2 is not over-etched. Further, since the polycrystalline semiconductor film 301 constituting the channel forming region 3 and the upper layer side semiconductor film 401 constituting the second source / drain region 4 are collectively formed by patterning, they are patterned in separate steps. There is an advantage that the patterning process can be reduced by one process compared to the method.
[0044]
[Other Embodiments]
In the above embodiment, since the doped semiconductor film is formed in the process described with reference to FIGS. 2A and 2D, the TFT 1 having the LDD structure is manufactured. However, FIGS. In the process described with reference to (D), when a semiconductor film containing no impurities is formed, a portion of the upper layer side semiconductor film 201 and the lower layer side semiconductor film 401 that faces the side end of the gate electrode 7 is not in the LDD region. Thus, the semiconductor region does not contain impurities. Therefore, an offset gate TFT can be manufactured. With this offset gate structure TFT, as with the LDD structure TFT, even if the channel length is short, that is, the polycrystalline semiconductor film 301 constituting the channel formation region 3 is thin, sufficient source / drain Since the breakdown voltage can be ensured, the time required for forming the channel formation region 3 can be shortened. An offset gate TFT is also suitable for pixel switching because it has a small off-leakage current.
[0045]
The LDD region (or the semiconductor region into which the impurity constituting the offset gate structure is not introduced) formed in the TFT may be formed in both the first and second source / drain regions 2 and 4. Either one may be formed only on the side that becomes the drain region, for example.
[0046]
Further, in the above embodiment, the LDD region (or the semiconductor region into which the impurity constituting the offset gate structure is not introduced) is used as the lower side semiconductor film 201 and the upper layer side including the first and second source / drain regions 2 and 4. An LDD region (or a semiconductor region into which an offset gate structure is not introduced) is formed by a semiconductor film formed in the semiconductor film 401 but formed separately from these semiconductor films and without introduction of impurities. May be formed.
[0047]
Furthermore, in the above embodiment, the silicon film is used as the semiconductor film. However, the present invention may be applied to a TFT using a semiconductor film such as germanium or silicon-germanium.
[0048]
【The invention's effect】
As described above, in the vertical TFT according to the present invention, the gate electrode is opposed to the side end face parallel to the column axis of the polycrystalline semiconductor film obtained from the amorphous semiconductor film by the crystallization process. The direction parallel to the column axis is the channel length direction. Therefore, in the channel length direction, the channel does not cross the grain boundary, so the carrier mobility is high. Therefore, an on-current can be improved in a TFT manufactured by a low temperature process. Further, in the present invention, although it is a vertical TFT, it has an LDD structure or an offset gate structure, so that the source-drain breakdown voltage is high even if the channel length is short. Therefore, since the polycrystalline semiconductor film constituting the channel formation region can be thin, there is an advantage that the time required for film formation can be shortened.
[Brief description of the drawings]
FIGS. 1A and 1B are a cross-sectional view and a plan view of a TFT to which the present invention is applied, respectively.
FIG. 2 is a process cross-sectional view illustrating a manufacturing method of the TFT shown in FIG.
3 is a process cross-sectional view illustrating each process performed subsequent to the process illustrated in FIG. 2 in the TFT manufacturing method illustrated in FIG. 1;
FIGS. 4A and 4B are a block diagram of an active matrix substrate of a liquid crystal display device and a circuit diagram showing a part of a drive circuit configured therefor, respectively.
FIGS. 5A and 5B are a cross-sectional view and a plan view, respectively, of a conventional TFT.
[Explanation of symbols]
1 TFT
2 First source / drain region
3 channel formation region
4 Second source / drain region
6 Gate insulation film
7 Gate electrode
8 Board
9 Insulating film for etching stopper
11 Interlayer insulation film
12 First source / drain electrode
13 Second source / drain electrode
201 Lower side semiconductor film
203, 403 LDD region
301 Polycrystalline semiconductor film
302 Side end surface of polycrystalline semiconductor film
401 Upper layer side semiconductor film
A Column axis of polycrystalline semiconductor film
B Grain Boundary
CH channel length direction

Claims (8)

A lower semiconductor film having a first region serving as one of source / drain regions, a polycrystalline semiconductor film including a channel forming region, and an upper semiconductor film including a second region serving as the other of the source / drain regions are formed on a substrate. And a gate insulating film formed to cover the lower semiconductor film, the polycrystalline semiconductor film, and the upper semiconductor film, and a gate electrode formed on the gate insulating film. Thin film transistor,
The polycrystalline semiconductor film and the upper semiconductor film have side end surfaces in the source / drain directions,
One side end face of the polycrystalline semiconductor film and one side end face of the upper layer side semiconductor film are disposed on the lower layer side semiconductor film,
The third region between the first region and the one side end surface of the polycrystalline semiconductor film of the lower-layer side semiconductor film is an LDD region into which a low-concentration impurity is introduced or an offset that does not contain an impurity. A region is formed,
A side end portion of a lower-layer side semiconductor film constituting the first region;
The fourth region between the second region and the one side end surface of the upper layer side semiconductor film of the upper layer side semiconductor film is an LDD region into which a low concentration impurity is introduced or an offset not containing an impurity. A region is formed,
The gate electrode is opposed to the side end face of the polycrystalline semiconductor film and the side end face of the upper semiconductor film through the gate insulating film,
The thin film transistor, wherein the gate electrode is opposed to the third region and the fourth region with the gate insulating film interposed therebetween.   2. The thin film transistor according to claim 1, wherein the polycrystalline semiconductor film has a columnar structure in which a column axis is directed upward in the substrate surface.   3. The thin film transistor according to claim 1, wherein a formation position of one side end face of the polycrystalline semiconductor film coincides with a formation position of one side end face of the upper semiconductor film.   4. The thin film transistor according to claim 1, wherein the polycrystalline semiconductor film and the upper semiconductor film have the same patterning shape. 5.   5. The insulating film is provided between the side end face of the polycrystalline semiconductor film and the lower semiconductor film so as to slightly cut between these films. A thin film transistor according to 1. A method of manufacturing a thin film transistor as defined in claim 3,
Crystallizing the amorphous semiconductor film for forming the channel formation region to form a polycrystalline semiconductor film having a columnar structure in which the column axis is directed upward on the substrate surface, and then patterning the polycrystalline semiconductor film Then, a side end face substantially parallel to the column axis is exposed, and then the gate insulating film and the gate electrode are sequentially formed. A method of manufacturing a thin film transistor as defined in claim 4,
After forming the polycrystalline semiconductor film and the upper layer side semiconductor film in this order,
A method of manufacturing a thin film transistor, wherein the polycrystalline semiconductor film and the upper semiconductor film are patterned in a lump, and then the gate insulating film and the gate electrode are sequentially formed. A method of manufacturing a thin film transistor as defined in claim 5,
After forming the lower-layer side semiconductor film and the insulating film in this order, the insulating film is patterned into a predetermined shape, and then the polycrystalline semiconductor film constituting the channel formation region is formed on the entire surface of the substrate. A method for manufacturing a thin film transistor, wherein the polycrystalline semiconductor film is patterned later.

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