JPH10256554A - Thin film transistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid complicating the manufacturing process and attain a high performance and high reliability by laminating two or more layers having different resistivities to form an Ohmic contact layer and specifying the film thickness of each layer. SOLUTION: An n-ch thin film transistor having an LDD structure is formed by depositing a metal film on an insulation substrate 101, patterning it to form a gate electrode 102, laminating a gate insulation film 103, active layer 104, low-concn. contact layer 105, high-concn. contact layer 106, and metal film for a source-drain electrode 107, patterning them to separate elements and depositing a transparent electrode 108 for a pixel electrode etc. The LDD length is specified by the thickness of the contact layer 105, this eliminating the need of a high-accuracy aligner or special process and greatly reducing the manufacturing process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used for a liquid crystal display device and the like and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, a driving circuit integrated type liquid crystal display device in which a pixel switching circuit and a driver circuit are formed using a thin film transistor on an insulating substrate has attracted attention. In such a liquid crystal display device integrated with a driving circuit, a thin film transistor having a coplanar structure in which polycrystalline silicon having high mobility is used for an active layer is generally used.

FIG. 14 shows an example of a thin film transistor used in such a liquid crystal display device, taking an n-ch transistor as an example. Hereinafter, description will be given according to the manufacturing process.

First, a semiconductor, for example, polycrystalline silicon is laminated on an insulating substrate 11, and is patterned to form an active layer 12, and then a gate insulating film 13 is formed (a). Next, a metal film is laminated and patterned to form a gate electrode 14 (b). Next, using the gate electrode 14 as a mask, an impurity such as P is implanted at a high concentration to form a contact region 15 (c). Next, the gate electrode 1
After etching the sidewalls of No. 4, impurities are implanted at a low concentration to form LDD regions 16 (d). Next, the interlayer insulating film 1
7 and a contact hole is opened, and a metal film is stacked and patterned to form a source / drain electrode 18 (e). Next, a transparent conductive film such as ITO is formed and patterned to form a transparent electrode 1 serving as a pixel electrode.
9 is formed (f).

When the field-effect mobility of the transistor increases, hot electrons are injected into the gate insulating film at the drain end, causing a change in transistor characteristics.
Therefore, in order to prevent this, the LDD region is provided as described above to reduce the electric field at the drain end.

However, a coplanar thin film transistor having an LDD structure requires many manufacturing steps and is expensive. In particular, when patterning an LDD region, patterning accuracy on the order of sub-microns is required to alleviate the electric field while keeping the on-current high. Therefore, a complicated process such as introduction of a high-precision exposure apparatus or etching of a side wall is required.

Further, in the conventional thin film transistor, in order to stabilize the characteristics of the active layer, a process of exposing to a hydrogen plasma is usually performed after the step (f). However,
Since the active layer to be implanted with hydrogen is not exposed on the surface,
It is necessary to perform a very long process to diffuse hydrogen to the active layer. In addition, in the process of exposure to hydrogen plasma, a large amount of hydrogen may be mixed into the gate insulating film, which may cause a change in transistor characteristics.

Further, an n-ch TFT and a p-ch TFT having the same channel width and channel length have different n-ch TFTs.
It is known that a TFT has a higher ON current. This is because, in the case of n-ch, the carrier is an electron and pc
In the case of h, the carrier is a hole. On the other hand, the p-ch leakage current (3 to 5E-12 pA / μ
m) is the n-ch leakage current (about 1E-12 pA / μ).
m) is lower than our research.

Therefore, there is a trade-off between reducing the leak current of the n-ch TFT and improving the on-current of the p-ch TFT. Therefore, TF
T (channel width / channel length) is n-channel TFT
Although it is conceivable to make the p-ch TFT larger than the p-ch TFT, there is a problem that the area occupied by the p-ch TFT becomes larger.

[0010]

As described above, the thin film transistor having a coplanar structure using polycrystalline silicon for the active layer has a problem that the manufacturing process is complicated and the manufacturing cost is high. In addition, since the active layer is not exposed to the surface when performing the process of exposing to the hydrogen plasma, it is necessary to perform a very long process to diffuse hydrogen to the active layer, and the hydrogen is contained in the gate insulating film. In a large amount, which may cause a variation in transistor characteristics.

On the other hand, since the n-ch TFT has a larger leak current and the p-ch TFT has a smaller on-current, the (channel width / channel length) of the n-ch TFT is determined by the n-ch TFT.
When the p-ch TFT is made larger than the FT,
There is a problem that the area occupied by the chTFT increases.

An object of the present invention is to provide a thin film transistor and a method for manufacturing the same, which can prevent the manufacturing process from becoming complicated and can achieve high performance and high reliability.

[0013]

A thin film transistor according to the present invention comprises a gate electrode formed on an insulating substrate, a gate insulating film covering the gate electrode, and a polycrystalline semiconductor formed on the gate insulating film. A pair of ohmic contact layers formed by stacking at least two semiconductor layers having different resistivity on the active layer, and a source / drain electrode formed on the pair of ohmic contact layers And characterized in that:

According to the invention, since the ohmic contact layer is formed by a laminated structure of at least two or more semiconductor layers having different resistivities, by defining the thicknesses of these layers, a high-precision LDD can be achieved. The structure can be easily obtained. Further, since a complicated manufacturing process is not required, a thin film transistor having an LDD structure using polycrystalline silicon for an active layer can be formed at low cost.

As the polycrystalline semiconductor, polycrystalline silicon can be used, but polycrystalline SiC or the like can also be used. In the method for manufacturing a thin film transistor according to the present invention, a step of forming a gate electrode on an insulating substrate, a step of forming a gate insulating film covering the gate electrode, and a step of forming a polycrystalline semiconductor layer on the gate insulating film Forming an ohmic contact layer on the polycrystalline semiconductor layer, forming a metal film pattern on the ohmic contact layer, using the metal film pattern as a mask, Removing the crystalline semiconductor layer and the gate insulating film, forming a conductive film pattern connected to the metal film pattern, and removing the metal film and the ohmic contact layer using the conductive film pattern as a mask. Forming a source / drain electrode using the metal film by removing the metal film. To.

According to the invention, the island-shaped structure is formed by removing the ohmic contact layer, the polycrystalline semiconductor layer and the gate insulating film using the pattern of the metal film as a mask, and the conductive film (generally, the pixel electrode) is formed. Conductive film)
The source / drain electrodes are formed by removing the metal film and the ohmic contact layer using this pattern as a mask, so that a thin film transistor using polycrystalline silicon for the active layer can be formed by a simple manufacturing process. In addition, hydrogen can be easily introduced into the active layer by a process of exposing to hydrogen plasma.

The polycrystalline semiconductor layer may be polycrystalline at the time of film formation or amorphous at the time of film formation and may be polycrystalline by laser annealing or the like. In addition, an n-type thin film transistor is provided on the same substrate (provided in a display region and a drive circuit portion).
In the case where a p-type thin film transistor (provided in a driver circuit portion) is provided, the source and drain electrodes of the n-type thin film transistor and the p-type thin film transistor may be formed of different materials.

The polycrystalline semiconductor may be polycrystalline silicon, but polycrystalline SiC or the like may be used. In addition, the CMOS in the present invention
A thin film transistor having a structure has polycrystalline silicon in a channel region, and a method of connecting an active layer and a source / drain is different between an n-type thin film transistor and a p-type thin film transistor. Specifically, in an n-type thin film transistor, an active layer and a source / drain are provided in separate layers, and in a p-type thin film transistor, an active layer and a source / drain are provided in the same layer. Note that this structure can be applied to not only a bottom gate thin film transistor but also a top gate thin film transistor.

According to the invention, an n-type thin film transistor having low leakage current (generally, an n-type polycrystalline silicon thin film transistor) and a p-type thin film transistor having a high on-current having the same size as the n-type thin film transistor (generally, Can obtain a p-type polycrystalline silicon thin film transistor). That is, in the n-type thin film transistor, since the active layer (channel region) is provided in a layer different from the source / drain region, a micro-offset structure is formed, and the leakage current which is a problem of the n-type thin film transistor can be reduced. it can. Further, since the micro-offset structure is formed, it is possible to improve the reliability particularly due to the Vds breakdown voltage. On the other hand, in the p-type thin film transistor, even if the active layer (channel region) is formed in the same layer as the source / drain regions, the leak current is small (<
(About 1 pA / μm), a high on-state current can be obtained by using the same layer structure without the micro offset structure.

Further, since the photolithography process for forming the micro-offset LDD region also serves as the formation of the source / drain, the manufacturing process can be simplified (the number of times of photolithography is six). ), The cost can be reduced and the yield can be improved. Also, in order to provide a micro-offset LDD,
The reliability of the TFT is improved.

[0021]

Embodiments of the present invention will be described below. First, a first embodiment of the present invention will be described with reference to FIG. In FIG. 1, 101 is an insulating substrate,
102 is a gate electrode, 103 is a gate insulating film, 104 is an active layer using polycrystalline silicon, 105 is a first contact layer, 106 is a second contact layer, 107 is a source / drain electrode, 108 is a transparent electrode, 109 is a protective film.

First, a metal film is deposited on an insulating substrate 101 and is patterned to form a gate electrode 102. In this example, a MoTa alloy having a thickness of 300 n was used as the metal film.
m (a).

Next, the gate insulating film 103 and the active layer 10
4. After laminating a low-concentration contact layer 105, a high-concentration contact layer 106, and a metal film for the source / drain electrodes 107, these are patterned to perform element isolation.
At this time, the gate contact portion is also opened. In this example,
The gate insulating film 103 is made of S by ECR plasma CVD.
An iO ₂ film is deposited to a thickness of 200 nm, and then undoped amorphous silicon is deposited as an active layer 104 by plasma CVD.
After laminating 0 nm, this is melted by an excimer laser to obtain a polycrystalline silicon film. The low concentration of the contact layer 105 SiH ₄ and PH ₃ amorphous silicon thin film in the plasma CVD method as a raw material gas resistivity 10 ⁴ [Omega] cm to 500nm is deposited, a high concentration of the contact layer 106
CV using SiH ₄ and PH ₃ as source gas
The amorphous silicon thin film having a resistivity of 200
nm. Further, as the metal film, a 300 nm MoW alloy is deposited by a sputtering method. Each layer is patterned by dry etching (b).

Next, a transparent electrode 108 used as a pixel electrode or the like is used.
And patterning is performed up to the active layer 104. At the time of etching, patterning is first performed with a resist, and then dry etching is performed with an alcohol-based gas. Subsequently, dry etching is performed in a mixed system of CF ₄ and O ₂ to pattern the source / drain electrodes 107 and the two contact layers 105 and 106. In this example, amorphous silicon is used for the contact layers 105 and 106,
Since polycrystalline silicon is used for the active layer 104, a selectivity of about 1:10 can be obtained in dry etching, and the etching can be completed before the active layer.

Finally, a protective film 109 is formed, and an n-ch thin film transistor having an LDD structure as shown in FIG. 1 is formed (c). Next, a second embodiment of the present invention will be described with reference to FIG. In the present embodiment, nc
This is an example of a case where a C-MOS is formed using an h thin film transistor and a p-ch thin film transistor.

First, a metal film is formed on an insulating substrate 121, and is patterned to form a gate electrode 122. Subsequently, a gate insulating film 123 and an active layer 124 using polycrystalline silicon are formed. Subsequently, a p-type amorphous silicon layer 125 and a metal film 126 are formed, and these are patterned to leave only a portion where a p-ch transistor is formed. Patterning can be performed by dry etching, but can also be performed by lift-off or selective film formation (a).

Next, the low-concentration n-type amorphous silicon layer 12
7, high concentration n-type amorphous silicon layer 128, metal film 12
9 is deposited (b), and the whole is patterned into an island shape. At this time, a contact hole of the gate is also opened (c).

Next, the transparent electrode 130 used as a pixel electrode or the like
And patterning is performed up to the active layer 124. Finally, a protective film 131 is formed, and a C-MO as shown in FIG.
An S structure is formed (d).

Since the deterioration due to the generation of hot electrons is relatively small in the p-ch transistor, the p-ch transistor does not have the LDD structure in this example, but if the low-concentration layer is formed, the p-ch transistor However, a thin film transistor having an LDD structure can be formed.

As described above, according to the first and second embodiments, L
Since the DD length is determined by the thickness of the low-concentration contact layer, a high-precision exposure apparatus and a special process are not required. Further, the number of manufacturing steps can be greatly reduced as compared with the conventional thin film transistor, and the thin film transistor can be manufactured at low cost.

Next, a third embodiment of the present invention will be described with reference to FIGS. First, a high-melting low-resistance metal film serving as a gate line and a gate electrode is formed on the transparent insulating substrate 201 by a method such as sputtering, and is patterned by using a method such as photolithography.
A gate line and a gate electrode 202 are formed (FIG. 3
(A)).

Next, an SiO _x film or a SiN _x film is formed as the gate insulating film 203 by a method such as plasma CVD (FIG. 3B). Next, the semiconductor layer (active layer) 20
As No. 4, a Si film is continuously formed by a method such as plasma CVD. At this time, the Si film may be amorphous Si or polycrystalline Si at the time of film formation. When the formed Si film is amorphous Si, crystallization is further performed using a method such as laser annealing (FIG. 3C).

Next, an n-type amorphous Si film or an n-type microcrystalline Si film to be the ohmic contact layer 205 of the n-type thin film transistor in the pixel portion and the drive circuit portion is formed by a method such as plasma CVD. Then, the signal line and the source
A low-resistance metal film 207a serving as a drain electrode is formed by a method such as sputtering. Subsequently, the low-resistance metal film 207a and the n-type ohmic contact layer 205 are patterned using the same mask by a method such as photolithography (FIG. 3D).

Next, p-type amorphous Si which becomes the ohmic contact layer 206 of the p-type thin film transistor of the drive circuit portion
A film or a p-type microcrystalline Si film is formed by a method such as plasma CVD. Subsequently, a low-resistance metal film 207b is formed by a method such as sputtering. Subsequently, the low-resistance metal film 207b and the p-type ohmic contact layer 206 are patterned using the same mask by a method such as photolithography (FIG. 3E).

Next, the semiconductor layer 204 and the gate insulating film 203 are continuously etched using the low-resistance metal films 207a and 207b serving as signal lines and source / drain electrodes as masks (FIG. 3F).

Next, a transparent conductive film 208 serving as a pixel electrode is formed by a method such as sputtering, and is patterned into a desired shape (FIG. 4G). Next, in order to separate the source and drain electrodes, the low-resistance metal films 207a and 207b between the source and drain and the ohmic contact layers 205 and 206 are etched using the pattern of the transparent electrode 208 as a mask. Subsequently, a process of exposing to hydrogen plasma is performed. In this example, hydrogenation can be performed very easily because the active layer 204 is exposed at the time of performing this process. Further, there is no possibility that excessive hydrogen is mixed into the gate insulating film 203, and the characteristics of the thin film transistor do not change (FIG. 4H).

Finally, the protective insulating film 209 is formed by plasma CV.
A film is formed by a method such as D, and is patterned into a desired shape using a method such as photolithography (FIG. 4 (i)).

Next, a fourth embodiment of the present invention will be described with reference to FIGS. The same or corresponding components as those of the third embodiment shown in FIGS. 3 and 4 are denoted by the same reference numerals.

First, a high-melting low-resistance metal film serving as a gate line and a gate electrode is formed on the transparent insulating substrate 201 by a method such as sputtering, and is patterned by using a method such as photolithography. A gate electrode 202 is formed (FIG. 5A).

Next, an SiO _x film or a SiN _x film is formed as the gate insulating film 203 by a method such as plasma CVD (FIG. 5B). Next, the semiconductor layer (active layer) 20
As No. 4, a Si film is continuously formed by a method such as plasma CVD. At this time, the Si film may be amorphous Si or polycrystalline Si at the time of film formation. When the formed Si film is amorphous Si, crystallization is further performed using a method such as laser annealing (FIG. 5C).

Next, an n-type amorphous Si film or an n-type microcrystalline Si film to be the ohmic contact layer 205 of the n-type thin film transistor in the pixel portion and the drive circuit portion is formed by a method such as plasma CVD. Then, the signal line and the source
A low-resistance metal film 207a serving as a drain electrode is formed by a method such as sputtering. Subsequently, the low-resistance metal film 207a and the n-type ohmic contact layer 205 are patterned using the same mask by a method such as photolithography (FIG. 5D).

Next, p-type amorphous Si which becomes the ohmic contact layer 206 of the p-type thin film transistor of the drive circuit portion
A film or a p-type microcrystalline Si film is formed by a method such as plasma CVD. Subsequently, a low-resistance metal film 207c is formed by a method such as sputtering. Subsequently, the low-resistance metal film 207c and the p-type ohmic contact layer 206 are patterned using the same mask by a method such as photolithography (FIG. 5E).

In this embodiment, the low-resistance metal film serving as the source / drain electrodes of the p-type thin film transistor is n-type.
It is made of a material different from the low resistance metal film serving as the source / drain electrodes of the thin film transistor. Specifically, a low resistance metal film serving as a source / drain electrode of an n-type thin film transistor is made of a material such as Al which is not removed by a dry etching technique, and a source / drain electrode of a p-type thin film transistor is made of MoW or the like. As described above, a material that can be removed by dry etching is used. By using such a combination of materials, it is possible to prevent the low-resistance metal film in the n-type thin film transistor portion from being etched by the influence of a pinhole or the like in the step of etching and removing the low-resistance metal film in the p-type thin film transistor portion. In addition, it is possible to prevent the yield from being lowered due to a defective etching process.

Next, the semiconductor layer 204 and the gate insulating film 203 are continuously etched using the low-resistance metal films 207a and 207c serving as signal lines and source / drain electrodes as masks (FIG. 5F).

Next, a transparent conductive film 208 serving as a pixel electrode is formed by a method such as sputtering, and is patterned into a desired shape by a method such as photoetching (FIG. 6G).

Next, in order to separate the source / drain electrodes, the low resistance metal films 207a and 207c between the source and the drain and the ohmic contact layers 205 and 206 are etched using the pattern of the transparent electrode 208 as a mask. . Subsequently, a process of exposing to hydrogen plasma is performed.
In this example, hydrogenation can be performed very easily because the active layer 204 is exposed at the time of performing this process. Further, there is no possibility that excessive hydrogen is mixed into the gate insulating film 203, and the characteristics of the thin film transistor do not change (FIG. 6).
(H)).

Finally, the protective insulating film 209 is formed by plasma CV.
A film is formed by a method such as D, and is patterned into a desired shape using a method such as photolithography (FIG. 6 (i)).

As described above, according to the third and fourth embodiments, it is possible to manufacture a drive circuit-integrated liquid crystal display device formed of a polycrystalline Si thin film transistor in fewer steps than in the related art. Further, due to its structure, hydrogen can be easily introduced into the active layer by the hydrogen plasma treatment, which contributes to an improvement in productivity. Further, occurrence of characteristic failure due to excessive hydrogen in the gate insulating film can be suppressed.

Further, according to the fourth embodiment, in the step of etching and removing the low-resistance metal film in the p-type thin film transistor portion, a defect that the low-resistance metal film in the n-type thin film transistor portion is etched occurs. Can be prevented.

Next, a fifth embodiment of the present invention will be described with reference to FIG. It is to be noted that components denoted by the same reference numerals are formed in the same process using the same material unless otherwise specified.

A gate electrode 302 made of, for example, MoTa is provided on an insulating substrate 301 made of, for example, glass, and a gate electrode 302 made of, for example, SiO _x and SiN _x is formed on the gate electrode 302.
A gate insulating film 303 having a layer structure is provided.

In an n-ch TFT, the gate insulating film 303
An intrinsic polycrystalline Si film 304 is provided thereon, and a source region 311 and a drain region 312 are separately provided thereon. The source region 311 and the drain region 312 have a structure in which a leakage current is reduced by, for example, a stacked structure of an n ⁻ silicon layer 305 and an n ⁺ silicon layer 306. An n-ch source / drain electrode 307 and a p-ch source / drain electrode 308 are stacked thereon, and are further electrically connected to an electrode 310 such as ITO through an insulating film 309.

In a p-ch TFT, the gate insulating film 303
An intrinsic polycrystalline Si film 304 is provided thereon, and p ⁺ source / drain regions 320 are provided in the same layer. These are connected to the p-ch source / drain electrodes 308 and further electrically connected to a wiring electrode 310 such as ITO through an insulating film 309.

As described above, the n-ch TFT and the p-chT
The FT differs from the FT in the manner of connection between the active layer and the source / drain. Note that, in the example of FIG.
In FT, the layer above the active layer is used as the source / drain, and p-
Although the active layer and the source / drain are the same layer in the chTFT, the n-ch TFT may have a structure in which the layer below the active layer is the source / drain. Also, p-
Although the source and drain electrodes of the chTFT and the n-chTFT are different from each other, the same material may be used. Further, the source / drain electrodes of the n-ch TFT may not be laminated, and may be constituted only by the electrode material of the p-ch TFT.
In this case, both the p-ch TFT and the n-ch TFT
Needless to say, it can be formed in a self-aligned manner by backside exposure.

Next, a sixth embodiment of the present invention will be described with reference to the sectional view shown in FIG. 8 and the plan view shown in FIG. It is to be noted that components denoted by the same reference numerals are formed in the same process using the same material unless otherwise specified.

A gate electrode 302 made of, for example, MoW is provided on an insulating substrate 301 made of, for example, a quartz substrate, and a gate insulating film 303 made of, for example, SiN _x or SiO _x is provided on the gate electrode 302.

In an n-ch TFT, the gate insulating film 303
An intrinsic polycrystalline Si film 304 is provided thereon, and a source region 311 and a drain region 312 are separately provided thereon. The source region 311 and the drain region 312 have a structure in which, for example, an n ⁻ silicon layer 305 and an n ⁺ silicon layer 306 are stacked to reduce a leak current. On top of that, a source using Al etc.
Is the drain electrode 308 is stacked, it is electrically connected to the SiO _x or BPSG, etc. of the insulating film 309 electrode 310 such as ITO through.

In the case of a p-ch TFT, the gate insulating film 303
An intrinsic polycrystalline Si film 304 is provided thereon, and p ⁺ polycrystalline Si source / drain regions 320 are provided in the same layer. These are connected to the source / drain electrodes 308 and are electrically connected to a wiring electrode 310 such as ITO through an insulating film 309.

The auxiliary capacitance Cs is determined by the electrode 302, the insulating film 30
3, a layer structure of the p ⁺ layer 320 and the electrode 308. The electrode 308 is connected to the pixel electrode 310 via the insulating film 309.

As described above, the present embodiment differs from the fifth embodiment in that the source and drain electrodes of the n-ch TFT and the p-ch TFT are the same. In this example, the pixel electrode is connected to the p-ch TFT.
It may be connected to an n-ch TFT.

In the fifth and sixth embodiments, n
In the −ch TFT, the source / drain is formed in a layer above the active layer, so that a leak current can be reduced.
In the p-ch TFT, the active layer and the source / drain are in the same layer, and a high ON current can be obtained even with the same size (W / L ratio) as the n-ch TFT.

Next, a seventh embodiment of the present invention (manufacturing process)
Will be described with reference to FIG. First, MoTa or the like is deposited on a light-transmitting insulating substrate 301 such as a glass substrate or a quartz substrate by a sputtering method, and a gate electrode 302 is formed by photolithography and etching (FIG. 10A).

Next, after forming the gate insulating film 303, an a-Si: H film is deposited to a thickness of about 80 nm by a CVD method or the like, and annealed at 500 ° C. for 1 hour. Subsequently, a-Si: H is applied by, for example, XeCl excimer laser annealing.
The film is melted and recrystallized to form a polycrystalline Si film 304. After that, for example, an n ⁻ polycrystalline Si film 305 and an n ⁺ polycrystalline Si film 306 are laminated and formed, for example, Mo or MoW.
Then, a metal film 307 is formed (FIG. 10B).

Next, the metal film 307, the n ⁺ film 306 and the n
^- The film 305 is etched by RIE or the like, followed by p-
P-type impurities such as B ⁺ and B ₂ H _x ⁺ are ion-doped or ion-implanted into the chTFT region (for example, an acceleration voltage of 10 kV and a dose of 5 × 10 ¹⁵ / cm ² ) to form a p ⁺ polycrystalline Si layer 320. (FIG. 10C).

Next, an activation treatment is performed at 300 ° C. for about 1 hour, and then the source / drain electrode film 3 of the p-ch TFT is formed using a metal such as Mo, MoTa, AlSi, or Al.
08 is formed and patterned by photolithography and etching (FIG. 10D).

Next, the source electrode and the drain electrode are separated by photolithography and etching.
An insulating film 309 such as _x , SiN _x , or BPSG is formed (FIG. 10E).

Next, after opening the insulating film 309 by photolithography and etching, a transparent electrode 310 using, for example, ITO or the like is formed. Thereafter, the electrode 310 is patterned by photolithography and etching to complete a TFT-LCD array (FIG. 10).
(F)).

The TFT-LC manufactured by using this manufacturing method
In the D array, the offset structure can be easily formed in the n-ch TFT, and the leakage current can be reduced to 0.7 pA / μm.
To a degree. On the other hand, in the p-ch TFT, a high on-state current can be obtained because no micro-offset is formed. Further, according to the present manufacturing method, T
Since the FT-LCD array can be manufactured in six photolithography / etching steps, the number of steps can be significantly reduced as compared with about ten conventional photolithography / etching steps.

In this example, the TF connected to the pixel electrode
Although a p-ch TFT is used for T, it goes without saying that an n-ch TFT may be used. Next, an eighth embodiment (manufacturing process) of the present invention will be described with reference to FIG. This embodiment is an example in which an n-ch TFT is formed by self-alignment.

First, MoTa or the like is deposited on a light-transmitting insulating substrate 301 such as a glass substrate or a quartz substrate by a sputtering method, and then a gate electrode 302 is formed by photolithography and etching (FIG. 11A). .

Next, after forming the gate insulating film 303,
An a-Si: H film having a thickness of about 80 nm is deposited by a CVD method or the like, and annealing is performed at 500 ° C. for 1 hour. Subsequently, the a-Si: H film is melted and recrystallized by, for example, XeCl excimer laser annealing to form a polycrystalline Si film 304.
Then, for example, a thickness of 30 nm n ^- polycrystalline Si film 305
Then, an n ⁺ polycrystalline Si film 306 having a thickness of 30 nm is formed. At this time, the length of the path in the n ⁻ layer 305 and the n ⁺ layer 306 can be determined in the film thickness direction, so that a high-precision one can be easily obtained as compared with a method of controlling the length of the n ⁻ layer by photolithography. Can be formed (FIG. 11B).

Next, the n ⁺ film 306 and the n ⁻ film 305 are
Etching by IE or the like is performed, and then p-type impurities such as B ⁺ or B ₂ H _x ⁺ are ion-doped or ion-implanted into the p-ch TFT region (for example, an acceleration voltage of 10 kV, a dose of 1 × 10 ¹⁵ / cm ² , ), P ⁺ polycrystalline Si layer 320
Is formed (FIG. 11C).

Next, an activation process is performed by, for example, a XeCl excimer laser, followed by Mo, MoTa, AlS
The source / drain electrode film 3 is formed by using a metal such as i or Al.
08 is formed and patterned by photolithography and etching (FIG. 11D).

Next, the source electrode and the drain electrode are separated by photolithography and etching using a backside exposure method. At this time, the source and drain can be formed in a self-aligned manner in the n-ch TFT. continue,
PECVD, APCVD, etc., for example, SiO2
An insulating film 309 of _x , SiN _x , BPSG or the like is formed (FIG. 11E).

Next, after opening the insulating film 309 by photolithography and etching, a transparent electrode 310 of, for example, ITO is formed. Thereafter, the electrode 310 is patterned by photolithography and etching to complete a TFT-LCD array (FIG. 11).
(F)).

TFT-LC manufactured by using this manufacturing method
In the D array, the offset structure can be easily formed in the n-ch TFT, and the leakage current can be reduced to 0.7 pA / μm.
To a degree. On the other hand, in the p-ch TFT, a high on-state current can be obtained because no micro-offset is formed. Further, since the n-ch TFT is manufactured in a self-aligned manner, there is almost no parasitic capacitance between the gate and the source. Therefore, high quality TFT-
LCD can be obtained.

FIG. 12 is a cross-sectional view schematically showing one example of a liquid crystal display device using a thin film transistor according to the present invention. In this liquid crystal display device, one transparent insulating substrate 3
A plurality of switching TFTs 352, pixel electrodes 353, gate lines (not shown), and signal lines (not shown) are provided on 51.
Are formed, and a driving circuit (not shown) using TFTs for driving these TFT arrays is also provided. A counter electrode 358 is formed on the other transparent insulating substrate 359.

FIG. 13 is an equivalent circuit diagram of a liquid crystal display device using the thin film transistor according to the present invention. A TFT 352, a gate line 354, a signal line 355, a liquid crystal layer 363, and a storage capacitor (Cs) 364 are formed in the display area, and a p-ch TFT 360 and an n-ch
A CMOS section 362 including a TFT 361 is formed. The connection of the circuit wiring, in particular, n-ch TFT and p-
The connection with the chTFT may be made via an ITO electrode.

In the above-described fifth to eighth embodiments, a known technique (Japanese Patent Application No. Hei 5-23626) is used.
0), an amorphous silicon film may be provided between the active layer and the n ⁺ region in the n-ch TFT. In this case as well, the effect of reducing the leak current is reduced, and the number of photolithography steps is not increased. C according to the gist of the invention
A MOS structure is obtained. Further, an offset structure may be formed using a polycrystalline Si layer or a microcrystalline Si layer. Further, n ⁺ ions are implanted into a non-doped layer of polycrystalline Si or the like, and the depth of the implanted impurities is controlled so that n ⁻
A layer and an n ⁺ layer may be formed. Also, by making the implantation depth shallow, an offset structure can be provided. The present invention is not limited to the above embodiments, and can be implemented with various modifications without departing from the scope of the invention.

[0080]

According to the present invention, since the ohmic contact layer is formed by a laminated structure of at least two semiconductor layers having different resistivities, the thickness of these layers is regulated to achieve high precision. Can easily be obtained. Further, since a complicated manufacturing process is not required, a thin film transistor having an LDD structure using polycrystalline silicon for an active layer can be formed at low cost.

According to the present invention, the ohmic contact layer, the polycrystalline semiconductor layer, and the gate insulating film are removed by using the pattern of the metal film as a mask to form an island structure, and the pattern of the conductive film is used as a mask. Since the source / drain electrodes are formed by removing the metal film and the ohmic contact layer, a thin film transistor using polycrystalline silicon for the active layer can be formed by a simple manufacturing process.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an example of a manufacturing process of a thin film transistor and the like according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing an example of a manufacturing process of a thin film transistor and the like according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing a part of an example of a manufacturing process of a thin film transistor and the like according to a third embodiment of the present invention.

FIG. 4 is a sectional view showing a part of an example of a manufacturing process of a thin film transistor and the like according to a third embodiment of the present invention.

FIG. 5 is a sectional view showing a part of an example of a manufacturing process of a thin film transistor and the like according to a fourth embodiment of the present invention.

FIG. 6 is a sectional view showing a part of an example of a manufacturing process of a thin film transistor and the like according to a fourth embodiment of the present invention.

FIG. 7 is a sectional view showing an example of a thin film transistor and the like according to a fifth embodiment of the present invention.

FIG. 8 is a sectional view showing an example of a thin film transistor and the like according to a sixth embodiment of the present invention.

FIG. 9 is a plan view showing an example of a thin film transistor and the like according to a sixth embodiment of the present invention.

FIG. 10 is a sectional view showing an example of a manufacturing process of a thin film transistor and the like according to a seventh embodiment of the present invention.

FIG. 11 is a sectional view showing an example of a manufacturing process of a thin film transistor and the like according to an eighth embodiment of the present invention.

FIG. 12 is a cross-sectional view illustrating an example of the configuration of an active matrix LCD configured using the thin film transistors according to the present invention.

FIG. 13 is an equivalent circuit diagram showing an example of an active matrix LCD configured using the thin film transistors according to the present invention.

FIG. 14 is a cross-sectional view illustrating a manufacturing process of a thin film transistor according to a conventional technique.

[Explanation of symbols]

101, 201, 301 ... insulating substrate 102, 202, 302 ... gate electrode 103, 203, 303 ... gate insulating film 104, 204, 304 ... active layer 105, 106, 205, 206, 305, 306 ... ohmic contact layer 107, 207, 307, 308: source / drain electrodes

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 29/78 616A (72) Inventor Yoshito Kawahisa 33, Shinisogo-cho, Isogo-ku, Yokohama-shi, Kanagawa Pref. Inside

Claims (2)

[Claims] A gate electrode formed on an insulating substrate;
A gate insulating film covering the gate electrode, an active layer formed using a polycrystalline semiconductor on the gate insulating film, and at least two or more semiconductor layers having different resistivity formed on the active layer. A thin film transistor comprising: a pair of ohmic contact layers formed as described above; and source / drain electrodes formed on the pair of ohmic contact layers. A step of forming a gate electrode on the insulating substrate; a step of forming a gate insulating film covering the gate electrode; a step of forming a polycrystalline semiconductor layer on the gate insulating film; Forming an ohmic contact layer on the semiconductor layer, forming a metal film pattern on the ohmic contact layer, and using the metal film pattern as a mask, the ohmic contact layer, the polycrystalline semiconductor layer, and the gate. Removing the insulating film;
Forming a pattern of a conductive film connected to the pattern of the metal film; and removing the metal film and the ohmic contact layer using the pattern of the conductive film as a mask, thereby forming a source / drain electrode using the metal film. Forming a thin film transistor.