JP2001274413A - Method of manufacturing thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a high-reliability thin film transistor with less characteristics variation wherein the offset structure or LDD structure can be formed in a simple process. SOLUTION: An insulation film 104 and a conductive film 105 are laminated on a semiconductor layer 103, a resist mask 106 with a specified pattern is formed on the conductive film, the conductive film is etched to form gate electrodes 107a, 107b tapered with broadened bottom faces, and an impurity is introduced by ion doping into the semiconductor layer through the gate electrodes used as a mask with the residual resist mask 106. The resist mask suppresses unwanted impurities such as hydrogen from infiltrating into the channel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for manufacturing a thin film transistor.

[0002]

2. Description of the Related Art Display devices such as plasma, light emitting diode, and liquid crystal display devices can be made thinner, and their demands are increasing for use in display devices such as office equipment and computers or special display devices.

Among these, a thin film transistor (TFT) using amorphous silicon (a-Si) which is amorphous or silicon having a crystal (polysilicon: poly-Si) is arranged on a matrix as a switching element. Such a liquid crystal display device (TFT-LCD) has been actively developed because of high display quality and low power consumption.

In particular, TFTs using poly-Si have a
The mobility is about 10 to 100 times higher than that of the SiTFT, and not only is it used as a pixel switching element by utilizing its advantage, but also the pixel TFT and the driving circuit TFT are formed on the same substrate by using a poly-SiTFT for the peripheral driving circuit. Research and development of a drive circuit integrated type TFT-LCD formed simultaneously on the LCD are being actively carried out.

The poly-Si TFT is an a-Si TFT
Mobility is higher than that of
There is a drawback that the leakage current flowing at F is higher than that of the a-Si TFT. When a driving circuit is configured, there is no particular problem, but when used for pixel switching, it causes image quality degradation.

Therefore, poly-SiT used for pixels
There are various types of FTs in which the structure is devised. As an example, when a TFT having an offset structure is manufactured, two photolithography steps are required to form a source / drain region and an offset region. Therefore, at least two masks are required for exposure, and a corresponding exposure step such as a PEP step is also required, resulting in a problem that the steps are complicated.

[0007]

The conventional method of manufacturing a thin film transistor has an offset structure which is advantageous for reducing the leak current, but requires two exposure steps which require at least two masks. However, there was a problem that it became complicated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an offset structure or an LDD structure can be formed in a single exposure step. The purpose is to provide a manufacturing method.

[0009]

In order to achieve the above object, a step of forming a semiconductor layer on a substrate in an island shape, a step of forming an insulating film on the semiconductor layer, and a step of forming a conductive film on the insulating film Forming a resist mask of a predetermined pattern on the conductive film, patterning the conductive film according to the resist mask to form a tapered gate electrode having a widened bottom surface, An object of the present invention is to provide a method for manufacturing a thin film transistor, comprising a step of introducing an impurity into the semiconductor layer using a mask and the gate electrode as a mask. Here, the semiconductor may be a processed semiconductor such as a group 4 semiconductor or a group 3-4,
Silicon is preferred from the viewpoint of improving image quality when used in a liquid crystal display device.

When a thin film transistor is manufactured on a transparent insulating substrate, a gate electrode etching step, an impurity implantation step, and a re-etching step are performed using the same mask, thereby forming a submicron or micron-order offset region manufacturing step. Can be simplified. In addition, unnecessary impurities are prevented from being injected into the channel via the mask, and fluctuations in characteristics can be suppressed. As a result, the cost can be reduced and the yield can be improved.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments. (Embodiment 1) Embodiment 1 will be described with reference to FIG. FIG. 1 shows a manufacturing process of an n-channel coplanar TFT.

First, an SiOx film 102 serving as a buffer layer is deposited to a thickness of about 100 nm on a light-transmitting insulating substrate 101 such as a glass substrate or a quartz substrate by a CVD method. Further, an a-Si: H film is deposited to a thickness of 50 nm by a CVD method,
After furnace annealing at 0 degrees for 1 hour, the a-Si: H film is melt-recrystallized by, for example, XeCl excimer laser annealing to form a poly-Si film 103. afterwards,
The poly-Si film, that is, the semiconductor layer 103 is patterned, etched, and processed into an island shape by photolithography or the like (FIG. 1A).

Next, after depositing a 100 nm thick SiOx film 104 as a gate insulating film by a CVD method, a conductive film 105 of, for example, phosphorus-doped a-Si is
1 nm (FIG. 1B).

After patterning the resist, the photosensitive polyimide 106, and the like by photolithography, the gate electrode 107a is etched by, for example, the CDE method so as to form an angle of θ ₁ = 25 ° (FIG. 1C).

Next, without removing the resist 106 such as polyimide, the resist 106 and the gate electrode 107a are removed.
Is used as a mask to implant phosphorus by an ion implantation or ion doping method. In the case of the ion implantation method, for example, the acceleration voltage is 100 keV and the dose is 5 × 10 ¹⁵ cm ⁻² . Phosphorus ion is a source without a gate electrode on top.
The drain region 108 is heavily doped with phosphorus ions. A region in which phosphorus ions are implanted through the end of the gate taper and electrically adjacent to this region, that is, a lightly doped region 109, and a film thickness of 215 nm is further adjacent to this region.
An active layer region immediately below the tapered portion having a length of m or more, that is, a region 110 which remains intrinsic Si is obtained (FIG. 1D). Phosphorus doping gas is PH ₃ / H ₂
The gate electrode has a masking effect on phosphorus ion doping. However, since the hydrogen ions easily penetrate the gate electrode and enter the channel of the semiconductor layer immediately below, the resist film exerts a masking action on doping of this light element such as hydrogen. In the embodiment, a-Si is used for the gate electrode. However, even if a metal such as MoW material is used, penetration of hydrogen occurs, so that the resist mask works effectively.

Next, the resist, polyimide or the like is not peeled off, and is used as a mask at the time of anisotropic etching by the RIE method while being used at the time of etching by the CDE method. When the gate electrode is re-etched by RIE at a taper angle of θ ₂ = 87 degrees, an offset region 110 of about 600 nm and an LDD region 109 of about 460 nm can be formed. The state of the active layer and the gate electrode at this time will be described. Due to the re-etching of the gate electrode, the length of the gate electrode 107b is shortened, and accordingly, the channel region is slightly shortened. The lightly doped (LDD) region 109 and the intrinsic Si region (offset region) 110 are added adjacent to the channel as a part of the source / drain region (FIG. 1E).

After the resist and the like are removed, the AP
An interlayer insulating film 111 is deposited to a thickness of about 400 nm by a CVD method (FIG. 1F). Next, the source / drain region and the gate electrode 107b are activated by, for example, XeCl excimer laser annealing. If the laser energy at this time is about 200 mJ / cm ² , activation can be sufficiently performed. When the laser activation method is used, the diffusion length of the impurity is at most about 60 nm, so that it is about 540 nm (0.5 μm).
m) of the offset region 110 is formed. Furthermore, L
Since the DD region 109 and the offset region 110 are melted at the same time, a good n / i junction can be formed, which also contributes to a reduction in leakage current (FIG. 1 (g)).

Further, a contact hole H is opened by photolithography (FIG. 1 (h)), and, for example, an Al film is formed as a source / drain electrode by a sputtering method. By patterning the source / drain electrodes 112 by photolithography or the like, an n-channel coplanar TFT is completed (FIG. 1 (i)).

Here, the taper processing of the gate electrodes 107a and 107b will be described. When taper etching the gate electrode, as shown in FIG.
The taper angle of the 7a and θ ₁ degrees. Next, impurities are implanted without using the gate electrode 107a as a mask without removing the resist or the like. Further, using the resist or the like used at the time of etching the gate electrode 107a as a mask, the gate electrode 107b is re-etched so that the edge portion of the gate electrode 107a is vertical or nearly vertical (θ ₂ ) to form the gate electrode 107b. At this time, it goes without saying that the etching is performed under the condition of θ ₂ > θ ₁ . Gate electrode 10
7a, the length (L) of the region into which impurities are implanted through the gate insulating film 104 and the length (L ₀ ) of the so-called offset region of intrinsic polysilicon adjacent to the channel region are controlled by the gate electrode. The film thickness of 107a and 107b, the ion acceleration voltage, and the angle (θ
₁ , θ ₂ ) and the like. The active layer 103 at this time
The average impurity density in the medium is shown in FIG. Thus, in one impurity implantation step, the high impurity concentration region 108 (> L), the low impurity concentration region 109 (L> L ₀ ), and the offset region 110 (L ₀ ) depend on the distance from the gate electrode end 107b.
> 0) can be formed.

Further, the gate electrode is formed under the above condition (θ ₂ >
After etching twice at θ ₁ ), an LDD structure can be obtained by further implanting impurities at a low concentration using the gate electrode as a mask.

At this time, poly-S containing no impurities is used.
High reliability is obtained when the ratio (L / L ₀ ) of the length (L) of the i region (offset region) 104 to the length (L ₀ ) of the low impurity concentration region 105 is 0.1 or more. Is preferred.

According to this manufacturing method, no new mask is required to form the offset region. Therefore, an extra PEP process or the like is not necessary, and the process can be greatly simplified.

In the TFT of the present invention, the offset structure can be easily formed, and the leakage current is reduced to 7 × 10
^-11 A, and even though the gate electrode is tapered, phosphorus ions are not implanted into the gate insulating film immediately below the gate electrode, thereby improving the reliability of the TFT. (Embodiment 2) This embodiment is different from Embodiment 1 in that the semiconductor is GaAs, a compound semiconductor other than Si, and the gate electrode is a WNx Schottky electrode. In this case, since a gate insulating film as in the first embodiment is not required, a GaAs layer is formed on a Si substrate, and a taper-shaped (trapezoid having a wide bottom surface) gate electrode further formed on the GaAs layer is used. Impurity ions are implanted to form source / drain regions, and then the side surfaces of the gate electrode are etched as in the first embodiment. The etched lower GaAs layer becomes an offset region. Thus, although the material system is different from that of the first embodiment, GaAs is used.
Can be formed in the same manner as in Embodiment 1 with a structure having an offset region.

In the present invention, a coplanar TFT has been described. However, various modifications can be made without departing from the gist of the present invention. For example, source
The same can be applied to a TFT in which the gate electrode is higher than the drain region and the channel region, for example, a staggered TFT. Needless to say, the present invention can be applied to an n-channel or p-channel type TFT. For the gate electrode material, a refractory metal, its progress, nitride, etc. can be used. For the gate insulating film, silicon nitride, silicon nitride oxide, etc. can be used. Further, the source / drain region, the channel region As for the above, various kinds of polycrystalline and amorphous semiconductors can be used.

[0025]

According to the present invention, the photolithography process for forming the offset region can be omitted, and the manufacturing process can be simplified. As a result, the cost can be reduced and the yield can be improved. In addition, when impurities such as phosphorus and boron are introduced from above the resist, the doping of a light impurity such as hydrogen into the polysilicon channel region can be effectively suppressed. Then, it is possible to suppress a change in the threshold voltage Vth of the transistor.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention in the order of steps.

FIG. 2 is an enlarged view of a main part of the embodiment of the present invention.

FIG. 3 is a diagram illustrating an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Substrate 102 Buffer layer 103 Polycrystalline silicon channel (semiconductor layer) 104 Gate insulating film 105 Conductive film 107a, 107b Gate electrode 108 Source / drain region 109 Low impurity concentration region 110 Offset region 111 Interlayer insulating film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/812 H01L 29/78 617A 29/80 B

Claims (3)

[Claims] A step of forming a semiconductor layer in an island shape on a substrate; a step of forming an insulating film on the semiconductor layer; a step of forming a conductive film on the insulating film; Forming a resist mask having a predetermined pattern, patterning the conductive film in accordance with the resist mask to form a tapered gate electrode having a widened bottom surface; and forming the semiconductor layer using the resist mask and the gate electrode as a mask. A method for manufacturing a thin film transistor, comprising: introducing an impurity into a thin film transistor. 2. The method according to claim 1, further comprising a step of forming a buffer layer on the substrate before the step of forming the semiconductor layer in an island shape. 3. The method according to claim 1, further comprising a step of activating the gate electrode by laser.