KR101186515B1 - Polysilicon liquid crystal display device and method for fabricating thereof - Google Patents

Abstract

The present invention relates to a method for manufacturing a polysilicon liquid crystal display device, and more particularly, to a liquid crystal display device having a CMOS and a method for manufacturing the same.

The present invention provides a storage electrode connection pattern that connects the storage line with a storage line and an insulating layer separated therebetween in a unit pixel, and the pixel electrode having the storage connection pattern formed on the same layer as the storage line; A capacitor is used to form a storage capacitor, and implantation of impurity ions and a pixel electrode in a transistor region are performed using a single mask, thereby reducing the number of masks, thereby reducing productivity and manufacturing cost.

Number of masks, CMOS, storage lines, pixel electrodes

Description

Structure of Polysilicon Liquid Crystal Display Device and Manufacturing Method Thereof {POLYSILICON LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THEREOF}

1 is a plan view of a typical integrated liquid crystal display device.

2 is a plan view of a unit pixel of a general polysilicon liquid crystal display device;

3A to 3H are flow charts illustrating a manufacturing process of a general polysilicon liquid crystal display device.

4 is a plan view of a unit pixel of a liquid crystal display of the present invention.

5A and 5B are cross-sectional views of the liquid crystal display device of the present invention.

6A to 6J are flowcharts showing manufacturing steps of the liquid crystal display device of the present invention.

7a to 7c are plan views according to the main manufacturing process of the present invention.

*********** Description of the symbols for the main parts of the drawings ************

401: gate line 402: data line

403: active pattern 404: storage line

405: Storage electrode connection pattern 411, 412, 413, 414, 415: Contact hole

401a: gate electrodes 402a and 402b: source and drain electrodes

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a polysilicon liquid crystal display device and a method of manufacturing the same, and more particularly, to a method of manufacturing a liquid crystal display device which reduces the number of masks used in the manufacture of a liquid crystal display device including a CMOS.

A separate liquid crystal display device having a separate driving circuit unit may be divided into a screen display unit on which an image is displayed and a driving circuit unit driving the screen display unit. The screen display unit and the driving circuit unit are connected to each other through a tape carrier package (TCP).

On the other hand, in the liquid crystal display device in which the driving circuit unit is integrated, the driving circuit unit and the screen display unit are formed on the same substrate. Therefore, the manufacturing process of the liquid crystal display device integrated with the driving circuit part is more convenient than the liquid crystal display device with the driving circuit part separation type.

However, in order to construct a liquid crystal display device integrated with a driving circuit unit, a polysilicon thin film transistor having fine and excellent operating characteristics should be used. In addition, the liquid crystal display device employing the polysilicon thin film transistor has excellent mobility compared to the liquid crystal display device using the amorphous silicon thin film transistor and is suitable for the manufacture of a liquid crystal display device requiring high-speed operation. Generally, the electrical mobility of amorphous thin film transistors (TFTs) is about 0.1-1 cm 2 / Vsec, whereas the electrical mobility of polysilicon TFTs manufactured using excimer lasers exceeds 100 cm 2 / Vsec. Have

A driving circuit unit integrated liquid crystal display device using the polysilicon thin film transistor will be described with reference to FIG. 1.

Referring to FIG. 1, a driving circuit region for driving elements of the screen display unit, which is formed on the screen display unit 120 in which the unit pixels are arranged in a matrix form on a substrate 100 such as glass, and is formed outside the screen display unit 120. 110 is formed. In the driving circuit region 110, driving circuit parts such as a gate driver 130 and a data driver 140 are formed.

Particularly, in the driving circuit unit, a CMOS having a pair of P-type and N-type complementary metal oxide semiconductors (MOS) to function as a unit transistor forms a unit and is connected to the unit pixels of the screen display unit. .

The CMOS of the driver circuit portion includes a P-type and an N-type TFT, and the switching element formed on the screen display portion 120 may mainly be formed with an N-type TFT.

Hereinafter, the planar structure of the unit pixel of the screen display unit employing the polysilicon thin film transistor will be described with reference to FIG. 2.

Referring to FIG. 2, a unit pixel area is defined by a plurality of gate lines 101 and a plurality of data lines 102 vertically crossing the gate lines. The thin film transistor 150 is formed as a switching element for controlling the unit pixel in a part of the unit pixel region.

The thin film transistor 150 includes an active pattern 104a constituting a channel of the thin film transistor, a gate electrode 101a formed on the active pattern 104a and branching from the gate line 101, and the active pattern 104a. And a source electrode 102a and a drain electrode 102b connected to the active pattern through a contact hole formed on the pattern 104a. The source and drain electrodes 102a and 102b are formed of a conductive layer branching from the data line 102. The thin film transistor 150 is connected to the pixel electrode 105 of a unit pixel.

The unit pixel further includes a storage capacitor for holding an image signal provided to the unit pixel. The storage capacitor is formed by a storage line 103 formed in parallel with the gate line, a polysilicon pattern 104b extending from the active pattern 104a, and an insulating layer formed therebetween.

Meanwhile, the source and drain regions formed in the active pattern 104a are doped with impurity ions for ohmic contact with the source and drain electrodes, and the polysilicon pattern 104b constituting the one electrode of the storage capacitor is made of metal. The impurity ions are doped to make it.

Typically, the thin film transistor of the unit pixel is an N-type TFT doped with N-type impurities.

The N-type TFT and the P-type TFT of the driving circuit region are usually formed at the same time. The manufacturing process of the N-type TFT of the screen display unit and the P-type TFT of the driving circuit region will be described with reference to FIGS. 3A to 3H.

3 shows one manufacturing process of the manufacturing process of the N-type TFT and the storage capacitor formed in the pixel region and the P-type TFT formed in the driving circuit region.

Referring to FIG. 3A, a substrate 300 such as transparent glass is prepared and a buffer layer 301 made of a silicon oxide film is formed on the substrate to a predetermined thickness.

Subsequently, an active pattern 104a is formed on the buffer layer 301 by plasma enhanced chemical vapor deposition (PECVD).

The process of forming the active pattern 104a will be described in more detail.

First, amorphous silicon is deposited on the buffer layer 301, and heat treatment is performed at a temperature of about 400 ° C. to dehydrogenate the hydrogen contained in the amorphous silicon film. In the dehydrogenation process, hydrogen gas is exploded in the process of crystallizing amorphous silicon to prevent damage to the substrate.

Next, in order to crystallize the amorphous silicon, the substrate on which the amorphous silicon layer is formed is heat-treated. Since the glass substrate may be modified by heat when the high temperature heat treatment is a glass substrate, the process of forming the polysilicon TFT using the glass substrate is performed by the instantaneous heat treatment at low temperature. A laser annealing method is used that can be made of crystalline silicon.

Therefore, the substrate on which amorphous silicon is formed is irradiated with an excimer laser to change the amorphous silicon formed on the entire substrate into polycrystalline silicon (polysilicon).

After the polysilicon is formed, the polysilicon is subjected to dry etching to form the active pattern 104a of the pixel region and the active pattern constituting the CMOS of the driving circuit portion (FIG. 3A illustrates a P-type TFT of the driving circuit portion). ). In this case, the first electrode 104b of the storage capacitor further extended from the active pattern is further formed.

Therefore, FIG. 3A shows the active pattern 104a of the N-type TFT formed in the pixel region, the first electrode 104b of the storage capacitor holding the image signal provided from the N-type TFT, and the P-type thin film transistor of the driving circuit section. The active pattern 320 is shown.

Subsequently, referring to FIG. 3B, after the active patterns are formed, impurity ion doping to metallize the first electrode 104b of the storage capacitor is performed. Doping an impurity in polysilicon improves the conductivity to improve the capacitor.

Therefore, referring to FIG. 3B, the storage first electrode 104b is exposed, and other regions are covered by the photoresist pattern 310 and doped with impurity ions.

Subsequently, the photoresist pattern 310 is removed and a first insulating layer 301 is formed to insulate the active patterns.

A conductive thin film of metal or the like is formed on the first insulating layer 301 and a photolithography process is performed to form a gate line (not shown), a gate electrode 101a branching from the gate line, and the storage first electrode. Corresponding to 104b, the storage line 103 constituting the capacitor and the gate electrode 321 of the P-type TFT are formed.

Subsequently, a low concentration of N-type impurities is doped into the active pattern 104a using the metal patterns as a mask.

Next, referring to FIG. 3D, an LDD region is defined in an active pattern of the N-type TFT, and a photoresist pattern 311 covering the storage capacitor and the P-type TFT is formed.

N-type high concentration impurity ions are implanted into the active pattern 104a using the photoresist pattern 311 as a blocking mask for doping ions. As a result, a low concentration impurity is formed near the channel of the active pattern, and a high concentration impurity is doped out to form an LDD type N-type TFT that forms a source and a drain region.

Next, referring to FIG. 3E, the P-type TFT is formed by covering the screen display unit on which the N-type TFT and the storage capacitor are formed by the photoresist pattern 312 and doping a high concentration of P-type impurities into the active pattern 320 of the P-type TFT. Form. Since the P-type impurity is higher in concentration than the N-type impurity, it is counter-doped to complete the P-type TFT.

Next, referring to FIG. 3F, a second insulating layer 303 is formed on the gate electrode, and a plurality of contact holes 304 are formed through a photo mask process.

The contact holes expose source and drain regions of the N-type TFT and the P-type TFT.

3G, source and drain electrodes 102a, 102b, 322a, and 322b connected to the source and drain regions of the N-type TFT and the P-type TFT are formed. The source and drain electrodes may be formed by sputtering a conductive film such as a metal film on the second insulating layer 303 and then performing a photolithography process.

Next, referring to FIG. 3H, a passivation layer 304 is formed to insulate the source and drain electrodes and a contact hole is formed to further expose the drain region of the pixel region. Subsequently, a transparent electrode material such as ITO is deposited on the passivation layer 304 and the pixel electrode 105 is formed by a photolithography process. The pixel electrode is connected to the drain electrode through a contact hole.

The polysilicon liquid crystal display device may be formed by the above-described process. As described above, since the conventional manufacturing process includes a plurality of mask processes, the number of masks used for shortening the process and improving productivity is as follows. Research continues to shorten the process.

Therefore, an object of the present invention is to reduce the number of masks used in forming a polysilicon liquid crystal display device as described above. In addition, by reducing the number of masks used to shorten the process it is aimed to lower the manufacturing cost and improve productivity.

The liquid crystal display device of the present invention for this purpose is a substrate divided into a pixel region and a driving circuit region; An active pattern formed in each of the pixel region and the driving circuit region of the substrate; A first insulating layer formed on the substrate on which the active pattern is formed; A gate line and a gate line formed on the first insulating layer, and storage lines separated from each other in a unit pixel of the pixel area; A pixel electrode formed on the first insulating layer of the unit pixel; A second insulating layer formed on the first insulating layer on which the gate electrode, the gate line, the storage line, and the pixel electrode are formed; And a storage electrode pattern connecting the source and drain electrodes formed on the second insulating layer, the data lines perpendicular to the gate lines, and the storage lines separated from each other in the unit pixel through contact holes. .

In addition, the manufacturing method of the liquid crystal display device of the present invention comprises the steps of providing a substrate divided into a pixel region and a driving circuit region; Forming an active pattern in each of a pixel area and a driving circuit area of the substrate; Forming a first insulating layer on the active pattern; Applying a first photoresist pattern as a mask to form a gate electrode, a gate line, and a storage line separated from each other in a unit pixel of the pixel area on the first insulating layer; Applying the first photoresist pattern as a mask to implant n-type high concentration impurity ions into an active pattern of the pixel region to form a source and a drain region; Acing the first photoresist pattern to form a second photoresist pattern to expose both sides of the gate electrode; Etching both sides of the exposed gate electrode; Implanting n-type low concentration impurity ions into the active pattern of the pixel region using the second photoresist pattern as a mask to form a lightly doped drain (LDD) region; Applying a third photoresist pattern as a mask to implant p-type high concentration impurity ions into an active pattern of the driving circuit region to form a source and a drain region; Forming a pixel electrode on the first insulating layer of the unit pixel; Forming a second insulating layer on the first insulating layer on which the gate electrode, the gate line, the storage line, and the pixel electrode are formed; And forming a storage electrode pattern on the second insulating layer to connect the source and drain electrodes, the data line perpendicular to the gate line, and the storage lines separated from each other in the unit pixel through contact holes. It is characterized by.

The present invention relates to a liquid crystal display device using polysilicon and a method for manufacturing the same, and provides a driving circuit-integrated liquid crystal display device including both an N-type TFT and a P-type TFT, and a method of manufacturing the same.

The unit pixels formed in the pixel region of the present invention are characterized in that the storage lines are separated from each other in the unit pixels. In addition, the separated storage lines are connected to each other by a storage electrode connection pattern formed on the insulating layer with an insulating layer interposed therebetween, and the connecting storage electrode connection patterns serve as one electrode of the storage capacitor. .

Further, the present invention is characterized in that the pixel electrode is formed under the source and drain electrodes, and is formed on the same layer as the gate line, that is, on the first insulating layer.

According to the above structural feature, the present invention defines a pixel region in a unit pixel when forming a photoresist pattern for injecting impurities into a P-type TFT region. In addition, the number of masks may be reduced by forming a pixel electrode in the pixel region through a contact hole filling effect.

Hereinafter, the structure of the liquid crystal display of the present invention will be described with reference to FIGS. 4 and 5a and 5b.

4 is a plan view of a unit pixel in the screen display unit of the present invention, FIG. 5A is a cutaway view of the thin film transistor through the cut line I-I of FIG. 4, and 5b is a cutaway view of the cut line II-II of FIG.

Referring to FIG. 4, a unit pixel formed in the screen display unit of the present invention is defined by a plurality of gate lines 401 and a plurality of data lines 402 perpendicular to the gate lines 401.

A thin film transistor 450 as a switching element is formed in one region of the unit pixel. In addition, a pixel electrode 406 including a transparent electrode is formed in the pixel region.

The thin film transistor 450 includes an active pattern 403 constituting a channel, a gate electrode 401a formed on the active pattern 403 and branching from the gate line 401, and the active pattern 403. ) And a source 402a and a drain electrode 402b connected through the contact holes 411 and 412. The source electrode 402a branches from the data line 402 and is connected to the active pattern by a first contact hole 411 formed on the source region of the active pattern 403, and the drain electrode 402b is active. It is connected to the active pattern 403 through the second contact hole 412 formed on the drain region of the pattern 403. In addition, the drain electrode 402b is connected to the pixel electrode 403 through the third contact hole 413.

On the other hand, a storage line 404 parallel to the gate line 401 is formed in the unit pixel, and the storage line 404 is separated from each other in the unit pixel. In addition, the storage lines 404 are connected to each other by a storage electrode connection pattern 405 with an insulating layer interposed therebetween. Therefore, the storage electrode connection pattern 405 and the pixel electrode 406 and the insulating layer interposed therebetween form a storage capacitor.

The cross-sectional structure of the unit pixel of the present invention will be described in more detail with reference to FIGS. 5A and 5B.

Referring to FIG. 5A, a buffer layer 501, which may be made of silicon nitride or silicon oxide, is formed on a substrate 500 made of glass or the like. An active pattern 403 made of polysilicon is formed on the buffer layer 501. When the active pattern 403 is formed, an active pattern constituting a channel of a switching element formed for each unit pixel and active patterns of a P-type TFT in CMOS in a driving circuit region are formed. The active pattern 403 includes a source and a drain region in which impurity ions are implanted to improve conductivity. The source and drain regions are formed at both edges of the active pattern 403, and a channel is formed therebetween.

A first insulating layer 502 is formed on the active pattern 403 to insulate the active pattern 403. The first insulating layer 502 may be made of silicon nitride or silicon oxide.

A gate electrode 401a made of a conductive material is formed on the first insulating layer 502. A gate line (not shown) and a storage line 404 parallel to the gate line are further formed on the first insulating layer 502.

Referring to FIG. 5B, the storage lines 404 are separated from each other in the unit pixel area.

The gate electrode 401a, the gate line (not shown), and the storage line 404 may be selected from a conductive metal, for example, a double layer of aluminum, aluminum alloy, aluminum and molybdenum, copper, platinum, or the like.

5B, a pixel electrode 406 formed of a transparent electrode material such as ITO or IZO is formed on the first insulating layer 502. The pixel electrode 406 is formed in each unit pixel area, and is formed between the storage lines 404 that are separated from each other.

Therefore, a gate line, a gate electrode 401a branching from the gate line, a storage line 404 separated in a unit pixel, and a pixel electrode 406 are formed on the first insulating layer 502.

A second insulating layer 503 is formed on the gate electrode 401a, the storage line 404, and the pixel electrode 406, so that the gate electrode 401a, the storage line 404, and the pixel electrode 406 are formed. I insulate it.

A data line (not shown), a source electrode 402a and a drain electrode 402b branching from the data line are formed on the second insulating layer 503. In addition, a storage electrode connection pattern 405 is further formed on the second insulating layer 503 to connect the storage lines 404 separated in the unit pixel to each other.

The source electrode 402a is connected to the active pattern 403 by a first contact hole 411 formed on the source region of the active pattern 403, and the drain electrode 402b is connected to the second contact hole ( It is connected to the drain region of the active pattern 403 through 412.

The third contact hole 413 connecting the drain electrode 402b and the pixel electrode 406 is formed on the second insulating layer 503. The drain electrode 402b is connected to the pixel electrode 406 through the third contact hole 413.

Referring to FIG. 5B, a storage electrode connection pattern 405 is formed on the second insulating layer 503 to connect the storage lines 404 separated in the unit pixel. The storage connection pattern 405 connects the storage line 404 through the fourth contact hole 414 and the fifth contact hole 415 formed in the second insulating layer 503. The storage electrode connection pattern 405 and the pixel electrode 406 and the second insulating layer 502 formed therebetween constitute one storage capacitor. The size of the storage connection pattern 405 may be set to a predetermined size according to the capacity of the storage capacitor.

As a result, data lines (not shown), source and drain electrodes 402a, 605, 402b, and 606, and a storage electrode connection pattern 405 are formed on the second insulating layer 503.

The data line (not shown), the source and drain electrodes 402a, 605, 402b and 606, and the storage electrode connection pattern 405 are insulated by the third insulating layer 504.

Hereinafter, a method of manufacturing a liquid crystal display device of the present invention will be described with reference to FIGS. 6A to 6I and 7A to 7C.

In the liquid crystal display device of the present invention, a switching element can be configured by selecting among an N-type TFT or a P-type TFT in the pixel region, and the N-type and P-type TFTs are formed in the driving circuit portion, but the unit pixel is shown in FIGS. 6A to 6I as an example. 4 is shown centering around the cutting line III-III of FIG. 4 and the process of manufacturing the P-type TFT of the drive circuit area.

Referring to FIG. 6A, a buffer layer made of silicon oxide or silicon nitride is formed on a transparent substrate 500 such as glass by plasma chemical vapor deposition (PECVD). The buffer layer 501 is formed to prevent diffusion of impurities and the like included in the substrate 500 when crystallizing the silicon layer constituting the active pattern.

Subsequently, amorphous silicon is deposited on the buffer layer 501. Since the amorphous silicon is not large in electrical mobility, it is not suitable as a driving device and needs to be changed to polysilicon having excellent electrical mobility. Therefore, after depositing the amorphous silicon, the amorphous silicon is crystallized. The crystallization may be performed by a heating method of heating amorphous silicon in a high temperature chamber or an excimer laser crystallization method of irradiating a laser beam of high energy. Subsequently, the crystallized silicon layer is patterned by a photolithography process to form an active pattern 403.

The active pattern forming process may include applying a photoresist on the crystallized silicon layer, exposing a mask including an active pattern, developing the exposed photoresist, and using the developed photoresist pattern as a mask. Applying to etch the crystallized silicon layer.

An active pattern of an N-type TFT and a P-type TFT is formed by the photolithography process.

Subsequently, a first insulating layer 502 covering the active patterns 403 and 601 is formed. The first insulating layer 502 may be formed by depositing silicon nitride or silicon oxide by PECVD.

6B and 7A, a first conductive layer such as a metal is deposited on the first insulating layer 502 by a sputtering method or the like. Subsequently, the first conductive layer is patterned through a photolithography process to form gate lines 401, gate electrodes 401a and 602, and a storage line 404. The gate electrodes 401a and 602 are formed in the N-type TFT and the P-type TFT regions, respectively. In addition, referring to FIG. 7A, the storage lines 404 are parallel to the gate line 401 and separated from each other in a unit pixel.

Referring back to FIG. 6B, after the first conductive layer is etched by the first photoresist pattern 610 to pattern the gate electrodes 401a and 602 and the storage line 404, the first photoresist pattern 610 may be formed. The gate electrodes 401a and 602 and the storage line 404 are applied as a blocking mask to implant n-type high concentration impurity ions into the active pattern. This is to form source and drain regions by doping impurity ions into the active pattern exposed by the gate electrode. The active pattern implanted with the impurity ions may improve conductivity to form ohmic contacts with source and drain electrodes made of a conductive material such as metal.

The implantation of the n-type high concentration impurity is performed in both the N-type TFT and the P-type TFT.

Subsequently, referring to FIG. 6C, the first photoresist pattern 610 is ashed and a portion of the gate electrode is exposed. Subsequently, the exposed gate electrode is further etched to define an LDD region. In FIG. 6C, reference numeral 610a indicates a second photoresist pattern formed by ace the first photoresist pattern 610, and reference numeral 401a indicates a gate electrode 401a etched by the second photoresist pattern 610a.

The second photoresist layer pattern 610a and the gate electrode 401a are applied as a mask, and low concentration n-type impurity ions are implanted to form lightly doped drain (LDD) regions on both sides of the gate electrode. As a result, LDD regions are formed in both sides of the channel in the pixel region, and high concentration impurities are implanted in both sides of the LDD region to form LDD type N-type TFTs having source and drain regions.

6D, a third photosensitive film pattern 620 is formed to expose the P-type TFT region and cover the N-type TFT region of the driving circuit portion.

The third photoresist pattern 620 may further include an intaglio pattern that exposes the pixel area of the unit pixel. That is, the third photoresist pattern 620 defines a region where pixel electrodes formed for each unit pixel are to be formed.

By applying the third photoresist pattern 620 as a mask, a high concentration of P-type impurities are implanted to form source and drain regions in the P-type TFT. The P-type impurity is counter-doped to the active pattern at a higher concentration than the high concentration N-type impurity to form P-type source and drain regions in the active pattern of the P-type TFT region.

Subsequently, a transparent electrode material 406a such as ITO is coated on the third photoresist pattern 620 by sputtering without removing the third photoresist pattern 620. The transparent electrode material 406a is also formed in an intaglio defining a region in which the pixel electrode is to be formed.

Next, referring to FIG. 6F, a photosensitive film is coated on the transparent electrode material to completely fill the intaglio. Subsequently, the photoresist is ashed so that the transparent electrode material in the remaining areas except for the intaglio is exposed. As a result, as shown in FIG. 6G, the fourth photoresist pattern 630a remains only in the intaglio. As described above, a process of forming a pattern in a predetermined intaglio formed by the photosensitive film pattern is called a contact hole filling process. The fourth photoresist pattern 630a is applied as an etch mask to remove the exposed transparent electrode material by wet etching to form the pixel electrode 406. Referring to FIG. 7B, the pixel electrode 406 is connected through a separate storage line 404 to be integrated in a unit pixel.

In the above process, the process of forming the pixel electrode from the process of injecting the impurity into the P-type TFT is performed using only one mask, so that the number of masks can be reduced as compared with the prior art.

Subsequently, the third photoresist pattern 620 and the fourth photoresist pattern 630a are stripped to be completely removed.

As a result, as shown in FIG. 6H, gate electrodes 401a and 602, a storage line 404, and a pixel electrode 406 are formed on the first insulating layer 502.

Next, referring to FIG. 6I, the gate electrodes 401a and 602, the storage line 404, and the second insulating layer 503 covering the pixel electrode 406 are formed by PECVD, and the source of the active pattern and the like. Contact holes 411, 412, 413, 414 and 415 exposing the storage line 404 and the pixel electrode 406 which are separated in the drain region and the unit pixel are formed. The contact hole is formed by a photo mask process.

Subsequently, as illustrated in FIG. 6J, a second conductive layer is formed on the second insulating layer 503, and a photolithography process is performed to cover the source electrodes 402a and 605, the drain electrodes 402b and 606, and the storage. An electrode connection pattern 405 is formed.

The drain electrode 402b of the N-type TFT is connected to the pixel electrode 406 formed on the first insulating layer 502, and the storage electrode connection pattern 405 connects the storage line 404 that is separated. Let's do it.

As a result, the storage electrode pattern 405, the pixel electrode 406, and the second insulating layer 503 interposed therebetween constitute one storage capacitor.

Referring to FIG. 7C, the storage electrode connection pattern 405 connects the storage line 404 within a unit pixel.

Subsequently, the liquid crystal display device of the present invention is completed by covering the storage electrode connection pattern 405 and the source and drain electrodes 402a, 605, 402b and 606 with a third insulating layer.

As described above, in the present invention, in manufacturing a liquid crystal display device including both P-type and N-type TFTs, impurity injection into the P-type TFT with only one mask is performed by simultaneously forming pixel electrodes when forming the P-type TFT. And a pixel electrode can be formed. Therefore, the present invention can reduce productivity by reducing the use of expensive masks and improve productivity by reducing various processes accompanying the mask process.

Claims (10)

A substrate divided into a pixel region and a driving circuit region; An active pattern formed in each of the pixel region and the driving circuit region of the substrate; A first insulating layer formed on the substrate on which the active pattern is formed; A gate line and a gate line formed on the first insulating layer, and storage lines separated from each other in a unit pixel of the pixel area; A pixel electrode formed on the first insulating layer of the unit pixel; A second insulating layer formed on the first insulating layer on which the gate electrode, the gate line, the storage line, and the pixel electrode are formed; And And a storage electrode pattern connecting the source and drain electrodes formed on the second insulating layer, the data lines perpendicular to the gate lines, and the storage lines separated from each other in the unit pixel through contact holes. Display element. The liquid crystal display device of claim 1, wherein the active pattern is made of polysilicon. The liquid crystal display of claim 2, wherein the active pattern of the pixel region includes a lightly doped drain (LDD) region. The storage capacitor of claim 1, wherein the pixel electrode is formed between storage lines separated from each other in the unit pixel, and forms a storage capacitor together with the storage electrode pattern with the second insulating layer interposed therebetween. Liquid crystal display device. Providing a substrate divided into a pixel region and a driving circuit region; Forming an active pattern in each of a pixel area and a driving circuit area of the substrate; Forming a first insulating layer on the active pattern; Applying a first photoresist pattern as a mask to form a gate electrode, a gate line, and a storage line separated from each other in a unit pixel of the pixel area on the first insulating layer; Applying the first photoresist pattern as a mask to implant n-type high concentration impurity ions into an active pattern of the pixel region to form a source and a drain region; Acing the first photoresist pattern to form a second photoresist pattern to expose both sides of the gate electrode; Etching both sides of the exposed gate electrode; Implanting n-type low concentration impurity ions into the active pattern of the pixel region using the second photoresist pattern as a mask to form a lightly doped drain (LDD) region; Applying a third photoresist pattern as a mask to implant p-type high concentration impurity ions into an active pattern of the driving circuit region to form a source and a drain region; Forming a pixel electrode on the first insulating layer of the unit pixel; Forming a second insulating layer on the first insulating layer on which the gate electrode, the gate line, the storage line, and the pixel electrode are formed; And Forming a storage electrode pattern on the second insulating layer to connect the source and drain electrodes, the data lines perpendicular to the gate lines, and the storage lines separated from each other in the unit pixel through contact holes; Characterized in that the liquid crystal display device manufacturing method. The method of claim 5, wherein the third photoresist pattern further comprises an intaglio pattern exposing the first insulating layer of the unit pixel. The method of claim 6, further comprising forming a transparent electrode material on the third photoresist pattern without removing the third photoresist pattern. The method of claim 7, further comprising applying a photoresist film to completely fill the intaglio on the transparent electrode material. The method of claim 8, further comprising acing the photoresist to form a fourth photoresist pattern only on the intaglio, thereby exposing transparent electrode materials in the remaining regions except for the intaglio. . The method of claim 9, wherein the pixel electrode is formed by removing the exposed transparent electrode material by applying the fourth photoresist pattern as an etching mask.

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