JP2000036602A - Thin-film transistor, manufacture of it, and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve operating characteristics and reliability by flattening a semiconductor thin-film which is to be an active layer of a thin-film transistor comprising a bottom gate structure. SOLUTION: Firstly, a substrate 1 comprising an insulating surface layer 2 is prepared. An impurity 4 is injected into the surface layer 2 through a resist 3 to form a buried gate electrode 5. On the substrate 1 where the gate electrode is buried, a gate nitrogen film 6 and a gate oxide film 7 are continuously formed. Further, a semiconductor thin-film 8 is formed over it. An impurity is injected in the semiconductor thin-film 8 through a resist 9 corresponding to the gate electrode 5, so that a source region S and a drain region D are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bottom gate type thin film transistor using a semiconductor thin film such as polycrystalline silicon formed on an insulating substrate as an active layer, and a method of manufacturing the same. More specifically, the present invention relates to a technique for flattening a stacked structure of a gate electrode and a semiconductor thin film.

[0002]

2. Description of the Related Art Thin film transistors are widely used as switching elements in active matrix display devices. In particular, polycrystalline silicon has been conventionally used as a semiconductor thin film serving as an active layer of a thin film transistor.

A polycrystalline silicon thin film transistor can be used not only as a switching element but also as a circuit element, and a peripheral driving circuit can be built on the same substrate together with the switching element. Further, since the polycrystalline silicon thin film transistor can be miniaturized, the area occupied by the switching element in the pixel structure can be reduced, and a high aperture ratio of the pixel can be achieved. By the way, the conventional polycrystalline silicon thin film transistor has a process maximum temperature of 1000 in the manufacturing process.
In this case, quartz glass or the like having a temperature of about ° C and having excellent heat resistance has been used as an insulating substrate. It has been difficult to use a glass substrate having a relatively low melting point due to the manufacturing process. However, in order to reduce the cost of the display device, the use of a low-melting glass material is indispensable. Therefore, in recent years, the development of a so-called low-temperature process in which the maximum process temperature is 600 ° C. or lower has been promoted. In particular, the low-temperature process is extremely advantageous in terms of cost when manufacturing a large display device.

Thin film transistors are roughly classified into a top gate type in which a gate electrode is formed on a semiconductor thin film via a gate insulating film, and a bottom gate type in which a gate electrode is provided below the semiconductor thin film via a gate insulating film. Can be In the case of the low-temperature process, the bottom gate structure is considered promising from the viewpoint of reliability, and FIG. 8 schematically shows the structure. As shown, a gate electrode 5 is patterned on a substrate 1 made of glass or the like. A semiconductor thin film 8 made of polycrystalline silicon or the like is formed on the gate electrode 5 with a gate insulating film 7 interposed therebetween. Impurities are selectively implanted into the semiconductor thin film 8 to form a source region S and a drain region D. The semiconductor thin film 8 is covered with an interlayer insulating film 10. A wiring electrode 11 is formed on the interlayer insulating film 10 by patterning, and is electrically connected to a source region S and a drain region D via a contact hole. The wiring electrode 11 is covered with a passivation film 12.

[0005]

As is apparent from FIG. 8, a conventional bottom gate type thin film transistor has a gate electrode 5 formed so as to protrude from the surface of the substrate 1. Therefore, the gate insulating film 7 is formed on the gate electrode 5.
A step 8a is generated in the semiconductor thin film 8 overlapping with the step. The step 8a causes a local decrease in the thickness of the semiconductor thin film 8 and also concentrates stress. This has resulted in disconnection of the semiconductor thin film 8 and deterioration of the operation characteristics of the thin film transistor. In particular, in the portion of the step 8a, the grain size of the polycrystalline silicon varies, causing the mobility of the thin film transistor to decrease.

[0006]

The following means have been taken in order to solve the above-mentioned problems of the prior art. That is, the thin film transistor according to the present invention comprises a substrate having an insulating surface layer, a buried gate electrode obtained by selectively lowering the resistance of the surface layer along a predetermined pattern, and a gate electrode. It comprises a gate insulating film formed on the buried substrate and a flat semiconductor thin film formed on the gate insulating film. Preferably, the gate electrode is a region provided with conductivity by selectively introducing impurities into the surface layer along a predetermined pattern. Also preferably, the surface layer is made of a semiconductor previously formed on the substrate. In some cases, a back gate electrode is formed on the semiconductor thin film via an insulating film at a position below and facing the gate electrode.

The present invention includes a method for manufacturing a thin film transistor. According to the present invention, a thin film transistor is manufactured by the following steps. First, in a first step, a substrate having an insulating surface layer is prepared. In a second step, an impurity is introduced into the surface layer through a predetermined mask to form a buried gate electrode. In a third step, a gate insulating film is formed on the substrate in which the gate electrode is embedded. In a fourth step, a semiconductor thin film is formed on the gate insulating film. Finally, in a fifth step, impurities are implanted into the semiconductor thin film via a mask corresponding to the gate electrode to form a source region and a drain region. Preferably, in the second step, an impurity is implanted into a surface layer made of a semiconductor previously formed on the substrate to form a buried gate electrode. Alternatively, in the second step, an impurity is implanted into a surface layer of the substrate itself made of glass to form a buried gate electrode. Preferably, in the fifth step, an impurity is implanted into the semiconductor thin film through the mask formed in alignment with the gate electrode by exposure processing from the back surface of the substrate to form a source region and a drain region. .

[0008] The present invention further includes a display device. As a basic configuration, the present display device has a pair of substrates joined to each other via a predetermined gap and an electro-optical material held in the gap, and a counter electrode is formed on one of the transparent substrates. In addition, a pixel electrode and a thin film transistor for driving the pixel electrode are formed on the other insulating substrate. As a characteristic feature, the thin film transistor has a buried gate electrode obtained by selectively reducing the resistance of a surface layer of the insulating substrate along a predetermined pattern, and a thin film transistor on the insulating substrate in which the gate electrode is buried. It comprises a gate insulating film formed and a flat semiconductor thin film formed on the gate insulating film.

According to the present invention, in a thin film transistor having a bottom gate structure in which a gate electrode is arranged between a substrate and a semiconductor thin film, for example, an embedded gate electrode is formed by injecting impurities into a surface layer of the substrate. . Thereby, the active layer of the semiconductor thin film following the source region / channel region / drain region can be made flat without any step.
For this reason, the step of the semiconductor thin film which has conventionally occurred at the end of the gate electrode can be removed. Breakage of strength of the semiconductor thin film due to disconnection or film stress, which has conventionally occurred at the stepped portion, can be eliminated, leading to higher reliability of the thin film transistor. In particular, the flattening of the active layer of the semiconductor thin film improves the transistor operating characteristics including carrier mobility and on-state current.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a process chart showing a first embodiment of a thin film transistor according to the present invention. In the present specification, each embodiment will be described using a process chart. First, the substrate 1 is prepared in the step (a). When an active matrix type display device is manufactured, a substrate 1 made of a transparent material such as glass, quartz glass, or quartz is prepared. However, the present invention is not limited to this, and a high-resistance silicon wafer may be used for the substrate 1. In the present embodiment, glass is prepared as the substrate 1. In this embodiment, an N-channel type bottom gate thin film transistor is formed on a substrate 1 made of glass. Needless to say, a P-channel thin film transistor can also be integrated. As shown, after preparing a substrate 1 having an insulating surface layer 2, an impurity 4 is introduced into the surface layer 2 through a predetermined mask formed of a resist 3 to form a buried type gate electrode 5. I do. In other words, the resistance of the surface layer 2 is selectively reduced along a predetermined pattern so that the buried type gate electrode 5 is formed.
Is provided. Specifically, after the resist 3 is patterned according to the shape of the gate electrode by photolithography, impurities such as P, As, and B are ion-doped or ion-implanted to 1 × 10 ¹⁴ / cm.
A dose of about ² or more is injected into the surface layer 2. Here, the surface layer 2 is a surface portion of the substrate 1 itself made of glass.

In step (b), a gate insulating film is formed on the substrate 1 in which the gate electrode 5 is embedded. here,
A two-layer structure of a gate nitride film 6 and a gate oxide film 7 was formed as a gate insulating film. Specifically, S by plasma CVD
iN _x was deposited to a thickness of 100 nm to form a gate nitride film 6, and similarly, SiO ₂ was deposited to a thickness of 100 nm by a plasma CVD method to form a gate oxide film 7. Subsequently, a semiconductor thin film 8 is continuously formed on the gate oxide film 7. Here, a semiconductor thin film 8 made of amorphous silicon was formed to a thickness of 50 nm by a plasma CVD method. As is apparent from the figure, since the gate electrode 5 is embedded in the substrate 1, the semiconductor thin film 8 is in a flat state. The flat semiconductor thin film 8 is irradiated with laser light using an excimer laser light source to convert amorphous silicon to polycrystalline silicon. That is, the amorphous silicon is once melted by the irradiation of the laser beam, and is crystallized in the cooling process to be converted into polycrystalline silicon. In the semiconductor thin film 8 which has been flattened as compared with the conventional semiconductor thin film including a step, heat is uniformly cooled, so that the grain size of the polycrystalline silicon becomes uniform, and the operation characteristics of the thin film transistor are improved. In addition, breakage of the semiconductor thin film at the stepped portion due to laser beam irradiation, which has conventionally been a problem, is eliminated. As described above, the laser light irradiation generates heat in the semiconductor thin film 8 to such an extent that the amorphous silicon is melted, and the residual heat is transmitted to the substrate 1 via the gate insulating film. The impurity implanted earlier is simultaneously activated by the conducted residual heat, and the gate electrode 5 is actually reduced in resistance.
An excimer laser light source such as KrF or XeCl is used for laser light irradiation. The energy density is set between 150 and 600 mJ / cm ² .

In step (c), a resist 9 is patterned on the semiconductor thin film 8 so as to face the gate electrode 5 by photolithography. Using the resist 9 as a mask, impurities such as P and As are implanted into the semiconductor thin film 8 to form a source region S and a drain region D. As a result, a channel region is provided immediately below the resist 9 and between the source region S and the drain region D. Thereafter, the laser light is again irradiated to activate the impurities injected into the semiconductor thin film 8.
At this time, the energy density of the laser light is set to be smaller than the energy density of the laser light used when converting the amorphous to the polycrystalline.

Finally, proceeding to step (d), after removing the used resist 9, a SiO 2 is formed on the semiconductor thin film 8.
₂ is formed to a thickness of, for example, 300 nm, and the interlayer insulating film 10 is formed.
And A contact hole communicating with the source region S and the drain region D is opened in the interlayer insulating film 10. A metal such as Al, Mo, W, and Ti is formed on the interlayer insulating film 10, patterned into a predetermined shape, and processed into the wiring electrode 11. SiN _x is applied to cover the wiring electrode 11.
The passivation film 12 is formed with a thickness of 00 nm. Thus, a bottom-gate thin film transistor is completed.

FIG. 2 is a manufacturing process diagram showing a second embodiment of the thin film transistor according to the present invention. Basically, Figure 1
Are similar to those of the first embodiment, and the corresponding parts are denoted by the corresponding reference numerals to allow understanding. A different point is that a semiconductor made of non-single-crystal silicon is formed in advance on a substrate 1 made of glass or the like to form a surface layer 2a. Non-single-crystal silicon is a concept including amorphous silicon or polycrystalline silicon. As shown in (a), a pattern of a resist 3 extracted in a gate shape is formed on a surface layer 2a made of non-single-crystal silicon. Using the resist 3 as a mask, impurities such as P, As, and B are ion-doped or ion-implanted to 1 ×.
The gate electrode 5 is implanted at a dose of 10 ¹⁴ / cm ² or more.
Is provided. Subsequent steps (b), (c) and (d)
Are the same as steps (b), (c) and (d) shown in FIG.

FIG. 3 is a manufacturing process diagram showing a third embodiment of the thin film transistor according to the present invention. Basically, it is the same as the second embodiment shown in FIG. 2, and the corresponding parts are denoted by the corresponding reference numerals, and the understanding is permitted. First, a surface layer 2a made of non-single-crystal silicon is formed on a substrate 1 as shown in FIG. Here, the surface layer 2a made of polycrystalline silicon was formed by a plasma CVD method or a low pressure CVD method at a process temperature of 400 ° C. or more.
Polycrystalline silicon is optically transparent. The resist 3 extracted in the shape of a gate is patterned on the surface layer 2a.
An impurity 4 such as As or B is implanted at a dose of 1 × 10 ¹⁴ / cm ² or more by ion doping or ion implantation. Thus, the gate electrode 5 is manufactured in a state of being embedded in the substrate 1. Proceeding to step (b), SiN _x and SiO ₂ are sequentially formed, and the gate oxide film 6 is formed.
And a gate nitride film 7. SiN _x film thickness is 100
nm, and the thickness of SiO ₂ is 100 nm. Further, a semiconductor thin film 8 serving as an active layer is formed. Here, 50
Polycrystalline silicon was deposited to a thickness of nm. For example, 40
Plasma CVD or LPCV at process temperature of 0 ° C or higher
D was used to form an optically transparent polycrystalline silicon film having a thickness of 50 nm. Proceeding to step (c), resist 9
Is applied over the entire surface. And a substrate 1 made of glass or the like.
By exposing from the back surface of the thin film transistor, a pattern that leaves the resist 9 only in a portion to be a channel region of the thin film transistor can be formed by self-alignment. That is, since only the gate electrode 5 into which the impurity is implanted becomes opaque, only the portion of the resist 9 that matches the gate electrode 5 becomes unexposed by backside exposure, and is left on the semiconductor thin film 8 in a later development process. become. Using the remaining resist 9 as a mask, impurities such as P and As are implanted to form a source region S and a drain region D by self-alignment. Here, in order to simultaneously increase the crystal grains of the polycrystalline silicon constituting the semiconductor thin film 8 and activate the impurities injected into the semiconductor thin film 8, a laser beam is irradiated. Here, Kr
The energy density was set to 150 to 550 mJ / cm ² using an excimer laser light source such as F or XeCl.
By the laser beam irradiation, the impurities contained in the gate electrode 5 embedded in the surface layer 2a are also activated at the same time. Finally, the process proceeds to step (d), where SiO _{2 is formed} to a thickness of 300 nm to form an interlayer insulating film 10. After opening a contact hole in the interlayer insulating film 10, Al, Mo,
A metal such as W or Ti is formed into a film and patterned into a predetermined shape to form a wiring electrode 11. Further, a 200 nm-thick SiN _x film is formed so as to cover the wiring electrode 11, and a passivation film 12 is provided.

FIG. 4 is a process chart showing a fourth embodiment of the thin film transistor according to the present invention. Basically, it is the same as the third embodiment shown in FIG. 3, and the corresponding parts are denoted by the corresponding reference numerals to allow understanding. Step (a)
Then, polycrystalline silicon is formed as a surface layer 2a on a substrate 1 made of glass or the like. A resist 3 extracted in a gate shape is patterned thereon, and impurities 4 such as P, As, and B are implanted at a dose of 1 × 10 ¹⁴ / cm ² or more by ion doping or ion implantation.
A gate electrode 5 is provided. Proceeding to step (b), SiN _x and SiO ₂ are each formed to a thickness of 100 nm, and a gate nitride film 6 and a gate oxide film 7 are provided. Further, a semiconductor thin film 8 made of amorphous silicon is formed with a thickness of 50 nm. Here, amorphous silicon is converted to polycrystalline silicon by irradiating a laser beam. This makes the semiconductor thin film 8 optically transparent. However, the irradiation energy of the laser beam needs to be set to a level at which the impurity implanted into the gate electrode 5 is not activated at this time. Therefore, at this time, the gate electrode 5 is optically opaque. An excimer laser beam such as KrF or XeCl is used as a laser light source, and has an energy density of 150 to 500 mJ / cm ^2.
Set to. Proceeding to step (c), a resist 9 is applied on the semiconductor thin film 8 and exposed from the back surface, so that the resist 9 can be left only in the channel region. Resist 9
Is used as a mask to implant an impurity such as P or As, and a source region S and a drain region D are provided by self-alignment. Further, annealing is performed by irradiating a laser beam to activate the impurities implanted in the source region S and the drain region D. At this time, the irradiation conditions of the laser beam are appropriately set so that the impurities implanted in the gate electrode 5 are also activated. Thereafter, the process proceeds to step (d), and after removing the unnecessary resist 9, SiO _{2 is formed} to a thickness of 300 nm to form an interlayer insulating film 10. After opening a contact hole in the interlayer insulating film 10, a wiring electrode 11 is provided. A passivation film 12 is provided so as to cover the wiring electrodes 11.

FIG. 5 is a process chart showing a fifth embodiment of the thin film transistor according to the present invention. Basically, it is the same as the third embodiment shown in FIG. 3, and the corresponding parts are denoted by the corresponding reference numerals to allow understanding. Step (a)
Then, a surface layer 2a made of polycrystalline silicon is provided on a substrate 1 made of glass or the like. A resist 3 extracted in a gate shape is patterned thereon, and impurities 4 are implanted to provide a buried gate electrode 5. In step (b), a gate nitride film 6, a gate oxide film 7, and a semiconductor thin film 8 are continuously formed on the surface layer 2a. The semiconductor thin film 8 is made of optically transparent polycrystalline silicon. Proceeding to step (c), a SiO ₂ film is formed on the semiconductor thin film 8. By applying a resist thereon and exposing it from the back surface, the resist is left only in a portion to be a channel region. By etching the previously formed SiO ₂ using this resist as a mask, a channel stopper film 9 a matching the gate electrode 5 and the channel region is provided. Impurities are implanted using the channel stopper film 9a as a mask to form the source region S and the drain region D by self-alignment. Here, a laser beam is applied to increase the grain size of the polycrystalline silicon of the semiconductor thin film 8 and activate the impurities implanted in the source region S and the drain region D. Again, an excimer laser light source is used and the energy density is 150 to 550 mJ / c.
m ² , and the semiconductor thin film 8 is irradiated. At this time, the impurities implanted in the gate electrode 5 are also activated at the same time. Finally, the process proceeds to step (d), where SiO _{2 is formed} to a thickness of 300 nm to form an interlayer insulating film 10. After opening a contact hole in the interlayer insulating film 10, a wiring electrode 11 is manufactured. Further, a passivation film 12 is provided thereon.

FIG. 6 is a manufacturing process diagram showing a sixth embodiment of the thin film transistor according to the present invention. Basically, Figure 2
Are similar to those of the second embodiment described above, and the corresponding parts are denoted by the corresponding reference numerals and are understood. The difference is that in step (d), after forming a contact hole in the interlayer insulating film 10 and then forming the wiring electrode 11 connected to the source region S and the drain region D, the back gate electrode 15 is formed at the same time. That is. That is, in the present embodiment, the back gate electrode 15 is formed on the semiconductor thin film 8 via the interlayer insulating film 10 at a position facing the lower gate electrode 5, and has a so-called dual gate structure.

Finally, an example of an active matrix type display device using the thin film transistors according to the first to sixth embodiments will be described with reference to FIG. As shown in the drawing, the display device has a pair of insulating substrates 101 and 102.
And a electro-optical substance 103 held between them. As the electro-optical material 103, for example, a liquid crystal material is used. On the lower insulating substrate 101, a pixel array section 104 and a drive circuit section are integrally formed.
The drive circuit section includes a vertical drive circuit 105 and a horizontal drive circuit 106
And divided into Further, a terminal portion 107 for external connection is formed at an upper end of a peripheral portion of the insulating substrate 101. The terminal portion 107 is connected to a vertical drive circuit 105 and a horizontal drive circuit 106 via a wiring 108. Pixel array unit 10
4 includes a row-shaped gate wiring 109 and a column-shaped signal wiring 110.
Are formed. The pixel electrode 111 is located at the intersection of both wirings.
And a thin film transistor 112 for driving the same. The gate electrode of the thin film transistor 112 is connected to the corresponding gate wiring 109, the drain region is connected to the corresponding pixel electrode 111, and the source region is connected to the corresponding signal wiring 110. The gate wiring 109 is connected to the vertical driving circuit 105, while the signal wiring 110 is connected to the horizontal driving circuit 106. The thin film transistor 112 for switching and driving the pixel electrode 111 and the thin film transistors included in the vertical drive circuit 105 and the horizontal drive circuit 106 have a bottom gate structure having an embedded gate electrode according to the present invention.

[0020]

As described above, according to the present invention,
In a bottom gate thin film transistor having a gate electrode at least on a substrate side of a channel region, an impurity is implanted into a surface layer of the substrate to form a gate electrode, thereby activating a semiconductor thin film following a source region / channel region / drain region. The layer can be made flat without any steps.
As a result, the breakage of the film at the step portion of the semiconductor thin film serving as the active layer, which has conventionally occurred at the gate end face, is eliminated, and it is possible to prevent the strength from decreasing due to the film stress, thereby improving the reliability of the transistor. Also, because the active layer was flattened,
The operating characteristics of the transistor including carrier mobility and on-state current are improved. Furthermore, in a bottom gate structure having a gate electrode at least on the substrate side of the channel, the gate electrode is buried, so that the semiconductor thin film formed thereon can be crystallized by laser light irradiation. The diffusion of heat into the semiconductor thin film is reduced, and the crystallization of the semiconductor thin film can be made uniform. In addition, since the semiconductor thin film is flattened, laser light can be uniformly irradiated, so that crystallization uniformity can be improved. Furthermore, unevenness on the substrate surface of the bottom gate structure, which has conventionally been a problem, can be reduced, and the uniformity of the screen can be improved, for example, when applied to an active matrix type display device.

[Brief description of the drawings]

FIG. 1 is a process chart showing a first embodiment of a thin film transistor according to the present invention.

FIG. 2 is a process chart showing a second embodiment.

FIG. 3 is a process chart showing a third embodiment.

FIG. 4 is a process drawing showing a fourth embodiment in the same manner.

FIG. 5 is a process chart showing a fifth embodiment.

FIG. 6 is a process chart showing a sixth embodiment.

FIG. 7 is a perspective view showing an example of an active matrix type display device which is an application example of the present invention.

FIG. 8 is a cross-sectional view illustrating an example of a conventional thin film transistor having a bottom gate structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Surface layer 3 Resist 4 Impurity 5 Gate electrode 6 Gate nitride film 7 Gate oxide film 8 Semiconductor thin film 9 Resist 10 Interlayer insulating film 11 Electrode 12 Passivation film

Claims (9)

[Claims] A substrate having an insulating surface layer; a buried gate electrode obtained by selectively lowering the resistance of the surface layer along a predetermined pattern; and a substrate having the gate electrode embedded therein. A thin film transistor comprising: a gate insulating film formed on the gate insulating film; and a flat semiconductor thin film formed on the gate insulating film. 2. The thin film transistor according to claim 1, wherein the gate electrode is a region provided with conductivity by selectively introducing impurities into the surface layer along a predetermined pattern. 3. The thin film transistor according to claim 1, wherein the surface layer is formed of a semiconductor formed on the substrate in advance. 4. The thin film transistor according to claim 1, wherein a back gate electrode is formed on the semiconductor thin film via an insulating film, at a position below and facing the gate electrode. 5. A first step of preparing a substrate having an insulating surface layer, a second step of introducing an impurity into the surface layer through a predetermined mask to form a buried gate electrode, A third step of forming a gate insulating film on the substrate in which the gate electrode is embedded, a fourth step of forming a semiconductor thin film on the gate insulating film, and a mask corresponding to the gate electrode. Forming a source region and a drain region by injecting impurities into the semiconductor thin film. 6. The method of manufacturing a thin film transistor according to claim 5, wherein in the second step, an impurity is implanted into a surface layer made of a semiconductor previously formed on the substrate to form an embedded gate electrode. 7. The method of manufacturing a thin film transistor according to claim 5, wherein in the second step, an impurity is implanted into a surface layer of the substrate itself made of glass to form a buried gate electrode. 8. The fifth step includes forming a source region and a drain region by injecting impurities into the semiconductor thin film through the mask formed in alignment with the gate electrode by exposure processing from the back surface of the substrate. A method for manufacturing a thin film transistor according to claim 5. 9. A semiconductor device comprising: a pair of substrates joined to each other via a predetermined gap; and an electro-optical material held in the gap;
A display device in which a counter electrode is formed on one transparent substrate, and a pixel electrode and a thin film transistor for driving the pixel electrode are formed on the other insulating substrate, wherein the thin film transistor is formed on a surface of the insulating substrate along a predetermined pattern. A buried gate electrode obtained by selectively reducing the resistance of a layer, a gate insulating film formed on the insulating substrate in which the gate electrode is buried, and a gate insulating film formed on the gate insulating film. A display device comprising a flat semiconductor thin film.