KR101123513B1 - TFT and fabrication method thereof - Google Patents

Abstract

Thin film transistor according to an embodiment of the present invention,

A substrate; A buffer layer formed on the substrate; An active layer formed in a predetermined pattern by depositing a silicon layer on the buffer layer; A first insulating film deposited on the active layer; A gate electrode formed on the first insulating layer and formed by patterning the gate electrode; A second insulating film deposited on the substrate on which the gate electrode is formed; A source-drain electrode having a molybdenum (Mo) / aluminum neodium (AlNd) / molybdenum (Mo) stacked structure formed on the second insulating film; A protective film deposited on the resultant; And a pixel electrode deposited on the passivation layer.

Description

Thin film transistor and its manufacturing method {TFT and fabrication method approximately}

1 is a view schematically illustrating a pixel area provided in a general liquid crystal display array substrate.

FIG. 2 is a cross-sectional view taken along line II ′ of the polysilicon thin film transistor of FIG. 1. FIG.

3A and 3B are cross-sectional and front views of a polysilicon thin film transistor according to an embodiment of the present invention.

4A and 4B are cross-sectional and front views of a polysilicon thin film transistor according to another embodiment of the present invention.

5A to 5F are cross-sectional views illustrating a process of manufacturing a polysilicon thin film transistor according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

303, 303 ': active layer 305: gate electrode

307: source electrode 308: drain electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor provided in a liquid crystal display device or an organic EL, and more particularly, to a top gate polysilicon thin film transistor and a manufacturing method thereof.

In general, a liquid crystal display device is provided with a first substrate (thin film transistor substrate) and a second substrate (color filter substrate) facing each other at a predetermined interval. The liquid crystal display device will be described in more detail. In the first substrate (thin film transistor substrate), gate lines and data lines are formed on the inner surface of one transparent substrate in a matrix.

A TFT (Thin Film Transistor) is formed at the intersection of the gate line and the data line, respectively, and functions as a switching element. A square pixel electrode contacting the drain electrode of the TFT is formed by the gate line and the data line. It is formed in each area.

The other second substrate (color filter substrate) facing the transparent substrate on which the plurality of pixel electrodes is formed has a BM (Black Matrix (BM)), a color filter layer and a common electrode formed on an inner surface of the transparent substrate.

When one gate line and one data line of the liquid crystal display device configured as described above are selected and a voltage is applied, only a thin film transistor (TFT) to which the voltage is applied is turned on, and the on Charges are accumulated in the pixel electrode connected to the drain electrode of the formed TFT to change the arrangement of the liquid crystal molecules between the common electrode.

On the other hand, the first substrate (thin film transistor substrate) generally has a bottom gate type of an amorphous silicon TFT and a top gate type of a polysilicon TFT.

In addition, the polysilicon TFT is divided into a low temperature process and a high temperature process according to the process temperature. The high temperature process uses a quartz substrate with a process temperature of around 1000 ° C, the crystallization uses solid phase crystallization, and injects silicon ions before crystallization to improve electrical characteristics.

The low temperature process uses a glass substrate, the process temperature is 450 ℃ or less, and the crystal is exposed to the laser light.

The polysilicon TFT has a larger on and off current than the amorphous silicon TFT.

1 is a view schematically illustrating a pixel area provided in a general liquid crystal display array substrate.

As shown in the drawing, the gate line 101 and the data line 102 cross each other, and a thin film transistor and a pixel electrode are provided at each intersection. In addition, the thin film transistor uses a portion of the gate line 101 as a gate electrode and a portion of the data line 102 as a source electrode and a drain electrode.

FIG. 2 is a cross-sectional view taken along line II ′ of the polysilicon thin film transistor of FIG. 1.

As shown therein, the substrate 201; A buffer layer 202 formed on the substrate 201; An active layer 203 formed in a predetermined pattern by depositing a silicon layer on the buffer layer 202; A first insulating film 204 deposited on the active layer 203; A gate electrode 205 formed on the first insulating film 204 and formed by patterning; A second insulating film 206 deposited on a substrate on which the gate electrode 205 is formed; Source-drain electrodes (207, 208) formed on said second insulating film (206); A protective film 209 deposited on the resultant; The pixel electrode 210 is deposited on the passivation layer 209. Here, the active layer 203 is made of polysilicon, and the source-drain electrode is made of aluminum (Al) or aluminum alloy (AlNd).

In the related art, as the liquid crystal display described above is narrowed, the size of the channel region of the active layer of the thin film transistor is also reduced.

However, to reduce the size of the active layer or to reduce the contact area between the active layer and the source / drain electrodes in order to implement a narrow bezel, depletion occurs in the active layer, that is, the active channel in the vicinity of the source / drain electrode. Field emission of electron-electron pairs easily occurs due to the many traps present in the grain boundaries and grain boundaries of the polysilicon in the region. Accordingly, the image quality of the liquid crystal panel is degraded due to a very large leakage current, and when the device is driven for a long time, the weak bond between silicon atoms is broken, or hydrogen is separated from the dangling bond bond of the silicon atom that is bonded with hydrogen, thereby causing the electrical There is a problem of deterioration of characteristics.

That is, in the conventional polysilicon thin film transistor, abnormal device characteristics such as light leakage occur in the active region from the source / drain contact portion to the gate electrode, which is caused by diffusion of aluminum (Al) constituting the source / drain electrode. Is estimated to be due to

In more detail, since the silicon atoms near the grain boundaries of the polysilicon are weakly bound, such silicon can easily diffuse into aluminum at a temperature of 350 ° C. or more, and the so-called aluminum fills the voids of the silicon thus formed. It is assumed that the abnormal device characteristics are caused by aluminum diffusion.

In the top gate type polysilicon thin film transistor, the active region from the source / drain contact portion to the gate electrode is formed by forming a source / drain electrode in a stacked structure of Mo / AlNd / Mo and narrowing the bezel of the liquid crystal display device. An object of the present invention is to provide a thin film transistor and a method of manufacturing the same, which overcomes abnormal device characteristics generated in the semiconductor device.

In order to achieve the above object, a thin film transistor according to an embodiment of the present invention,

A substrate; A buffer layer formed on the substrate; An active layer formed in a predetermined pattern by depositing a silicon layer on the buffer layer; A first insulating film deposited on the active layer; A gate electrode formed on the first insulating layer and formed by patterning the gate electrode; A second insulating film deposited on the substrate on which the gate electrode is formed; A source-drain electrode having a molybdenum (Mo) / aluminum neodium (AlNd) / molybdenum (Mo) stacked structure formed on the second insulating film; A protective film deposited on the resultant; And a pixel electrode deposited on the passivation layer.

The active layer may be formed of polysilicon, and the source-drain electrode may contact the active layer exposed under the contact hole through a contact hole formed at a predetermined position of the second insulating layer.

In addition, the active layer is formed to have a width including the contact hole region, so that the source-drain electrode is in front contact with the active layer in the region where the contact hole is formed or includes a portion of the contact hole region. The width of the source and drain electrodes may be partially in contact with the active layer in a region where the contact hole is formed.

In addition, the thickness of the lower molybdenum metal in contact with the active layer of the metal constituting the source-drain electrode is characterized in that the 100 ~ 300Å.

In addition, the method of manufacturing a thin film transistor according to the present invention comprises the steps of forming a buffer layer on a substrate; Forming an active layer of a predetermined pattern in the buffer layer; Forming a first insulating film on the active layer; Forming a gate electrode in a predetermined region on the first insulating film; Forming a second insulating film on the substrate on which the gate electrode is formed; Forming a source-drain electrode having a molybdenum (Mo) / aluminum neodium (AlNd) / molybdenum (Mo) stacked structure on the second insulating film; Forming a protective film on the resultant product; And forming a pixel electrode on the passivation layer.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

3A and 3B are cross-sectional views and a front view of a polysilicon thin film transistor according to an embodiment of the present invention.

The present invention relates to a thin film transistor which is provided as a switching element in each pixel of an active matrix liquid crystal display device or an organic light emitting display device (organic EL). In particular, the present invention relates to a top gate polysilicon thin film transistor. By forming a source / drain electrode constituting the polysilicon thin film transistor in a stacked structure of Mo / AlNd / Mo, abnormal device characteristics such as light leaking near a contact point between the source / drain electrode and the active layer are prevented. It is characterized by the prevention.

That is, the lower metal of the source / drain electrode in contact with the active layer is formed of molybdenum (Mo) instead of aluminum or aluminum alloy to prevent diffusion of aluminum (Al) generated in a conventional polysilicon thin film transistor. It is possible to overcome abnormal device characteristics due to.

Referring to Figure 3 describes the structure of a polysilicon thin film transistor according to an embodiment of the present invention.

As shown in FIG. 3A, this includes a substrate 301; A buffer layer (302) formed on the substrate (301); An active layer 303 formed by depositing a silicon layer on the buffer layer 302 in a predetermined pattern; A first insulating film 304 deposited on the active layer 303; A gate electrode 305 formed on the first insulating film 304 and patterned; A second insulating film 306 deposited on a substrate on which the gate electrode 205 is formed; Source-drain electrodes 307 and 308 having a Mo / AlNd / Mo stacked structure formed on the second insulating film 306; A protective film 309 deposited on the resultant; The pixel electrode 310 is deposited on the passivation layer 309.

Here, the source-drain electrodes 307 and 308 are in contact with the active layer 303 exposed under the contact hole through a contact hole formed at a predetermined position of the second insulating layer 306.

As shown in FIG. 3B, the active layer 303 of the thin film transistor according to the embodiment of the present invention is formed to include the contact hole 311, so that the source-drain electrodes 307 and 308 are the active layer. 303 and front contact with the contact hole 311 is formed.

The embodiment of the present invention shown in FIG. 3 does not form the source-drain electrodes 307 and 308 in a single metal or a double layered structure, but instead of molybdenum (Mo) / aluminum neodium (AlNd) / molybdenum (Mo). It is characterized by forming in a triple laminated structure.

Here, the lower molybdenum among the metals constituting the source-drain electrodes 307 and 308 is provided to overcome abnormal device characteristics due to metal diffusion generated in the conventional thin film transistor, and serves as a barrier metal. Its thickness is 100Å ~ 300Å.

When the thickness of molybdenum as the protective metal is 100 kPa or less, the device characteristics are unstable, and when the thickness of the molybdenum is 300 kPa or more, there is a possibility that the overhang and the device characteristics may be affected during the source-drain metal etching, and the thickness thereof is preferably 100 kPa to 300 kPa, In particular, the most preferable device characteristic is 200 kHz.

According to the present invention, a conventional polysilicon thin film transistor is formed by forming the lower layer metal of the source / drain electrodes 307 and 308 in contact with the active layer 303 with molybdenum (Mo) instead of aluminum or aluminum alloy. It is possible to overcome the light leakage caused by the diffusion (diffusion) of aluminum (Al) generated in.

4A and 4B are cross-sectional views and a front view of a polysilicon thin film transistor according to another embodiment of the present invention.

However, this feature is characterized in that the size of the active layer 303 ′, that is, the active channel size, is narrow when compared with the polysilicon thin film transistor according to the embodiment of the present invention described with reference to FIG. 3.

Therefore, the same reference numerals are used for the same components as in FIG. 3, and a detailed description thereof will be omitted.

As shown in Fig. 4A, this includes a substrate 301; A buffer layer (302) formed on the substrate (301); An active layer 303 'formed by depositing a silicon layer on the buffer layer 302 in a predetermined pattern; A first insulating film 304 deposited on the active layer 303 '; A gate electrode 305 formed on the first insulating film 304 and patterned; A second insulating film 306 deposited on a substrate on which the gate electrode 305 is formed; Source-drain electrodes 307 and 308 having a Mo / AlNd / Mo stacked structure formed on the second insulating film 306; A protective film 309 deposited on the resultant; The pixel electrode 310 is deposited on the passivation layer 309.

Here, the source-drain electrodes 307 and 308 come into contact with the active layer 303 ′ exposed under the contact hole through a contact hole formed at a predetermined position of the second insulating layer 306. Unlike the example, only a part of the active layer 303 'is contacted.

That is, as shown in FIG. 4B, the active layer 303 ′ of the thin film transistor according to the embodiment of the present invention is formed to include only a part of the contact hole 311, so that the source-drain electrodes 307 and 308 are formed. Is partially in contact with the active layer 303 'in the region where the contact hole 311 is formed. That is, the source-drain electrodes 307 and 308 and the active layer 303 'form side contacts.

The embodiment shown in FIG. 4 does not form the source-drain electrodes 307 and 308 in a single metal or double stack structure, but triple stacks of molybdenum (Mo) / aluminum neodium (AlNd) / molybdenum (Mo). By forming the structure, even when the active layer 303 'and the source-drain electrodes 307 and 308 are in side contact, normal device characteristics can be exhibited.

As a result, by reducing the contact size between the source-drain electrodes 307 and 308 and the active layer 303 ', the area of the thin film transistor can be greatly reduced, and by reducing the active size, the liquid crystal display device or the organic EL The narrow bezel of display devices using the same thin film transistor can be realized.

Here, the lower molybdenum among the metals constituting the source-drain electrode is provided to overcome abnormal device characteristics due to metal diffusion generated in the conventional thin film transistor, and serves as a barrier metal, and has a thickness of 100 μs. It is characterized by being ~ 300Å.

When the thickness of molybdenum as the protective metal is 100 kPa or less, the device characteristics are unstable, and when the thickness of the molybdenum is 300 kPa or more, there is a possibility that the overhang and the device characteristics may be affected during the source-drain metal etching, and the thickness thereof is preferably 100 kPa to 300 kPa, In particular, the most preferable device characteristic is 200 kHz.

5A to 5F are cross-sectional views illustrating a process of manufacturing a polysilicon thin film transistor according to an embodiment of the present invention.

First, as shown in FIG. 5A, silicon oxide and amorphous silicon are sequentially deposited on the entire surface of the substrate 301 to form a buffer layer 302 and an amorphous silicon layer, and annealing using an excimer laser (ExcimerLaser) on the amorphous silicon layer ( Annealing) is performed to crystallize the polysilicon layer 303.

Thereafter, as shown in FIG. 5B, the crystallized polysilicon layer 303 is patterned to form an active layer 303, and silicon nitride (SiNx) or silicon oxide is formed on the entire surface including the active layer 303. An inorganic insulating film such as (SiOx) is deposited to form a first insulating film 304.

In this case, the active layer 303 is in contact with the source-drain electrode later to serve as a channel. In the present invention, as shown in FIG. 4B, the source-drain electrode is connected to an end of the active layer. It can also be patterned by reducing its size to achieve side contact.

Next, as illustrated in FIG. 5C, a conductive material is deposited on the entire surface including the first insulating layer 304 and patterned by a photolithography method using a mask on a predetermined portion of the upper portion of the active layer 303. The gate electrode 305 is formed.

As illustrated in FIG. 5D, an inorganic insulating film is deposited on the entire surface including the gate electrode 305 to form a second insulating film 306.

Subsequently, as shown in FIG. 5E, the second insulating layer 306 and the first insulating layer 304 are selectively removed using a predetermined mask to form a contact hole so that a predetermined portion of the source / drain region is exposed. do.

In more detail, after the second insulating film 306 and the first insulating film 304 are selectively removed to form contact holes, impurities are added to the active layer 303 using the gate electrode 305 as a mask. Ion implantation forms a source / drain region.

At this time, an active layer masked by the gate electrode 305 and not implanted with ions becomes a channel region.

Then, molybdenum (Mo) / aluminum neodium (AlNd) / molybdenum (Mo) metal is sequentially deposited on the second insulating layer 306 through the contact hole, and patterned by a photolithography method using a predetermined mask. A source electrode 307 and a drain electrode 308 connected to the source / drain region are formed through the contact hole.

That is, in the present invention, the source-drain electrode is not formed as a single metal or a double stacked structure, but is formed as a triple stacked structure of molybdenum (Mo) / aluminum neodium (AlNd) / molybdenum (Mo). The lower molybdenum among the metals constituting the source-drain electrode is provided to overcome abnormal device characteristics due to the metal diffusion generated in the conventional thin film transistor, and serves as a barrier metal, and has a thickness of 100 μs to 300 μs. It features.

When the thickness of molybdenum as the protective metal is 100 kPa or less, the device characteristics are unstable, and when the thickness of the molybdenum is 300 kPa or more, there is a possibility that the overhang and the device characteristics may be affected during the source-drain metal etching, and the thickness thereof is preferably 100 kPa to 300 kPa, In particular, the most preferable device characteristic is 200 kHz.

According to the present invention, the lower layer metal of the source / drain electrode in contact with the active layer is composed of molybdenum (Mo) instead of aluminum or aluminum alloy of the conventional aluminum (Al) generated in the polysilicon thin film transistor. It is possible to overcome abnormal device characteristics due to diffusion.

In addition, the source-drain electrode and the active layer contacted by the contact hole may be contacted through the contact hole forming region as shown in the figure, but as described above with reference to FIG. Source-drain electrodes and the active layer may be in side contact.

Finally, as shown in FIG. 5F, after the passivation layer 309 is deposited on the formed source-drain electrodes 307 and 308, a contact hole in the drain electrode region is formed using a mask.

The pixel electrode 310 is deposited on the resultant and then patterned.

According to the present invention, it is possible to overcome the metal diffusion generated in the active region of the thin film transistor, to suppress the occurrence of defects, and to reduce the contact size of the source / drain electrodes and the active layer, thereby reducing the area of the thin film transistor. There is an advantage that can be greatly reduced.

In addition, by reducing the active size, there is an advantage that a narrow bezel of a display device employing a thin film transistor such as a liquid crystal display device or an organic EL can be realized.

Claims (12)

A substrate; A buffer layer formed on the substrate; An active layer formed in a pattern by depositing a silicon layer on the buffer layer; A first insulating film deposited on the active layer; A gate electrode formed on the first insulating layer and formed by patterning the gate electrode; A second insulating film deposited on the substrate on which the gate electrode is formed; A source-drain electrode having a molybdenum (Mo) / aluminum neodium (AlNd) / molybdenum (Mo) stacked structure formed on the second insulating film; A protective film deposited on the source-drain electrode; A pixel electrode deposited on the passivation layer; The source electrode and the drain electrode each contact the both sides of the active layer through the contact hole formed in the second insulating film and the first insulating film. The method of claim 1, The active layer is a thin film transistor, characterized in that formed of polysilicon. delete delete delete The method of claim 1, A thin film transistor, characterized in that the thickness of the lower molybdenum metal in contact with the active layer of the metal constituting the source-drain electrode is 100 ~ 300Å. Forming a buffer layer on the substrate; Forming an active layer on the buffer layer; Forming a first insulating film on the active layer; Forming a gate electrode on a portion of the first insulating layer; Forming a second insulating film on the substrate on which the gate electrode is formed; Forming a source-drain electrode having a molybdenum (Mo) / aluminum neodium (AlNd) / molybdenum (Mo) stacked structure on the second insulating film; Forming a protective film on the source-drain electrode; Forming a pixel electrode on the passivation layer; And the source electrode and the drain electrode are in contact with both sides of the active layer through contact holes formed in the second insulating film and the first insulating film. The method of claim 7, wherein The active layer is a thin film transistor manufacturing method, characterized in that formed of polysilicon. delete delete delete The method of claim 7, wherein The thickness of the lower molybdenum metal in contact with the active layer of the metal constituting the source-drain electrode is 100 Å ~ 300 Å a thin film transistor manufacturing method.

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