KR20090059843A - Organic lighting emitting diode display device and method for fabricating of the same - Google Patents

Abstract

An organic electroluminescent display device and a manufacturing method thereof are provided to prevent breaking of a film by preventing an electric field concentration between a second electrode and a polysilicon layer pattern of a second region, between a gate electrode and a polysilicon layer pattern of a first region. A substrate(200) includes a first region(A) and a second region(B). Semiconductor layer patterns(220,223) are formed in the first region and the second region. A first gate insulation film(230) is formed on a whole surface of the substrate. A second gate insulation film pattern(231a,231b) is formed on the first gate insulation film. The second gate insulation film pattern is formed on an edge part of the semiconductor layer pattern of the second region, an edge part and a channel region of the semiconductor layer pattern of the first region. A conductive layer pattern is formed on the channel region of the first region and the semiconductor layer pattern of the second region. An interlayer insulation film(240) is formed on a whole surface of the substrate. A source electrode(251) and a drain electrode(252) are connected to the semiconductor layer pattern of the first region through the first gate insulation film and the interlayer insulation film of the first region.

Description

Organic Light Emitting Diode Display Device and Method for Fabricating of the same}

The present invention relates to an organic light emitting display device and a method of manufacturing the same, and more specifically, between the polysilicon layer pattern 120 of the first region A and the gate electrode 134 of the first region A. By preventing the concentration of an electric field between the polysilicon layer pattern 124 of the second region B and the second electrode 136 of the second region B, it is possible to prevent the film from bursting and to stabilize the insulating characteristics. The present invention relates to an organic light emitting display device and a method of manufacturing the same.

In general, a flat panel display device such as an active matrix organic light emitting display device includes a thin film transistor and a capacitor, each of which unit pixels are basically connected to a gate line, a data line, and a power supply line, and an organic light emitting display device. The capacitor is formed with a plurality of conductive layers to form gate lines and gate electrodes, data lines, source / drain electrodes, power supply layers, and anode electrodes. The conductive layer is electrically connected by forming a contact hole after forming a contact hole in the insulating layer formed between the conductive layers.

1 is a plan view of a conventional organic light emitting display device.

Referring to FIG. 1, a conventional active matrix organic light emitting display device includes a plurality of gate lines 310, a plurality of data lines 320 and a plurality of power supply lines 330, and the gate lines 310 and data lines. And a plurality of pixels connected to the 320 and the power supply line 330.

Each pixel includes a switching thin film transistor 370 connected to a corresponding one of a plurality of gate lines 310 and a corresponding one of a plurality of data lines 320, and the power supply line. A thin film transistor 350 for driving the organic EL device 360 connected to the 330, a capacitor 340, an organic EL device for maintaining the voltage between the gate and the source of the driving thin film transistor 350, and the like. Is done.

The driving thin film transistor 350 includes a semiconductor layer 352 having a source / drain region, a gate electrode 354, and a source / drain electrode connected to the source / drain region through contact holes 355a and 355b, respectively. 356a and 356b, the switch thin film transistor 370 also has the same structure.

The capacitor 340 is one of source / drain electrodes of the switch thin film transistor 370, for example, a lower electrode 344 connected to a source electrode and a gate of the driving thin film transistor 350, and the driving One of the source / drain electrodes of the thin film transistor 350, for example, a source electrode 356a and an upper electrode 146 connected to the common power line 330, is provided. The pixel electrodes 360 and 361, which are anode electrodes of the EL device having the opening 365, are one of the source / drain electrodes 356a and 356b of the driving thin film transistor 350 through the via hole 358, for example. For example, it is connected to the drain electrode 356b.

2 is a cross-sectional view illustrating an organic light emitting display device according to the related art.

First, a silicon oxide is deposited on a front surface of the transparent insulating substrate 100 divided into the first region A and the second region B by a plasma-enhanced chemical vapor deposition (PECVD) method. Buffer layer 110 is formed. In this case, the buffer layer 110 prevents the diffusion of impurities in the transparent insulating substrate 100 during the crystallization process of the amorphous silicon layer formed in a subsequent process.

Next, an amorphous silicon layer (not shown) having a predetermined thickness is deposited on the buffer layer 110. Subsequently, the amorphous silicon layer is crystallized using Excimer Laser Annealing (ELA), Sequential Lateral Solidification (SLS), Metal Induced Crystallization (MIC), or Metal Induced Lateral Crystallization (MILC), and patterned by photolithography. The polysilicon layer patterns 120 and 124 are formed in the first region A and the second region B in the pixel.

Next, a first gate insulating layer 130 is formed on the entire surface. In this case, the first gate insulating layer 130 is formed to a thickness of 400 to 1000 Å using a silicon oxide film (SiO 2).

Next, a second gate insulating film (not shown) is formed on the first gate insulating film 130. The second gate insulating film is formed to a thickness of 200 to 800 Å using a silicon nitride film (SiNx) or a silicon oxynitride film.

Next, a photoresist pattern (not shown) is formed on the second gate insulating layer to protect a portion of the gate electrode and a channel region of the transistor. The second gate insulating layer is etched using the photoresist pattern as an etching mask to form a second gate insulating layer pattern 131.

 In addition, by using the photoresist pattern as an ion implantation mask, impurities are implanted into the polysilicon layer pattern 120 to form source / drain regions 121 and 122 in the first region A, and the second region ( In B), a first electrode 124 used as a lower electrode of the capacitor is formed. Thereafter, the photosensitive film pattern is removed.

Next, a single layer of an alloy such as molybdenum (Mo) or molybdenum tungsten (MoW), aluminum (Al), or aluminum-neodymium (Al-Nd) on the transparent insulating substrate on which the second gate insulating film pattern 131 is formed. A metal layer for a gate electrode (not shown) is formed by a single layer of an aluminum alloy such as or a double layer of the above-mentioned metals. Subsequently, the gate electrode metal layer is etched by the photolithography process to form the gate electrode 134 in the first region A, and the second electrode 136 used as the upper electrode of the capacitor in the second region B. ). In this case, the first gate insulating layer 130 interposed between the first electrode 124 and the second electrode 136 is used as a dielectric film of the capacitor.

Next, an interlayer insulating film 140 of a predetermined thickness is formed on the entire surface. Here, the interlayer insulating film 140 is formed to a thickness of about 3000 to 5000 kPa using a silicon oxide film, a silicon nitride film or a stacked structure of a silicon oxide film and a silicon nitride film.

Next, the interlayer insulating layer 140 and the first gate insulating layer 130 are etched by a photolithography process to form contact holes (not shown) that expose the source / drain regions 122.

Next, an electrode material is formed on the entire surface including the contact hole, and the electrode material is etched by a photolithography process so that the source / drain is connected to the source / drain area 122 in the first area A. FIG. Electrodes 151 and 152 are formed. In this case, the electrode material may be a single layer of an alloy such as molybdenum (Mo) or molybdenum tungsten (MoW), or a single layer of an aluminum alloy such as aluminum (Al) or aluminum-neodymium (Al-Nd), or the metal mentioned above. Bilayers of these may be used.

Thereafter, the protective film 160 is formed of an inorganic insulating film such as a silicon nitride film having a predetermined thickness on the entire surface.

Although not shown in the drawings, a via hole (not shown) exposing any one of the source / drain electrodes 151 and 152, for example, a part of the drain electrode 152 by performing a manufacturing process of a general flat panel display device. Next, a lower electrode (not shown) electrically connected to the drain electrode 152 is formed. Subsequently, a pixel definition layer (not shown) is formed on the lower electrode (not shown), a via hole for exposing the pixel region of the lower electrode (not shown) is formed, and an organic functional layer (not shown) is formed thereon. ) And an upper electrode (not shown) to form an organic light emitting display device.

In the organic light emitting display having the above structure, the first electrode 124, the first gate insulating layer 130, and the second electrode 136 are used as capacitors.

However, since the capacitor uses only the first gate insulating film as the dielectric film due to the characteristics of the capacitor in which the capacitance value increases in inverse proportion to the thickness of the dielectric film, the capacitance value of the capacitor uses the first gate insulating film and the second gate insulating film. The thickness of the first region A may be increased due to the thin thickness of the first gate insulation layer at the edges of the polysilicon layer patterns 120 and 124 by removing the second gate insulation layer as described above. Between the polysilicon layer pattern 120 and the gate electrode 134 of the first region A, the first electrode 124 of the second region B and the second electrode 136 of the second region B There is a problem that the first gate insulating film bursts due to the concentration of the electric field.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems of the prior art, and between the polysilicon layer pattern 120 of the first region A and the gate electrode 134 of the first region A without further processing. To prevent an electric field from concentrating between the polysilicon layer pattern 124 of the second region B and the second electrode 136 of the second region B, thereby preventing the film from bursting and stabilizing insulation characteristics. An object of the present invention is to provide an organic light emitting display device and a method of manufacturing the same.

In order to achieve the above object, the present invention provides a substrate comprising a first region and a second region; A semiconductor layer pattern provided in each of the first region and the second region of the substrate; A first gate insulating film provided on an entire surface of the substrate including the semiconductor layer pattern; A second gate insulating layer pattern formed on the first gate insulating layer and provided on the channel region and the edge portion of the semiconductor layer pattern in the first region and on the edge portion of the semiconductor layer pattern in the second region. ; A conductive layer pattern provided on the channel region of the first region and the semiconductor layer pattern of the second region, respectively; An interlayer insulating film provided on the entire surface of the substrate on which the conductive layer pattern is formed; And a source / drain electrode connected to the semiconductor layer pattern of the first region through the interlayer insulating layer and the first gate insulating layer of the first region.

In addition, the present invention provides a substrate including a first region and a second region, the semiconductor layer pattern is formed in each of the first region and the second region of the upper substrate, the front surface of the substrate on which the semiconductor layer pattern is formed A first gate insulating film is formed, a second gate insulating film is formed on the entire surface of the first gate insulating film, and is formed on the second gate insulating film, and the channel region and the edge portion of the semiconductor layer pattern of the first region are protected. Forming a photoresist pattern and a photoresist pattern protecting the edge portion of the semiconductor layer pattern of the second region, and etching the second gate insulation layer using the photoresist pattern as a mask to form a second gate insulation layer pattern, and the photoresist pattern After the removal, the conductive layer pattern is formed on the channel region of the semiconductor layer pattern of the first region and the semiconductor layer pattern of the second region, respectively, and the conductive layer pattern is provided. An interlayer insulating layer is formed on the entire surface of the substrate, and a contact hole is formed to expose the semiconductor layer pattern of the first region by etching the interlayer insulating layer of the first region and the first gate insulating layer of the first region; A method of manufacturing an organic light emitting display device includes forming a source / drain electrode connected to a semiconductor layer pattern of a first region through a hole.

The present invention also provides an organic electroluminescent display device wherein the semiconductor layer pattern of the first region is a channel region and a source / drain region of a thin film transistor, and the semiconductor layer pattern of the second region is a lower electrode of a capacitor. It provides a method for producing the same.

The present invention also provides an organic light emitting display device and a method of manufacturing the same, wherein the conductive layer pattern of the first region is a gate electrode, and the conductive layer pattern of the second region is an upper electrode of a capacitor.

According to the embodiment of the present invention as described above, the capacitor of the present invention is composed of the first electrode 223, the first gate insulating film 230 and the second electrode 235, the capacitor is a first gate insulating film Since only the dielectric film is used, the capacitance value of the capacitor can still be increased than using the first gate insulating film and the second gate insulating film.

The second gate insulating film pattern may be formed in the edge portion region of the polysilicon layer pattern 120 of the first region A and the edge portion region of the polysilicon layer pattern of the second region B. Between the polysilicon layer pattern of the first region A and the gate electrode 134 of the first region A, the polysilicon layer pattern 124 of the second region B and the second region B Condensation of the electric field between the two electrodes 136 may be prevented to prevent the film from bursting.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

3A to 3D are cross-sectional views illustrating a forming procedure of the organic light emitting display device according to the present invention.

Referring to FIG. 3A, first, plasma-enhanced chemical vapor deposition of silicon oxide on the front surface of a transparent insulating substrate 200 divided into a first region A and a second region B, PECVD) to form a buffer film 210 of a predetermined thickness. In this case, the buffer layer 210 prevents the diffusion of impurities in the transparent insulating substrate 200 during the crystallization process of the amorphous silicon layer formed in a subsequent process.

Next, an amorphous silicon layer (not shown), which is a semiconductor layer, is deposited on the buffer layer 210 by a predetermined thickness. Subsequently, the amorphous silicon layer is crystallized using Excimer Laser Annealing (ELA), Sequential Lateral Solidification (SLS), Metal Induced Crystallization (MIC), or Metal Induced Lateral Crystallization (MILC), and patterned by photolithography. Polysilicon layer patterns 220 and 223, which are semiconductor layer patterns, are formed in the first region A and the second region B in the pixel.

Next, a first gate insulating film 230 is formed over the entire surface. In this case, the first gate insulating film 230 is formed to have a thickness of 400 to 1000 GPa using a silicon oxide film (SiO 2), preferably about 800 GPa using a silicon oxide film (SiO 2).

Next, a second gate insulating film 231 is formed over the entire surface. The second gate insulating film 231 is formed to have a thickness of 200 to 800 kW using a silicon nitride film (SiNx) or a silicon oxynitride film, preferably about 400 kW using a silicon nitride film (SiNx).

Next, a photoresist pattern 232 is formed on the second gate insulating film to protect portions of the channel region and the edge portion of the semiconductor layer pattern of the first region and the portion of the semiconductor layer pattern of the second region. ).

Next, referring to FIG. 3B, the second gate insulating film is etched using the photoresist pattern as an etching mask to form second gate insulating film patterns 231a and 231b. Accordingly, the second gate insulating film pattern is formed only in the channel region 231a and the edge region 231b of the semiconductor layer pattern of the first region and the edge region 231b of the semiconductor layer pattern of the second region. .

Next, an impurity is ion-implanted into the polysilicon layer patterns 220 and 223 by using the photoresist pattern 232 as an ion implantation mask to be used as the source / drain regions 221 and 222 and a lower electrode of the capacitor. One electrode 223 is formed. In this case, the ion implantation process is performed using n + or p + impurities as a dopant. When the thin film transistor is a CMOS thin film transistor, it is advantageous that n + impurities are implanted into the first electrode 223.

Thereafter, the photoresist pattern 232 is removed.

Next, referring to FIG. 3C, an alloy such as molybdenum (Mo) or molybdenum-tungsten (MoW) is formed as a first conductive layer on the transparent insulating substrate 200 on which the second gate insulating film patterns 231a and 231b are formed. A single layer, a single layer of an aluminum alloy such as aluminum (Al) or aluminum-neodymium (Al-Nd), or a metal layer (not shown) for a double layer gate electrode of the above-mentioned metals is formed. Subsequently, the first conductive layer pattern is formed by etching the gate electrode metal layer by a photolithography process, wherein the gate electrode 234 is formed in the first region A, and the upper portion of the capacitor is formed in the second region B. A second electrode 235 used as an electrode is formed. In the first region A, the first gate insulating layer 230 and the second gate insulating layer patterns 231a and 231b are used as the gate insulating layer and are 600 to 1800 Å thick. In the second region B, the first gate insulating film 230 is used as the dielectric film of the capacitor, and is formed to have a thickness of 400 to 1000 mW, preferably about 800 mW.

Therefore, the capacitor formed as described above is composed of the first electrode 223, the first gate insulating film 230, and the second electrode 235, and the capacitance of the capacitor increases in inverse proportion to the thickness of the dielectric film. In view of the characteristics, since the capacitor uses only the first gate insulating film as the dielectric film, the capacitance value of the capacitor can still be increased than using the first gate insulating film and the second gate insulating film.

The second gate insulating film pattern may be formed in the edge portion region of the polysilicon layer pattern 120 of the first region A and the edge portion region of the polysilicon layer pattern of the second region B. Between the polysilicon layer pattern of the first region A and the gate electrode 134 of the first region A, the polysilicon layer pattern 124 of the second region B and the second region B Condensation of the electric field between the two electrodes 136 may be prevented to prevent the film from bursting. In this case, the first gate insulating layer 231 and the second gate insulating layer pattern 234 are used as gate insulating layers in the edge region of the polysilicon layer patterns of the first region A and the second region B.

Next, referring to FIG. 3D, an interlayer insulating film 240 having a predetermined thickness is formed on the entire surface.

Next, the interlayer insulating layer 240 and the first gate insulating layer 232 are etched by a photolithography process to form contact holes (not shown) that expose the source / drain regions 221 and 222.

Next, an electrode material is formed on the entire surface including the contact hole as a second conductive layer, and the electrode material is etched by a photolithography process so that the source / drain regions 221 and 222 are formed on the first area A. FIG. Source / drain electrodes 251 and 252 are formed. In this case, the electrode material may be a single layer of an alloy such as molybdenum (Mo) or molybdenum tungsten (MoW), or a single layer of an aluminum alloy such as aluminum (Al) or aluminum-neodymium (Al-Nd), or the metal mentioned above. Bilayers of these may be used.

Thereafter, a protective film 260 is formed over the entire surface of an inorganic insulating film such as a silicon nitride film having a predetermined thickness.

Although not shown in the drawings, a via hole (not shown) exposing any one of the source / drain electrodes 151 and 152, for example, a part of the drain electrode 152 by performing a manufacturing process of a general flat panel display device. Next, a lower electrode (not shown) electrically connected to the drain electrode 152 is formed. Subsequently, a pixel defining layer (not shown) is formed on the lower electrode (not shown), a via hole for exposing the pixel region of the lower electrode (not shown) is formed, and an organic layer (not shown) is formed thereon. And an upper electrode (not shown) to form an organic light emitting display device.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the present invention. .

1 is a plan view of a conventional organic light emitting display device.

2 is a cross-sectional view of an organic light emitting display device according to the prior art.

3A to 3D are cross-sectional views illustrating a forming procedure of the organic light emitting display device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

200: transparent insulating substrate 210: buffer layer

220, 223 polysilicon layer pattern 230: first gate insulating film

231: second gate insulating film 232: photosensitive film pattern

231a and 231b Second gate insulating film patterns 221 and 222 Source / drain regions

223: first electrode 234: gate electrode

235: second electrode 240: interlayer insulating film

251, 252: source / drain electrodes 260: protective film

Claims (13)

A substrate including a first region and a second region; A semiconductor layer pattern provided in each of the first region and the second region of the substrate; A first gate insulating film provided on an entire surface of the substrate including the semiconductor layer pattern; A second gate insulating layer pattern formed on the first gate insulating layer and provided on the channel region and the edge portion of the semiconductor layer pattern in the first region and on the edge portion of the semiconductor layer pattern in the second region. ; A conductive layer pattern provided on the channel region of the first region and the semiconductor layer pattern of the second region, respectively; An interlayer insulating film provided on the entire surface of the substrate on which the conductive layer pattern is formed; And And a source / drain electrode connected to the semiconductor layer pattern of the first region through the interlayer insulating layer and the first gate insulating layer of the first region. The method of claim 1, And the semiconductor layer pattern is a polysilicon layer pattern. The method of claim 1, The semiconductor layer pattern of the first region is a channel region and a source / drain region of the thin film transistor. The method of claim 1, And the semiconductor layer pattern of the second region is a lower electrode of the capacitor. The method of claim 1, The first gate insulating film is a silicon oxide film. The method according to claim 1 or 5, The thickness of the first gate insulating film is 400 to 1000 Å, the organic light emitting display device. The method of claim 1, The second gate insulating layer pattern is formed of a silicon nitride film or a silicon oxynitride film. The method according to claim 1 or 7, The thickness of the second gate insulating film pattern is 200 to 800 GHz, the organic light emitting display device. The method of claim 1, The conductive layer pattern of the first region is a gate electrode. The method of claim 1, The conductive layer pattern of the second region is an upper electrode of the capacitor. The method of claim 4, wherein The organic light emitting display device of claim 2, wherein the semiconductor layer pattern of the second region is doped with impurities. Providing a substrate including a first region and a second region, Forming a semiconductor layer pattern on the first region and the second region on the substrate, Forming a first gate insulating film on an entire surface of the substrate on which the semiconductor layer pattern is formed, Forming a second gate insulating film on the entire surface of the first gate insulating film, Forming a photoresist pattern on the second gate insulating layer, the photoresist pattern protecting the channel region and the edge of the semiconductor layer pattern of the first region, and the photoresist pattern protecting the edge of the semiconductor layer pattern of the second region; The second gate insulating layer is etched using the photoresist pattern as a mask to form a second gate insulating layer pattern, After removing the photoresist pattern, a conductive layer pattern is formed on the channel region of the semiconductor layer pattern of the first region and the semiconductor layer pattern of the second region, respectively, An interlayer insulating film is formed on the entire surface of the transparent insulating substrate including the conductive layer pattern, Forming a contact hole exposing the semiconductor layer pattern of the first region by etching the interlayer insulating layer of the first region and the first gate insulating layer of the first region, And forming a source / drain electrode connected to the semiconductor layer pattern of the first region through the contact hole. The method of claim 9, And implanting impurities into the semiconductor layer pattern by using the photoresist pattern as an ion implantation mask to form a source / drain region in the first region and to form a first electrode in the second region. A method of manufacturing an organic light emitting display device.

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