KR100811997B1 - Thin film transistor and fabrication method thereof and flat panel display including thereof - Google Patents

Abstract

A thin film transistor, a method for manufacturing the same, and a flat panel display including the same are provided to form a lightly doped drain structure in a junction part between an active region and source/drain regions by using a sidewall effect. A semiconductor layer(13) includes an active region, source/drain regions, and a lightly doped region. A gate insulating layer(14) and a gate electrode(15) are overlapped on the active region. A first interlayer dielectric(16) is formed on the source/drain regions and the gate electrode. A second interlayer dielectric(17) is formed on the first interlayer dielectric and includes a contact hole for exposing a part of the source/drain regions. Source/drain electrodes(18,19) are connected through the contact hole to the source/drain regions. The amount of the first interlayer dielectric deposited on a sidewall of the gate insulating layer is larger than the amount of the first interlayer dielectric deposited on the source/drain regions.

Description

Thin film transistor and its manufacturing method and flat panel display device including same {Thin Film Transistor and fabrication method

Figure 1a to 1f is a cross-sectional view showing a conventional thin film transistor manufacturing process.

2A to 2G are cross-sectional views illustrating a process of manufacturing a thin film transistor according to an embodiment of the present invention.

3 is a schematic plan view of a flat panel display device including a thin film transistor according to an embodiment of the present invention.

4 is a cross-sectional view taken along the line AA ′ of FIG. 3.

FIG. 5 is a circuit diagram illustrating an embodiment of one pixel of FIG. 3. FIG.

6A and 6B illustrate a portable electronic device including a thin film transistor according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

13 semiconductor layer 14 gate insulating film

15 gate electrode 16 first interlayer insulating film

17: second interlayer insulating film 18: source electrode

19: drain electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a flat panel display device including the same, and more particularly, to a thin film transistor, a method for manufacturing the same, and a flat panel display device including the same, which implement an LDD structure.

Thin Film Transistors (TFTs) generally comprise a semiconductor layer, a gate electrode and a source / drain electrode, where the semiconductor layer comprises a source / drain regions and a channel region interposed between the source / drain regions. Equipped. Meanwhile, the semiconductor layer may be formed of polysilicon (Poly Silicon, Poly-Si) or amorphous silicon (a-Si), but the electron mobility of the polycrystalline silicon is higher than that of amorphous silicon. Mainly applied.

In general, when a poly-Si TFT is fabricated on a glass substrate, crystallization of an a-Si thin film and dopant activation of a source / drain are performed by using an excimer laser or the like so that the glass substrate is not damaged by a high temperature process.

1A to 1F are cross-sectional views illustrating a conventional thin film transistor manufacturing process.

First, as shown in FIG. 1A, a buffer layer 22 made of silicon oxide is formed on a substrate 21, and an amorphous silicon layer is formed on the buffer layer 22.

Subsequently, the amorphous silicon layer is irradiated with energy such as a laser to polycrystallize to form the polycrystalline silicon layer 23.

Next, as shown in FIG. 1B, a buffer oxide layer 24 is formed on the polycrystalline silicon layer 23, and channel ions n for controlling a threshold voltage are formed on the entire surface of the insulating substrate 21. Or p-type impurity ions).

Next, as shown in FIG. 1C, the oxide layer 24 is removed, and the polycrystalline silicon layer 23 is selectively removed through a photo and etching process to form an island-shaped active layer 25.

Here, since the oxide film 24 causes device deterioration when a gate insulating film is used due to damage during channel ion implantation, the oxide film 24 is removed. In this case, when the oxide film 24 is removed, damage is applied to the polycrystalline silicon layer 23 to lower the reliability of the device.

In addition, since the gate insulating film is formed through a separate process after the oxide film 24 is removed, the process is complicated.

Next, as shown in FIG. 1D, a gate insulating layer 26 is formed on the entire surface of the substrate 21 including the active layer 25, a metal layer is formed on the gate insulating layer 26, and then selectively removed. The electrode 27 is formed.

Subsequently, source / drain impurity ions are implanted into the entire surface using the gate electrode 27 as a mask to form a source / drain region 28 in the active layer 25 on both sides of the gate electrode 27. In other words,

Next, as shown in FIG. 1E, an interlayer dielectric (ILD) 29 is formed on the entire surface of the substrate 21 including the gate electrode 27, and the surface of the source / drain region 28 is formed. The interlayer insulating layer 29 and the gate insulating layer 26 are selectively removed to expose the predetermined portion to form the contact hole 30.

Finally, as shown in FIG. 1F, a thin film transistor is deposited on the entire surface of the insulating substrate 21 including the contact hole 30, and the source / drain electrodes 31 are formed through photo and etching processes. The manufacturing process of is completed.

However, the conventional thin film transistor and its manufacturing process have the following problems.

First, after forming the buffer oxide film on the polycrystalline silicon layer, the channel ion is implanted, the buffer oxide film is removed, and the gate insulating film is formed again.

Second, crystal defects remain in the junction between the active region and the source / drain region, and such junction defects act as traps of electrons and holes in the on state of the TFT, thereby degrading the current driving capability of the TFT. In addition, it is easy to generate additional traps, which causes deterioration of the TFT characteristics due to long-term operation.

According to the present invention, a lightly doped region is formed at a junction between an active region and a source / drain region by using a side-wall phenomenon generated during interlayer dielectrics (ILD) formation. In other words, by implementing a lightly doped drain (LDD) structure, to provide a thin film transistor, a method of manufacturing the same and a flat panel display device including the same that can heal the junction defects occurring in the junction between the active region and the source / drain region without additional processes There is a purpose.

In order to achieve the above object, a thin film transistor manufacturing method according to an embodiment of the present invention, the step of depositing an amorphous silicon (a-Si) layer on the substrate; Crystallizing the amorphous silicon layer; Etching the crystallized silicon (Poly-Si) layer to pattern an active region, and sequentially forming a gate insulating layer and a gate electrode on the patterned crystallized silicon layer; Etching the gate electrode and the gate insulating layer to expose a source / drain region of the crystalline silicon layer; Forming a first interlayer insulating film on the gate electrode and the source / drain region; Implanting impurity ions onto the first interlayer insulating layer to cause the source / drain region to be amorphous, and to form a low concentration impurity region of the crystallized silicon (poly-Si) layer corresponding to the sidewall region of the gate electrode and the gate insulating layer Wow; Recrystallizing the silicon thin film of the amorphous source / drain region and electrically injecting the dopant; A second interlayer insulating layer covering the gate electrode and the source / drain region and having a contact hole for exposing a portion of the source / drain region is formed, and a source / drain respectively connected to the source / drain region through the contact hole; And a step of forming a drain electrode.

In addition, a thin film transistor according to an embodiment of the present invention, the substrate; A semiconductor layer comprising an active region, a source / drain region, and a low concentration impurity region; A gate insulating film and a gate electrode formed to overlap the active region; A first interlayer insulating film formed on the source / drain regions and the gate electrode; A second interlayer insulating layer formed on the first interlayer insulating layer and having a contact hole for exposing a portion of the source / drain region; A source / drain electrode connected to the source / drain region through the contact hole, respectively, wherein the first interlayer insulating layer is formed by the height difference between the height of the gate electrode and the gate insulating layer and the source / drain region. A larger amount is deposited on the sidewalls of the insulating film.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2G are cross-sectional views illustrating a process of manufacturing a thin film transistor according to an embodiment of the present invention.

First, as shown in FIG. 2A, plasma enhanced chemical vapor deposition (hereinafter referred to as PECVD) or low pressure chemical vapor deposition (hereinafter referred to as LPCVD) is used on the substrate 11. A-Si thin film 12 is deposited. At this time, the thickness of the a-Si thin film 12 is between 10 nm and 200 nm.

In addition, a buffer layer (not shown) may be formed on the entire surface of the substrate 11 before the a-Si thin film 12 is deposited, and the buffer layer is formed in a subsequent process from impurities flowing out of the substrate. The layer for protecting the transistor may be formed of a silicon oxide film or a silicon nitride film.

In addition, since a large amount of hydrogen is contained in the a-Si thin film deposited using the PECVD, hydrogen is removed by performing a heat treatment at a temperature of 400 ° C. or higher after deposition.

Subsequently, as illustrated in FIG. 2B, the a-Si thin film 12 is determined using Excimer Laser Annealing (ELA), Sequential Lateral Solidification (SLS), or Metal Induced Lateral Crystallization (MILC).

However, in the exemplary embodiment of the present invention, crystallization of the a-Si thin film 12 into the poly-Si thin film 13 by irradiating excimer laser light will be described as an example.

In other words, the a-Si thin film 12 is crystallized to form a poly-Si semiconductor layer 13.

Next, the active region of the TFT is patterned by etching the poly-Si semiconductor layer 13 using a general photo-lithography process and an etching process in FIG. 2C. Subsequently, a silicon oxide film is deposited as the gate insulating film 14 on the poly-Si semiconductor layer 13, a metal is deposited as the gate electrode 15, and then a photo-resist film formed using a photolithography process. Using a pattern (not shown) as a mask, the lower gate electrode 15 and the gate insulating layer 14 are sequentially etched to expose a surface of the poly-Si semiconductor layer 13 in a source / drain region to be formed later. do.

At this time, the metal as the gate electrode 15 is preferably formed of one metal selected from the group consisting of aluminum (Al), aluminum alloy (Al alloy), molybdenum (Mo) and molybdenum alloy (Mo alloy). .

Next, as shown in FIG. 2D, a first interlayer insulating layer (ILD) 16 is formed on the gate electrode 15 formed on the substrate and the source / drain regions of the exposed semiconductor layer.

At this time, the first interlayer insulating film 16 is formed by depositing SiO2 or SiNx, the thickness is characterized in that 200 ~ 2000 ~.

When the first interlayer insulating layer 16 having the thickness is deposited on the gate electrode 15 and the exposed source / drain regions, the height of the gate electrode 15 and the gate insulating layer 14 and the source / drain regions, that is, the semiconductor layer As shown by the difference between the heights of 13, a phenomenon in which a larger amount is deposited on the sidewalls of the gate electrode and the gate insulating film, that is, a side wall is generated.

Thereafter, high concentration n-type or p-type impurity ions are implanted on the first interlayer insulating layer 16 having the sidewalls formed thereon as shown in FIG. 2E.

In this case, the high concentration of impurity ions are implanted into the source / drain region where the first interlayer insulating layer 16 is flatly deposited, whereby the semiconductor layer 13 of the source / drain region is amorphous.

In addition, the amount of ion implantation is naturally reduced in the sidewall region of the gate electrode and the gate insulating film on which the first interlayer insulating film 16 is deposited, and thus the poly-Si semiconductor layer 13 corresponding to the region. ) Becomes a lightly doped region.

That is, a junction defect that occurs in the poly-Si active region and the amorphous source / drain region junction without the additional process by forming the first interlayer insulating layer 16 and resulting sidewall phenomenon by the gate electrode and the gate insulating layer. LDD (Lightly doped drain) structure that can heal the will be able to implement.

Next, as shown in FIG. 2F, secondary excimer laser annealing is performed to recrystallize the silicon thin film of the amorphous source / drain region and to electrically activate the implanted dopant. By excimer laser annealing of the source / drain, the source / drain regions become n-type or p-type heavily doped polycrystalline silicon thin films, and in the OFF state, a small number of carriers (n-type holes) , in the case of the p-type, blocks the flow of electrons and acts as a conductor that supplies the majority carriers and connects the channel of the TFT and the metal wiring in the ON state.

That is, the first semiconductor layer 13 is divided into a source / drain region, a lightly doped region LDD, and an active region.

Finally, as shown in FIG. 2G, a second interlayer insulating layer 17 covering the gate electrode 15 and the source / drain region is formed, and the source / drain is formed in the first and second interlayer insulating layers 16 and 17. Forming a source / drain contact hole that exposes an area, and forming a source / drain electrode 18 and 19 by stacking and patterning a source / drain conductive film on the entire surface of the substrate where the source / drain contact hole is formed, thereby forming a thin film transistor. Is prepared.

In this case, the second interlayer insulating layer 17 may be deposited by a CVD method, and may be an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO 2), or an organic compound of acrylic type, Teflon, BCB ( It may be formed of an organic insulator having a low dielectric constant such as benzocyclobutene), cytotope or perfluorocyclobutane (PFCB).

In addition, the second interlayer insulating film 17 is preferably deposited to a thickness of 3000 ~ 4000Å.

Next, as an example of a flat panel display including a thin film transistor according to an embodiment of the present invention described above will be described for an organic electroluminescent display.

3 is a schematic plan view of a flat panel display device including a thin film transistor according to an exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along line AA ′ of FIG. 3.

3 and 4 illustrate an organic electroluminescent display of the flat panel display, but this is only an example and the flat panel display according to the present invention is not necessarily limited thereto.

3 and 4, the organic light emitting display device includes a substrate 100, an encapsulation substrate 200, and a sealing material 300. For convenience of description, the substrate 100 refers to a substrate including an organic light emitting device, and the deposition substrate 110 refers to a substrate serving as a substrate on which an organic light emitting device is formed.

The substrate 100 is a plate including an organic light emitting element, and includes a pixel region 100a on which at least one organic light emitting element including the first electrode 101, the organic layer 102, and the second electrode 103 is formed. And a non-pixel region 100b formed at the outer edge of the pixel region 100a. Hereinafter, in the description of the present specification, the pixel area 100a is an area where an image is displayed due to the light emitted from the organic light emitting element, and the non-pixel area 100b is any area other than the pixel area 100a on the substrate 100. Means.

The pixel area 100a includes a plurality of scan lines S1 to Sn arranged in the row direction and a plurality of data lines D1 to Dm arranged in the column direction, and the scan lines S1 to Sn and the data lines D1 to Dm) is formed with a plurality of pixels to which a signal is applied from the driving integrated circuit for driving the organic light emitting element.

In the non-pixel region 100b, a driver IC for driving an organic light emitting diode and a metal wiring electrically connected to scan lines S1 to Sn and data lines D1 to Dm of the pixel region, respectively, are provided. Is formed. In this embodiment, the driving integrated circuit includes a data driver and a scan driver.

The buffer layer 111 is formed on the base substrate 110, and the buffer layer 111 is formed of an insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx). The buffer layer 111 is formed to prevent the substrate 100 from being damaged due to factors such as heat from the outside.

In addition, the thin film transistor described with reference to FIG. 2 is formed on the buffer layer 111.

That is, the semiconductor layer 120 includes an active region 122, source / drain regions 124 and 126, and a low concentration impurity region 128 on the buffer layer 111; A gate insulating layer 130 and a gate electrode 140 formed to overlap the active region 122; A first interlayer insulating film 150a formed on the source / drain regions 124 and 126 and the gate electrode 140; A second interlayer insulating film 150b formed on the first interlayer insulating film 150a and having a contact hole to expose a portion of the source / drain regions 124 and 126; A thin film transistor including source / drain electrodes 160a and 160b respectively connected to the source / drain regions through the contact hole is formed, wherein the first interlayer insulating layer 150a includes the gate electrode 140 and the gate. Due to the height difference between the height of the insulating layer 130 and the source / drain regions 124 and 126, a larger amount is deposited on the sidewalls of the gate electrode 140 and the gate insulating layer 130.

In addition, a planarization layer 170 is formed on the second interlayer insulating layer 150b, and a first electrode 101 is formed on one region of the planarization layer 170, wherein the first electrode 101 is a via hole ( h2) is connected to the exposed one of the source and drain electrodes 160a and 160b.

The pixel defining layer 180 including an opening (not shown) that exposes at least one region of the first electrode 101 is formed on the planarization layer 170 including the first electrode 101.

The organic layer 102 is formed on the opening of the pixel defining layer 180, and the second electrode layer 103 is formed on the pixel defining layer 180 including the organic layer 102. In this case, the second electrode layer 103 is formed. A passivation layer may be further formed on top.

The encapsulation substrate 200 encapsulates at least a pixel area of the substrate on which the organic light emitting element is formed, and the encapsulant 300 may be formed of an inorganic material such as frit or an organic material such as epoxy.

5 shows a circuit diagram of one pixel of FIG. One pixel of the organic electroluminescent display may include at least one driving transistor M1 and a switching transistor M2 as shown in the drawing. In this embodiment, although not shown, a threshold voltage compensation circuit or voltage may be included. Of course, more thin film transistors can be used by employing the drop compensation circuit.

Meanwhile, the flat panel display device having the thin film transistor according to the present invention may be used in a portable electronic device. Such a portable electronic device is a mobile phone, a laptop computer, a digital camera, a personal multimedia player (PMP), and the like, and FIGS. 6A and 6B illustrate an electronic device including a flat panel display device according to the present invention.

At this time, the flat panel display device 400 provides an image for the operation and use of the portable electronic device.

According to the present invention, a lightly doped region is formed at a junction between an active region and a source / drain region by using a sidewall phenomenon generated when forming an interlayer dielectric (ILD). By implementing a structure that forms a structure, that is, a lightly doped drain (LDD) structure, there is an advantage that the junction defect occurring in the active region and the source / drain region junction may be healed without an additional process.

Claims (14)

Substrate, A semiconductor layer comprising an active region, a source / drain region, and a low concentration impurity region; A gate insulating film and a gate electrode formed to overlap the active region; A first interlayer insulating film formed on the source / drain regions and the gate electrode; A second interlayer insulating layer formed on the first interlayer insulating layer and having a contact hole for exposing a portion of the source / drain region; A source / drain electrode connected to the source / drain area through the contact hole, respectively, The first interlayer insulating layer may be formed so that the amount deposited on the sidewalls of the gate electrode and the gate insulating layer is greater than the amount deposited on the source / drain region due to the difference between the height of the gate electrode and the gate insulating layer and the source / drain region. Thin film transistor, characterized in that. The method of claim 1, The first interlayer insulating film is a thin film transistor, characterized in that deposited to a thickness of 200 ~ 2000Å. The method of claim 1, The second interlayer insulating film is thin film transistor, characterized in that deposited to a thickness of 3000 ~ 4000Å. Depositing an amorphous silicon (a-Si) layer on the substrate; Crystallizing the amorphous silicon layer; Etching the crystallized silicon (Poly-Si) layer to pattern an active region, and sequentially forming a gate insulating layer and a gate electrode on the patterned crystallized silicon layer; Etching the gate electrode and the gate insulating layer to expose a source / drain region of the crystalline silicon layer; Forming a first interlayer insulating film on the gate electrode and the source / drain region; Implanting impurity ions onto the first interlayer insulating layer to cause the source / drain region to be amorphous, and to form a low concentration impurity region of the crystallized silicon (poly-Si) layer corresponding to the sidewall region of the gate electrode and the gate insulating layer Wow; Recrystallizing the silicon thin film of the amorphous source / drain region and electrically injecting the dopant; A second interlayer insulating layer covering the gate electrode and the source / drain region and having a contact hole for exposing a portion of the source / drain region is formed, and a source / drain respectively connected to the source / drain region through the contact hole; A method of manufacturing a thin film transistor, comprising the step of forming a drain electrode. The method of claim 4, wherein And removing hydrogen by performing heat treatment at a temperature of 400 ° C. or higher after the deposition of the amorphous silicon layer. The method of claim 4, wherein The crystallization of the amorphous silicon is a thin film transistor manufacturing method characterized in that it is made through one of: Excimer Laser Annealing (ELA), Sequential Lateral Solidification (SLS), or Metal Induced Lateral Crystallization (MILC) method. The method of claim 4, wherein The gate electrode is a thin film transistor manufacturing method, characterized in that formed of one metal selected from the group consisting of aluminum (Al), aluminum alloy (Al alloy), molybdenum (Mo) and molybdenum alloy (Mo alloy). The method of claim 4, wherein The first interlayer insulating film is a thin film transistor manufacturing method, characterized in that deposited to a thickness of 200 ~ 2000Å. The method of claim 8, The first interlayer insulating layer may be formed so that the amount deposited on the sidewalls of the gate electrode and the gate insulating layer is greater than the amount deposited on the source / drain region due to the difference between the height of the gate electrode and the gate insulating layer and the source / drain region. Thin film transistor manufacturing method characterized in that. The method of claim 4, wherein The second interlayer insulating film is a thin film transistor manufacturing method, characterized in that deposited to a thickness of 3000 ~ 4000Å. In a flat panel display device including a thin film transistor, The thin film transistor, A semiconductor layer comprising an active region, a source / drain region, and a low concentration impurity region; A gate insulating film and a gate electrode formed to overlap the active region; A first interlayer insulating film formed on the source / drain regions and the gate electrode; A second interlayer insulating layer formed on the first interlayer insulating layer and having a contact hole for exposing a portion of the source / drain region; A source / drain electrode connected to the source / drain area through the contact hole, respectively, The first interlayer insulating layer may be formed so that the amount deposited on the sidewalls of the gate electrode and the gate insulating layer is greater than the amount deposited on the source / drain region due to the difference between the height of the gate electrode and the gate insulating layer and the source / drain region. Flat panel display device characterized in that. The method of claim 11, And the first interlayer insulating film is deposited to a thickness of 200 to 2000Å. The method of claim 11, And the second interlayer insulating film is deposited to a thickness of 3000 to 4000 GPa. Portable electronic device comprising the flat panel display according to claim 11.

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